SM4 algorithm first-order threshold implementation method and system based on RAM

Abstract

The invention discloses an SM4 algorithm first-order threshold implementation method and system based on an RAM, and belongs to the technical field of cryptography, and the method comprises the steps: obtaining the mask representation of a master key; performing key expansion based on the mask representation of the master key to obtain a plurality of round keys, and storing the round keys in an RAM (Random Access Memory); and encrypting or decrypting the data in combination with the round key in the RAM memory to obtain an encryption or decryption result of the data. According to the invention, the existing RAM resources in the equipment are fully utilized, and the chip area occupied by the SM4 algorithm threshold implementation scheme is remarkably reduced, so that the application field of the SM4 algorithm threshold implementation scheme is further widened, and the RAM resources in the electronic equipment are more efficiently utilized.

Description

Technical Field

[0001] The present invention belongs to the technical field of cryptography, and in particular relates to a first-order threshold implementation method and system of the SM4 algorithm based on RAM. Background Art

[0002] As the national block cipher algorithm standard in China, the SM4 algorithm has been widely recognized internationally. This algorithm is based on the Feistel structure, with both the plaintext and the key length being 128 bits, and the number of encryption rounds being 32 rounds. Due to its high theoretical security and relatively fast encryption and decryption speed, this algorithm is widely used in key fields such as 5G communication, vehicle networking, and the Internet of Things. However, in actual deployment, the implementation carriers of the SM4 algorithm often face untrusted or malicious environments. In such scenarios, attackers may attempt to recover the key by analyzing the physical information generated during the operation of the carrier (i.e., side-channel attacks), which seriously threatens the implementation security of the SM4 algorithm on security chips.

[0003] In response to the threat of side-channel attacks to the SM4 algorithm, existing protection strategies currently achieve protection by destroying the correlation between side information and intermediate values of cryptographic operations. According to different protection ideas, side-channel protection methods at the algorithm level can be divided into hiding techniques and masking techniques. The core idea of the hiding technique is to resist side-channel attacks by eliminating the relationship between the energy of the cryptographic device and the operations performed by the device or the intermediate values being processed. Although the protection schemes designed based on the hiding technique can increase the attack difficulty for attackers to a certain extent, such schemes do not provide an absolute theoretical security guarantee. By means such as increasing the number of collected side-channel curves and implementing fine signal preprocessing, attackers may still break through such protection. The core idea of the masking technique is to perform a randomization operation on the intermediate values of the cryptographic algorithm, thereby masking the original intermediate values. Compared with the hiding technique, the masking technique has higher provable security, a wider application range, and better performance efficiency. Boolean masking, arithmetic masking, private circuits, etc. are representative methods in the early stage of the masking technique. Among them, the core idea of Boolean masking is to randomize the intermediate values processed by the cryptographic chip using random numbers. This method has obvious advantages compared with other early protection means due to its strong generality, and has thus received extensive research and attention since its proposal.

[0004] Early masking methods were all based on an idealized premise, that is, the intermediate operations of the cryptographic algorithm were either fully executed or not executed at all. Such an assumption enabled these schemes to operate securely in software implementations. However, due to hardware circuits, especially circuits composed of CMOS components, being prone to glitch phenomena, the practicality of early masking methods at the hardware level was greatly reduced.

[0005] To overcome this problem, Nikova et al. proposed the novel masking method of threshold implementation. In the d-threshold implementation, the original input variable x is split into S x masked components, i.e., the original intermediate operation circuit f is split into S f operation sub-circuits, i.e., the original output variable y is split into S y masked components, i.e., Then, these S x input masked components are brought into the S f operation sub-circuits to complete the original intermediate operation process, so as to obtain the specific value of the output masked component To ensure that the threshold implementation can effectively resist the d-th order side-channel attack, the above splitting process needs to satisfy three properties:

[0006] (1) Correctness: Ensure that the threshold implementation scheme can perform operations correctly. Specifically, the exclusive-or sum of all input masked components x0, …, is equal to the original input variable x, i.e., Similarly, the exclusive-or sum of all output masked components y0, …, is equal to the original output variable y, i.e.,

[0007] (2) Non-completeness: Ensure that the process of calculating each output masked component does not leak the secret original variable in the case of glitches in the circuit. In the threshold implementation scheme of the function y = f(x), each masked component function f i (.) only involves a part of the input masked components x0, …, In the d-th order attack, the attacker combines any d masked component functions f i (.) and the input is at least independent of one masked component of the input variable x.

[0008] (3) Uniformity: Ensure that the input variable of the next masked function is uniformly masked. When the input masked components x0, …, follow a uniform distribution, the calculated output masked components y0, …, should also follow a uniform distribution.

[0009] In the practical applications of embedded devices, limited by resources such as chip area, operating speed, and power consumption, the implementation of the threshold implementation scheme of the SM4 algorithm faces huge challenges. These limitations require the SM4 algorithm to maintain a high level of security under limited resources, while achieving high efficiency and cost control. Most existing threshold implementation schemes of the SM4 algorithm are difficult to implement in resource-constrained cryptographic devices, which greatly restricts the wide application and progress of the threshold technology of the SM4 algorithm in the industrial community. Therefore, the industrial community generally adopts traditional Boolean masking as an alternative solution at present. Although it can provide security guarantees to a certain extent, it also correspondingly increases the security risks of cryptographic devices. In view of this situation, how to design a first-order threshold implementation scheme of SM4 that is both highly secure and low-cost to meet the urgent needs of embedded devices in the implementation of cryptographic algorithms has become a research hotspot in the current field of cryptography.

[0010] Since the Boolean masking method was proposed, Bai Xuefei et al. designed a traditional Boolean masking scheme for the composite field implementation structure of the S-box of the SM4 algorithm. This scheme ensures that all intermediate values during the encryption process are randomized. However, this scheme has the following deficiencies: First, it fails to provide a masking strategy for key expansion; second, its encryption masking scheme is vulnerable to zero-value attacks; finally, since this scheme occupies a relatively large chip area (25kGE), it is limited in application on resource-constrained cryptographic chips. To address the first problem above, Tan Ruineng et al. proposed an innovative multi-path multiplication masking method, which combines multiplication masking and dual-path masking techniques to comprehensively randomize all intermediate values during the encryption process and key expansion process of the SM4 algorithm. However, this dual-path design idea leads to a significant increase in the circuit area required for the protection scheme. To address the second problem above, Pei Chao et al. proposed a random masking scheme based on the S-box look-up table method. This scheme effectively improves the algorithm's resistance to zero-value attacks by performing random linear transformations on the S-box and combining the characteristics of multi-path multiplication masking. To address the third problem above, Niu Yanbo et al. optimized the traditional Boolean masking scheme by introducing the PPRM circuit structure. This optimized scheme significantly reduces the demand for chip area, reducing it to 18.6kGE, making it more suitable for deployment on resource-limited cryptographic chips.

[0011] Currently, the hardware implementation of the SM4 algorithm mainly relies on chips composed of CMOS components. However, glitches in CMOS circuits may cause the SM4 algorithm based on Boolean masking to leak sensitive information, thus threatening its security at the hardware level. To address this problem, Li Xinchao et al. used the method of adding masks to the multipliers in the GF(2 4 ) field and GF(2 2)A multiplier over a finite field designs a 2-share first-order threshold implementation scheme, which resists side-channel attacks by adding masks to the multiplier over the finite field of the S-box. Although this scheme has improved security, its large chip area (28kGE) and the 58-bit extra random numbers required during the execution of each S-box limit its wide application in resource-constrained cryptographic chips. To address this issue, when implementing the first-order threshold implementation scheme of the SM4 algorithm, Wu Xiaonian et al. used the RAM memory in the security chip to store the sub-keys expanded from the key. This method not only makes full use of various resources in the security chip (such as RAM memory and PPRM circuit), but also effectively reduces the logic gate area required for the protection scheme. To further optimize the chip area of the SM4 threshold implementation scheme, Wei Man and Pu Jinwei et al. respectively proposed optimization methods based on the serial implementation of the S-box. The work of Wei Man et al. is particularly remarkable. They extended the classical threshold implementation scheme and introduced a non-balanced threshold implementation technique. By allocating different numbers of mask components to different input variables in the objective function, this technique not only ensures the uniformity of the threshold implementation, but also increases the flexibility of the design. Applying this technique to the SM4 algorithm, they successfully designed a serial-implementation-based SM4 threshold encryption circuit. This circuit has a small chip area (7.7kGE), requires 198 clock cycles to perform a block encryption, and only needs 8-bit random numbers for each S-box, significantly improving the resource utilization efficiency and security. Pu Jinwei et al. introduced a domain-oriented multiplication mask for the S-box. Their serial-implementation-based SM4 algorithm threshold implementation scheme occupies a chip area of 6.8kGE, requires 292 clock cycles for each block encryption, and needs 12-bit random numbers for each S-box during the encryption process. Both of these optimization strategies have significantly improved the security and efficiency of the SM4 algorithm in hardware implementation.

[0012] Although the existing threshold implementation schemes of the SM4 algorithm have successfully reduced the chip area from the initial 28kGE to 6.8kGE, this optimization mainly relies on the adjustment of the circuit implementation structure, that is, by reducing the data width. However, current electronic devices on the market, such as 5G SIM cards, second-generation resident identity cards, and bank cards, are all equipped with sufficient RAM to store sensitive data, but the utilization efficiency of these RAM resources is not high. Summary of the Invention

[0013] The present invention provides a first-order threshold implementation method and system for the SM4 algorithm based on RAM, which moves the threshold implementation scheme of each sub-domain operation of the S-box in the SM4 algorithm to the RAM memory for execution, and stores the generated round keys in the RAM as well. This method not only makes full use of the existing RAM resources in the device, but also significantly reduces the chip area occupied by the SM4 algorithm threshold implementation scheme, thereby further broadening the application field of the SM4 algorithm threshold implementation scheme and making more efficient use of the RAM resources in these electronic devices.

[0014] To achieve the above object, the technical solution of the present invention includes the following content.

[0015] A first-order threshold implementation method for the SM4 algorithm based on RAM, the method comprising:

[0016] Obtaining a masked representation of the master key;

[0017] Performing key expansion based on the masked representation of the master key to obtain a plurality of round keys, and storing the round keys in the RAM memory;

[0018] Combining the round keys in the RAM memory to encrypt or decrypt the data to obtain the encrypted or decrypted result of the data.

[0019] Further, performing key expansion based on the masked representation of the master key to obtain a plurality of round keys, including:

[0020] Feeding the masked representation of the master key into a multiplexer; wherein, the multiplexer is used to feed the masked representation of the master key into the shared S-box module when the round number is the first round, and feed the round key obtained in the previous round into the shared S-box module when the round number is other rounds, and the shared S-box module is a masked S-box shared by key expansion and data encryption or key expansion and data decryption;

[0021] Performing byte substitution operation on the output of the multiplexer by using the shared S-box module;

[0022] Performing linear transformation on the result of the byte substitution operation to obtain a linear transformation result;

[0023] Performing exclusive OR calculation on the linear transformation result and the output of the multiplexer to obtain the round function of this round.

[0024] Further, the operations of the shared S-box module include: linear mapping, GF(2 i ).MulXorSqSc operation, GF(2 i ).Inv operation, GF(2 i).Mul operation and inverse linear mapping; where i = {1, 2, 4}, in the byte substitution operation on the output of the multiplexer using the shared S-box module, for GF(2 i ).MulXorSqSc operation, the GF(2 i ).Inv operation or the execution process of the GF(2 i ).Mul operation includes:

[0025] Generate the masked components of the input variable;

[0026] Based on the masked components of the input variable, look up the corresponding masked value in the RAM memory; where the masked value is the value of a function composed of several masked terms obtained by substituting the masked components for the input variable into the Boolean function, and the masked values in the RAM memory are pre-generated by traversing all the values of the masked components of the input variable;

[0027] According to the masked value, obtain the masked components of the output variable.

[0028] Furthermore, for the GF(2 4 ).MulXorSqSc operation, based on the masked components of the input variable, looking up the corresponding masked value in the RAM memory includes:

[0029] Set the input variables of the GF(2 4 ).MulXorSqSc operation to be (d0, c0, b0, a0) and (h0, g0, f0, e0) respectively; where d0, c0, b0, a0 are the bits in the input variable (d0, c0, b0, a0), and h0, g0, f0, e0 are the bits in the input variable (h0, g0, f0, e0);

[0030] Set the masked components of the input variable (d0, c0, b0, a0) to be and where is the bit in the masked component (d0, c0, b0, a0), is the bit in the masked component ;

[0031] Set the masked components of the input variable (h0, g0, f0, e0) to be and where is the bit in the masked component ; is the bit in the masked component ;

[0032] Traverse the masked components Mask component Mask component and the mask component to obtain a first mask value table by taking bit values in the mask component, and store the first mask value table in the RAM memory; wherein, the elements in the first mask value table include: mask values Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value and mask values

[0033] Mask value

[0034] Mask value

[0035] Mask value

[0036] Mask value

[0037] Mask value

[0038] Mask value

[0039] Mask value

[0040] Mask value

[0041] Mask value

[0042] Mask value

[0043] Mask value

[0044] Mask value

[0045] Mask value

[0046] Mask value

[0047] Mask value

[0048] Mask value

[0049] When performing byte substitution operations on the output of the multiplexer using the shared S-box module, based on the values of each bit in the mask components of the input variables for the GF(2 4 ).MulXorSqSc operation, look up in the first mask value table in the RAM memory to obtain the corresponding mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value and mask value

[0050] Furthermore, for the GF(2 4 ).MulXorSqSc operation, based on this mask value, obtain the mask components of the output variables, including:

[0051] Generate the mask components of the output variables Among them, the bit value Bit value Bit value Bit value

[0052] Generate the mask components of the output variables Among them, the bit value Bit value Bit value Bit value

[0053] Furthermore, for the GF(2 4 ).Inv operation, based on the mask components of this input variable, look up the corresponding mask values in the RAM memory, including:

[0054] Set the input variables of the GF(2 4 ).Inv operation to (d1, c1, b1, a1); where d1, c1, b1, and a1 are the bits in the input variables (d1, c1, b1, a1).

[0055] Set the mask components of the input variables (d1, c1, b1, a1) to be respectively and where is the bit in the mask component and is the bit in the mask component .

[0056] Traverse the bit values of the mask component and the mask component to obtain the second mask value table and store the second mask value table in the RAM memory; where the elements in the first mask value table include: mask values mask value mask value mask value mask value mask value mask value mask value mask value mask value mask value mask value mask value mask value mask value mask value mask value mask value mask value mask value mask value mask value mask value mask value mask value mask value mask value mask value mask value mask value mask value and mask value

[0057] mask value

[0058] mask value

[0059] Mask value

[0060] Mask value

[0061] Mask value

[0062] Mask value

[0063] Mask value

[0064] Mask value

[0065] Mask value

[0066] Mask value

[0067] Mask value

[0068] Mask value

[0069] Mask value

[0070] Mask value

[0071] Mask value

[0072] Mask value

[0073] Mask value

[0074] Mask value

[0075] Mask value

[0076] Mask value

[0077] Mask value

[0078] Mask value

[0079] Mask value

[0080] Mask value

[0081] Mask value

[0082] Mask value

[0083] Mask value

[0084] Mask value

[0085] Mask value

[0086] Mask value

[0087] Mask value

[0088] Mask value

[0089] When performing byte substitution operation on the output of the multiplexer using the shared S-box module, based on the values of each bit in the mask component of the input variable for the GF(2 4 ).MulXorSqSc operation, look up in the second mask value table in the RAM memory to obtain the corresponding mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value And mask value

[0090] Furthermore, for the GF(2 4 ).Inv operation, according to this mask value, obtain the mask component of the output variable, including:

[0091] Generate the mask component of the output variable where the bit value bit value bit value bit value

[0092] Generate the mask component of the output variable where the bit value bit value bit value bit value

[0093] Furthermore, for the GF(2 4 ).Mul operation, look up the corresponding mask value in the RAM memory based on the mask component of the input variable, including:

[0094] Set the input variables of the GF(2 4 ).Mul operation to be (d2, c2, b2, a2) and (h2, g2, f2, e2) respectively; where d2, c2, b2, a2 are the bits in the input variable (d2, c2, b2, a2), and h2, g2, f2, e2 are the bits in the input variable (h2, g2, f2, e2);

[0095] Set the mask components of the input variable (d2, c2, b2, a2) to be and where is the bit in the mask component and is the bit in the mask component ;

[0096] Set the mask components of the input variable (h2, g2, f2, e2) to be and where is the bit in the mask component and is the bit in the mask component ;

[0097] Traverse the bit values of the mask component and the mask component to obtain the third mask value table, and store the third mask value table in the RAM memory; where the elements in the third mask value table include: mask value mask value mask value mask value mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value and mask value

[0098] Mask value

[0099] Mask value

[0100] Mask value

[0101] Mask value

[0102] Mask value

[0103] Mask value

[0104] Mask value

[0105] Mask value

[0106] Mask value

[0107] Mask value

[0108] Mask value

[0109] Mask value

[0110] Mask value

[0111] Mask value

[0112] Mask value

[0113] Mask value

[0114] When performing byte substitution operations on the output of a multiplexer using a shared S-box module, based on the values of each bit in the mask component of the input variable of the GF(2 4 ).Mul operation, look up in the second mask value table in the RAM memory to obtain the corresponding mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value and mask value

[0115] Furthermore, for the GF(2 4 ).Mul operation, according to the mask value, obtain the mask component of the output variable, including:

[0116] Generate the mask component of the output variable Among them, the bit value Bit value Bit value Bit value

[0117] Generate the mask component of the output variable Among them, the bit value Bit value Bit value Bit value

[0118] A first-order threshold implementation system of the SM4 algorithm based on RAM, the system includes:

[0119] A key expansion module, used to obtain the mask representation of the master key; perform key expansion based on the mask representation of the master key to obtain a number of round keys, and store the round keys in the RAM memory;

[0120] A RAM memory, used to store round keys;

[0121] An encryption / decryption module, used to combine the round keys in the RAM memory to encrypt or decrypt data to obtain the encrypted or decrypted result of the data.

[0122] Compared with the prior art, each operation of the S-box of the present invention requires one clock cycle to ensure the glitch detection security of the scheme. Therefore, one round function needs to consume 5 clock cycles to complete the operation. The SM4 algorithm consists of 32 round functions. Therefore, encrypting a block of plaintext requires 160 clock cycles. Compared with the scheme of Pu Jinwei, the present invention achieves a significant 45% reduction in latency.

[0123] In the use of random numbers, the present invention introduces certain additional requirements in the operation of each S-box. Specifically, the GF(2 4 ).MulXorSqSc operation requires 8 bits of additional random numbers, the GF(2 4 ).Inv operation requires 16 bits of additional random numbers, and the GF(2 4 ).Mul operation requires 16 bits of additional random numbers. Therefore, in the encryption and decryption process, each S-box requires a total of 40 bits of additional random numbers. Although this requirement increases compared with the scheme of Pu Jinwei, the present invention uses an efficient pseudo-random number generator to generate these random numbers, thus ensuring the efficiency and security of the overall system.

[0124] To reduce the chip area occupied by the threshold implementation scheme of the SM4 algorithm, the present invention uses a RAM memory to implement the GF(2 4 ).MulXorSqSc operation, GF(2 4 ).Inv operation, and GF(2 4 ).Mul operation of the S-box. To further improve the utilization rate of the RAM, the present invention also stores the generated masked sub-keys, the key expansion module, and the round intermediate states of the encryption and decryption modules in the RAM. This strategy maximally utilizes the existing RAM resources and realizes the optimal configuration of resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0125] Figure 1 is the composite field implementation structure of the S-box of the SM4 algorithm.

[0126] Figure 2 is the hardware implementation structure of the first-order threshold implementation scheme of the SM4 algorithm. DETAILED DESCRIPTION OF THE INVENTION

[0127] The present invention will be further described in detail below with reference to the accompanying drawings. The examples given are only used to explain the present invention and are not intended to limit the scope of the present invention.

[0128] 1. Description of the SM4 Algorithm

[0129] The SM4 algorithm performs encryption operations and key expansion in units of words. A 128-bit plaintext is represented as 4 32-bit words (X0, X1, X2, X3), and the round key for each round is a 32-bit word rki Then, the encryption transformation can be expressed as X i+4 = F(X i , X i+1 , X i+2 , X i+3 , rk i ) = X i ⊕ T(X i+1 ⊕ X i+2 ⊕ X i+3 ⊕ rk i ), where i ∈ [0, 31]. The round function T is an invertible transformation. First, a non - linear S - box transformation is performed on each byte of the input, and then an L linear transformation is performed.

[0130] Represent the 128 - bit key as 4 32 - bit words (K0, K1, K2, K3). Then, the key expansion can be expressed as K i+4 = F′(K i , K i+1 , K i+2 , K i+3 , CK i ) = K i ⊕ T′(K i+1 ⊕ K i+2 ⊕ K i+3 ⊕ CK i ), where CK i is a fixed constant. The round function T′ is composed of a non - linear transformation S - box and a linear transformation L′. The following gives an introduction to the non - linear transformation S - box and the two linear transformations L and L′.

[0131] (1) S - box transformation: This transformation divides the 32 - bit input into 4 bytes. Each byte passes through an 8 - in - 8 - out S - box respectively to obtain 4 output bytes. This S - box is composed of an inner affine transformation, an inverse operation in the finite field GF(2 8 ) field, and an outer affine transformation. The algebraic expression is y = S(x) = M(Mx + c) -1 + c, where the linear transformation matrix M is:

[0132]

[0133] The 8 - bit constant vector c is: c = (1, 1, 0, 1, 0, 0, 1, 1) T .

[0134] (2) Linear transformation L: This transformation performs a shift operation on the 32 - bit output Y of the S - box transformation in the encryption process to obtain a 32 - bit word output Z. The specific expression is:

[0135] Z = L(Y) = Y⊕(Y <<< 2)⊕(Y <<< 10)⊕(Y <<< 18)⊕(Y <<< 24)

[0136] (3) Linear transformation L': This transformation is basically the same as the L linear transformation in the encryption process, except that the shift parameter is changed. The specific expression is:

[0137] Z = L'(Y) = Y ⊕ (Y <<< 13) ⊕ (Y <<< 23)

[0138] 2. Construction method for threshold implementation scheme of any Boolean function

[0139] For any Boolean function, the present invention first designs a first-order threshold implementation scheme for it to ensure that while meeting the correctness requirement, it also meets the incompleteness requirement. To further enhance the security of the scheme, the present invention introduces additional random numbers to ensure the uniformity of the output and meet the first-order glitch detection security.

[0140] Taking x = ab + a as an example, introduce how to construct a first-order threshold implementation scheme that meets the correctness and incompleteness requirements for any Boolean function. Let the masked components of the input variables a and b be a 0 , a 1 , b 0 , b 1 , and the masked components of the output variable x be x 0 , x 1 . The present invention substitutes the input masked components for the original input variables into the original function x = ab + a, and the masked function x = a 0 b 0 + a 0 b 1 + a 1 b 0 + a 1 b 1 + a 0 + a 1 can be obtained. Then, place these masked terms in the 4 masked component functions x a , x b , x c , x d to ensure that the formed threshold implementation scheme meets the correctness and first-order incompleteness. The specific expressions are as follows:

[0141]

[0142] Then, the present invention introduces 2-bit additional random numbers to re-mask the output masked components of these 4 masked component functions to ensure the independence of the output masked component functions from each other. When re-masking, the present invention adopts a circular re-masking method, which is beneficial to reducing the required external random numbers. The specific expressions after re-masking are as follows:

[0143]

[0144] To prevent the backward transmission of the glitch, the outputs of these 4 mask component functions need to be stored in registers. After storage, the outputs of the first two mask component functions are XORed to obtain the final output mask component x 0 , and the outputs of the last two mask component functions are XORed to obtain the final output mask component x 1 . The specific expression of the XOR is as follows:

[0145]

[0146] It should be noted that the number of mask component functions changes with the algebraic degree of the target Boolean function. Generally speaking, when the algebraic degree of the target Boolean function is 2, the lower limit of the number of mask component functions is 4; when the algebraic degree of the target Boolean function is 3, the lower limit of the number of mask component functions is 8.

[0147] 3. Threshold implementation scheme of the SM4 algorithm

[0148] When designing a protection scheme for the SM4 algorithm using the threshold implementation principle, the present invention splits a 128-bit plaintext (or key) into two 128-bit mask components through random numbers, and then encrypts and expands the key of these 2 128-bit mask components through a protected circuit.

[0149] According to the above introduction of the SM4 algorithm, the operation components of the SM4 algorithm can be divided into linear operation components (such as linear transformations L and L') and non-linear operation components (such as S-box transformation). Below, the present invention respectively gives how to design a protection scheme for the linear operation component and the non-linear operation component using the principle of threshold implementation.

[0150] (1) Linear operations L and L': Since threshold implementation has linear properties, the output value of first performing a linear operation on each mask component and then performing an XOR operation is equal to the output value of first performing an XOR operation on each mask component and then performing a linear operation. Therefore, when the present invention designs a threshold implementation scheme for the linear operations L and L', only each input mask component needs to pass through this linear operation component to complete the protection process. Specifically, let the input variable x of the linear operation L L The two input mask components of are and Then the protection scheme for this operation is:

[0151]

[0152] (2) Non-linear operation: The core operation of the S-box is an inversion operation in the finite field GF(2 8 ). The present invention uses the method of composite fields to decompose the S-box into subfields GF(24 ) Operations on or smaller subdomains, first design a composable first-order threshold implementation scheme for each decomposed sub-module, and then obtain the threshold implementation scheme of the entire S-box through combination. When designing the threshold implementation scheme for the S-box, considering performance factors such as chip area and delay, this embodiment selects to decompose the inverse operation value on the finite field GF(2 8 ) to perform the inverse operation on GF(2 4 ), as shown in Figure 1 .

[0153] Among them, the linear mapping and the inverse linear mapping are linear operations, and the protection strategy can be designed by using the foregoing construction method. GF(2 4 ).MulXorSqSc and GF(2 4 ).Mul are non-linear operations with an algebraic degree of 2, and GF(2 4 ).Inv is a non-linear operation with an algebraic degree of 3. For these three operation modules, the present invention can construct a threshold implementation scheme with first-order glitch detection security for them according to the construction method of the threshold implementation scheme of any Boolean function given above.

[0154] ① GF(2 4 ).MulXorSqSc operation: Let the two 4-bit input variables of this operation be (d0, c0, b0, a0) and (h0, g0, f0, e0) respectively, and the output variable be (t0, z0, y0, x0). Then the algebraic normal form of this operation is:

[0155]

[0156] Let the two mask components of the input variable (d0, c0, b0, a0) of this operation be and Let the two mask components of the input variable (h0, g0, f0, e0) be and Let the two mask components of the output variable (t0, z0, y0, x0) be and Then, the threshold implementation scheme constructed for the first coordinate function of this operation is:

[0157]

[0159] The threshold implementation scheme constructed for the second coordinate function of this operation is:

[0160]

[0161] The threshold implementation scheme constructed for the third coordinate function of this operation is:

[0162]

[0163] The threshold implementation scheme constructed for the fourth coordinate function of this operation is as follows:

[0164]

[0165] ② GF(2 4 ).Inv operation: Let the 4-bit input variables of this operation be (d1, c1, b1, a1), and the output variables be (t1, z1, y1, x1). Then the algebraic normal form of this operation is:

[0166]

[0167] Let the two mask components of the input variables (d1, c1, b1, a1) of this operation be and Let the two mask components of the output variables (t1, z1, y1, x1) be and Then, the threshold implementation scheme constructed for the first coordinate function of this operation is:

[0168]

[0169] The threshold implementation scheme constructed for the second coordinate function of this operation is:

[0170]

[0171] The threshold implementation scheme constructed for the third coordinate function of this operation is:

[0172]

[0173] The threshold implementation scheme constructed for the fourth coordinate function of this operation is:

[0174]

[0175] ③ GF(2 4 ).Mul operation: Let the two 4-bit input variables of this operation be (d2, c2, b2, a2) and (h2, g2, f2, e2) respectively, and the output variable be (t2, z2, y2, x2). Then the algebraic normal form of this operation is:

[0176]

[0177] Let the two mask components of the input variable (d2, c2, b2, a2) of this operation be and Two masked components of the input variables (h2, g2, f2, e2) are and Two masked components of the output variables (t2, z2, y2, x2) are and Then, the threshold implementation scheme constructed for the first coordinate function of this operation is as follows:

[0178]

[0179] The threshold implementation scheme constructed for the second coordinate function of this operation is as follows:

[0180]

[0181] The threshold implementation scheme constructed for the third coordinate function of this operation is as follows:

[0182]

[0183] The threshold implementation scheme constructed for the fourth coordinate function of this operation is as follows:

[0184]

[0185] 4. Hardware Implementation of Threshold Implementation of SM4 Algorithm

[0186] In this section, the present invention will introduce in detail the hardware architecture of the first-order threshold implementation scheme of the SM4 algorithm. As Figure 2 shown, this architecture mainly consists of the following key modules: masked key expansion module, masked encryption / decryption module, shared masked S-box module, and RAM memory.

[0187] (1) S-box module: This module is composed of 4 parallel masked S-boxes. Each masked S-box includes operations such as linear mapping, GF(2 4 ).MulXorSqSc operation, GF(2 4 ).Inv operation, GF(2 4 ).Mul operation, and inverse linear mapping. For the threshold implementation scheme of each coordinate function of each non-linear operation (including GF(2 4 ).MulXorSqSc operation, GF(2 4 ).Inv operation, GF(2 4 ).Mul operation), the present invention uses RAM to store each possible value. When in use, the input masked component is used as the address to quickly obtain its corresponding output value.

[0188] For example, for GF(2 4When implementing the threshold implementation scheme of the first coordinate function of the MulXorSqSc operation (see formula (6)) in hardware, the present invention first traverses all input mask components and respectively pre-calculate all possible values of as follows:

[0189]

[0190] Then, the present invention stores these calculated output values in the RAM so that they can be quickly retrieved during actual operations. During actual operations, the present invention uses the specific value of the input variable of as the address index of the RAM to directly read and obtain the corresponding output value. This method significantly improves the operation efficiency because it avoids real-time calculation and quickly obtains the corresponding output value by looking up the pre-stored results. Similarly, the threshold implementation schemes of other coordinate functions of the GF(2 4 ).MulXorSqSc operation and the GF(2 4 ).Inv operation, GF(2 4 ).Mul operation can also adopt a similar process to implement, that is, pre-calculate and store possible results, and directly retrieve the output value through the input value during actual operations, so as to achieve the purpose of optimizing the operation speed and saving chip area.

[0191] (2) Key expansion module: This module mainly includes three sub-modules: a multiplexer, calculating fixed parameter CK, and linear transformation L'. The multiplexer is used to select the correct input: when it is the first round, the multiplexer feeds the masked representation of the master key into the shared S-box module; when it is other rounds, the multiplexer feeds the output of the previous round function into the shared S-box module. The key fixed parameter part is used to calculate the fixed parameter CK. In each round function of the key expansion, this module first feeds the output of the multiplexer into the shared S-box module to complete the byte substitution operation. Then, this module performs a linear transformation L' on the output of the shared S-box module to complete the key expansion of one round function. The sub-keys generated by each round function are stored in the RAM for the correct execution of encryption and decryption operations.

[0192] (3) Encryption and decryption module: This module is also composed of two sub-modules, a multiplexer and a linear transformation L. The function of the multiplexer is the same as that in the key expansion. The linear transformation L is implemented by a combinational logic. Different from the key expansion process, this module needs to read the correct sub-key from the RAM according to the number of encryption and decryption rounds.

[0193] In summary, in view of the deficiencies of the traditional threshold implementation scheme of the SM4 algorithm in terms of chip area occupation and the low utilization rate of RAM in current electronic devices on the market, the present invention proposes an innovative optimization method. This method constructs a first-order threshold implementation scheme with extremely low resource consumption for the SM4 algorithm by using the construction method of the threshold implementation scheme of any Boolean function. In the hardware implementation stage, the present invention ingeniously uses RAM to execute each operation of the masked S-box. This implementation method not only maintains the ability of the S-box to resist side-channel attacks but also significantly improves the utilization efficiency of RAM in electronic devices.

[0194] It is worth mentioning that the present invention adopts a design of sharing the S-box module between the key expansion module and the encryption / decryption module. This is based on the observation that the main key does not often change in most application scenarios. By sharing the S-box module, the present invention greatly reduces the chip area occupied by the protection scheme without disturbing the normal operation of the embedded chip, bringing higher cost performance to the embedded system.

Claims

1. A first-order threshold implementation method of the SM4 algorithm based on RAM, characterized in that, The method includes: Obtaining a masked representation of the master key; Performing key expansion based on the masked representation of the master key to obtain a plurality of round keys, and storing the round keys in a RAM memory; Combining the round keys in the RAM memory to encrypt or decrypt data to obtain an encrypted or decrypted result of the data.

2. The method according to claim 1, characterized in that, Performing key expansion based on the masked representation of the master key to obtain a plurality of round keys, including: Feeding the masked representation of the master key into a multiplexer; wherein, the multiplexer is configured to feed the masked representation of the master key into a shared S-box module when the round number is the first round, and feed the round key obtained in the previous round into the shared S-box module when the round number is other rounds, and the shared S-box module is a masked S-box shared for key expansion and data encryption or key expansion and data decryption; Performing a byte substitution operation on the output of the multiplexer using the shared S-box module; Performing a linear transformation on the result of the byte substitution operation to obtain a linear transformation result; Performing an XOR calculation on the linear transformation result and the output of the multiplexer to obtain the round function of this round.

3. The method according to claim 2, characterized in that, The operations of the shared S-box module include: linear mapping, GF(2 i ).MulXorSqSc operation, GF(2 i ).Inv operation, GF(2 i ).Mul operation and inverse linear mapping; where i = {1, 2, 4}, in the operation of byte substitution on the output of the multiplexer using the shared S-box module, for the execution process of the GF(2 i ).MulXorSqSc operation, the GF(2 i ).Inv operation or the GF(2 i ).Mul operation, it includes: Generating a masked component of the input variable; Looking up a corresponding masked value in the RAM memory based on the masked component of the input variable; wherein, the masked value is the value of a function composed of a plurality of masked terms obtained by substituting the masked component for the input variable into a Boolean function, and the masked values in the RAM memory are pre-generated by traversing the values of the masked components of all input variables; Obtaining a masked component of the output variable according to the masked value.

4. The method according to claim 3, wherein For the GF(2 4 ).MulXorSqSc operation, look up the corresponding mask value in the RAM memory based on the mask component of the input variable, including: Set the input variables of the GF(2 4 ).MulXorSqSc operation to be (d0, c0, b0, a0) and (h0, g0, f0, e0) respectively; where d0, c0, b0, a0 are the bits in the input variable (d0, c0, b0, a0), and h0, g0, f0, e0 are the bits in the input variable (h0, g0, f0, e0); Set the mask components of the input variables (d0, c0, b0, a0) to be respectively and where are bits in the mask components (d0, c0, b0, a0), is a bit in the mask component ; Set the mask components of the input variables (h0, g0, f0, e0) to be respectively and where are the mask components bits in are the mask components bits in; Traverse the mask components Mask component Mask component And mask component Obtain the first mask value table according to the bit values of the mask components, and store the first mask value table in the RAM memory; wherein, the elements in the first mask value table include: mask values Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value And mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value When performing byte substitution operations on the output of the multiplexer using the shared S-box module, based on the values of each bit in the mask component of the input variable of the GF(2 4 ).MulXorSqSc operation, look up in the first mask value table in the RAM memory to obtain the corresponding mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value and mask value 5. The method according to claim 4, characterized in that For the GF(2 4 ).MulXorSqSc operation, according to the mask value, obtain the masked components of the output variable, including: Generate the mask component of the output variable where the bit value bit value bit value bit value Generate a mask component of the output variable where the bit value The bit value The bit value The bit value 6. The method according to claim 3, characterized in that, For the GF(2 4 ).Inv operation, look up the corresponding mask value in the RAM memory based on the mask components of the input variable, including: Set GF(2 4 ). The input variables of the Inv operation are (d1, c1, b1, a1); where d1, c1, b1, and a1 are the bits in the input variables (d1, c1, b1, a1). Set the mask components of the input variables (d1, c1, b1, a1) to be respectively and where are bits in the mask component and are bits in the mask component ; Traverse the mask components and the mask components to obtain a second mask value table, and store the second mask value table in the RAM memory; wherein, the elements in the first mask value table include: mask values Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value and mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value When performing byte substitution operations on the output of the multiplexer using the shared S-box module, based on the values of each bit in the mask component of the input variable of the GF(2 4 ).MulXorSqSc operation, look up in the second mask value table in the RAM memory to obtain the corresponding mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value and the mask value 7. The method according to claim 6, wherein For the GF(2 4 ).Inv operation, according to the mask value, obtain the mask component of the output variable, including: Generate the mask component of the output variable where the bit value bit value bit value bit value Generate a masked component of the output variable where the bit value bit value bit value bit value 8. The method according to claim 3, characterized in that For the GF(2 4 ).Mul operation, look up the corresponding mask value in the RAM memory based on the mask components of the input variable, including: Set GF(2 4 ). The input variables of the Mul operation are (d2, c2, b2, a2) and (h2, g2, f2, e2) respectively; among them, d2, c2, b2, a2 are the bits in the input variable (d2, c2, b2, a2), and h2, g2, f2, e2 are the bits in the input variable (h2, g2, f2, e2); Set the mask components of the input variables (d2, c2, b2, a2) to be respectively and where are mask components bits in are mask components bits in; Set the mask components of the input variables (h2, g2, f2, e2) to be respectively and where are the mask components in which the bits are the mask components in which the bits; Traverse the mask components and the mask components to obtain a third mask value table, and store the third mask value table in the RAM memory; wherein, the elements in the third mask value table include: mask values Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value and mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value When performing byte substitution operations on the output of a multiplexer using a shared S-box module, based on the values of each bit in the mask component of the input variable for the GF(2 4 ).Mul operation, look up in the second mask value table in the RAM memory to obtain the corresponding mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value Mask value and mask value 9. The method according to claim 8, characterized in that, For the GF(2 4 ).Mul operation, according to the mask value, obtain the mask component of the output variable, including: Generate a masked component of the output variable where the bit value The bit value The bit value The bit value Generate a masked component of the output variable where the bit value The bit value The bit value The bit value 10. A first-order threshold implementation system of the SM4 algorithm based on RAM, characterized in that, The system includes: A key expansion module, configured to obtain a masked representation of the master key; perform key expansion based on the masked representation of the master key to obtain a plurality of round keys, and store the round keys in a RAM memory; A RAM memory, configured to store round keys; An encryption / decryption module, configured to combine the round keys in the RAM memory to encrypt or decrypt data to obtain an encrypted or decrypted result of the data.

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