Decision feedback equalizer and receiver

Abstract

The invention discloses a decision feedback equalizer and a receiver. The decision feedback equalizer comprises four data paths with the same structure, and each data path comprises an adder, a comparator module, a data selector, a latch, a primary clock control latch and a secondary clock control latch which are electrically connected in sequence. In the application, after receiving the input data, the adders in the four data paths are summed with the tap coefficients of the last four taps to obtain the summed data, then the comparator sums the summed data and the first tap coefficient, and sampling is carried out to obtain the sampling data; the data selector selects a correct summation result according to the output data and the sampling data of the previous path; the data output by the data selector is converted into non-return-to-zero code data through the latches, and the non-return-to-zero code data passes through the first-stage clock control latch and the second-stage clock control latch to obtain delayed data, so that rapid and accurate data equalization is realized, and the equalization capability of the decision feedback equalizer is improved.

Description

Technical Field

[0001] This application relates to the field of power electronics technology, and particularly to a decision feedback equalizer and a receiver. Background Art

[0002] Currently, a SerDes system includes a transmitter, a wired channel, and a receiver. Among them, due to non-ideal factors such as skin effect, dielectric loss, and signal reflection in the wired channel, the transmission quality of the signal will be seriously affected, resulting in the eye diagram of the signal received by the receiver being reduced or even closed. In addition, with the rapid increase in the signal transmission rate, the attenuation of the signal quality becomes more serious, which further seriously affects the working range and signal transmission rate of the SerDes system.

[0003] To address the above problems, a feed-forward equalizer (FFE), a decision feedback equalizer (DFE), and a continuous-time linear equalizer (CTLE) are usually set in the SerDes system. Among them, the decision feedback equalizer is the most widely applied and has the most obvious equalization effect at the receiving end of a high-speed serial interface. However, the existing decision feedback equalizers have the problem of low equalization ability. Summary of the Invention

[0004] In view of this, this application provides a decision feedback equalizer and a receiver, mainly aiming to solve the problem of low equalization ability existing in current decision feedback equalizers.

[0005] To solve the above problems, this application provides a decision feedback equalizer, including: four data paths with the same structure, each of the data paths respectively includes an adder, a comparator module, a data selector, a latch, a first clocked latch, and a second clocked latch that are electrically connected in sequence;

[0006] Each of the adders in the data paths respectively includes 5 differential input terminals, which are respectively used to receive input data, a second tap coefficient, a third tap coefficient, a fourth tap coefficient, and a fifth tap coefficient. The differential input terminals for receiving input data of each of the adders are also respectively electrically connected to the output terminal of the second clocked latch of the previous data path, the output terminal of the latch of the next data path, and the output terminal of the data selector of another data path, and are used to perform data addition processing based on the received input data, second tap coefficient, third tap coefficient, fourth tap coefficient, fifth tap coefficient, the output data of the second clocked latch of the previous data path, the output data of the latch of the next data path, and the output data of the data selector of another data path to obtain added data;

[0007] The comparator modules in each of the data paths are configured to sample the added data output by the adder in the same data path at a quarter rate based on the corresponding first sampling clock signal and the first tap coefficient to obtain sampled data; the first sampling clock signals corresponding to the comparators in two adjacent data paths are 90 degrees out of phase with each other.

[0008] The data selectors in each of the data paths are also electrically connected to the output end of the data selector in the previous data path, and are configured to perform a selection process on the sampled data output by the comparator module in the same data path and the selected data output by the data selector in the previous data path to obtain the selected data corresponding to the current data selector.

[0009] The latches in each of the data paths are configured to perform a latch conversion process on the selected data output by the data selector in the same data path to obtain non-return-to-zero (NRZ) latched data.

[0010] The first-stage clocked latches in each of the data paths are configured to perform a delayed sampling process on the latched data output by the latch in the same data path based on the second sampling clock signal to obtain first-stage latched data; the second sampling clock signal in the same data path is 180 degrees out of phase with the first sampling clock signal.

[0011] The second-stage clocked latches in each of the data paths are configured to perform a delayed sampling process on the first-stage latched data output by the first-stage latch in the same data path based on the third sampling clock signal to obtain second-stage latched data, so as to obtain equalized data corresponding to each data path; the second sampling clock signal and the third sampling clock signal in the same data path have the same phase.

[0012] Optionally, the decision feedback equalizer further includes a first error path and a second error path.

[0013] The first error path and the second error path have the same structure, and each includes an adder, a comparator module, a latch module, a first-stage clocked latch module, a second-stage clocked latch module, and a data selector that are electrically connected in sequence; in the same error path, the clock sampling signal received by the comparator module is the same as the clock sampling signal received by the second-stage clocked latch module, and is 180 degrees out of phase with the clock sampling signal received by the first-stage clocked latch module.

[0014] The first error path and the second error path are used to sum the input data, the second tap coefficient, the third tap coefficient, the fourth tap coefficient, and the fifth tap coefficient by using an adder to obtain the sum data, and use a comparator module to sample the sum data output by the adder at a quarter rate based on the adjusted first tap coefficient and the received clock sampling information to obtain the sampled data, and use a latch module, a first-level clocked latch module, and a second-level clocked latch module to perform latch conversion processing and delayed sampling processing on the sampled data in sequence to obtain error data corresponding to each error path and used to adjust the tap coefficient.

[0015] Optionally, each of the comparator modules includes a first comparator and a second comparator connected in parallel;

[0016] The latch module includes a first latch and a second latch. The first latch is connected in series with the first comparator, and the second latch is connected in series with the second comparator;

[0017] The first-level clocked latch module includes a first first-level clocked latch and a second first-level clocked latch. The first first-level clocked latch is connected in series with the first latch, and the second first-level clocked latch is connected in series with the second latch;

[0018] The second-level clocked latch module includes a first second-level clocked latch and a second second-level clocked latch. The first second-level clocked latch is connected in series with the first first-level clocked latch, and the second second-level clocked latch is connected in series with the second first-level clocked latch.

[0019] Optionally, each of the comparator modules in each data path includes a first comparator and a second comparator connected in parallel;

[0020] The input ends of the first comparator and the second comparator in the same comparator module are respectively electrically connected to the output end of the adder in the same data path, and are used to receive the output data of the adder in the same data path and the required first tap coefficient; the signs of the first tap coefficients received by the two comparators in the same comparator module are opposite.

[0021] Optionally, each of the first comparators and the second comparators is a two-stage comparator.

[0022] Optionally, each of the data selectors includes 4 transmission gates.

[0023] Optionally, each of the latches is a symmetric RS latch.

[0024] Optionally, each of the clocked latches is a clocked latch with a cross-coupled inverter structure.

[0025] To solve the above problems, the present application provides a receiver, which includes the decision feedback equalizer described in any one of the above, and further includes: a first multiplexer, a second multiplexer, and an adaptive logic module;

[0026] The first multiplexer is electrically connected to the output ends of each data path respectively, and is used to receive the equalized data output by each data path of the decision feedback equalizer, so as to decompose each equalized data to obtain the decomposed equalized data;

[0027] The second multiplexer is electrically connected to the output ends of the decision feedback equalizer and each error path respectively, and is used to receive the error data output by each error path, so as to decompose each error data to obtain the decomposed error data;

[0028] The input ends of the adaptive logic module are electrically connected to the output end of the first multiplexer and the output end of the second multiplexer respectively, and are used to receive the decomposed equalized data and the decomposed error data, and generate 5 external control voltages based on the decomposed equalized data and the decomposed error data, so as to adaptively adjust the magnitudes of each tap coefficient based on each external control voltage.

[0029] In the decision feedback equalizer of the present application, the adder in the four data paths sums the input data with the tap coefficients of the last four taps to obtain the sum data, and then the comparator sums and samples the sum data and the first tap coefficient to obtain the sampled data; the data selector selects the correct sum result according to the output data of the previous path and the sampled data; the data output by the data selector is converted into non-return-to-zero code data through a latch, and the non-return-to-zero code data obtains the delayed data through a first-stage clocked latch and a second-stage clocked latch, thereby realizing fast and accurate data equalization and improving the equalization ability of the decision feedback equalizer.

[0030] The above description is only an overview of the technical solution of the present invention. In order to be able to understand the technical means of the present application more clearly, it can be implemented according to the content of the specification. And in order to make the above and other purposes, features and advantages of the present application more obvious and understandable, the following specifically illustrates the specific embodiments of the present application. Brief Description of the Drawings

[0031] By reading the following detailed description of the preferred embodiments, various other advantages and benefits will become clear to those of ordinary skill in the art. The drawings are only for the purpose of showing the preferred embodiments and are not considered to be a limitation of the present invention. And throughout the drawings, the same reference numerals are used to represent the same components. In the drawings:

[0032] Figure 1 It is a system block diagram of a decision feedback equalizer according to an embodiment of the present application;

[0033] Figure 2 It is a system block diagram of a decision feedback equalizer in another embodiment of the present application;

[0034] Figure 3 It is a circuit diagram of an adder in an embodiment of the present application;

[0035] Figure 4 It is a circuit diagram of a comparator in an embodiment of the present application;

[0036] Figure 5 It is a circuit diagram of a data selector in an embodiment of the present application;

[0037] Figure 6 It is a circuit diagram of a latch in an embodiment of the present application;

[0038] Figure 7 It is a circuit diagram of a clocked latch in an embodiment of the present application;

[0039] Figure 8 It is a timing waveform diagram of the decision feedback equalizer;

[0040] Figure 9 It is a comparison diagram of the input and output data of the decision feedback equalizer;

[0041] Figure 10 It is a system block diagram of the receiver. Detailed implementation manners

[0042] Various solutions and features of the present application are described herein with reference to the accompanying drawings.

[0043] It should be understood that various modifications can be made to the embodiments applied herein. Therefore, the above description should not be regarded as a limitation, but only as an example of the embodiments. Those skilled in the art will think of other modifications within the scope and spirit of the present application.

[0044] The accompanying drawings included in and forming a part of the specification illustrate embodiments of the present application and, together with the general description of the present application given above and the detailed description of the embodiments given below, are used to explain the principles of the present application.

[0045] These and other features of the present application will become apparent from the following description of the preferred forms of the embodiments given as non-limiting examples with reference to the accompanying drawings.

[0046] It should also be understood that although the present application has been described with reference to some specific examples, those skilled in the art can surely implement many other equivalent forms of the present application.

[0047] When combined with the accompanying drawings, the above and other aspects, features, and advantages of the present application will become more apparent in view of the following detailed description.

[0048] Specific embodiments of the present application will be described hereinafter with reference to the accompanying drawings. However, it should be understood that the embodiments claimed are merely examples of the present application and can be implemented in various ways. Well-known and / or repetitive functions and structures are not described in detail to avoid obscuring the present application with unnecessary or redundant details. Therefore, the specific structural and functional details claimed herein are not intended to be limiting, but are merely a basis and representative basis for the claims to teach those skilled in the art to use the present application in substantially any suitable detailed structure in a variety of ways.

[0049] This specification may use the phrase "in one embodiment", "in another embodiment", "in yet another embodiment", or "in other embodiments", each of which may refer to one or more of the same or different embodiments according to the present application.

[0050] An embodiment of the present application provides a decision feedback equalizer, specifically as Figure 1 shown, including: four data paths with the same structure, namely the first data path A, the second data path B, the third data path C, and the fourth data path D in sequence; wherein, the previous data path of the first data path is the fourth data path, and the next data path of the fourth data path is the first data path. Each of the data paths respectively includes, connected in series in sequence: an adder, a comparator module COMP, a data selector MUX, a latch L, a first-level clocked latch L1, and a second-level center-controlled latch L2; the sampling clock signals of the comparators COMP in two adjacent data paths differ by 90 degrees;

[0051] Each of the adders in the data paths respectively includes 5 differential input terminals, which are respectively used to receive input data, the second tap coefficient, the third tap coefficient, the fourth tap coefficient, and the fifth tap coefficient. The differential input terminals of each adder for receiving input data are also respectively electrically connected to the output terminal of the second-level clocked latch L2 of the previous data path, the output terminal of the latch of the next data path, and the output terminal of the data selector of another data path, and are used to perform data addition processing based on the received input data, the second tap coefficient, the third tap coefficient, the fourth tap coefficient, the fifth tap coefficient, the output data of the second-level clocked latch of the previous data path, the output data of the latch of the next data path, and the output data of the data selector of another data path to obtain added data;

[0052] Each of the comparator modules COMP in the data paths is used to perform sampling processing on the added data output by the adder in the same data path at a quarter rate based on the corresponding target sampling clock signal and the first tap coefficient to obtain sampled data;

[0053] The data selector MUX in each of the data paths is also electrically connected to the output end of the data selector in the previous data path, and is used to perform selection processing on the sampled data output by the comparator module COMP in the same data path and the selected data output by the data selector in the previous data path, so as to obtain the selected data corresponding to the current data selector;

[0054] The latch in each of the data paths is used to perform latch conversion processing on the selected data output by the data selector in the same data path, so as to obtain the latched data of the non-return-to-zero code;

[0055] The first-stage clock-controlled latch in each of the data paths is used to perform delayed sampling processing on the latched data output by the latch in the same data path based on the non-target sampling clock signal that is 180 degrees different from the target sampling clock signal, so as to obtain the first-stage latched data;

[0056] The second-stage clock-controlled latch in each of the data paths is used to perform delayed sampling processing on the first-stage latched data output by the first-stage latch in the same data path based on the sampling clock signal with the same phase as the target sampling clock signal, so as to obtain the second-stage latched data, so as to obtain the equalized data corresponding to each data path, that is, to obtain the equalized data DATA_OUT(1), DATA_OUT(2), DATA_OUT(3), and DATA_OUT(4).

[0057] In the decision feedback equalizer of this embodiment, the adders in the four data paths will sum the input data with the tap coefficients of the last four taps to obtain the sum data, and then the comparator sums and samples the sum data and the first tap coefficient to obtain the sampled data; the data selector selects the correct sum result according to the output data of the previous path and the sampled data; the output data of the data selector is converted into non-return-to-zero code data through the latch, and the non-return-to-zero code data is delayed through the first-stage clock-controlled latch and the second-stage clock-controlled latch, so as to achieve fast and accurate data equalization and improve the equalization ability of the decision feedback equalizer.

[0058] Another embodiment of the present application provides a decision feedback equalizer. The decision feedback equalizer in this embodiment can specifically be as Figure 2As shown, it further includes a first error path X1 and a second error path X2. The first error path X1 and the second error path X2 have the same structure, and each includes, connected electrically in sequence: an adder, a comparator module, a latch module, a first clocked latch module, a second clocked latch module, and a data selector; in the same error path, the clock sampling signal received by the comparator module is the same as the clock sampling signal received by the second clocked latch module, and has a 180-degree phase difference from the clock sampling signal received by the first clocked latch module. In this embodiment, the sampling clock signal received by the first error path comparator is the same as the sampling clock signal received by the first data path comparator. The input received by the second error path adder is the same as the input received by the fourth data path adder, and the sampling clock signal received by the second error path comparator is the same as the sampling clock signal received by the fourth data path comparator.

[0059] In this embodiment, the comparator module in each error path includes a first comparator and a second comparator connected in parallel. The latch module in each error path includes a first latch LA and a second latch LB. The first latch LA is connected in series with the first comparator, and the second latch LB is connected in series with the second comparator. The first clocked latch module in each error path includes a first first-level clocked latch L11 and a second first-level clocked latch L12. The first first-level clocked latch L11 is connected in series with the first latch LA, and the second first-level clocked latch L12 is connected in series with the second latch LB. The second clocked latch module includes a first second-level clocked latch L21 and a second second-level clocked latch L22. The first second-level clocked latch L21 is connected in series with the first first-level clocked latch L11, and the second second-level clocked latch L22 is connected in series with the second first-level clocked latch L12.

[0060] In this embodiment, the first error path and the second error path are used to sum the input data, the second tap coefficient, the third tap coefficient, the fourth tap coefficient, and the fifth tap coefficient by using an adder to obtain the sum data, and use a comparator module to sample the sum data output by the adder at a quarter rate based on the adjusted first tap coefficient and the received clock sampling information to obtain the sampled data, and use a latch module, a first-level clock-controlled latch module, and a second-level clock-controlled latch module to perform latch conversion processing and delayed sampling processing on the sampled data in sequence. Finally, a data selector MUX selects data according to the data obtained by the delayed sampling and the equalized data output by the data path, so as to obtain the error data ERROR_OUT(1) and ERROR_OUT(2) corresponding to each error path and used to adjust the tap coefficient. In this embodiment, the tap coefficients superimposed at the comparator in the two error paths change from the tap coefficients +T1 superimposed in the original data path to L1 (L1 = +T1 + VREF, VREF is the desired voltage), and -T1 changes to L2 (L1 = -T1 + VREF, VREF is the desired voltage).

[0061] The specific working principle of the decision feedback equalizer in this embodiment is as follows: The received high-speed serial data is respectively input into six paths. Four of them are data paths and two are error paths; each data path has the same structure. The input data is first summed with the feedback signals of the last four taps in an adder, and the summation of the first tap coefficient is performed at the comparator connected after the adder; the tap coefficients superimposed at the two comparators are opposite, one is the positive first tap coefficient +T1, and the other is the negative first tap coefficient -T1; the data selector selects the correct summation result according to the output of the previous data path. The data output by the data selector is converted into non-return-to-zero code data through a latch, and the non-return-to-zero code data passes through two clock-controlled latches to obtain the delayed data. By reasonably combining the delayed data of the four paths, the feedback signals of the last four taps can be obtained. The input data first realizes the summation of the last four taps at the adder, and then realizes the summation of the first tap coefficient at the comparator, so as to obtain the quarter-rate data after decision.

[0062] At the error path, the input data first realizes the summation of the last four taps at the adder and then superimposes the first tap coefficient at the comparator. Since the error path needs to complete the comparison between the equalized data and the desired data, the coefficients superimposed at the comparator need to change. The original +T1 becomes L1 (L1 = +T1 + VREF, where VREF is the desired voltage), and -T1 becomes L2 (L1 = -T1 + VREF, where VREF is the desired voltage). After the delay of two levels of clocked latches, according to the data in the data path, the correct error signal is selected in the data selector module. According to the error signal, the size of the decision feedback equalizer feedback coefficient / tap coefficient can be adjusted in real time, so as to complete the function of adaptive decision feedback, and thus achieve the purpose of compensating for channel attenuation and overcoming inter-symbol interference.

[0063] Specifically, the adder in the data path and the adder in the error path in this embodiment can be as Figure 3 shown. The gates of the NMOS input pair transistors M1 and M2 are connected to the differential input signals VTN_P and VTN_N. The drains of M1 and M2 are respectively connected to the load resistors RD1 and RD2. The source negative feedback resistor RS is connected between the sources of M1 and M2. The adder tail current sources I sum_p 、I sum_n are connected to the sources of the input pair transistors M1 and M2. The gates of the NMOS input pair transistors M3 and M4 are connected to the differential input signals T2_P and T2_N. The drains of M3 and M4 are respectively connected to the load resistors RD2 and RD1. The controllable current source I tap2 is connected to the sources of the input pair transistors M3 and M4. The gates of the NMOS input pair transistors M3 and M4 are connected to the differential input signals T3_P and T3_N. The drains of M5 and M6 are respectively connected to the load resistors RD2 and RD1. The controllable current source I tap3 is connected to the sources of the input pair transistors M5 and M6. The gates of the NMOS input pair transistors M7 and M8 are connected to the differential input signals T4_P and T4_N. The drains of M7 and M8 are respectively connected to the load resistors RD2 and RD1. The controllable current source I tap4 is connected to the sources of the input pair transistors M7 and M8. The gates of the NMOS input pair transistors M9 and M10 are connected to the differential input signals T5_P and T5_N. The drains of M9 and M10 are respectively connected to the load resistors RD2 and RD1. The controllable current source I tap5Connected to the sources of the input differential pair transistors M9 and M10. Five differential pairs share a pair of resistor loads. A source negative feedback resistor array is added at the input differential pair transistors to form a variable gain amplifier. On the one hand, it can adjust the amplitude of the input signal. On the other hand, due to the negative feedback effect, the linearity is improved. Among them, VIN_P and VIN_N are the first differential input terminals. T2_P, T2_N are the second differential input terminals, T3_P, T3_N are the third differential input terminals, T4_P, T4_N are the fourth differential input terminals, T5_P, T5_N are the fifth differential input terminals, and VIN_P and VIN_N are the first differential output terminals; the first differential input terminal of the adder is used to receive the data that has undergone channel attenuation, the second differential input terminal is used to input the data of the second tap fed back, the third differential input terminal is used to input the data of the third tap fed back, the fourth differential input terminal is used to input the data of the fourth tap fed back, and the fifth differential input terminal is used to input the data of the fifth tap fed back; the feedback tap coefficients TAP2, TAP3, TAP4, TAP5 are controlled by four tail current sources I tap2 、I tap3 、I tap4 、I tap5 ; the four tail current sources I yap2 、I yap3 、I yap4 、I tap5 are controlled by the external voltages V post2 、V post3 、V post4 、V post5 .

[0064] The output voltage V sum of the decision feedback equalization adder can be expressed by the following formula:

[0065] V sum = (G m V in - I tap )R D

[0066] where G m is the equivalent input transconductance of the entire adder circuit, V in is the input differential voltage difference of the first differential pair (VIN_P - VIN_N), I tap is ((T2_P - T2_N)I tap2 + (T2_P - T2_N)I tap2 + T3_P - T3_NItap3 + T4_P - T4_NItap4 + T5_P - T5_NItap5, and RD is the load resistor.

[0067] In the specific implementation process of this embodiment, the comparators in the data path and the comparators in the error path can adopt a standard two-stage structure, that is, each of the first comparator and the second comparator is a two-stage comparator. Specifically, it can be as Figure 4 shown. M1, M2, M3, M4, M5, M6, and M7 constitute the pre-amplification circuit of the first stage of the comparator. The gates of the NMOS input pair transistors M1 and M2 are connected to the differential input signals INP and INN, and the gates of the NMOS input pair transistors M3 and M4 are connected to the differential input signals VTN and VTP. The gate of the NMOS transistor M7 is connected to the input clock signal CK, the source is grounded, and the drain is connected to the sources of the input pair transistors M1, M2, M3, and M4. The gates of the PMOS transistors M5 and M6 are connected to the input clock signal CK. The drain of M5 is connected to the drains of M1 and M3, and the source of M5 is connected to the level AVDD; the drain of M6 is connected to the drains of M4 and M2, and the source of M6 is connected to the level AVDD; M8, M9, M10, M11, M12, M13, M14, M15, and M16 constitute the latch circuit of the second stage of the comparator. The NMOS transistor M9 is connected to the drains of M1 and M3, and is interconnected with the drain and source of the NMOS transistor M10; the NMOS transistor M12 is connected to the drains of M2 and M4, and is interconnected with the drain and source of the NMOS transistor M11. The drain terminal of the NMOS transistor M8 is connected to the sources of M9, M10, M11, and M12. The drain of the NMOS transistor M10 is connected to the drain of the PMOS transistor M14 and their gates are connected, forming an inverter. The drain of the NMOS transistor M11 is connected to the drain of the PMOS transistor M15 and their gates are connected, forming an inverter. The gates of the NMOS transistor M10 and the PMOS transistor M14 are connected to the drains of the NMOS transistor M11 and the PMOS transistor M15, and the gates of the NMOS transistor M11 and the PMOS transistor M15 are connected to the gates of the NMOS transistor M10 and the PMOS transistor M14. The gates of the NMOS transistor M10 and the PMOS transistor M14 are connected to the output signal VOUT_P, and the gates of the NMOS transistor M15 and the PMOS transistor M11 are connected to the output signal VOUT_N. The gate of the PMOS transistor M13 is connected to the input clock signal CK, and the PMOS transistor M13 is interconnected with the drain and source of the PMOS transistor M14; the gate of the PMOS transistor M16 is connected to the input clock signal CK, and the PMOS transistor M15 is interconnected with the drain and source of the PMOS transistor M16; the sources of M13, M14, M15, and M16 are connected to the level AVDD. Compared with the single-stage comparator, the influence of the kickback noise is reduced, and the comparator offset is lower; at the same time, this type of comparator is a dynamic comparator without static power consumption, meeting the low-power requirements. Among them, INP and INN are connected to the adder outputs VIN_P and VIN_N, and VTP and VTN are the first tap coefficients of the feedback. The pressure difference between them is V post1For regulation. The superposition of the first tap coefficients is performed at the comparator. Compared with adding an additional analog adder in the traditional architecture to perform the superposition of the first tap coefficients, the method of directly performing coefficient superposition at the comparator in this structure reduces the power consumption and complexity of the overall circuit.

[0068] In the specific implementation process of this embodiment, the selector in the data path and the data selector in the error path each include 4 transmission gates. The specific circuit structure can be as Figure 5 shown. The PMOS transistor M1 and the NMOS transistor M2 are connected source-drain to form the transmission gate TG1. The PMOS transistor M3 and the NMOS transistor M4 are connected source-drain to form the transmission gate TG2. The PMOS transistor M5 and the NMOS transistor M6 are connected source-drain to form the transmission gate TG3. The PMOS transistor M7 and the NMOS transistor M8 are connected source-drain to form the transmission gate TG4. The input signal IN_O_P is connected to the transmission gate TG1, and the input signal IN_1_P is connected to the transmission gate TG2. The outputs of the transmission gate TG1 and the transmission gate TG2 are connected. The connected output signal IN_P is connected to the input of the inverter INV1. The output of the inverter INV1 is connected to the input of the inverter INV2. The output signal OUT_P of the reverse INV2. The input signal IN_O_N is connected to the transmission gate TG3, and the input signal IN_1_N is connected to the transmission gate TG4. The outputs of the transmission gate TG3 and the transmission gate TG4 are connected. The connected output signal IN_N is connected to the input of the inverter INV3. The output of the inverter INV3 is connected to the input of the inverter INV4. The output signal OUT_N of the reverse INV4. In the data selector of this embodiment, a data selector circuit is built using 4 transmission gates. When SEL_P is 1 and SEL_N is 0, the IN_1_P and IN_1_N signals are selected. When SEL_P is 0 and SEL_N is 1, the IN_0_P and IN_0_N are selected. The transmission gate is followed by an inverter buffer circuit to ensure the driving ability of the data selector.

[0069] In the specific implementation process of this embodiment, the latches in the data path and the latches in the error path are Figure 6 the symmetric RS latches as shown. S and R are differential input terminals, and Q and Q_b are differential output terminals.

[0070] The gates of the PMOS transistor M1 and the NMOS transistor M2 are connected to the input signal S. The drains of M1 and M2 are connected to form an inverter. At the same time, the drains of M1 and M2 are respectively connected to the gates of the NMOS transistor M6 and the PMOS transistor M9. The drains of the NMOS transistor M6 and the PMOS transistor M5 are connected. The gates of the PMOS transistor M5 and the NMOS transistor M11 are connected to the input signal R;

[0071] The gates of PMOS transistor M3 and NMOS transistor M4 are connected to the input signal R. The drains of M3 and M4 are connected together to form an inverter. At the same time, the drains of M3 and M4 are respectively connected to the gates of NMOS transistor M8 and PMOS transistor M10. The drains of NMOS transistor M8 and PMOS transistor M7 are connected together. The gates of PMOS transistor M7 and NMOS transistor M12 are connected to the input signal S.

[0072] The drain of PMOS transistor M13 is connected to the drain of NMOS transistor M14, which is connected to the output signal Q_b. At the same time, it is also connected to the drains of NMOS transistor M8 and PMOS transistor M7. The source of PMOS transistor M13 is connected to the drain of PMOS transistor M9. The source of NMOS transistor M14 is connected to the drain of NMOS transistor M11.

[0073] The drain of PMOS transistor M15 is connected to the drain of NMOS transistor M16, which is connected to the output signal Q. At the same time, it is also connected to the drains of NMOS transistor M6 and PMOS transistor M5. The source of PMOS transistor M15 is connected to the drain of PMOS transistor M10. The source of NMOS transistor M16 is connected to the drain of NMOS transistor M12.

[0074] The sources of PMOS transistors M1, M5, M9, M10, M7, and M3 are connected to the level AVDD. The sources of NMOS transistors M2, M6, M11, M12, M8, and M4 are grounded.

[0075] Each time the state is converted, only one transistor in each branch is in the conducting state, and the two cross-coupled inverters in the middle can be made very small in size, which reduces the load driving pressure for the output of the previous comparator.

[0076] In the specific implementation process of this embodiment, the clocked latches in the data path and the clocked latches in the error path are clocked latches with a cross-coupled inverter structure, specifically as Figure 7 shown.

[0077] The gates of PMOS transistor M1 and NMOS transistor M2 are connected to the input signal DP. The gate terminal of PMOS transistor M5 is connected to the input clock signal CKB. The gate of NMOS transistor M7 is connected to the input signal CK. The drain terminal of PMOS transistor M5 is connected to the source terminal of PMOS transistor M1. The drain terminal of NMOS transistor M7 is connected to the source terminal of NMOS transistor M2.

[0078] The gates of PMOS transistor M3 and NMOS transistor M4 are connected to the input signal DN. The gate terminal of PMOS transistor M6 is connected to the input clock signal CKB. The gate of NMOS transistor M8 is connected to the input signal CK. The drain terminal of PMOS transistor M6 is connected to the source terminal of PMOS transistor M3. The drain terminal of NMOS transistor M8 is connected to the source terminal of NMOS transistor M4.

[0079] The output of the inverter INV1 in the circuit structure is connected to the input of INV2, and the output signals QP, the drain of PMOS transistor M3, and the drain of NMOS transistor M4; the output of the inverter INV2 is connected to the input of INV1, and the output signals QN, the drain of PMOS transistor M1, and the drain of NMOS transistor M2.

[0080] The sources of PMOS transistor M5 and PMOS transistor M6 are connected to AVDD, and the sources of NMOS transistor M7 and NMOS transistor M8 are grounded.

[0081] The first differential input terminals of the clocked latch are DP and DN, and the second differential input terminals CK and CKB of the clocked latch are used to input differential clock signals; the first differential output terminal of the clocked latch is used to output quarter-rate output data after one-stage delay equalization.

[0082] By using the decision feedback equalizer in the above embodiments of the present application to perform equalization processing on the input data, the Figure 8 shown timing waveform diagram can be obtained. Among them, DATA_IN is the input data signal, and CLK_00 and CLK_90 are quarter-rate sampling clocks; after the input data signal is sampled by the quarter-rate sampling clocks CLK_00 and CLK_90 in the decision feedback equalizer, four paths of data are obtained; and because each path has a comparator and two clocked latches to introduce delay to the input data, the output data will have a delay of three UIs compared to the input data DATA_IN.

[0083] Further as Figure 9 shown, the first row of data is the input ideal data, the second row of data is the data after channel attenuation, and by comparing the data in the third, fourth, fifth, and sixth rows with the input ideal data, it can be seen that the decision feedback equalizer in the present application can recover the correct codeword from the data after channel attenuation, demonstrating that the decision feedback equalizer in the present application has a high equalization effect.

[0084] Another embodiment of the present application provides a receiver, as Figure 10 shown. The receiver in this embodiment includes a decision feedback equalizer DFE, a first multiplexer (DEMUX), a second multiplexer (DEMUX), and an adaptive logic module. The decision feedback equalizer in this embodiment is the decision feedback equalizer in any of the above embodiments. Both the first multiplexer and the second multiplexer are 1:4 multiplexers.

[0085] In this embodiment, the first multiplexer is electrically connected to the output terminals of each data path respectively, and is used to receive the equalized data (DATA1, DATA2, DATA3, and DATA4) output by the 4 data paths of the decision feedback equalizer, so as to decompose each equalized data to obtain the decomposed equalized data.

[0086] The second multiplexer is electrically connected to the output ends of the decision feedback equalizer and each error path respectively, and is used to receive the error data (ERROR1 and ERROR2) output by each error path, so as to decompose each error data to obtain the decomposed error data;

[0087] The input ends of the adaptive logic module are electrically connected to the output end of the first multiplexer and the output end of the second multiplexer respectively, and are used to receive the decomposed equalization data (DATA1, DATA2, DATA3, and DATA4) and the decomposed error data (ERROR1 and ERROR2), and generate 5 external control voltages based on the decomposed equalization data and the decomposed error data, so as to adaptively adjust the magnitudes of each tap coefficient based on each external control voltage. That is, the decision feedback equalizer receives the data signal input from the outside and attenuated by the channel, and operates normally under the control of 5 external control voltages V post1 、V post2 、V post3 、V podt4 、V post5 to realize the function of decision feedback, and output 4 1 / 4-rate data signals and 2 1 / 4-rate error signals. The 1:4 DEMUX decomposes these 4 1 / 4-rate data into 16 equalization data after the decision feedback equalizer; meanwhile, 2 error data ERROR1 and ERROR2 are generated in the decision feedback equalizer, and are decomposed into 8 error data through the 1:4 DEMUX; the adaptive logic module generates 5 external control voltages V post1 、V post2 、V post3 、V post4 、V post5 from the 16 equalization data and 8 error data to adaptively adjust the magnitudes of the tap coefficients of the decision feedback equalizer.

[0088] In this embodiment, by adopting the quarter-rate pre-decision feedback equalizer architecture, different from the classical full-rate and half-rate architecture decision feedback equalizers, the quarter-rate architecture further reduces the pressure on the clock part; at the same time, in order to meet the requirements of high equalization ability, this application designs a pre-decision architecture, and transfers the superposition of the first feedback coefficient to the comparator, reducing the load pressure of the adder, and further reducing the limit of the number of feedback taps of the entire decision feedback equalizer; this application takes advantage of the quarter-rate pre-decision feedback equalizer architecture to optimize the adder structure, expands the number of feedback taps to 5, realizes the quarter-rate five-tap adaptive decision feedback equalizer structure, and meets the requirements of high speed and high equalization ability.

[0089] Meanwhile, in the entire quarter-rate decision feedback equalizer system, two error paths are added in this application, and a comparator is used to compare the equalized data with the expected data. According to the error signal output by the error path, the equalization situation of the entire decision feedback equalizer is fed back in real time, and then the tap coefficients of the entire decision feedback equalizer are adjusted in real time, meeting the requirements of adaptive decision feedback equalization.

[0090] The above embodiments are only exemplary embodiments of this application and are not used to limit this application. The protection scope of this application is defined by the claims. Those skilled in the art can make various modifications or equivalent replacements to this application within the essence and protection scope of this application, and such modifications or equivalent replacements should also be regarded as falling within the protection scope of this application.

Claims

1. A decision feedback equalizer, characterized in that, Comprising: Four data paths with the same structure, each of the data paths respectively including an adder, a comparator module, a data selector, a latch, a first clocked latch, and a second clocked latch that are electrically connected in sequence; The adders in each of the data paths respectively include 5 differential input terminals, which are respectively used for receiving input data, a second tap coefficient, a third tap coefficient, a fourth tap coefficient, and a fifth tap coefficient. The differential input terminals for receiving input data in each of the adders are also respectively electrically connected to the output terminal of the second clocked latch of the previous data path, the output terminal of the latch of the next data path, and the output terminal of the data selector of another data path, and are used for performing data addition processing based on the received input data, second tap coefficient, third tap coefficient, fourth tap coefficient, fifth tap coefficient, the output data of the second clocked latch of the previous data path, the output data of the latch of the next data path, and the output data of the data selector of another data path to obtain added data; The comparator modules in each of the data paths are used for performing sampling processing on the added data output by the adder in the same data path at a quarter rate based on the corresponding first sampling clock signal and the first tap coefficient to obtain sampled data; the first sampling clock signals corresponding to the comparators in two adjacent data paths differ by 90 degrees; The data selectors in each of the data paths are also electrically connected to the output terminal of the data selector in the previous data path, and are used for performing selection processing on the sampled data output by the comparator module in the same data path and the selected data output by the data selector in the previous data path to obtain the selected data corresponding to the current data selector; The latches in each of the data paths are used for performing latch conversion processing on the selected data output by the data selector in the same data path to obtain non-return-to-zero latch data; The first clocked latches in each of the data paths are used for performing delayed sampling processing on the latch data output by the latch in the same data path based on the second sampling clock signal to obtain first-level latch data; the second sampling clock signal in the same data path differs from the first sampling clock signal by 180 degrees; The second clocked latches in each of the data paths are used for performing delayed sampling processing on the first-level latch data output by the first-level latch in the same data path based on the third sampling clock signal to obtain second-level latch data, so as to obtain equalization data corresponding to each data path; the second sampling clock signal and the third sampling clock signal in the same data path have the same phase.

2. The decision feedback equalizer according to claim 1, wherein, The decision feedback equalizer further includes a first error path and a second error path; The first error path and the second error path have the same structure, and respectively include an adder, a comparator module, a latch module, a first clocked latch module, a second clocked latch module, and a data selector that are electrically connected in sequence; in the same error path, the clock sampling signal received by the comparator module is the same as the clock sampling signal received by the second clocked latch module, and differs from the clock sampling signal received by the first clocked latch module by 180 degrees; The first error path and the second error path are used to sum the input data, the second tap coefficient, the third tap coefficient, the fourth tap coefficient, and the fifth tap coefficient by using an adder to obtain sum data, and use a comparator module to sample the sum data output by the adder at a quarter rate based on the adjusted first tap coefficient and the received clock sampling information to obtain sampled data, and use a latch module, a first clocked latch module, and a second clocked latch module to perform latch conversion processing and delayed sampling processing on the sampled data in sequence to obtain error data corresponding to each error path and used to adjust the tap coefficient.

3. The decision feedback equalizer according to claim 2, wherein Each of the comparator modules includes a first comparator and a second comparator connected in parallel; The latch module includes a first latch and a second latch. The first latch is connected in series with the first comparator, and the second latch is connected in series with the second comparator; The first clocked latch module includes a first first-level clocked latch and a second first-level clocked latch. The first first-level clocked latch is connected in series with the first latch, and the second first-level clocked latch is connected in series with the second latch; The second clocked latch module includes a first second-level clocked latch and a second second-level clocked latch. The first second-level clocked latch is connected in series with the first first-level clocked latch, and the second second-level clocked latch is connected in series with the second first-level clocked latch.

4. The decision feedback equalizer according to claim 1, characterized in that, The comparator modules in each of the data paths respectively include a first comparator and a second comparator connected in parallel; The input ends of the first comparator and the second comparator in the same comparator module are respectively electrically connected to the output end of the adder in the same data path, and are used to receive the output data of the adder in the same data path and the required first tap coefficient; the signs of the first tap coefficients received by the two comparators in the same comparator module are opposite.

5. The decision feedback equalizer according to claim 3 or 4, characterized in that, Each of the first comparators and the second comparators is a two-stage comparator.

6. The decision feedback equalizer according to claim 1 or 3, characterized in that, Each of the data selectors includes 4 transmission gates.

7. The decision feedback equalizer according to claim 1 or 3, characterized in that, Each of the latches is a symmetric RS latch.

8. The decision feedback equalizer according to claim 1 or 3, characterized in that, Each of the clocked latches is a clocked latch with a cross-coupled inverter structure.

9. A receiver, characterized in that, Comprising the decision feedback equalizer according to any one of claims 1-8, further comprising: a first multiplexer, a second multiplexer, and an adaptive logic module; The first multiplexer is respectively electrically connected to the output ends of each data path, and is used to receive the equalized data output by each data path of the decision feedback equalizer to decompose the equalized data to obtain decomposed equalized data; The second multiplexer is respectively electrically connected to the decision feedback equalizer and the output ends of each error path, and is used to receive the error data output by each error path to decompose the error data to obtain decomposed error data; The input ends of the adaptive logic module are electrically connected to the output end of the first multiplexer and the output end of the second multiplexer respectively, and are used for receiving the decomposed equalization data and the decomposed error data, and generating five external control voltages based on the decomposed equalization data and the decomposed error data, so as to adaptively adjust the magnitudes of the respective tap coefficients based on the respective external control voltages.

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