Monolithic integrated binocular 3D imaging chip structure and method

Abstract

The invention provides a monolithic integrated binocular 3D imaging chip structure. The monolithic integrated binocular 3D imaging chip structure comprises an image sensor chip, a first lens and a second lens, the image sensor chip comprises any one of a CMOS (Complementary Metal Oxide Semiconductor) image sensor, a CCD (Charge Coupled Device) image sensor, an organic matter image sensor, a quantum dot image sensor and an infrared image sensor; the image sensor control circuit is arranged between the first pixel array and the second pixel array, or is arranged in an area with a preset distance on the periphery of the first pixel array or the second pixel array, or the image sensor control circuit is arranged below the pixel array by adopting a BSI stacking process. A binocular 3D imaging function is realized by utilizing one chip, the cost is low, auxiliary equipment such as a specific light source is not needed, the device is simple, the area is small, the power consumption is low, stereo imaging is carried out by utilizing a disparity map principle, two images are simultaneously acquired, and the accuracy is high.

Description

Technical Field

[0001] The present invention relates to the field of 3D imaging technology, and particularly to a monolithic integrated binocular 3D imaging chip structure and method. Background Art

[0002] Currently, 3D imaging methods are mainly divided into monocular 3D imaging, binocular 3D imaging, time-of-flight (ToF) 3D imaging, structured light 3D imaging, etc. Monocular 3D imaging uses one camera, that is, only one image sensor chip is needed. Monocular 3D imaging is small in size, but it cannot directly obtain a depth map, so it poses high requirements on algorithms. This requires the support of powerful data processing capabilities, increasing the cost and power consumption of the chip.

[0003] After binocular 3D imaging directly measures distance using the principle of disparity map, three-dimensional image information can be obtained. Its disadvantage is that it requires an imaging system composed of two imaging chips, that is, a lens is configured on each chip. This device occupies a large area, has high power consumption and high cost, and the parameter consistency between the lenses is poor. The other two commonly used 3D imaging methods use time-of-flight and structured light imaging, and both of these methods require an external specific light source, further increasing the power consumption and area of the product.

[0004] Aiming at the problems that monocular 3D imaging cannot directly obtain a depth map and requires a separate algorithm to obtain depth information, and binocular 3D imaging requires the use of two imaging systems (two image sensor chips), and ToF and structured light imaging require a separate specific light source, the present invention proposes a monolithic integrated binocular 3D imaging chip structure and method. Summary of the Invention

[0005] The present invention provides a monolithic integrated binocular 3D imaging chip structure to solve the technical problem that monocular 3D imaging cannot directly obtain a depth map and requires a separate algorithm to obtain depth information.

[0006] A monolithic integrated binocular 3D imaging chip structure includes: an image sensor chip, a first lens, and a second lens.

[0007] The image sensor chip includes any one of a CMOS image sensor, a CCD image sensor, an organic image sensor, a quantum dot image sensor, and an infrared image sensor;

[0008] The image sensor chip includes a first pixel array, a second pixel array, and an image sensor control circuit.

[0009] The image sensor control circuit is disposed between the first pixel array and the second pixel array, or in a region at a preset distance around the first pixel array or the second pixel array, or, using the BSI stacking process, the image sensor control circuit is disposed below the pixel array.

[0010] The sub-circuit modules of the image sensor control circuit are respectively disposed in the middle between the first pixel array and the second pixel array and in the region at a preset distance around them.

[0011] The sub-circuit modules of the image sensor control circuit include one or a combination of more of a row decoding circuit, a column decoding circuit, a column reading circuit, an AD / DA module, a clock / timing control module, a serial control module, an image processing module (ISP), an image input / output interface module, and a voltage / current biasing module.

[0012] The acquisition, processing, and data transmission of the images of the first pixel array and the second pixel array are controlled by a unified control circuit inside the chip. The two pixel arrays share some or all of the sub-circuit modules in the image sensor control circuit, and the data of the two pixel arrays are fully synchronized inside the chip.

[0013] The first lens and the second lens are on-chip wafer-level lenses or off-chip optical lenses.

[0014] The first lens and the second lens are in the same plane;

[0015] The first lens is perpendicularly placed with respect to the plane where the first pixel array is located, and the line connecting the geometric center of the first lens and the first pixel array is perpendicular to the plane where the pixel array is located;

[0016] The second lens is perpendicularly placed with respect to the plane where the second pixel array is located, and the line connecting the geometric center of the second lens and the second pixel array is perpendicular to the plane where the pixel array is located.

[0017] The first pixel array is composed of m1 columns × n1 rows of pixels, and the second pixel array is composed of m2 columns × n2 rows of pixels (both m and n are positive integers, and m can be equal to n). m1 and m2 can be equal or not equal, and n1 and n2 can be equal or not equal. The pixel array 1 and the pixel array 2 are in the same plane, and the distance d between the first pixel array and the second pixel array is between 0 and 300 mm.

[0018] A method for single-chip 3D imaging using a monolithic integrated binocular 3D imaging chip structure, the steps including:

[0019] S1, the image sensor control circuit controls the pixel array 1 and the pixel array 2 to simultaneously perform image acquisition and processing on the target object, obtaining two images;

[0020] S2. By establishing the correspondence of feature points between these two images, the image points of the same spatial physical point in different images are corresponding to each other, and a disparity image is obtained.

[0021] S3. According to the disparity image, the three-dimensional spatial coordinate information of the target object is obtained, and after calculation and processing, a 3D image is obtained.

[0022] The acquisition, processing, and data transmission of the images of pixel array 1 and pixel array 2 are controlled by a unified control circuit inside the chip. The two pixel arrays are controlled by the same image sensor control circuit module, and the complete synchronization of the data of the two pixel arrays is achieved inside the chip.

[0023] The present invention can achieve the following beneficial effects:

[0024] 1. Using a single chip to implement the binocular 3D imaging function, with low cost, no need for additional auxiliary devices such as special light sources, simple device, small area, and low power consumption.

[0025] 2. Using the principle of disparity map for stereoscopic imaging, two images are collected simultaneously, with high accuracy.

[0026] Other features and advantages of the present invention will be described in the following specification, and part of them will become obvious from the specification or be understood by implementing the present invention. The objectives and other advantages of the present invention can be achieved and obtained through the structures specifically pointed out in the written specification and the drawings.

[0027] Next, through the drawings and embodiments, the technical solutions of the present invention will be further described in detail. Description of the Drawings

[0028] The drawings are used to provide a further understanding of the present invention, and constitute a part of the specification. They are used together with the embodiments of the present invention to explain the present invention, and do not constitute a limitation to the present invention. In the drawings:

[0029] Figure 1 It is a top view of the image sensor structure of the arrangement mode of the control circuit in an embodiment of the present invention.

[0030] Figure 2 It is a top view of the image sensor structure of the arrangement mode of the control circuit in another embodiment of the present invention.

[0031] Figure 3 It is a top view of the image sensor structure of the arrangement mode of the control circuit in another embodiment of the present invention.

[0032] Figure 4 It is a schematic cross-sectional view of the image sensor structure in an embodiment of the present invention.

[0033] Figure 5Schematic cross-sectional view of the image sensor structure in another embodiment of the present invention.

[0034] Figure 6 Schematic cross-sectional view of the image sensor structure in another embodiment of the present invention.

[0035] Figure 7 Schematic diagram of the spatial coordinate calculation process of the single-chip 3D imaging method in the present invention.

[0036] Figures 8 - 13 Schematic diagram of the settings of each module in the image sensor control circuit in the embodiment of the present invention. Detailed implementation manners

[0037] The preferred embodiments of the present invention will be described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are only for the purpose of illustrating and explaining the present invention, and are not intended to limit the present invention.

[0038] As Figures 1 - 6 shown, the embodiment of the present invention provides a monolithic integrated binocular 3D imaging chip structure, including: an image sensor chip, a first lens, and a second lens.

[0039] The working principle of the above technical solution: By setting two lenses, the image information of the target object is synchronously collected from two different perspectives.

[0040] The beneficial effects of the above technical solution: The monolithic integrated binocular 3D imaging chip can achieve three-dimensional imaging efficiently and with low power consumption.

[0041] In one embodiment, the image sensor chip includes any one of a CMOS image sensor, a CCD image sensor, an organic image sensor, a quantum dot image sensor, and an infrared image sensor;

[0042] The image sensor chip includes a first pixel array, a second pixel array, and an image sensor control circuit.

[0043] In this embodiment, the CMOS image sensor is widely used in fields such as low power consumption, high integration, and fast response;

[0044] In this embodiment, the CCD image sensor is widely used in fields that require higher image quality and low noise;

[0045] In this embodiment, the organic image sensor is widely used in fields that require flexibility and good optical response;

[0046] In this embodiment, the quantum dot image sensor is widely used in fields that require high-quality imaging;

[0047] In this embodiment, the infrared image sensor is mainly used for night vision or thermal imaging applications.

[0048] The working principle of the above technical solution: The image sensor includes a first pixel array, a second pixel array, and an image sensor control circuit. The function of this image sensor is to collect image signals and convert them into digital data, and at the same time cooperate with other components to generate a three-dimensional image with depth information.

[0049] The beneficial effects of the above technical solution:

[0050] The most suitable sensor type can be flexibly selected according to actual application requirements. For example, an infrared image sensor can be selected in low-light environments, while a CMOS or quantum dot image sensor can be selected when high-quality color imaging is required.

[0051] Through the binocular system design, combining two pixel arrays, the depth information of the image can be accurately obtained, thereby generating an accurate three-dimensional image. The parallax method can effectively calculate the distance of objects in the scene and achieve high-quality three-dimensional reconstruction.

[0052] Due to the adoption of the image sensor control circuit, the image data can be preprocessed after being collected, optimizing the image quality, reducing noise, and improving the clarity and contrast of the image. This makes the finally output three-dimensional image more real and delicate.

[0053] Integrating multiple functions into a single image sensor reduces the complexity and cost of the hardware, while improving the reliability and efficiency of the system. Through optimized design, the overall manufacturing cost is reduced.

[0054] In one embodiment, the image sensor control circuit is disposed in the middle of the first pixel array and the second pixel array, or in a region at a preset distance around the first pixel array or the second pixel array.

[0055] The working principle of the above technical solution is:

[0056] The image sensor control circuit is disposed between the two pixel arrays and is usually responsible for coordinating the synchronous operation of the two arrays and performing synthesis processing on their acquisition signals. With this layout, the control circuit can more accurately compare and calibrate the signals between the two arrays, especially in a three-dimensional imaging system that requires calculating depth information, effectively ensuring the timing and synchronization of the image.

[0057] In a binocular imaging system, such a layout helps to ensure that the two pixel arrays capture image data simultaneously at the same time, thereby reducing parallax errors and ensuring the accuracy of calculating depth information.

[0058] The image sensor control circuit is arranged in the peripheral area of the pixel array. The control circuit transmits the control signal and the data processing signal to the two arrays respectively through efficient wiring. This layout can generally reduce the crosstalk within the image sensor, reduce the interference of the control circuit on the pixel array, and can more conveniently expand other processing functions (such as data compression, noise suppression, etc.).

[0059] This design helps to reduce the signal noise in the circuit and improve the stability of image data transmission. For a high-density integrated pixel array, the control circuit arranged peripherally can effectively optimize power consumption and heat dissipation.

[0060] The beneficial effects of the above technical solutions are as follows:

[0061] The design of the control circuit located between the pixel arrays or around the arrays can effectively optimize the transmission of the synchronization signal between the two arrays. In a binocular system, the synchronization of the image sensor is very crucial, which affects the accuracy of depth calculation and stereo image synthesis. By reasonably arranging the control circuit, the acquisition time of the two pixel arrays can be ensured to be synchronized, thereby reducing the parallax error and improving the accuracy of three-dimensional imaging.

[0062] Arranging the control circuit in the peripheral area of the pixel array can effectively isolate the signal transmission path, reduce the signal interference inside the circuit, and reduce the influence of the circuit noise in the pixel array. Such a design helps to improve the quality of the image, reduce the image noise, especially in low-light environments, and can optimize the signal processing effect.

[0063] In one embodiment, the sub-circuit modules of the image sensor control circuit include one or more combinations of a row decoding circuit, a column decoding circuit, a column reading circuit, an AD / DA module, a clock / timing control module, a serial control module, an image processing module (ISP), an image input / output interface module, and a voltage / current bias module.

[0064] In this embodiment, the row decoding circuit is responsible for selecting the rows of the image sensor and controlling which row of pixel data is activated and read. It reads the image data of the pixel array row by row according to the timing control signal and sends the image data row signal to the column decoding circuit for further processing.

[0065] In this embodiment, the column decoding circuit works in cooperation with the row decoding circuit, is responsible for selecting columns, and transmits the pixel signals of the selected columns to the column reading circuit. Through the combination of row and column decoding, the image sensor can effectively access all pixel points of each pixel array to realize data reading.

[0066] In this embodiment, the column readout circuit is responsible for converting the analog signals of each pixel column into a signal form suitable for subsequent processing. It is mainly used to read the analog signals generated by the pixel units and perform preliminary gain adjustment.

[0067] In this embodiment, analog-to-digital conversion (ADC) is responsible for converting the output of the pixel array, which is usually an analog signal. The AD module converts these analog signals into digital signals for subsequent digital image processing.

[0068] Digital-to-analog conversion (DAC) is responsible for converting digital signals back into analog signals, such as outputting images to a display device.

[0069] In this embodiment, the clock / timing control module is responsible for the timing control of the entire image sensor, ensuring that each sub-circuit module operates in an accurate timing sequence. It coordinates operations such as row and column decoding, data reading, and AD conversion by controlling the clock frequency of the control signal, guaranteeing the synchronization and stability of the image acquisition process.

[0070] In this embodiment, the serial control module is usually used to communicate with external devices through a serial interface. It is responsible for receiving and decoding external control commands and converting these commands into operation instructions inside the image sensor. This can be used to set parameters such as the working mode, exposure time, and gain of the image sensor.

[0071] In this embodiment, the image processing module (ISP) is responsible for further processing the digital images after AD conversion, including denoising, color correction, exposure adjustment, white balance, sharpening, etc. The ISP module can significantly improve image quality, especially in low-light or high-dynamic range (HDR) environments.

[0072] In this embodiment, the image input / output interface module is responsible for data exchange with external devices (such as image processors, display screens, memories, etc.). It usually provides various standard interfaces (such as MIPI, LVDS, etc.) to transmit the processed image data or receive external control signals.

[0073] In this embodiment, the voltage / current bias module provides stable voltage and current for each circuit inside the image sensor, ensuring the stable operation of the image sensor in different working states. It can provide the required power supply voltage for the pixel array, analog signal processing circuit, timing control circuit, etc.

[0074] The working principle and beneficial effects of the above technical solution are as follows: The image sensor control circuit realizes the acquisition, processing, and output of image data through the collaborative work of multiple sub-circuit modules. Each sub-circuit module plays a specific role in the entire system. By integrating multiple sub-circuit modules into the control circuit of the image sensor, efficient data acquisition, processing, and output are achieved. This design not only improves the accuracy and speed of image acquisition and processing but also significantly enhances the image quality through the image processing module and supports flexible external control and configuration. By optimizing power consumption management and interface design, it can meet the requirements of modern image sensors in terms of low power consumption, high definition, and fast response.

[0075] In one embodiment, the monolithic integrated binocular 3D imaging chip structure adopts the BSI stacking process, and the image sensor control circuit is arranged below the first pixel array and the second pixel array.

[0076] In this embodiment, the BSI stacking process places the photodiodes of the sensor on the back of the image sensor chip, so that light can directly irradiate the photodiodes without the need to penetrate metal wires or other circuit layers. Therefore, the BSI image sensor can achieve higher photosensitivity and better low-light performance.

[0077] In a binocular 3D imaging system, there are usually two image sensors that respectively capture image data from different perspectives. The BSI stacking process can not only improve the image quality of a single sensor but also contribute to enhancing the overall performance of the system.

[0078] The working principle and beneficial effects of the above technical solution are as follows: The monolithic integrated binocular 3D imaging chip realizes efficient image acquisition and processing by adopting the BSI stacking process and arranging the image sensor control circuit below the pixel array. Its working principle relies on the BSI technology to improve the imaging quality in low-light environments, reduce signal loss, and calculate depth information through binocular perspectives to generate high-quality 3D images. The beneficial effects of this technical solution include: improving low-light performance, enhancing image quality and sensitivity, reducing circuit interference, increasing system integration, enhancing 3D imaging accuracy, and optimizing power consumption management.

[0079] In one embodiment, the first lens and the second lens are on-chip wafer-level lenses or off-chip optical lenses.

[0080] In this embodiment, the on-chip wafer-level lens is an optical lens directly integrated with the image sensor chip, which is manufactured together with the image sensor during the production process and is usually completed through mass production technology of micro-optical elements. This lens is directly packaged on the wafer, making the distance between the optical element and the sensor shorter and the optical alignment accuracy higher.

[0081] In a binocular imaging system, the first lens and the second lens are intra-chip wafer-level lenses, which can be closely integrated with the image sensor, reducing the optical path loss between the traditional lens and the sensor and improving the imaging quality and efficiency.

[0082] An off-chip optical lens is a traditional independent lens component, usually assembled into the device separately after the production of the sensor chip. These lenses are usually composed of multiple optical elements, with strong adjustment capabilities and high optical performance, suitable for higher-end imaging requirements.

[0083] In this configuration, the first lens and the second lens are docked with the image sensor through precise optical design. Off-chip optical lenses usually provide more flexible optical characteristics and can handle more complex optical requirements, such as a larger aperture, higher resolution, and higher optical quality.

[0084] The working principle and beneficial effects of the above technical solutions are as follows:

[0085] By adopting intra-chip wafer-level lenses or off-chip optical lenses in the binocular imaging system, high-integration and high-quality image acquisition are achieved. In terms of the working principle, the intra-chip wafer-level lens is directly integrated with the image sensor, which can reduce the optical alignment error and improve the system performance; while the off-chip optical lens provides stronger optical flexibility and higher imaging quality.

[0086] Using on-chip wafer-level lenses, lenses with different pixel arrays are manufactured simultaneously. On the basis of overcoming the size and consistency problems of traditional optical lenses, they also have the advantages of the heat resistance and high refractive index of glass lenses.

[0087] In one embodiment, the acquisition, processing, and data transmission of the first pixel array and the second pixel array images are controlled by a unified control circuit inside the chip. The two pixel arrays share some or all of the sub-circuit modules in the image sensor control circuit, and complete synchronization of the data of the two pixel arrays is achieved inside the chip.

[0088] The working principle and beneficial effects of the above technical solutions are as follows:

[0089] The two pixel arrays share some or all of the sub-circuit modules in the image sensor control circuit, avoiding the need to design a complete set of control circuits for each pixel array separately, reducing the area and complexity of the chip, and thus reducing the manufacturing cost of the chip.

[0090] Complete synchronization of the data of the two pixel arrays is achieved inside the chip, which is very important for some application scenarios that require simultaneous processing of the data of the two pixel arrays. For example, in applications such as stereovision and multispectral imaging, the synchronization of the data can ensure the accuracy and consistency of the images and improve the accuracy and reliability of subsequent data processing.

[0091] The shared sub - circuit module enables the processing of data from two pixel arrays to be carried out simultaneously, reducing the processing time and improving the processing efficiency of the entire system. Moreover, the unified control circuit can more efficiently coordinate various links such as image acquisition, processing, and data transmission, further enhancing the operating efficiency of the system.

[0092] Controlled by the unified control circuit inside the chip, the interfaces and coordination work between various parts of the system are reduced, simplifying the overall design of the system and reducing the design difficulty and risk.

[0093] In one embodiment, the first lens and the second lens are located in the same plane, and the diameter, thickness, focal length, aperture number, relative aperture, spherical aberration, distortion, and transmittance of the first lens and the second lens are all the same;

[0094] The first lens is perpendicularly placed with respect to the plane where the first pixel array is located, and the line connecting the geometric center of the first lens and the first pixel array is perpendicular to the plane where the pixel array is located;

[0095] The second lens is perpendicularly placed with respect to the plane where the second pixel array is located, and the line connecting the geometric center of the second lens and the second pixel array is perpendicular to the plane where the pixel array is located;

[0096] The first pixel array is composed of m1 columns × n1 rows of pixels, and the second pixel array is composed of m2 columns × n2 rows of pixels (both m and n are positive integers, and m can be equal to n). m1 and m2 can be equal or not equal, and n1 and n2 can be equal or not equal. The pixel array 1 and the pixel array 2 are located in the same plane, and the distance d between the first pixel array and the second pixel array is between 0 and 300 mm.

[0097] The working principle and beneficial effects of the above - mentioned technical solution are as follows: By designing the first lens and the second lens to have the same optical parameters and be perpendicularly placed with respect to the corresponding pixel arrays, the high precision and high consistency of the imaging system are ensured. Combining the working principle of binocular imaging, the system can obtain depth information through the images with different perspectives captured by the two lenses and achieve efficient stereoscopic vision through parallax calculation.

[0098] As Figure 8 shown, in one embodiment, the first pixel array and the second pixel array are in the same plane. When the first pixel array and the second pixel array are horizontally placed, in the image sensor control circuit, the first pixel array and the second pixel array are controlled by the same row decoding circuit. The first pixel array corresponds to columnADC1 and SRAM1, the second pixel array corresponds to columnADC2 and SRAM2, and the first pixel array and the second pixel array share the common AMP, AD conversion module, timing control module, I2C bus module, image processing module, and output interface.

[0099] When the first pixel array and the second pixel array acquire images, they are controlled by the same row decoding circuit. The image signals in the two pixel arrays are acquired simultaneously. After being subjected to analog-to-digital conversion by the corresponding column ADCs, they are stored in the corresponding SRAMs. The size of the SRAM is equal to the number of columns of the pixel array. The image data stored in SRAM1 and SRAM2 are sequentially output to the AMP, and then the data is processed and output via the AMP, the AD conversion module, the image processing module, and the output interface.

[0100] As Figure 9 shown, in one embodiment, when the first pixel array and the second pixel array are horizontally placed, in the image sensor control circuit, the first pixel array and the second pixel array are controlled by the same row decoding circuit. The first pixel array corresponds to column ADC1, and the second pixel array corresponds to column ADC2. The first pixel array and the second pixel array use a common SRAM, AMP, AD conversion module, timing control module, I2C bus module, image processing module, and output interface.

[0101] When the first pixel array and the second pixel array acquire images, they are controlled by the same row decoding circuit. The image signals in the two pixel arrays are acquired simultaneously. After being subjected to analog-to-digital conversion by the corresponding column ADCs, they are sequentially stored in the same SRAM. The size of the SRAM is equal to the number of columns of the pixel array. The data stored in the SRAM is sequentially output to the AMP, and then the data is processed and output via the AMP, the AD conversion module, the image processing module, and the output interface.

[0102] As Figure 10 shown, in one embodiment, when the first pixel array and the second pixel array are horizontally placed, in the image sensor control circuit, the first pixel array and the second pixel array are controlled by the same row decoding circuit. The first pixel array corresponds to column ADC1, SRAM1, AMP1, AD conversion module 1, image processing module 1, and output interface 1. The second pixel array corresponds to column ADC2, SRAM2, AMP2, AD conversion module 2, image processing module 2, and output interface 2. The first pixel array and the second pixel array use a common timing control module and I2C bus module.

[0103] When the first pixel array and the second pixel array collect images, they are controlled by the same row decoding circuit. The image signals in the two pixel arrays are collected simultaneously. After being converted by the corresponding column ADCs, they are stored in the corresponding SRAMs. The size of the SRAM is equal to the number of columns of the corresponding pixel array. The image data stored in SRAM1 and SRAM2 are sequentially output to the corresponding AMps, and the data are processed and output by the AMps, AD conversion modules, image processing modules, and output interfaces corresponding to each array. The image information of the first pixel array and the second pixel array can be converted, processed, and output simultaneously.

[0104] As Figure 11 shown, in one embodiment, when the first pixel array and the second pixel array are vertically placed, in the image sensor control circuit, the first pixel array and the second pixel array are controlled by the same row decoding circuit. The first pixel array and the second pixel array use a common column ADC, SRAM, AMP, AD conversion module, timing control module, I2C bus module, image processing module, and output interface.

[0105] When the first pixel array and the second pixel array collect images, they are controlled by the same row decoding circuit. The image signals in the two pixel arrays are collected sequentially. After being converted by the column ADCs, they are stored in the SRAM. The size of the SRAM is equal to the number of columns of the corresponding pixel array. The image data of the first pixel array and the second pixel array stored in the SRAM are sequentially output to the AMP, and then the data are processed and output by the AD conversion module, image processing module, and output interface.

[0106] As Figure 12 shown, in one embodiment, when the first pixel array and the second pixel array are vertically placed, in the image sensor control circuit, the first pixel array and the second pixel array are controlled by the same row decoding circuit. The first pixel array corresponds to column ADC1, the second pixel array corresponds to column ADC2, and the first pixel array and the second pixel array use a common SRAM, AMP, AD conversion module, timing control module, I2C bus module, image processing module, and output interface.

[0107] When the first pixel array and the second pixel array collect images, they are controlled by the same row decoding circuit. The image signals in the two pixel arrays are collected simultaneously. After being converted by the corresponding column ADCs, they are stored in the same SRAM. The size of the SRAM is equal to the sum of the number of columns of the first pixel array and the second pixel array. The image data of the first pixel array and the second pixel array stored in the SRAM are sequentially output to the AMP, and then the data are processed and output by the AD conversion module, image processing module, and output interface.

[0108] As Figure 13As shown, in one embodiment, when the first pixel array and the second pixel array are vertically placed, in the image sensor control circuit, the first pixel array and the second pixel array are controlled by the same row decoding circuit. The first pixel array corresponds to column ADC1, SRAM1, AMP1, AD conversion module 1, image processing module 1, and output interface 1, and the second pixel array corresponds to column ADC2, SRAM2, AMP2, AD conversion module 2, image processing module 2, and output interface 2. The first pixel array and the second pixel array use a common timing control module and I2C bus module.

[0109] When the first pixel array and the second pixel array acquire images, they are controlled by the same row decoding circuit. The image signals in the two pixel arrays are acquired simultaneously. After being converted by the corresponding column ADCs, they are stored in the corresponding SRAMs. The size of the SRAM is equal to the number of columns of the corresponding pixel array. The image data stored in SRAM1 and SRAM2 are sequentially output to the corresponding AMps, and the data are processed and output by the AMPs, AD conversion modules, image processing modules, and output interfaces corresponding to each array. The image information of the first pixel array and the second pixel array can be acquired, converted, processed, and output simultaneously.

[0110] In one embodiment, a method for single-chip 3D imaging using a monolithic integrated binocular 3D imaging chip structure includes the following steps:

[0111] S1, the image sensor control circuit controls the first pixel array and the second pixel array to simultaneously acquire and process images of the target object to obtain two images;

[0112] S2, by establishing the corresponding relationship of feature points between the two images, the image points of the same spatial physical point in different images are corresponding to obtain a disparity image;

[0113] S3, obtain the three-dimensional spatial coordinate information of the target object according to the disparity image, and obtain a 3D image after calculation and processing.

[0114] The working principle of the above technical solution is: As Figure 7 shown, point P is a point in the target object in space, P1 and P2 are the imaging points of point P on the left and right image planes, Z is the depth of point P in the target object. f is the focal length, O L and O R are the optical centers of the left and right pixel arrays, that is, the geometric centers of the left and right pixel arrays. The distance between O L and O R is the disparity B. The optical axes of the left and right pixel arrays are parallel. X L and X R are the distances of the two imaging points from the left edge of the image on the left and right image planes.

[0115] The relational expression between the parallax B and the depth Z of point P is as follows:

[0116]

[0117] It is derived that:

[0118]

[0119] According to the above formula and two parallax images, the three-dimensional coordinate information of any point in the image can be obtained, and a 3D image is obtained after calculation and processing.

[0120] The beneficial effects of the above technical solution are as follows:

[0121] Through the monolithic integrated binocular 3D imaging chip structure, efficient, compact and accurate 3D imaging is realized. This method uses two pixel arrays to simultaneously collect images of the target object, and obtains the three-dimensional spatial coordinates of the target object through parallax calculation, thereby generating a 3D image.

[0122] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalent technologies, the present invention is also intended to include these changes and modifications.

Claims

1. A monolithic integrated binocular 3D imaging chip structure, characterized in that, Comprising: An image sensor chip, a first lens, and a second lens.

2. The monolithic integrated binocular 3D imaging chip structure according to claim 1, characterized in that, The image sensor chip includes any one of a CMOS image sensor, a CCD image sensor, an organic image sensor, a quantum dot image sensor, and an infrared image sensor.

3. The monolithic integrated binocular 3D imaging chip structure according to claim 1, wherein The image sensor chip includes a first pixel array, a second pixel array, and an image sensor control circuit.

4. The monolithic integrated binocular 3D imaging chip structure according to claim 3, characterized in that, The image sensor control circuit is disposed between the first pixel array and the second pixel array, or in a region at a preset distance around the first pixel array or the second pixel array, or, using a BSI stacking process, the image sensor control circuit is disposed below the pixel array.

5. The monolithic integrated binocular 3D imaging chip structure according to claim 3, characterized in that The image sensor control circuit includes a plurality of sub-circuit modules, which are respectively disposed between the first pixel array and the second pixel array and in a region at a preset distance around them.

6. The monolithic integrated binocular 3D imaging chip structure according to claim 5, characterized in that, The sub-circuit modules of the image sensor control circuit include one or a combination of a row decoding circuit, a column decoding circuit, a column reading circuit, an AD / DA module, a clock / timing control module, a serial control module, an image processing module, an image input / output interface module, and a voltage / current biasing module.

7. The monolithic integrated binocular 3D imaging chip structure according to claim 6, wherein The first lens and the second lens respectively include: an on-chip wafer-level lens or an off-chip optical lens.

8. The monolithic integrated binocular 3D imaging chip structure according to claim 6, wherein The acquisition, processing, and data transmission of the images of the first pixel array and the second pixel array are controlled by a unified control circuit inside the chip. The two pixel arrays share some or all of the sub-circuit modules in the image sensor control circuit to achieve complete synchronization of the data of the two pixel arrays inside the chip.

9. The monolithic integrated binocular 3D imaging chip structure according to claim 5, characterized in that, The first lens and the second lens are located in the same plane; The first lens is vertically placed with respect to the plane where the first pixel array is located, and the line connecting the geometric center of the first lens and the first pixel array is perpendicular to the plane where the pixel array is located; The second lens is vertically placed with respect to the plane where the second pixel array is located, and the line connecting the geometric center of the second lens and the second pixel array is perpendicular to the plane where the pixel array is located; The first pixel array and the second pixel array are located in the same plane, and the distance between the first pixel array and the second pixel array is between 0 and 300 mm.

10. A method for single-chip 3D imaging using a monolithic integrated binocular 3D imaging chip structure, characterized in that the steps Comprising: S1, the image sensor control circuit controls the first pixel array and the second pixel array to simultaneously collect and process images of the target object to obtain two images; S2, by establishing a correspondence relationship of feature points between these two images, the image points of the same spatial physical point in different images are corresponded to obtain a disparity image; S3, according to the disparity image, the three-dimensional spatial coordinate information of the target object is obtained, and after calculation and processing, a 3D image is obtained.

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