Semiconductor structure and preparation method thereof, storage system and electronic equipment

Abstract

The invention provides a semiconductor structure and a preparation method thereof, a storage system and electronic equipment, relates to the technical field of semiconductor chips, and aims to solve the problem that a grid layer connected with an adjacent lead-out structure fails to control a semiconductor column due to short circuit of the adjacent lead-out structure. The invention provides a semiconductor structure. The semiconductor structure comprises a plurality of semiconductor columns, a plurality of word line groups and a plurality of lead-out structures, wherein the plurality of semiconductor columns are arranged in multiple rows and multiple columns. One word line group is connected with one row of semiconductor columns. The word line group comprises a plurality of gate layers which are sequentially arranged at intervals in the row direction, and one gate layer is connected with a part of semiconductor columns in one row of semiconductor columns. One lead-out structure is connected with one gate layer. The plurality of lead-out structures are arranged in multiple rows and multiple columns, and two adjacent rows of lead-out structures are arranged in a staggered manner in the column direction. Through the arrangement, short circuit caused by connection of two adjacent rows of lead-out structures can be prevented, and the yield of the semiconductor structure can be improved.

Description

Technical Field

[0001] This application relates to the technical field of semiconductor chips, and particularly to a semiconductor structure, a preparation method thereof, a storage system, and an electronic device. Background Art

[0002] Dynamic Random Access Memory (DRAM) is composed of multiple memory cells, and each memory cell is composed of a storage capacitor controlled by a transistor. That is, DRAM is a memory cell with 1 transistor corresponding to 1 storage capacitor (1T1C).

[0003] Among them, the storage capacitor is used to store the charge representing the stored information, and the storage transistor is a switch that controls the inflow and release of the charge of the storage capacitor. The storage transistor is connected to the internal circuit in the memory to receive the control signal of the internal circuit. Summary of the Invention

[0004] Embodiments of this application provide a semiconductor structure, a preparation method thereof, a storage system, and an electronic device.

[0005] Embodiments of this application adopt the following technical solutions:

[0006] On the one hand, a semiconductor structure is provided. The semiconductor structure includes multiple semiconductor columns arranged in multiple rows and columns; the plane where the row direction and the column direction of the multiple semiconductor columns are located is a reference plane, and the length direction of the semiconductor column intersects with the reference plane. Multiple word line groups, one word line group is connected to one row of the semiconductor columns; the word line group includes multiple gate layers sequentially arranged at intervals along the row direction, and one gate layer is connected to a part of the semiconductor columns in one row of the semiconductor columns. Multiple lead-out structures, one lead-out structure is connected to one gate layer; the multiple lead-out structures are arranged in multiple rows and columns, and adjacent two rows of the lead-out structures are staggered in the column direction.

[0007] In some embodiments, the semiconductor structure has an array region and a transition region alternately arranged along the row direction; the multiple semiconductor columns are located in the array region. The semiconductor structure further includes multiple partition structures; two adjacent gate layers in the word line group along the row direction are partitioned by the partition structures in the transition region.

[0008] In some embodiments, the partition structure includes a first extension part and / or a second extension part; the size of the first extension part along the row direction is greater than the size along the column direction, and the size of the second extension part along the row direction is less than the size along the column direction. When the partition structure includes a first extension part and a second extension part, the first extension part and the second extension part are arranged in a cross manner.

[0009] In some embodiments, the word line groups are separated in each of the transition regions.

[0010] In some embodiments, the number of the transition regions is multiple, and the multiple transition regions are divided into a first transition region and a second transition region. Among two adjacent word line groups, one word line group is separated in each of the first transition regions, and the other word line group is separated in each of the second transition regions.

[0011] In some embodiments, the first transition region and the second transition region are alternately arranged along the row direction.

[0012] In some embodiments, for two adjacent gate layers along the column direction, the overlapping length in the row direction is: 40%-60% of the length of the longer gate layer along the row direction.

[0013] In some embodiments, the lead-out structure is located in the transition region.

[0014] In some embodiments, the lead-out structures arranged staggeredly in the column direction are located in different transition regions.

[0015] In some embodiments, the lead-out structure is connected to the middle part or both ends of the gate layer along the row direction.

[0016] In some embodiments, a driving circuit is further included. The driving circuit is connected to the lead-out structure, and the driving circuit is located on one side of the multiple vertical transistors along the target direction, where the target direction is perpendicular to the row direction and the column direction.

[0017] In some embodiments, the gate layer is located on at least one side of the semiconductor column. The semiconductor structure further includes: a capacitor and a bit line. The capacitor is connected to one end of the semiconductor column, and the bit line is connected to the other end of the semiconductor column.

[0018] On the other hand, a method for manufacturing a semiconductor structure is further provided, including: forming a plurality of semiconductor columns and a plurality of word line groups; the plurality of semiconductor columns are arranged in multiple rows and multiple columns; one word line group is connected to one row of the semiconductor columns; each word line group includes a plurality of gate layers sequentially arranged at intervals along the row direction, and one gate layer is connected to a part of the semiconductor columns in one row of the semiconductor columns. Forming a plurality of lead-out structures, one lead-out structure is connected to one gate layer; the plurality of lead-out structures are arranged in multiple rows and multiple columns, and adjacent two rows of the lead-out structures are arranged staggeredly in the column direction.

[0019] In some embodiments, forming a plurality of semiconductor pillars and a plurality of word line groups includes: forming a plurality of first grooves on a semiconductor substrate, the plurality of first grooves all extending along a first direction, and the plurality of first grooves partitioning a plurality of semiconductor walls on the semiconductor substrate. Filling a first insulating material in the plurality of first grooves. Forming a plurality of second grooves on the semiconductor substrate, the plurality of second grooves extending along a second direction, the second direction intersecting with the first direction, and the plurality of second grooves partitioning each semiconductor wall into a plurality of semiconductor pillars; the semiconductor substrate includes an array region and a transition region that alternate along the second direction, and the second grooves penetrate through a plurality of the array regions. Forming gate rings on sidewalls of the second grooves, and filling a remaining space in the second grooves with a second insulating material. Forming a plurality of partition structures in the transition region, the partition structures partitioning the gate rings into a plurality of gate layers, and each row of gate layers in the plurality of gate layers is a word line group.

[0020] In some embodiments, after forming a plurality of partition structures in the transition region, it further includes: forming a lead-out structure located in the transition region, and the lead-out structure is connected to a middle part or two end parts of the gate layer along the second direction.

[0021] In some embodiments, after forming the lead-out structure, it further includes: forming a driving circuit, the driving circuit is connected to the lead-out structure, and the driving circuit is located on one side of the plurality of semiconductor pillars along a target direction, and the target direction is perpendicular to the first direction and the second direction.

[0022] On the other hand, a storage system is also provided. The storage system includes: a semiconductor structure and a controller. The semiconductor structure is the semiconductor structure provided in the above embodiments. The controller is coupled to the semiconductor structure to control the semiconductor structure to store data.

[0023] On the other hand, an electronic device is also provided. The electronic device includes a host and the storage system provided in the above embodiments, and the host and the storage system are coupled. Description of the Drawings

[0024] In order to more clearly illustrate the technical solutions in the present application, the drawings required to be used in some embodiments of the present application will be briefly introduced below. Obviously, the drawings in the following description are only the drawings of some embodiments of the present application, and those of ordinary skill in the art can also obtain other drawings according to these drawings. In addition, the drawings in the following description can be regarded as schematic diagrams, and are not limitations on the actual sizes of the products, the actual processes of the methods, the actual timings of the signals, etc. involved in the embodiments of the present application.

[0025] Figure 1 It is a block diagram of an electronic device according to some embodiments;

[0026] Figure 2 A block diagram of a storage system according to some embodiments;

[0027] Figure 3 A block diagram of a storage system according to other embodiments;

[0028] Figure 4 A three - dimensional structure diagram of a memory according to some embodiments;

[0029] Figure 5 A cross - sectional view of a memory according to some embodiments;

[0030] Figure 6 is Figure 4 A schematic structural diagram of a storage cell in

[0031] Figure 7 is Figure 6 An equivalent circuit diagram of the storage cell shown in

[0032] Figure 8 A top - view of a semiconductor structure according to some embodiments;

[0033] Figure 9 A top - view of a word - line group according to some embodiments;

[0034] Figure 10 is Figure 8 A cross - sectional view along the section line A - A in

[0035] Figure 11 A schematic structural diagram of a partition structure according to some embodiments;

[0036] Figure 12 A top - view of a semiconductor structure according to some embodiments;

[0037] Figure 13 A top - view of a semiconductor structure according to some embodiments;

[0038] Figure 14 A flowchart of a method for manufacturing a semiconductor structure according to some embodiments;

[0039] Figure 15 A schematic structural diagram of a semiconductor structure during manufacturing according to some embodiments;

[0040] Figure 16 is Figure 15 A cross - sectional view along the section line B - B in

[0041] Figure 17 A schematic structural diagram of a semiconductor structure during manufacturing according to some embodiments;

[0042] Figure 18 is Figure 17 a sectional view along section line C-C in

[0043] Figure 19 is Figure 17 a schematic structural view of after removing sacrificial material in the gate trench along section line C-C in

[0044] Figure 20 is Figure 17 a schematic structural view of after expanding the width and depth of the gate trench along section line C-C in

[0045] Figure 21 is Figure 17 a schematic structural view of after filling the bottom dielectric material in the gate trench along section line C-C in

[0046] Figure 22 is Figure 17 a schematic structural view of after forming a gate ring along section line C-C in

[0047] Figure 23 is Figure 17 a schematic structural view of after forming a gate layer along section line C-C in Detailed implementation manners

[0048] Next, the technical solutions in some embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments provided by the present application, all other embodiments obtained by those of ordinary skill in the art shall fall within the protection scope of the present application.

[0049] In the description of the present application, it should be understood that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the accompanying drawings. It is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the present application.

[0050] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is to be construed in an open, inclusive sense, i.e., "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples", etc. are intended to indicate that the specific features, structures, materials or characteristics related to the embodiment or example are included in at least one embodiment or example of the present application. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0051] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the embodiments of the present application, unless otherwise specified, the meaning of "a plurality" is two or more.

[0052] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components have direct physical contact or electrical contact with each other. Also, for example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components have direct physical contact or electrical contact. However, the term "coupled" may also mean that two or more components do not have direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content herein.

[0053] "At least one of A, B, and C" has the same meaning as "at least one of A, B, or C", and both include the following combinations of A, B, and C: only A, only B, only C, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0054] "A and / or B" includes the following three combinations: only A, only B, and the combination of A and B.

[0055] The use of "suitable for" or "configured to" herein means open and inclusive language, which does not exclude a device suitable for or configured to perform additional tasks or steps.

[0056] In addition, the use of "based on" means open and inclusive, because a process, step, calculation or other action "based on" one or more of the said conditions or values may, in practice, be based on additional conditions or values beyond the said ones.

[0057] In the context of the present application, the meanings of "on", "above", and "over" should be interpreted in the broadest possible way such that "on" not only means "directly on something", but also includes "on something" with intermediate features or layers therebetween, and "above" or "over" not only means "above" or "over something", but also includes "above" or "over something" with no intermediate features or layers therebetween (i.e., directly on something).

[0058] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions is exaggerated for clarity. Thus, variations in the shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Accordingly, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing. For example, an etched region shown as rectangular will typically have curved features. Thus, the regions shown in the drawings are schematic in nature, and their shapes are not intended to depict the actual shape of the regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0059] As used herein, the term "substrate" refers to a material on which subsequent material layers can be added. The substrate itself can be patterned. The material added on the substrate can be patterned or can remain unpatterned. In addition, the substrate can include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of a non-conductive material such as glass, plastic, or a sapphire wafer.

[0060] Some embodiments of the present application provide an electronic device. Figure 1 A block diagram of the electronic device provided by some embodiments of the present application. As Figure 1 shown, the electronic device 1 includes a storage system 2 and a circuit board 3. Among them, the storage system 2 is electrically connected to the circuit board 3. In addition, the electronic device 1 may further include at least one of a central processing unit CPU (Central Processing Unit), a cache, etc.

[0061] Exemplarily, the electronic device 1 can be any one of a mobile phone, a desktop computer, a tablet computer, a laptop computer, a server, a vehicle-mounted device, a wearable device (such as a smart watch, a smart bracelet, smart glasses, etc.), a mobile power supply, a game console, a digital multimedia player, etc.

[0062] Some embodiments of the present application further provide a storage system 2. The storage system 2 can be applied to the above-mentioned electronic device 1. Of course, the storage system 2 can also be applied to other electronic devices 1, and the present application does not limit this.

[0063] Figure 2 A block diagram of the storage system 2 provided for some embodiments of the present application. As Figure 2 shown, the storage system 2 includes a controller 4 and a memory 5. Among them, the controller 4 is coupled to the memory 5 and is configured to control the memory 5 to store data.

[0064] Among them, the storage system 2 can be integrated into various types of storage devices. For example, it can be included in the same package (for example, Universal Flash Storage (UFS) package or Embedded Multi Media Card (eMMC) package). That is to say, the storage system 2 can be applied to and packaged into different types of electronic products, such as mobile phones (such as cell phones), desktop computers, tablet computers, laptop computers, servers, in-vehicle devices, game consoles, printers, positioning devices, wearable devices, smart sensors, mobile power supplies, Virtual Reality (VR) devices, Augmented Reality (AR) devices, or any other suitable electronic device 1 with a storage.

[0065] In some embodiments, as Figure 2 shown, the storage system 2 includes a controller 4 and a single memory 5, and the storage system 2 can be integrated into a memory card.

[0066] Among them, the memory card includes any one of a PC card (PCMCIA, Personal Computer Memory Card International Association), a Compact Flash (CF) card, a Smart Media (SM) card, a Memory Stick, a Multimedia Card (MMC), a Secure Digital Memory Card (SD) card, and a UFS.

[0067] In other embodiments, as Figure 3 shown, the storage system 2 includes a controller 4 and multiple memories 5, and the storage system 2 is integrated into a Solid State Drive (SSD).

[0068] In the storage system 2, in some embodiments, the controller 4 is configured to operate in a low duty cycle environment, such as an SD card, a CF card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices 2 such as personal calculators, digital cameras, mobile phones, etc.

[0069] In some other embodiments, the controller 4 is configured to operate in a high duty cycle environment SSD or eMMC, which is used as a data storage for mobile devices such as smart phones, tablets, laptops, etc. and enterprise storage arrays.

[0070] In some embodiments, the controller 4 may be configured to manage the data stored in the memory 5 and communicate with external devices (such as a host). In some embodiments, the controller 4 may also be configured to control the operations of the memory 5, such as read, erase, and program operations. In some embodiments, the controller 4 may also be configured to manage various functions regarding the data stored in or to be stored in the memory 5, including at least one of bad block management, garbage collection, logical to physical address translation, and wear leveling. In some embodiments, the controller 4 is also configured to process the error correction code regarding the data read from or written to the memory 5.

[0071] Of course, the controller 4 may also perform any other suitable functions, such as formatting the memory 5; for example, the controller 4 may communicate with external devices (such as a host) through at least one of various interface protocols.

[0072] It should be noted that the interface protocol includes at least one of USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI Express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer System Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics 2 (IDE) protocol, and Firewire protocol.

[0073] The above-mentioned controller 4 may be, for example, a Central Processing Unit (CPU), a general-purpose processor, a Digital Signal Processor (DSP), an Application-Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof.

[0074] Some embodiments of the present application provide a memory 5. The memory 5 may be applied to the above-mentioned storage system 2. Of course, the memory 5 may be applied to other storage systems 2, and the present application does not limit this.

[0075] Figure 4Stereoscopic structure diagram of a memory according to some embodiments Figure 5 Cross-sectional view of a memory according to some embodiments Figure 6 is Figure 4 Structure diagram of a storage cell in Figure 7 is Figure 6 Equivalent circuit diagram of the storage cell shown

[0076] It should be noted that in Figure 4 and Figure 5 , a memory 5 provided by an embodiment of the present application is in a three-dimensional coordinate system of X - Y - Z. The memory 5 extends in the X - Y plane. The first direction X and the second direction Y are, for example, two orthogonal directions in the plane where the memory 5 is located (for example, the plane where the source layer SL is located): The first direction X is, for example, the extending direction of the word line WL, and the second direction Y is, for example, the extending direction of the bit line BL. The third direction Z is perpendicular to the X - Y plane

[0077] See Figure 4 and Figure 5 , some embodiments of the present application provide a memory 5, including a semiconductor device 6 and a peripheral device 7. The peripheral device 7 can be disposed on one side of the semiconductor device 6

[0078] As Figure 5 shown, the semiconductor device 6 can include a storage cell array 8 and a source layer SL. The peripheral device 7 can be disposed, for example, on the side of the storage cell array 8 away from the source layer SL

[0079] As used in the present application, whether a component (such as a layer, a structure, or a device) is "on", "above", or "below" another component (such as a layer, a structure, or a device) of the memory 5 (such as a three - dimensional memory 5) is determined with respect to the peripheral device 7 of the memory 5 in the third direction Z when the peripheral device 7 is in the lowest plane of the memory 5 in the third direction Z. Throughout the content of the present application, the same concept is applied to describe the spatial relationship

[0080] See Figure 5 and Figure 6 , the source layer SL can be connected to a first reference voltage, and the first reference voltage can be a ground voltage or other voltages. The source layer SL can include a semiconductor material, and the semiconductor material is, for example, single - crystal silicon, single - crystal germanium, III - V group compound semiconductor material, II - VI group compound semiconductor material, and other suitable semiconductor materials. The source layer SL can be partially or fully doped. Exemplarily, the source layer SL can include a doped region doped with a p - type dopant. The source layer SL can also include an undoped region

[0081] See Figure 4 and Figure 5, the memory cell array 8 includes a plurality of memory cells 81 arranged in an array along a first direction X and a second direction Y.

[0082] Among them, as Figure 6 and Figure 7 shown, the memory cell 81 includes a vertical transistor T and a capacitor C. The vertical transistor T can be formed by a channel structure formed by a semiconductor pillar 10 and a gate layer 11 adjacent to the channel structure. Among them, a gate dielectric layer 12 is further provided between the semiconductor pillar 10 and the corresponding gate layer 11. The semiconductor pillar 10 has a source and a drain, and the source and the drain are respectively located at both ends of the semiconductor pillar 10. Among them, the material of the channel structure includes a semiconductor material, and the materials of the source and the drain can include a semiconductor material doped with a P-type dopant or an N-type dopant.

[0083] It should be noted that the semiconductor material is, for example, single crystal silicon, polycrystalline silicon, single crystal germanium, III-V group compound semiconductor material, II-VI group compound semiconductor material, and other suitable semiconductor materials. The P-type dopant includes boron or gallium. The N-type dopant includes phosphorus or arsenic.

[0084] The drain of the vertical transistor T is connected to the bit line BL, the source of the vertical transistor T is connected to one plate of the capacitor C, and the other plate of the capacitor C can be connected to the source layer SL. The capacitor C represents logical 1 and 0 by the amount of charge stored therein, or rather, the high and low voltage difference across the capacitor C. The gate layer 11 of the vertical transistor T is connected to the word line WL. In this way, a voltage can be applied through the word line WL to control the vertical transistor T to conduct or cut off, and when the vertical transistor T conducts, the bit line BL performs a read or write operation on the vertical transistor T.

[0085] In some embodiments, referring to Figure 4 and Figure 5 , the semiconductor device 6 may further include an array interconnect layer 13. The array interconnect layer 13 can be coupled to the memory cells 81.

[0086] Among them, the array interconnect layer 13 can include the word line WL and the bit line BL. The word line WL can be coupled to the gate layer 11 of the vertical transistor T in at least one memory cell 81. The bit line BL can be coupled to the drain of the vertical transistor T in at least one memory cell 81. Among them, the gate layers 11 of a plurality of vertical transistors T spaced apart along the first direction X are coupled to the same word line WL.

[0087] In the above embodiments, as Figure 5As shown, the peripheral device 7 coupled to the semiconductor device 6 may include a substrate 15 and a peripheral circuit 14 disposed on the substrate 15. Among them, the material of the substrate 15 may be single-crystalline silicon or other suitable materials, such as silicon germanium, germanium, or silicon-on-insulator thin film. The peripheral circuit 14 is configured to control and sense the array devices. The peripheral circuit 14 may be any suitable digital, analog, and / or mixed-signal control and sensing circuit for supporting the operation (or work) of the array devices, including but not limited to page buffers, decoders (such as row decoders and column decoders), sense amplifiers, drive circuits (such as word line drivers), charge pumps, current or voltage references, or any active or passive components of the circuit (such as transistors, diodes, resistors, or capacitors C). The peripheral circuit 14 may also include any other circuits compatible with advanced logic processes, including logic circuits (such as processors and programmable logic devices (Programmable Logic Device, abbreviated as PLD)) or storage circuits (such as static random access memory 5 (Static Random-Access Memory, abbreviated as SRAM)).

[0088] The peripheral circuit 14 may be coupled to the array interconnect layer 13 such that the semiconductor device 6 and the peripheral device 7 can be coupled. Specifically, since the peripheral circuit 14 is coupled to the array interconnect layer 13, the peripheral circuit 14 in the peripheral device 7 can be coupled to the vertical transistor TT in the semiconductor device 6 to achieve the transmission of electrical signals between the peripheral circuit 14 and the vertical transistor T. In some possible implementation manners, a bonding interface may be provided between the peripheral circuit 14 and the array interconnect layer 13, and through the bonding interface, the peripheral circuit 14 and the array interconnect layer 13 can be bonded and coupled to each other.

[0089] In the above embodiment, a first connection portion 16 located in the array interconnect layer 13 may be provided on one side of the semiconductor device 6 close to the peripheral circuit 14, and the first connection portion 16 is used to connect to the vertical transistor T inside the semiconductor device 6; the peripheral circuit 14 may include a second connection portion 17 and a transistor disposed on the substrate 15. The second connection portion 17 is connected to the transistor and is located on the side of the transistor close to the semiconductor device 6, where the transistor may include complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS). In the above embodiment, the first connection portion 16 and the second connection portion 17 are bonded and connected, and the connection between the vertical transistor T and the transistor is achieved through the bonding between the first connection portion 16 and the second connection portion 17, thereby achieving the connection between the semiconductor device 6 and the peripheral circuit 14.

[0090] Figure 8 Is a top view of a semiconductor structure according to some embodiments. Refer to Figure 4, Figure 5 and Figure 8 , some embodiments of the present application provide a semiconductor structure 18, which may be a memory 5. For example, the semiconductor structure 18 includes semiconductor devices 6 and peripheral devices 7. Alternatively, the semiconductor structure 18 may also be a part of the memory 5. For example, the semiconductor structure 18 is the semiconductor device 6 in the memory 5. The embodiments of the present application do not make specific limitations on this.

[0091] Figure 9 Is a top view of a word line group according to some embodiments. Figure 10 Is Figure 8 A cross-sectional view taken along the section line A-A in Figure 5 , Figure 8 , Figure 9 and Figure 10 , the semiconductor structure 18 provided by some embodiments of the present application includes a plurality of semiconductor pillars 10, a plurality of word line groups 19, and a plurality of lead-out structures 22.

[0092] Please refer to Figure 5 and Figure 9 , the plurality of semiconductor pillars 10 are arranged in multiple rows and multiple columns along the first direction X and the second direction Y. That is, the first direction X is the row direction, and the second direction Y is the column direction. Taking the plane where the row direction and the column direction of the plurality of semiconductor pillars 10 are located as the reference plane (i.e., the X-Y plane), the length direction of the semiconductor pillar 10 intersects with the reference plane. In the present application, taking the length direction of the semiconductor pillar 10 perpendicular to the reference plane as an example (i.e., the length direction of the semiconductor pillar 10 is the third direction Z), the embodiments of the present application are explained. Continue to refer to Figure 9 and Figure 10 , the semiconductor structure 18 includes an array region A and a transition region B that are alternately arranged along the first direction X, and the plurality of semiconductor pillars 10 arranged in an array are located in the array region A.

[0093] As Figure 9 shown, the semiconductor structure 18 in this embodiment further includes a plurality of word line groups 19. One word line group 19 connects one row of semiconductor pillars 10, that is, one word line group 19 connects the semiconductor pillars 10 located in the same row in a plurality of array regions A, so as to control the semiconductor pillars 10 located in the same row in a plurality of array regions A. Exemplarily, the word line group 19 may include a plurality of gate layers 11 that are sequentially spaced apart along the first direction X. Among them, one gate layer 11 may connect a part of the semiconductor pillars 10 in one row of semiconductor pillars 10. For example, one gate layer 11 may connect one row of semiconductor pillars in one array region A; or, one gate layer 11 may connect the semiconductor pillars in the same row in two array regions A; or, one gate layer 11 may connect the semiconductor pillars in the same row in a plurality of array regions A.

[0094] Please refer to Figure 5 ,Figure 8 , Figure 9 and Figure 10 , the vertical transistor T in the semiconductor structure 18 may include a MSG (mirror single gate) vertical transistor T. The above gate layer 11 is located on one side of the semiconductor pillar 10. Adjacent two gate layers 11 are arranged at intervals along the second direction Y, and the gate layer 11 extends along the first direction X. The gate layer 11 and the adjacent semiconductor pillar 10 form a vertical transistor TT, and there is a mirror symmetry distribution between two adjacent gate layers 11 along the second direction Y, that is, the formed vertical transistor T is a MSG vertical transistor T. In other embodiments, the vertical transistor T in the semiconductor device 6 may also include a single-gate vertical transistor T, a double-gate vertical transistor T, a tri-gate vertical transistor T, and a GAA (gate all around) vertical transistor T, etc.

[0095] Continuing to refer to Figure 9 , the semiconductor structure 18 in this embodiment further includes a plurality of lead-out structures 22. One lead-out structure 22 is connected to one gate layer 11 for connecting the gate layer 11 to the peripheral circuit 14. The plurality of lead-out structures 22 are arranged in multiple rows and columns, and adjacent two rows of lead-out structures 22 are staggeredly arranged in the second direction Y. It should be noted that the "staggered arrangement" means that there is no overlap between adjacent two rows of lead-out structures 22 in the second direction Y. Exemplarily, adjacent two rows of lead-out structures 22 may be located in different transition regions. For example Figure 9 , in [example], the lead-out structures 22 of one word line group 19 are located in the same row. Then, the lead-out structures 22 of two adjacent word line groups 19 are adjacent two rows of lead-out structures 22, and the lead-out structures 22 of two adjacent rows in the second direction Y are respectively located in different transition regions B, that is, the lead-out structures 22 of adjacent two rows are staggeredly arranged in the second direction Y. It should be noted that the fact that the lead-out structures 22 of one word line group 19 are located in the same row in this embodiment is an example. In some other embodiments, there may be a situation where the lead-out structures 22 of two word line groups 19 are located in the same row. Therefore, the "non-overlap of the lead-out structures 22 of adjacent two rows in the second direction Y" should be defined by the positions of the lead-out structures 22, rather than specifically referring to the lead-out structures of one word line group as one row of lead-out structures.

[0096] With the above settings, the lead-out structures 22 of adjacent two rows are staggeredly arranged in the second direction Y, which can prevent the lead-out structures 22 of adjacent two rows from being connected in the second direction Y, thus causing a short circuit, and solve the problem that the gate layer 11 connected thereto fails to control the semiconductor column 10 due to the short circuit of the lead-out structures 22 of adjacent two rows in the second direction Y, which is beneficial to improving the yield of the semiconductor structure 18. Moreover, the lead-out structures 22 of the same row are also respectively located in different transition regions B. Therefore, it can prevent the lead-out structures 22 of adjacent two rows from being connected in the first direction X, thus causing a short circuit, and improve the problem that the gate layer 11 connected thereto fails to control the semiconductor column 10 due to the short circuit of the adjacent lead-out structures 22 in the first direction X, which is beneficial to improving the yield of the semiconductor structure 18.

[0097] In some embodiments, as Figure 9 shown, the semiconductor structure 18 further includes a plurality of partition structures 21. The positional relationship of the plurality of partition structures 21 in some embodiments will be explained below in conjunction with Figure 9 .

[0098] Referring to Figure 9 , in this embodiment, the plurality of partition structures 21 are located in the transition region B. If a gate layer 11 connects the semiconductor columns 10 of multiple array regions A to control the semiconductor columns 10 of multiple array regions A. Then, the too-long gate layer 11 has a problem of open circuit, resulting in the failure of the gate layer 11 to control some of the semiconductor columns 10. Based on this, in this embodiment, two adjacent gate layers 11 in the word line group 19 along the first direction X are partitioned by the partition structure 21 in the transition region B. The partition structure 21 can extend along the third direction Z to partition two adjacent gate layers 11 along the first direction X. Exemplarily, the material of the partition structure 21 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, and other insulating materials.

[0099] By partitioning two adjacent gate layers 11 in the word line group 19 along the first direction X by the partition structure 21, the length of the gate layer 11 in the first direction X can be reasonably set. For example, Figure 8 in, one gate layer 11 can connect at most the semiconductor columns 10 of the same row of two array regions A, which is beneficial to improving the problem that the gate layer 11 fails to control some of the semiconductor columns 10 due to the open circuit of the gate layer 11, and is beneficial to improving the yield of the semiconductor. In addition, the partition structure 21 can insulate two adjacent gate layers 11 along the first direction X, which is beneficial to preventing two adjacent gate layers 11 along the first direction X from short-circuiting.

[0100] In addition, taking the example of a gate layer 11 connecting semiconductor columns 10 in the same row of two array regions A, in the present application, only two partition structures 21 need to be provided in the two array regions A to partition an annular gate layer 11 into two gate layers 11, so as to control the semiconductor columns 10 in two rows of the two array regions A. In the related art, two partition structures 21 are required in one array region A to partition the annular gate layer 11 into two gate layers 11 to control the semiconductor columns 10 in two rows of one array region A. Then, four partition structures 21 are required for the two array regions A. Since the partition structure 21 usually includes an etching process during formation, in order to prevent the structures around the partition structure 21 from being damaged, a safety distance is usually set around the partition structure 21. Therefore, one partition structure 21 will occupy a relatively large space. Compared with the related art, the semiconductor structure 18 in this embodiment saves the number of partition structures 21 provided, can further reduce the size of the semiconductor structure 18, and is beneficial to the development of the device towards miniaturization.

[0101] The following combines Figure 11 and Figure 12 , and explains the positional relationship of the partition structure 21 in some embodiments.

[0102] In some embodiments, as Figure 11 and Figure 12 shown, the partition structure 21 as a whole can extend along the third direction Z (not shown in the figure), so as to play the role of partitioning the gate layer 11. In addition, the partition structure 21 may include one or both of a first extension portion 211 and a second extension portion 212. Among them, the dimension of the first extension portion 211 along the first direction X is greater than its dimension along the second direction Y, that is, the length of the first extension portion 211 in the first direction X is greater than its length in the second direction Y. The dimension of the second extension portion 212 along the first direction X is less than its dimension along the second direction Y, that is, the length of the second extension portion 212 along the first direction X is less than its length in the second direction Y.

[0103] When the partition structure 21 includes the first extension portion 211 and the second extension portion 212, the first extension portion 211 and the second extension portion 212 are arranged in a cross manner. For example Figure 11 shown, a plurality of first extension portions 211 are alternately arranged on the left and right sides of the second extension portion 212 along the second direction Y, and the plurality of first extension portions 211 are staggered in the first direction X, that is, the plurality of first extension portions 211 do not overlap in the first direction X. Through the above settings, combined with Figure 12, in this embodiment, the partition structure 21 can partition the word line group 19 in each transition region B. Then, a lead-out structure 22 needs to be provided for each gate layer 11 to connect to the driving circuit in the peripheral circuit 14. In a transition region B, one such partition structure 21 can partition the gate layers 11 of two adjacent array regions A. Moreover, two adjacent gate layers 11 along the first direction X are located on both sides of the first extension portion 211, and the first extension portion 211 can further partition the two adjacent gate layers 11 by a certain distance, so as to facilitate the arrangement of the lead-out structure 22 for the gate layer 11.

[0104] Continuing to refer to Figure 10 , Figure 11 and Figure 12 , the lead-out structures 22 of multiple array regions A can be alternately arranged on both sides of the second extension portion 212 with the lead-out structures 22 of its adjacent array regions A. Moreover, the lead-out structure 22 is correspondingly arranged with the first extension portion 211, that is, one lead-out structure 22 and one first extension portion 211 are located in the same word line group 19. The first extension portion 211 can prevent the lead-out structure 22 of the gate layer 11 from being connected to the gate layer 11 adjacent to it along the first direction X, resulting in a short circuit, and can also prevent the lead-out structure 22 of the gate layer 11 from being connected to the gate layer 11 adjacent to it along the second direction Y, resulting in a short circuit, which is beneficial to improving the situation where the failure of the gate layer 11 to control the semiconductor pillar 10 is caused by the short circuit of the lead-out structure 22. In addition, with the same partition distance, the first extension portions 211 are alternately arranged on both sides of the second extension portion 212, which is beneficial to reducing the gap between the array regions A. Since the semiconductor structure 18 includes multiple array regions A, there are gaps between multiple array regions A. Therefore, reducing the gap between the array regions A is beneficial to compressing the size of the semiconductor structure 18 and facilitating the miniaturization development of the memory 5.

[0105] In another case, the partition structure 21 only includes the first extension portion 211. The following will explain the positional relationship of the partition structure 21 in combination with Figure 9 , Figure 10 and Figure 13 .

[0106] In one embodiment, the word line group 19 is partitioned in each transition region B, which is beneficial to improving the failure of the gate layer 11 to control the semiconductor pillar 10 due to being too long, such as the embodiment shown in Figure 12 above.

[0107] In some other embodiments, referring to Figure 9 and Figure 13, the number of transition regions B is multiple, and the multiple transition regions B are divided into a first transition region B1 and a second transition region B2. In two adjacent word line groups 19, one word line group 19 is interrupted in each first transition region B1, and the other word line group 19 is interrupted in each second transition region B2. Exemplarily, the first transition region B1 and the second transition region B2 may be alternately arranged along the first direction X, or two first transition regions B1 may be arranged continuously, or two second transition regions B2 may be arranged continuously. In this embodiment, the arrangement positions of the first transition region B1 and the second transition region B2 are not specifically limited. Then, the gate layer 11 in one word line group 19 may be connected to a row of semiconductor columns 10 in one array region A, or may be connected to a row of semiconductor columns 10 in two array regions A, or may also be connected to the semiconductor columns 10 in multiple array regions A. The gate layer 11 in the word line group 19 may be adjusted accordingly according to the arrangement modes of different semiconductor columns 10.

[0108] Through the above settings, the lead-out structures 22 of two adjacent word line groups 19 can be arranged staggeredly in the second direction Y, which can prevent the lead-out structures 22 in two adjacent rows from being connected in the second direction Y, thus causing a short circuit, and solves the problem that the gate layer 11 connected thereto fails to control the semiconductor column 10 due to the short circuit of the lead-out structures 22 in two adjacent rows in the second direction Y, which is beneficial to improving the yield of the semiconductor structure 18. Moreover, the lead-out structures 22 in the same row are also located in different transition regions B respectively. Therefore, it can prevent the lead-out structures 22 in two adjacent rows from being connected in the first direction X, thus causing a short circuit, and solves the problem that the gate layer 11 connected thereto fails to control the semiconductor column 10 due to the short circuit of the adjacent lead-out structures 22 in the first direction X, which is beneficial to improving the yield of the semiconductor structure 18.

[0109] In some embodiments, referring to Figure 9 and Figure 13 , the overlapping length of two adjacent gate layers 11 along the second direction Y in the first direction X is: 40%-60% of the length of the longer gate layer 11 along the first direction X. In this embodiment, one gate layer 11 may be connected to the semiconductor columns 10 in the same row in two adjacent array regions A, and two adjacent gate layers 11 overlap in the first direction X. And, exemplarily, the length of the overlapping part is 40% of the length of the longer gate layer 11 along the first direction X; or, the length of the overlapping part is 50% of the length of the longer gate layer 11 along the first direction X; or, the length of the overlapping part is 60% of the length of the longer gate layer 11 along the first direction X.

[0110] With the above settings, the lead-out structures 22 of two adjacent word line groups 19 can be staggeredly arranged in the second direction Y. The lead-out structures 22 of two adjacent rows are staggeredly arranged in the second direction Y, which can prevent the lead-out structures 22 of two adjacent rows from being connected in the second direction Y, thus causing a short circuit, and solves the problem that the gate layer 11 connected thereto fails to control the semiconductor column 10 due to the short circuit of the lead-out structures 22 of two adjacent rows in the second direction Y, which is beneficial to improving the yield of the semiconductor structure 18.

[0111] In some embodiments, as Figure 5 、 Figure 9 and Figure 13 shown, the lead-out structure 22 is located in the transition region B, and the lead-out structures 22 of two adjacent rows are staggeredly arranged in the second direction Y. Exemplarily, specifically refer to Figure 10 , the lead-out structures 22 of two adjacent rows can be located in the same transition region B. Or, refer to Figure 8 and Figure 11 , the lead-out structures 22 of two adjacent rows can be located in different transition regions B. In this embodiment, the gate layer 11 is led out through the lead-out structure 22 in the transition region B and then connected to the peripheral circuit 14, which is beneficial to arranging more semiconductor columns 10 in the array region A and improving the space utilization rate of the semiconductor structure 18.

[0112] Exemplarily, when the lead-out structures 22 of two adjacent rows staggeredly arranged in the second direction Y are located in different transition regions B, there is no problem of short circuit caused by mis-touch between the lead-out structures 22 of two adjacent rows, so there is no need to arrange a partition structure 21 between the adjacent lead-out structures 22, which is beneficial to compressing the size of the semiconductor structure 18.

[0113] In the following, in combination with Figure 9 and Figure 13 the positional relationship between the lead-out structure 22 and the gate layer 11 will be explained.

[0114] In some embodiments, as Figure 9 shown, the lead-out structure 22 is connected to both ends of the gate layer 11 in the first direction X. The lead-out structures 22 in two adjacent word line groups 19 are respectively connected to both ends of the gate layer 11. Exemplarily, the word line group 19a and the word line group 19b are two adjacent word line groups 19. The lead-out structures 22 in the word line group 19a are all connected to the left end of the gate layer 11, and the lead-out structures 22 in the word line group 19b are all connected to the right end of the gate layer 11. And, the lead-out structures 22 of the word line group 19a and the lead-out structures 22 of the word line group 19b are respectively located in different transition regions B, or the lead-out structures 22 of the word line group 19a and the lead-out structures 22 of the word line group 19b can be located in the same transition region B. At the same time, the lead-out structures 22 of the two word line groups 19 are staggered in the second direction Y.

[0115] With the above settings, the lead-out structures 22 of adjacent two rows are staggeredly arranged in the second direction Y, which can prevent the lead-out structures 22 of adjacent two rows from being connected in the second direction Y, thus causing a short circuit, and solves the problem that the gate layer 11 connected thereto fails to control the semiconductor column 10 due to the short circuit of the lead-out structures 22 of adjacent two rows in the second direction Y, which is beneficial to improving the yield of the semiconductor structure 18.

[0116] In some other embodiments, as Figure 13 shown, the lead-out structure 22 is connected to the middle part of the gate layer 11 along the first direction X. The lead-out structures 22 in adjacent two word line groups 19 are both connected to the intermediate part of the gate layer 11 along the first direction X. However, the lead-out structures 22 in adjacent two word line groups 19 are respectively located in different transition regions B. Then, the lead-out structures 22 of adjacent two rows are staggeredly arranged in the second direction Y, which can prevent the lead-out structures 22 of adjacent two rows from being connected in the second direction Y, thus causing a short circuit, and solves the problem that the gate layer 11 connected thereto fails to control the semiconductor column 10 due to the short circuit of the lead-out structures 22 of adjacent two rows in the second direction Y, which is beneficial to improving the yield of the semiconductor structure 18.

[0117] Due to the problem of electrical interference between adjacent semiconductor columns 10, to solve the above problem, in some embodiments, referring to Figure 9 and Figure 13 , an isolation structure 23 is further provided between adjacent two rows of semiconductor columns 10. The isolation structure 23 includes a conductive layer 231, and leads out and connects the conductive layer 231 to a fixed low potential. Exemplarily, the conductive layer 231 can be grounded or connected to a negative voltage. The conductive layer 231 includes a conductive material, such as tungsten metal, cobalt metal or titanium nitride, etc. It should be noted that the positive projection of the isolation structure 23 on the X-Z plane coincides with at least a part of the positive projection of the adjacent gate layer 11 on the X-Z plane, so as to reduce the interference between two gate layers 11 located on the opposite sides of the isolation structure 23.

[0118] Continuing to refer to Figure 9 and Figure 13 , in the semiconductor structure 18 provided by the embodiment of the present application, the isolation structure 23 is located between adjacent two rows of semiconductor columns 10. During the conduction process of the semiconductor column 10, the isolation structure 23 can prevent the electrons in the conducted semiconductor column 10 from easily passing through the conductive layer 231 in the isolation structure 23 and moving to the adjacent semiconductor column 10, reducing the coupling effect between adjacent semiconductor columns 10, and further reducing the leakage between adjacent semiconductor columns 10.

[0119] In some other embodiments, referring to Figure 9, an isolation structure 23 is provided between adjacent two rows of semiconductor pillars 10. The isolation structure 23 includes an insulating layer 232. Exemplarily, the insulating layer 232 may include any one of silicon oxide, silicon nitride, silicon oxynitride, and high-k insulating materials. In this embodiment, the isolation structure 23 is located between adjacent two rows of semiconductor pillars 10. During the conduction process of the semiconductor pillars 10, the isolation structure 23 can prevent electrons in the conductive semiconductor pillars 10 from easily passing through the insulating layer 232 and moving to adjacent semiconductor pillars 10, reducing the coupling effect between adjacent semiconductor pillars 10, and further reducing the leakage between adjacent semiconductor pillars 10.

[0120] In some embodiments, as Figure 8 and Figure 10 shown, the semiconductor structure 18 further includes an insulating structure 24. The insulating structure 24 at least covers both ends of the gate layer 11 in the third direction Z to play a supporting role, thereby reducing the risk of collapse of the semiconductor structure 18. At the same time, the insulating structure 24 can also play an insulating role to prevent the gate layer 11 from being short-circuited with other conductive structures (such as the source or drain of the semiconductor pillar 10).

[0121] Exemplarily, referring to Figure 10 , the insulating structure 24 includes a first insulating portion 241 and a second insulating portion 242.

[0122] As Figure 10 shown, the first insulating portion 241 includes a first part 2411 and a second part 2412. Along the second direction Y, the first part 2411 is located between the gate layers 11 in the same gate structure to reduce the risk of short-circuiting between the gate layers 11 in the same gate structure and provide support. Along the third direction Z, the second part 2412 covers one end of the gate layer 11 and the first part 2411 and is located between the gate dielectric layers 12 in the same gate structure to play a flattening and supporting role.

[0123] As Figure 10 shown, the second insulating portion 242 is disposed between two adjacent semiconductor pillars 10. Along the third direction Z, the second insulating portion 242 covers the gate layer 11, the gate dielectric layer 12, and the other end of the first part 2411 away from the second part 2412 to prevent the gate layer 11 from being short-circuited with the source or drain of the semiconductor pillar 10 and provide support.

[0124] In some embodiments, referring to Figure 10 , the second insulating portion 242 includes a third part 2421 and a fourth part 2422.

[0125] As Figure 10As shown, the third part 2421 is located between the fourth part 2422 and the semiconductor columns 10 on both sides, and on the side of the fourth part 2422 away from the first insulating part 241. Among them, the part of the third part 2421 located on the side of the fourth part 2422 away from the first insulating part 241 can be flush with the end of the semiconductor column 10.

[0126] Some embodiments of the present application also provide a method for manufacturing a semiconductor structure 18, which will be described below in conjunction with Figures 14 to 23 to explain the method for manufacturing the semiconductor structure 18 provided by some embodiments of the present application.

[0127] Figure 14 is a flowchart of the method for manufacturing a semiconductor structure 18 according to some embodiments of the present application. As Figure 14 shown, the method for manufacturing the semiconductor structure 18 includes: S100 - S200.

[0128] S100. Form a plurality of semiconductor columns and a plurality of word line groups; the plurality of semiconductor columns are arranged in multiple rows and multiple columns; one word line group connects one row of semiconductor columns; each word line group includes a plurality of gate layers sequentially arranged at intervals in the row direction, and one gate layer connects a part of the semiconductor columns in one row of semiconductor columns.

[0129] In the above steps, referring to Figure 15 and Figure 16 , before forming a plurality of semiconductor columns and a plurality of word line groups, a semiconductor substrate 25 will be provided. The semiconductor substrate 25 may include at least one of single crystal silicon, polycrystalline silicon, single crystal germanium, III - V group compound semiconductor materials, II - VI group compound semiconductor materials, or other semiconductor materials known in the art. Then, a mask layer 26 is formed above the semiconductor substrate 25. Exemplarily, the material of the mask layer 26 may include silicon nitride. Before forming the mask layer 26 above the semiconductor substrate 25, an oxide layer 27 may be formed on the semiconductor substrate 25 through a deposition process, and then the mask layer 26 is formed on the oxide layer 27 to avoid stress problems caused by direct contact between the mask layer 26 formed of silicon nitride and the silicon in the semiconductor substrate 25.

[0130] Continuing to refer to Figure 15 and Figure 16 , a plurality of first grooves 28 are formed on the semiconductor substrate 25 through the mask layer 26. The plurality of first grooves 28 all extend along the second direction Y. The plurality of first grooves 28 separate a plurality of semiconductor walls on the semiconductor substrate 25. After forming the plurality of first grooves 28, an epitaxial growth layer of oxide 27 is formed on the inner wall of the first grooves 28 under high - temperature conditions, that is, the single - crystal silicon on the inner wall of the first grooves 28 is oxidized into silicon dioxide to repair the exposed semiconductor substrate 25. Here, the first grooves 28 can be formed by a dry or wet etching process.

[0131] After forming the oxide layer 27 in the first grooves 28, the first insulating material 29 is filled in the plurality of first grooves 28, and chemical mechanical polishing (CMP) is performed on the upper surface of the semiconductor substrate 25. Exemplarily, the first insulating material 29 may include at least one of silicon oxide or nitride.

[0132] Reference Figure 15 、 Figure 16 、 Figure 17 And Figure 22 In this step, it also includes: forming a plurality of second grooves 30 on the semiconductor substrate 25. The plurality of second grooves 30 extend along the first direction X, the first direction X intersects with the second direction Y, and the plurality of second grooves 30 divide each semiconductor wall into a plurality of semiconductor columns 10. The semiconductor substrate 25 includes an array region A and a transition region B that alternate along the second direction. The second grooves 30 penetrate through the plurality of array regions A. The plurality of second grooves 30 include gate grooves 301 and isolation grooves 302 that are spaced apart along the second direction Y. Subsequently, a gate ring 34 is formed in the gate grooves 301, and an isolation structure 23 is formed in the isolation grooves 302. Among them, the gate ring 34 and the isolation structure 23 penetrate through the plurality of array regions A. Exemplarily, the isolation structure 23 may be formed before the gate ring 34, or the gate ring 34 may be formed after the isolation structure 23, or the gate structure may be formed during the formation of the isolation structure 23.

[0133] Before forming the gate ring 34 and the isolation structure 23 that are spaced apart in the plurality of second grooves 30, it also includes filling a sacrificial material 32 in the second grooves 30. Exemplarily, the sacrificial material 32 may include spin on carbon (SOC), carbon, etc.

[0134] So far, please refer to Figure 16 、 Figure 17 And Figure 18, a plurality of semiconductor pillars 10 surrounded by a first insulating material 29 and a sacrificial material 32 are formed on the remaining semiconductor layer. The semiconductor pillars 10 extend along a third direction Z, and the plurality of semiconductor pillars 10 are arranged in an array along a first direction X and a second direction Y. In the second direction Y, there is a sacrificial material 32 between adjacent semiconductor pillars 10, and in the first direction X, there is a first insulating material 29 between adjacent semiconductor pillars 10. Here, the sacrificial material 32 can be formed, for example, by a thin film deposition process. Among them, the thin film deposition process includes any one of chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD).

[0135] Continue to refer to Figure 18 and Figure 19 , after the sacrificial material 32 is formed in the second groove 30, a mask layer 26 can be formed to protect the sacrificial material 32 in the gate groove 301, etch the sacrificial material 32 in the isolation groove 302 to a certain depth, and fill a layer of covering layer 31, for example, titanium nitride material can be filled. Here, the mask layer 26 can be formed, for example, by a coating process, an exposure process, and a development process in sequence. Subsequently, the sacrificial material 32 in the gate groove 301 is removed. Exemplarily, when the sacrificial material 32 includes carbon, the process of removing all the sacrificial material 32 in the gate groove 301 can include ashing to remove all the sacrificial material 32 in the gate groove 301.

[0136] Refer to Figure 18 , Figure 19 , Figure 20 and Figure 21 , after all the sacrificial material 32 in the gate groove 301 is removed, it further includes expanding the width and depth of the gate groove 301 by wet etching, and then filling a bottom dielectric material 33 in the gate groove 301. After its surface is polished by a CMP process, the dielectric material 33 in the gate groove 301 is etched, and only the bottom dielectric material 33 is retained. The sacrificial material 32 in the isolation groove 302 can be removed while the dielectric material 33 in the gate groove 301 is etched.

[0137] Refer to Figure 22, forming the gate ring 34 includes: oxidizing a layer of gate oxide layer 35 on the sidewall of the gate groove 301, and forming the gate ring 34 on the sidewall of the gate groove 301. In this step, the gate ring 34 can be formed on the sidewall of the gate groove 301 through a deposition process. The gate ring 34 covers the sidewall of the gate groove 301 extending along the third direction Z, and covers the dielectric material 33 at the bottom of the gate groove 301. In the Y-Z cross-section, the gate ring 34 forms a structure similar to a "U" shape. It should be noted that the gate ring 34 can include a first gate layer 341 and a second gate layer 342, and the materials of the first gate layer 341 and the second gate layer 342 can include at least one of titanium nitride or tungsten metal materials. In this embodiment, a layer of titanium nitride is first deposited in the gate groove 301, and then a layer of tungsten metal is deposited to form the gate ring 34.

[0138] In addition, when forming the gate ring 34 in the gate groove 301, since the width of the isolation groove 302 is small, the isolation groove 302 can be filled with titanium nitride material during the deposition of titanium nitride material. Even if the isolation groove 302 is not filled with titanium nitride material, it will be filled with tungsten metal during the subsequent deposition of tungsten metal in the gate groove 301, so as to form the isolation structure 23 in the gate groove 301.

[0139] Reference Figure 22 and Figure 23 , after forming the gate ring 34 in the gate groove 301, the bottom of the gate ring 34 can be broken by a punching process to form the gate layer 11. Subsequently, the conductive materials in the gate groove 301 and the isolation groove 302 are etched from the top to the same height, and then the remaining space in the second groove 30 is filled with the second insulating material 36. The second insulating material 36 is connected to the dielectric material 33 at the bottom of the gate groove 301 to form the isolation structure 23. Exemplarily, the second insulating material 36 can include at least one of insulating oxides and nitrogen oxides.

[0140] Combined with Figure 9 、 Figure 10 、 Figure 17 and Figure 23 , after filling the remaining space in the second groove 30 with the second insulating material 36, a plurality of partition structures 21 are formed in the transition region B. The partition structures 21 separate the gate ring 34 into a plurality of gate layers 11, and each row of gate layers 11 in the plurality of gate layers 11 is a word line group 19. Exemplarily, a plurality of partition grooves can be formed in the transition region B through an etching process, and then insulating materials are filled in the partition grooves to form the partition structures 21.

[0141] S200, forming a plurality of lead-out structures, one lead-out structure is connected to one gate layer; the plurality of lead-out structures are arranged in multiple rows and multiple columns, and adjacent two rows of lead-out structures are staggered in the column direction.

[0142] In this step, referring to Figure 9 , an extraction structure 22 can be formed at the partition structure 21 in the transition region B. In some embodiments, the extraction structure 22 is connected to the middle part of the gate layer 11 along the first direction X. In other embodiments, the extraction structure 22 is connected to both ends of the gate layer 11 along the first direction X. Exemplarily, a conductive hole can be first formed on the gate layer 11, and the conductive hole extends to the gate layer 11 along the third direction Z. Subsequently, a conductive column is formed in the conductive hole to connect the conductive column to the gate layer 11, thereby forming the extraction structure 22. The extraction structure 22 is used to extract the gate layer 11 and connect it to the driving circuit in the peripheral circuit 14. It should be noted that the extraction structure 22 can be extracted from any one of the two ends of the gate layer 11, and the present application does not limit this.

[0143] Referring to Figure 5 and Figure 9 , after forming the extraction structure 22, it further includes: forming a driving circuit. The driving circuit is connected to the extraction structure 22, and the driving circuit is located on one side of the plurality of semiconductor pillars 10 along the target direction, and the target direction is the third direction Z. It should be noted that the driving circuit is one of the peripheral circuits 14.

[0144] The manufacturing method provided by the embodiment of the present application may further include forming a capacitor C, where the formed capacitor C is located on the side of the semiconductor pillar 10 away from the bottom wall of the gate groove 301 or the bottom wall of the isolation groove 302, and the capacitor C is correspondingly connected to one end of the semiconductor pillar 10 away from the bottom wall of the gate groove 301 or the bottom wall of the isolation groove 302.

[0145] For the semiconductor structure 18 prepared by the above semiconductor manufacturing method, the extraction structures 22 in adjacent two rows are staggeredly arranged in the second direction Y, which can prevent the extraction structures 22 in adjacent two rows from being connected in the second direction Y, thereby causing a short circuit, and solves the problem that the gate layer 11 connected thereto fails to control the semiconductor pillar 10 due to the short circuit of the extraction structures 22 in adjacent two rows in the second direction Y, which is beneficial to improving the yield of the semiconductor structure 18. And, the extraction structures 22 in the same row are also respectively located in different transition regions B. Therefore, it can prevent the extraction structures 22 in adjacent two rows from being connected in the first direction X, thereby causing a short circuit, and solves the problem that the gate layer 11 connected thereto fails to control the semiconductor pillar 10 due to the short circuit of the adjacent extraction structures 22 in the first direction X, which is beneficial to improving the yield of the semiconductor structure 18.

[0146] Moreover, in the method for manufacturing a semiconductor provided in the above embodiments, the formed gate ring 34 penetrates through multiple array regions A, and the gate ring 34 is separated into multiple gate layers 11 by the partition structure 21. In the related art, to form a gate ring 34 in one array region A, two partition structures 21 need to be formed to partition one gate ring 34 into two gate layers 11, and one gate layer 11 is connected to one row of semiconductor pillars 10 in one array region A, so as to control one row of semiconductor pillars 10 in one array region A. Since the process of forming the partition structure 21 includes an etching process, some space needs to be reserved at both ends of the partition structure 21 to avoid damage to the semiconductor pillars 10. Therefore, one partition structure 21 needs to occupy a relatively large space. Taking the example that one gate layer 11 is connected to the semiconductor pillars 10 in two array regions A in the method for manufacturing a semiconductor provided in some embodiments of the present application, two partition structures 21 may be included in the two array regions A, while four partition structures 21 are included in the two array regions A in the related art. The semiconductor structure 18 includes multiple array regions A. Therefore, the semiconductor structure 18 prepared according to the method for manufacturing the semiconductor structure 18 provided in some embodiments can reduce the number of partition structures 21, thereby reducing the size of the semiconductor structure 18, which is beneficial to the miniaturization development of the device.

[0147] The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention should be covered by the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims

1. A semiconductor structure, characterized in that, Including: A plurality of semiconductor columns arranged in multiple rows and columns; The plane where the row direction and the column direction of the plurality of semiconductor columns are located is a reference plane, and the length direction of the semiconductor column intersects with the reference plane; A plurality of word line groups, one word line group connecting one row of the semiconductor columns; the word line group includes a plurality of gate layers sequentially arranged at intervals along the row direction, and one gate layer connects a part of the semiconductor columns in one row of the semiconductor columns; A plurality of lead-out structures, one lead-out structure connected to one gate layer; the plurality of lead-out structures are arranged in multiple rows and columns, and adjacent two rows of the lead-out structures are staggered in the column direction.

2. The semiconductor structure according to claim 1, wherein The semiconductor structure has an array region and a transition region alternately arranged along the row direction; the plurality of semiconductor columns are located in the array region; The semiconductor structure further includes a plurality of partition structures; two adjacent gate layers in the word line group along the row direction are partitioned by the partition structure in the transition region.

3. The semiconductor structure according to claim 2, wherein The partition structure includes a first extension part and / or a second extension part; the size of the first extension part along the row direction is greater than the size along the column direction, and the size of the second extension part along the row direction is less than the size along the column direction; In the case where the partition structure includes a first extension part and a second extension part, the first extension part and the second extension part are arranged in a cross manner.

4. The semiconductor structure according to claim 2, wherein The word line group is partitioned in each transition region.

5. The semiconductor structure according to claim 2, wherein The number of the transition regions is multiple, and the multiple transition regions are divided into a first transition region and a second transition region; In two adjacent word line groups, one word line group is partitioned in each first transition region, and the other word line group is partitioned in each second transition region.

6. The semiconductor structure according to claim 5, wherein The first transition region and the second transition region are alternately arranged along the row direction.

7. The semiconductor structure according to claim 2, wherein For two adjacent gate layers along the column direction, the overlapping length in the row direction is: 40%-60% of the length of the longer gate layer along the row direction.

8. The semiconductor structure according to any one of claims 2-7, wherein The lead-out structure is located in the transition region.

9. The semiconductor structure according to any one of claims 2-7, wherein The lead-out structures staggered in the column direction are located in different transition regions.

10. The semiconductor structure according to any one of claims 5-7, wherein The lead-out structure is connected to the middle part or both ends of the gate layer along the row direction.

11. The semiconductor structure according to any one of claims 10, characterized in that, It further includes a driving circuit, the driving circuit is connected to the lead-out structure, and the driving circuit is located on one side of the plurality of vertical transistors along the target direction, and the target direction is perpendicular to the row direction and the column direction.

12. The semiconductor structure according to any one of claims 1-7, characterized in that, The gate layer is located on at least one side of the semiconductor column; The semiconductor structure further includes: a capacitor and a bit line; The capacitor is connected to one end of the semiconductor column, and the bit line is connected to the other end of the semiconductor column.

13. A method for preparing a semiconductor structure, characterized in that, Comprising: Forming a plurality of semiconductor columns and a plurality of word line groups; The plurality of semiconductor columns are arranged in multiple rows and multiple columns; one word line group connects one row of the semiconductor columns; each word line group includes a plurality of gate layers sequentially arranged at intervals along the row direction, and one gate layer connects a part of the semiconductor columns in one row of the semiconductor columns; Forming a plurality of lead-out structures, one lead-out structure is connected to one gate layer; the plurality of lead-out structures are arranged in multiple rows and multiple columns, and adjacent two rows of the lead-out structures are staggered in the column direction.

14. The manufacturing method of the semiconductor structure according to claim 13, characterized in that, The forming of the plurality of semiconductor columns and the plurality of word line groups includes: Forming a plurality of first grooves on a semiconductor substrate, the plurality of first grooves all extend along a first direction, and the plurality of first grooves divide the semiconductor substrate into a plurality of semiconductor walls; Filling a first insulating material in the plurality of first grooves; Forming a plurality of second grooves on the semiconductor substrate, the plurality of second grooves extend along a second direction, the second direction intersects with the first direction, and the plurality of second grooves divide each semiconductor wall into a plurality of semiconductor columns; the semiconductor substrate includes an array region and a transition region alternating along the second direction, and the second grooves penetrate through a plurality of the array regions; Forming a gate ring on the side wall of the second groove, and filling the remaining space in the second groove with a second insulating material; Forming a plurality of partition structures in the transition region, the partition structures divide the gate ring into a plurality of gate layers, and each row of gate layers in the plurality of gate layers is a word line group.

15. The method for preparing a semiconductor structure according to claim 14, wherein, After forming the plurality of partition structures in the transition region, it further includes: Forming a lead-out structure, located in the transition region, the lead-out structure is connected to the middle part or both ends of the gate layer along the second direction.

16. The method for preparing a semiconductor structure according to claim 15, wherein, After forming the lead-out structure, it further includes: Forming a driving circuit, the driving circuit is connected to the lead-out structure, and the driving circuit is located on one side of the plurality of semiconductor columns along a target direction, and the target direction is perpendicular to the first direction and the second direction.

17. A storage system, characterized in that, Comprising: A semiconductor structure, the semiconductor structure is the semiconductor structure according to any one of claims 1-12; A controller, coupled to the semiconductor structure to control the semiconductor structure to store data.

18. An electronic device, characterized in that, Including a host, and the storage system according to claim 17, the host and the storage system are coupled.

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