Memory element comprising capacitor contact comprising

Abstract

The present disclosure provides a memory element including a bit line structure disposed over a semiconductor substrate, and a lower capacitor contact disposed in the semiconductor substrate and extending over the semiconductor substrate. The lower capacitor contact includes polysilicon. The memory element also includes a higher capacitor contact disposed over the lower capacitor contact. The higher capacitor contact includes titanium nitride. The memory element also includes a first spacer layer disposed between the lower capacitor contact and the bit line structure and between the higher capacitor contact and the bit line structure. In addition, the memory element includes a capacitor disposed over the first spacer layer.

Description

[0001] Cross-reference

[0002] This application claims priority to U.S. Patent Application No. 18 / 419,854 (i.e., the priority date is "January 23, 2024"), the content of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a memory element and a method for manufacturing the same. In particular, it relates to a memory element including capacitor contacts having different materials and a method for manufacturing the same. Background Art

[0004] Due to the simplicity of the structure, compared to other types of memories such as static random access memories (SRAMs), dynamic random access memories (DRAMs) can provide more memory cells per unit chip area. A DRAM is composed of multiple DRAM cells, and each DRAM cell includes a capacitor for storing information and a transistor coupled to the capacitor for regulating when the capacitor is charged or discharged. During a read operation, a word line (WL) is asserted, thereby turning on the transistor. The turned-on transistor allows a sense amplifier to read the voltage across the capacitor through a bit line (BL). During a write operation, the data to be written is provided on the BL when the WL is asserted.

[0005] To meet the increasing memory storage requirements, the size of DRAM memory cells has been continuously reduced, so the packaging density of these DRAMs has been greatly increased. However, the manufacturing and integration of semiconductor devices involve many complex steps and operations. The integration in semiconductor devices has become increasingly complex. The increasing complexity in the manufacturing and integration of semiconductor devices may cause defects. Therefore, it is necessary to continuously improve the structure and manufacturing process of semiconductor devices to solve the defects and improve the performance.

[0006] The above description of "prior art" only provides background art and does not admit that the above description of "prior art" discloses the subject matter of the present disclosure, does not form the prior art of the present disclosure, and any description of the above "prior art" should not be taken as any part of the present disclosure. Summary of the Invention

[0007] In one embodiment of the present disclosure, a memory element is provided. The memory element includes: a bit line structure disposed on a semiconductor substrate, and a lower capacitor contact disposed in the semiconductor substrate and extending above the semiconductor substrate. The lower capacitor contact includes polysilicon. The memory element also includes a higher capacitor contact disposed on the lower capacitor contact. The higher capacitor contact includes titanium nitride (TiN). The memory element further includes a first spacer layer disposed between the lower capacitor contact and the bit line structure and between the higher capacitor contact and the bit line structure. In addition, the memory element includes a capacitor disposed on the first spacer layer.

[0008] In one embodiment, the higher capacitor contact is in direct contact with the lower capacitor contact. In one embodiment, a height of the higher capacitor contact is greater than or equal to a height of the lower capacitor contact. In one embodiment, a ratio of the height of the higher capacitor contact to the height of the lower capacitor contact is in a range of about 1 to about 1.5. In one embodiment, the memory element further includes a second spacer layer disposed between the lower capacitor contact and the first spacer contact layer and between the higher capacitor contact and the first spacer layer, wherein an air gap is disposed between the first spacer layer and the second spacer layer.

[0009] In one embodiment, the memory element further includes a bit line mask layer disposed on the bit line structure, wherein the capacitor is disposed on and in direct contact with the bit line mask layer. In one embodiment, a top surface of the bit line mask layer is higher than a top surface of the higher capacitor contact. In one embodiment, the memory element further includes a third spacer layer covering the bit line mask layer, wherein the third spacer layer extends to contact the higher capacitor contact. In one embodiment, the memory element further includes a landing pad disposed on the higher capacitor contact, wherein the landing pad is in direct contact with the third spacer layer. In one embodiment, the landing pad is in direct contact with the higher capacitor contact.

[0010] In another embodiment of the present disclosure, a memory element is provided. The memory element includes: a bit line structure disposed on a semiconductor substrate, and a lower capacitor contact disposed in the semiconductor substrate and extending above the semiconductor substrate. The memory element also includes a higher capacitor contact disposed on the lower capacitor contact. The higher capacitor contact and the lower capacitor contact include different materials. The memory element further includes a first spacer layer disposed between the lower capacitor contact and the bit line structure and between the higher capacitor contact and the bit line structure. In addition, the memory element includes a capacitor disposed on the first spacer layer, and a landing pad disposed on and in direct contact with the higher capacitor contact.

[0011] In one embodiment, the lower capacitor contact comprises polysilicon, and the higher capacitor contact comprises titanium nitride (TiN). In one embodiment, a height of the higher capacitor contact is greater than or equal to a height of the lower capacitor contact. In one embodiment, a ratio of the height of the higher capacitor contact to the height of the lower capacitor contact ranges from about 1 to about 1.5. In one embodiment, the lower capacitor contact is in direct contact with the higher capacitor contact, and the higher capacitor contact is in direct contact with the landing pad.

[0012] In one embodiment, the memory element further comprises a second spacer layer that separates the lower capacitor contact and the higher capacitor contact from the first spacer layer, wherein an air gap is disposed between the first spacer layer and the second spacer layer. In one embodiment, the second spacer layer is in direct contact with the lower capacitor contact and the higher capacitor contact. In one embodiment, the memory element further comprises a third spacer layer that is disposed on the higher capacitor contact and separates the landing pad from the second spacer layer, wherein the third spacer layer is in direct contact with the capacitor and the higher capacitor contact. In one embodiment, the memory element further comprises a bit line mask layer that is disposed between the bit line structure and the capacitor, wherein the first spacer layer and the second spacer layer extend between the bit line mask layer and the landing pad. In one embodiment, a top surface of the bit line mask layer is higher than a top surface of the higher capacitor contact.

[0013] In another embodiment of the present disclosure, a method of fabricating a memory element is provided. The method includes: forming a bit line structure over a semiconductor substrate, and forming a first spacer layer and a second spacer layer on a sidewall of the bit line structure. The method also includes etching the second spacer layer and the semiconductor substrate to form a first opening adjacent to the bit line structure, and filling the first opening with a lower capacitor contact. The lower capacitor contact protrudes above the semiconductor substrate. The method further includes forming a higher capacitor contact over the lower capacitor contact. The higher capacitor contact and the lower capacitor contact comprise different materials. Additionally, the method includes forming a landing pad over the higher capacitor contact, etching the landing pad, the first spacer layer, and the second spacer layer to form a second opening, and forming a capacitor in the second opening.

[0014] In one embodiment, the method further includes forming a bit line mask layer over the bit line structure, wherein the first spacer layer extends to cover a sidewall of the bit line mask layer. In one embodiment, a top surface of the bit line mask layer is higher than a top surface of the higher capacitor contact, and the bit line mask layer is partially removed to form the second opening. In one embodiment, the method further includes forming a third spacer material that covers the first spacer layer, the second spacer layer, and the higher capacitor contact, and partially removing the third spacer material to expose the higher capacitor contact before forming the landing pad. In one embodiment, forming the lower capacitor contact includes filling the first opening with a lower capacitor contact layer, wherein the lower capacitor contact layer extends over the first spacer layer, the second spacer layer, and the bit line structure. Additionally, forming the lower capacitor contact includes etch-back of the lower capacitor contact layer to expose a sidewall of the second spacer layer. In one embodiment, the lower capacitor contact layer includes polysilicon.

[0015] In one embodiment, forming the higher capacitor contact includes forming a higher capacitor contact layer over the lower capacitor contact, wherein the higher capacitor contact layer extends over the first spacer layer, the second spacer layer, and the bit line structure. Additionally, forming the higher capacitor contact includes etch-back of the higher capacitor contact layer to expose a sidewall of the second spacer layer. In one embodiment, the higher capacitor contact layer includes titanium nitride (TiN). In one embodiment, the method further includes forming a sacrificial layer on a sidewall of the first spacer layer before forming the second spacer layer, and removing the sacrificial layer to form an air gap before forming the first opening. In one embodiment, the method further includes forming a sacrificial layer on a sidewall of the first spacer layer before forming the second spacer layer, and removing the sacrificial layer through the second opening to form an air gap.

[0016] Embodiments of a memory element and a method of manufacturing the same are provided. In some embodiments, the memory element includes a bit line structure disposed over a semiconductor substrate, a lower capacitor contact disposed in the semiconductor substrate and extending above the semiconductor substrate, and a higher capacitor contact disposed over the lower capacitor contact. The lower capacitor contact and the higher capacitor contact include different materials, and the height of the higher capacitor contact is greater than or equal to the height of the lower capacitor contact. Accordingly, the sheet resistances of the capacitor contacts can be reduced while eliminating or suppressing junction leak current. As a result, the performance of the memory element can be improved.

[0017] The technical features and advantages of the present disclosure have been outlined quite extensively above, so that a better understanding of the following detailed description of the present disclosure can be obtained. Other technical features and advantages forming the subject matter of the claims of the present disclosure will be described below. Those skilled in the art to which the present disclosure pertains should understand that the concepts disclosed below and specific embodiments can be quite easily utilized as a basis for modifying or designing other structures or processes to achieve the same purpose as the present disclosure. Those skilled in the art to which the present disclosure pertains should also understand that such equivalent constructs cannot depart from the spirit and scope of the present disclosure as defined by the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] A more complete understanding of the present disclosure can be obtained by reference to the detailed description and the claims when considered in conjunction with the drawings, in which like reference numerals represent like elements throughout the drawings, and:

[0019] Figure 1 A cross-sectional view of a memory element is shown in accordance with some embodiments.

[0020] Figure 2 A flowchart of a method of fabricating a memory element is shown in accordance with some embodiments.

[0021] Figure 3 A flowchart of a method of fabricating a memory element is shown in accordance with some alternative embodiments.

[0022] Figure 4 An intermediate-stage cross-sectional view showing the formation of a plurality of isolation structures and doping regions in a semiconductor substrate during the formation of a memory element is shown in accordance with some embodiments.

[0023] Figure 5 An intermediate-stage cross-sectional view showing the formation of a bit line contact in the semiconductor substrate during the formation of a memory element is shown in accordance with some embodiments.

[0024] Figure 6 An intermediate-stage cross-sectional view showing the sequential formation of a lower bit line material, a higher bit line material, and a bit line mask material on the semiconductor substrate during the formation of a memory element is shown in accordance with some embodiments.

[0025] Figure 7 An intermediate-stage cross-sectional view showing the etching of the lower bit line material, the higher bit line material, and the bit line mask material to form a plurality of bit line structures and a bit line mask layer during the formation of a memory element is shown in accordance with some embodiments.

[0026] Figure 8 An intermediate-stage cross-sectional view showing the sequential formation of a first spacer material and a sacrificial material covering the bit line mask layer and the semiconductor substrate during the formation of a memory element is shown in accordance with some embodiments.

[0027] Figure 9 Intermediate stage cross-sectional view showing partial removal of the first spacer material and the sacrificial material during the formation of the memory element to form a plurality of first spacer layers and sacrificial layers on the sidewalls of the bit line structure and on the sidewalls of the bit line mask layer, according to some embodiments.

[0028] Figure 10 Intermediate stage cross-sectional view showing sequential formation of a second spacer material and a dielectric layer covering the bit line mask layers, the first spacer layers, the sacrificial layers, and the semiconductor substrate during the formation of the memory element, according to some embodiments.

[0029] Figure 11 Intermediate stage cross-sectional view showing planarization of the second spacer material and the dielectric layer to form a plurality of second spacer layers and expose the bit line mask layers during the formation of the memory element, according to some embodiments.

[0030] Figure 12 Intermediate stage cross-sectional view showing removal of the sacrificial layers to form a plurality of air gaps during the formation of the memory element, according to some embodiments.

[0031] Figure 13 Intermediate stage cross-sectional view showing removal of the dielectric layer during the formation of the memory element, according to some embodiments.

[0032] Figure 14 Intermediate stage cross-sectional view showing etching of the second spacer layers and the semiconductor substrate to form a plurality of openings adjacent to the bit line structures during the formation of the memory element, according to some embodiments.

[0033] Figure 15 Intermediate stage cross-sectional view showing filling of the openings with a lower capacitor contact layer during the formation of the memory element, according to some embodiments.

[0034] Figure 16 Intermediate stage cross-sectional view showing back-etching of the lower capacitor contact layer to form a plurality of lower capacitor contacts during the formation of the memory element, according to some embodiments.

[0035] Figure 17 Intermediate stage cross-sectional view showing formation of a higher capacitor contact layer over the lower capacitor contacts during the formation of the memory element, according to some embodiments.

[0036] Figure 18 Intermediate stage cross-sectional view showing back-etching of the higher capacitor contact layer to form a plurality of higher capacitor contacts during the formation of the memory element, according to some embodiments.

[0037] Figure 19Intermediate stage cross-sectional views showing the formation of a third spacer material covering the bit line mask layer and the higher capacitor contacts during the formation of a memory element, according to some embodiments.

[0038] Figure 20 Intermediate stage cross-sectional views showing the partial removal of the third spacer material to form a plurality of third spacer layers and expose the higher capacitor contacts during the formation of a memory element, according to some embodiments.

[0039] Figure 21 Intermediate stage cross-sectional views showing the formation of a landing pad layer covering the third spacer layers and the higher capacitor contacts during the formation of a memory element, according to some embodiments.

[0040] Figure 22 Intermediate stage cross-sectional views showing the etching of the landing pad layer, the first spacer layers, the second spacer layers, and the third spacer layers to form a plurality of openings during the formation of a memory element, according to some embodiments.

[0041] Figure 23 Intermediate stage cross-sectional views showing the etching of the second spacer layers and the semiconductor substrate to form the openings adjacent to the bit line structures after planarizing the second spacer material and the dielectric layer during the formation of a memory element, according to some embodiments.

[0042] Figure 24 Intermediate stage cross-sectional views showing the formation of the lower capacitor contacts in the openings during the formation of a memory element, according to some embodiments.

[0043] Figure 25 Intermediate stage cross-sectional views showing the formation of the higher capacitor contacts over the lower capacitor contacts during the formation of a memory element, according to some embodiments.

[0044] Figure 26 Intermediate stage cross-sectional views showing the formation of the third spacer layers covering the bit line mask layer, the first spacer layers, the sacrificial layers, and the second spacer layers during the formation of a memory element, according to some embodiments.

[0045] Figure 27 Intermediate stage cross-sectional views showing the etching of the landing pad layer, the first spacer layers, the sacrificial layers, the second spacer layers, and the third spacer layers to form the openings during the formation of a memory element, according to some embodiments.

[0046] Description of reference numerals:

[0047] 10: Method

[0048] 20: Method

[0049] 100: Memory element

[0050] 101: Semiconductor substrate

[0051] 103: Isolation structure

[0052] 105a: Doped region

[0053] 105b: Doped region

[0054] 105c: Doped region

[0055] 107: Bit line contact

[0056] 109: Lower bit line material

[0057] 109a: Lower bit line layer

[0058] 109b: Lower bit line layer

[0059] 111: Higher bit line material

[0060] 111a: Higher bit line layer

[0061] 111b: Higher bit line layer

[0062] 113a: Bit line structure

[0063] 113b: Bit line structure

[0064] 115: Bit line mask material

[0065] 115a: Bit line mask layer

[0066] 115b: Bit line mask layer

[0067] 117: Patterned mask

[0068] 120a: Opening

[0069] 120b: Opening

[0070] 120c: Opening

[0071] 122a: Opening

[0072] 122b: Opening

[0073] 122c: Opening

[0074] 125: First spacer material

[0075] 125a: First spacer layer

[0076] 125b: First spacer layer

[0077] 125c: First spacer layer

[0078] 125d: First spacer layer

[0079] 127: Sacrificial material

[0080] 127a: Sacrificial layer

[0081] 127b: Sacrificial layer

[0082] 127c: Sacrificial layer

[0083] 127d: Sacrificial layer

[0084] 129: Second spacer material

[0085] 129a: Second spacer layer

[0086] 129b: Second spacer layer

[0087] 129b1: Second spacer layer

[0088] 129b2: Second spacer layer

[0089] 129c: Second spacer layer

[0090] 131: Dielectric layer

[0091] 134a: Air gap

[0092] 134b: Air gap

[0093] 134c: Air gap

[0094] 134d: Air gap

[0095] 136a: Opening

[0096] 136b: Opening

[0097] 136c: Opening

[0098] 141: Lower capacitor contact layer

[0099] 141a: Lower capacitor contact

[0100] 141b: Lower capacitor contact

[0101] 141c: Lower capacitor contact

[0102] 143: Lower capacitor contact layer

[0103] 143a: Higher capacitor contact

[0104] 143b: Higher capacitor contact

[0105] 143c: Higher capacitor contact

[0106] 145: Third spacer material

[0107] 145a: Third spacer layer

[0108] 145b: Third spacer layer

[0109] 147: Landing cushion

[0110] 147a: Landing pad

[0111] 147b: Landing pad

[0112] 147c: Landing pad

[0113] 150a: Opening

[0114] 150b: Opening

[0115] 153a: Bottom electrode

[0116] 153b: Bottom electrode

[0117] 155a: Capacitor dielectric layer

[0118] 155b: Capacitor dielectric layer

[0119] 157a: Top electrode

[0120] 157b: Top electrode

[0121] 159a: Capacitor

[0122] 159b: Capacitor

[0123] H1: Height

[0124] H2: Height

[0125] S11: Step

[0126] S13: Step

[0127] S15: Step

[0128] S17: Step

[0129] S19: Step

[0130] S21: Step

[0131] S23: Step

[0132] S25: Step

[0133] S27: Step

[0134] S29: Step

[0135] S31: Step

[0136] S33: Step

[0137] S41: Step

[0138] S43: Step

[0139] S45: Step

[0140] S47: Step

[0141] S49: Step

[0142] S51: Step

[0143] S53: Step

[0144] S55: Step

[0145] S57: Step

[0146] S59: Step

[0147] S61: Step

[0148] S63: Step

[0149] SW1: Side Wall

[0150] SW2: Side Wall

[0151] SW3: Side Wall

[0152] SW4: Side Wall

[0153] SW5: Side Wall

[0154] SW6: Side Wall

[0155] SW7: Side Wall

[0156] SW8: Side Wall

[0157] SW9: Side Wall

[0158] SW10: Side Wall

[0159] SW11: Side Wall

[0160] SW12: Side Wall

[0161] SW13: Side Wall

[0162] SW14: Side Wall

[0163] SW15: Side Wall

[0164] SW16: Side Wall

[0165] T1: Top Surface

[0166] T2: Top Surface

[0167] T3: Top surface

[0168] T4: Top surface

[0169] T5: Top surface Detailed implementation manners

[0170] The following disclosure provides many different embodiments or examples for implementing different components of the embodiments of the present disclosure. The following describes examples of specific elements and their arrangements to simplify the embodiments of the present disclosure. Of course, these are only examples and should not limit the scope of the embodiments of the present disclosure. For example, when it is described in the description that the first component is formed "on" or "above" the second component, it may include an embodiment in which the first component is in direct contact with the second component, and it may also include an embodiment in which other components are formed between the two without direct contact. In addition, the present disclosure may repeat reference signs and / or labels in different embodiments. These repetitions are for the purpose of simplicity and clarity and are not used to define the relationship between the different embodiments and / or structures discussed.

[0171] In addition, the spatially relative terms used herein, such as "below", "beneath", "lower", "above", "upper", and the like, are for the purpose of facilitating the description of the relationship between one element or component shown in the drawings and another element or component. These spatially relative terms are intended to cover different orientations of the element in use or operation in addition to the orientation depicted in the drawings. The element may be turned in a different orientation (rotated 90 degrees or other orientations), and the spatially relative adjectives used therein may be interpreted accordingly.

[0172] Figure 1 According to some embodiments, a cross-sectional view of a memory element 100 is shown. As Figure 1 shown, the memory element 100 includes a semiconductor substrate 101, a plurality of isolation structures 103, and doped regions 105a, 105b, and 105c disposed in the semiconductor substrate 101. In some embodiments, the doped regions 105a, 105b, and 105c are active regions that are electrically isolated from each other by the isolation structures 103. In addition, the memory element 100 includes a bit line contact 107 disposed in the doped region 105a.

[0173] In addition, the memory element 100 includes a plurality of bit line structures 113a and 113b disposed on the semiconductor substrate 101. In some embodiments, the bit line structure 113a includes a lower bit line layer 109a and a higher bit line layer 111a disposed on the lower bit line layer 109a. In some embodiments, the bit line structure 113b includes a lower bit line layer 109b and a higher bit line layer 111b disposed on the lower bit line layer 109b. In addition, bit line mask layers 115a and 115b are respectively disposed on the bit line structures 113a and 113b.

[0174] In some embodiments, lower capacitor contacts 141a, 141b, and 141c are disposed in the semiconductor substrate 101 and extend above the semiconductor substrate 101. In some embodiments, the lower capacitor contacts 141a, 141b, and 141c are adjacent to the bit line structures 113a and 113b. For example, the lower capacitor contact 141a is disposed adjacent to the bit line structure 113a, the lower capacitor contact 141b is disposed between the bit line structures 113a and 113b and adjacent to the bit line structures 113a and 113b, and the lower capacitor contact 141c is disposed adjacent to the bit line structure 113b. In some embodiments, higher capacitor contacts 143a, 143b, and 143c are respectively disposed on the lower capacitor contacts 141a, 141b, and 141c. In some embodiments, the higher capacitor contacts 143a, 143b, and 143c are in direct contact with the lower capacitor contacts 141a, 141b, and 141c respectively.

[0175] In some embodiments, first spacer layers 125a and 125b are disposed on opposite sidewalls of the bit line structure 113a and are in direct contact therewith, and first spacer layers 125c and 125d are disposed on opposite sidewalls of the bit line structure 113b and are in direct contact therewith. In addition, according to some embodiments, the first spacer layers 125a and 125b extend to cover the opposite sidewalls of the bit line mask layer 115a, and the first spacer layers 125c and 125d extend to cover the opposite sidewalls of the bit line mask layer 115b.

[0176] In addition, according to some embodiments, a second spacer layer 129a is disposed between the lower capacitor contact 141a and the first spacer layer 125a and between the higher capacitor contact 143a and the first spacer layer 125a, and an air gap 134a is located between the first spacer layer 125a and the second spacer layer 129a. In some embodiments, a second spacer layer 129b1 is disposed between the lower capacitor contact 141b and the first spacer layer 125b and between the higher capacitor contact 143b and the first spacer layer 125b, and an air gap 134b is located between the first spacer layer 125b and the second spacer layer 129b1.

[0177] In some embodiments, a second spacer layer 129b2 is disposed between the lower capacitor contact 141b and the first spacer layer 125c and between the upper capacitor contact 143b and the first spacer layer 125c, and an air gap 134c is located between the first spacer layer 125c and the second spacer layer 129b2. In some embodiments, a second spacer layer 129c is disposed between the lower capacitor contact 141c and the first spacer layer 125d and between the upper capacitor contact 143c and the first spacer layer 125d, and an air gap 134d is located between the first spacer layer 125d and the second spacer layer 129c.

[0178] The memory also includes third spacer layers 145a and 145b. In some embodiments, the third spacer layer 145a covers the bit line mask layer 115a, the first spacer layer 125b, and the second spacer layer 129b1, and the third spacer layer 145a extends to directly contact the upper capacitor contacts 143a and 143b. In some embodiments, the third spacer layer 145b covers the bit line mask layer 115b, the first spacer layer 125d, and the second spacer layer 129c, and the third spacer layer 145b extends to directly contact the upper capacitor contacts 143b and 143c. In some embodiments, the air gap 134b is sealed by the third spacer layer 145a, and the air gap 134d is sealed by the third spacer layer 145b.

[0179] The memory element 100 further includes landing pads 147a, 147b, and 147c disposed respectively above the upper capacitor contacts 143a, 143b, and 143c. In some embodiments, the landing pads extend over one of the adjacent bit line mask layers. For example, according to some embodiments, the landing pad 147b extends over the bit line mask layer 115a, and the landing pad 147c extends over the bit line mask layer 115b.

[0180] In some embodiments, the first spacer layer 125a, the air gap 134a, and the second spacer layer 129a extend between the bit line mask layer 115a and the landing pad 147a. In some embodiments, the first spacer layer 125b, the air gap 134b, and the second spacer layer 129b1 extend between the bit line mask layer 115a and the landing pad 147b. In some embodiments, the first spacer layer 125c, the air gap 134c, and the second spacer layer 129b2 extend between the bit line mask layer 115b and the landing pad 147b. In some embodiments, the first spacer layer 125d, the air gap 134d, and the second spacer layer 129c extend between the bit line mask layer 115b and the landing pad 147c.

[0181] In some embodiments, the bit line mask layer 115a, the first spacer layer 125b, the air gap 134b, and the second spacer layer 129b1 are separated from the landing pad 147b by a third spacer layer 145a. In some embodiments, the bit line mask layer 115b, the first spacer layer 125d, the air gap 134d, and the second spacer layer 129c are separated from the landing pad 147c by a third spacer layer 145b.

[0182] In addition, according to some embodiments, the memory element 100 includes a capacitor 159a disposed over the first spacer layer 125a, the air gap 134a, and the second spacer layer 129a, and a capacitor 159b disposed over the first spacer layer 125c, the air gap 134c, and the second spacer layer 129b2. In some embodiments, the capacitor 159a includes a bottom electrode 153a, a top electrode 157a disposed over and surrounded by the bottom electrode 153a, and a capacitor dielectric layer 155a sandwiched between the bottom electrode 153a and the top electrode 157a. In some embodiments, the capacitor 159b includes a bottom electrode 153b, a top electrode 157b disposed over and surrounded by the bottom electrode 153b, and a capacitor dielectric layer 155b sandwiched between the bottom electrode 153b and the top electrode 157b.

[0183] The present disclosure provides embodiments of a memory element 100 and a method of fabricating the same. In some embodiments, the lower capacitor contacts 141a, 141b, 141c and the higher capacitor contacts 143a, 143b, 143c include different materials. In some embodiments, the lower capacitor contacts 141a, 141b, 141c include polysilicon, and the higher capacitor contacts 143a, 143b, 143c include titanium nitride (TiN). In some embodiments, the lower capacitor contacts 141a, 141b, 141c have a height H1, the higher capacitor contacts 143a, 143b, 143c have a height H2, and the height H2 is greater than or equal to the height H1. In some embodiments, the ratio of the height H2 to the height H1 is in the range of about 1 to about 1.5. Accordingly, the sheet resistance of the capacitor contacts can be reduced while eliminating or suppressing junction leakage current. In addition, the air gaps 134a, 134b, 134c, and 134d can help reduce parasitic capacitance and accordingly improve device performance (e.g., by reducing signal noise). As a result, the performance of the memory element 100 can be improved.

[0184] Figure 2 A flowchart showing a method 10 of fabricating a memory element 100 according to some embodiments, and the method 10 includes steps S11, S13, S15, S17, S19, S21, S23, S25, S27, S29, S31, and S33. In conjunction withFigures 4 to 22 Step S11 to S33 of Figure 2 will be described in detail.

[0185] Figure 3 A flowchart showing a method 20 of fabricating a memory element 100 according to some alternative embodiments is presented, and the method 20 includes steps S41, S43, S45, S47, S49, S51, S53, S55, S57, S59, S61, and S63. In conjunction with Figures 23 to 27 Step S41 to S63 of Figure 3 will be described in detail.

[0186] Figures 4 to 22 A cross-sectional view of an intermediate stage of forming a memory element 100 is shown according to some embodiments.

[0187] As Figure 4 shown, a semiconductor substrate 101 is provided. The semiconductor substrate 101 may be a semiconductor wafer, such as a silicon wafer. Optionally or additionally, the semiconductor substrate 101 may include elemental semiconductor materials, compound semiconductor materials, and / or alloy semiconductor materials. Examples of elemental semiconductor materials may include but are not limited to crystalline silicon, polysilicon, amorphous silicon, germanium, and / or diamond. Examples of compound semiconductor materials may include but are not limited to silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide. Examples of alloy semiconductor materials may include but are not limited to SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP.

[0188] In some embodiments, the semiconductor substrate 101 includes an epitaxial layer. For example, the semiconductor substrate 101 has an epitaxial layer covering a bulk semiconductor. In some embodiments, the semiconductor substrate 101 is a semiconductor-on-insulator substrate, which may include a substrate, a buried oxide layer located above the substrate, and a semiconductor layer located above the buried oxide layer, such as a silicon-on-insulator (SOI) substrate, a silicon germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. Separation by implantation oxygen (SIMOX), wafer bonding, and / or other applicable methods can be used to fabricate the semiconductor-on-insulator substrate.

[0189] Still referring to Figure 4, According to some embodiments, an isolation structure 103 is formed in a semiconductor substrate 101, and the isolation structure 103 is a shallow trench isolation (STI) structure. In addition, the isolation structure 103 may include silicon oxide, silicon nitride, silicon oxynitride, or another applicable dielectric material, and the formation of the isolation structure 103 may include forming a patterned mask (not shown) on the semiconductor substrate 101, etching the semiconductor substrate 101 using the patterned mask as a mask to form a plurality of openings (not shown), depositing a dielectric material in the openings and on the semiconductor substrate 101, and planarizing the dielectric material until the semiconductor substrate 101 is exposed.

[0190] In addition, doped regions 105a, 105b, and 105c are formed in the active regions defined by the isolation structure 103. In some embodiments, the fabrication techniques for the doped regions 105a, 105b, and 105c include one or more ion implantation processes, and depending on the conduction type of the memory element 100, a P-type dopant such as boron (B), gallium (Ga), or indium (In), or an N-type dopant such as phosphorus (P) or arsenic (As) may be implanted into the active regions to form the doped regions 105a, 105b, and 105c. In addition, the doped regions 105a, 105b, and 105c will become the source / drain regions of the memory element 100 in subsequent processes.

[0191] As Figure 5 shown, according to some embodiments, after forming the isolation structure 103 and the doped regions 105a, 105b, and 105c, a bit line contact 107 is formed in the semiconductor substrate 101. In some embodiments, the bit line contact 107 is formed in the doped region 105a. In some embodiments, the bit line contact 107 includes doped polysilicon, metal, metal silicide, or another applicable conductive material, and the formation of the bit line contact 107 includes forming a patterned mask (not shown) on the semiconductor substrate 101, etching the semiconductor substrate 101 using the patterned mask as a mask to form an opening (not shown), depositing a conductive material in the opening and on the semiconductor substrate 101, and planarizing the conductive material until the semiconductor substrate 101 is exposed.

[0192] Next, as Figure 6As shown, according to some embodiments, a lower bit line material 109, a higher bit line material 111, a bit line mask material 115, and a patterned mask 117 are sequentially formed on a semiconductor substrate 101. In some embodiments, the patterned mask 117 has openings 120a, 120b, and 120c that expose the bit line mask material 115. In some embodiments, the lower bit line material 109 includes titanium nitride (TiN), tantalum nitride (TaN), tantalum carbide (TaC), and titanium carbide (TiC), or another suitable conductive material.

[0193] In some embodiments, the higher bit line material 111 includes tungsten (W), titanium (Ti), nickel (Ni), cobalt (Co), or a combination of the foregoing. In some embodiments, the bit line mask material 115 includes silicon nitride. However, this material is only an example. Any other suitable material can be optionally used to form the bit line mask material 115. In some embodiments, the bit line mask material 115 and the patterned mask 117 include different materials such that the etch selectivity can be different in subsequent etching processes.

[0194] Furthermore, according to some embodiments, the fabrication technique of the lower bit line material 109 includes deposition processes such as chemical vapor deposition (CVD) processes, physical vapor deposition (PVD) processes, atomic layer deposition (ALD) processes, spin-on coating processes, sputtering processes, or another suitable deposition process. Some processes for forming the higher bit line material 111 and the bit line mask material 115 are similar to or the same as those for forming the lower bit line material 109, and the details thereof will not be repeated here.

[0195] Subsequently, as Figure 7 shown, according to some embodiments, an etching process is performed using the patterned mask 117 as an etching mask to form bit line structures 113a and 113b. The corresponding steps are shown as step S11 in method 10 shown in Figure 2 In some embodiments, openings 122a, 122b, and 122c are formed through the bit line mask material 115, the higher bit line material 111, and the lower bit line material 109. After the etching process, the bit line structures 113a and 113b are separated from each other, and the bit line structures 113a and 113b are covered by the remaining portions of the bit line mask material 115, and the remaining portions of the bit line mask material 115 are referred to as bit line mask layers 115a and 115b.

[0196] In some embodiments, the bit line structure 113a includes a lower bit line layer 109a and a higher bit line layer 111a, and the bit line structure 113a is covered by a bit line mask layer 115a. In some embodiments, the bit line structure 113b includes a lower bit line layer 109b and a higher bit line layer 111b, and the bit line structure 113b is covered by a bit line mask layer 115b.

[0197] In addition, according to some embodiments, the opening 122a exposes the sidewall SW1 of the bit line structure 113a and the sidewall SW5 of the bit line mask layer 115a. In some embodiments, the opening 122b exposes the sidewall SW2 of the bit line structure 113a, the sidewall SW6 of the bit line mask layer 115a, the sidewall SW3 of the bit line structure 113b, and the sidewall SW7 of the bit line mask layer 115b. In some embodiments, the opening 122c exposes the sidewall SW4 of the bit line structure 113b and the sidewall SW8 of the bit line mask layer 115b.

[0198] In some embodiments, the etching process for forming the bit line structures 113a, 113b and the bit line mask layers 115a, 115b includes a wet etching process, a dry etching process, or a combination of the foregoing. After forming the bit line structures 113a and 113b, the patterned mask 117 can be removed, exposing the top surfaces T1 and T2 of the bit line mask layers 115a and 115b. In some embodiments, the patterned mask 117 is removed by an ashing process or a wet etching process.

[0199] Then, according to some embodiments, a first spacer material 125 and a sacrificial material 127 are sequentially formed on the Figure 7 structure. In some embodiments, as Figure 8 shown, the first spacer material 125 and the sacrificial material 127 are conformally deposited on the bit line mask layers 115a, 115b and line the openings 122a, 122b and 122c. In some embodiments, the first spacer material 125 covers the sidewalls SW1, SW2 of the bit line structure 113a, the sidewalls SW3, SW4 of the bit line structure 113b, the top surface T1 and the sidewalls SW5, SW6 of the bit line mask layer 115a, the top surface T2 and the sidewalls SW7, SW8 of the bit line mask layer 115b, and the top surface of the semiconductor substrate 101. In some embodiments, the sacrificial material 127 covers the first spacer material 125.

[0200] In some embodiments, the first spacer material 125 and the sacrificial material 127 comprise different materials. In some embodiments, the first spacer material 125 comprises silicon nitride, while the sacrificial material 127 comprises silicon oxide. In some embodiments, the fabrication techniques for the first spacer material 125 and the sacrificial material 127 include deposition processes such as CVD, PVD, ALD, spin coating, or another suitable process.

[0201] Next, as Figure 9 shown, according to some embodiments, an etching process is performed on the first spacer material 125 and the sacrificial material 127 to remove the horizontal portions of the first spacer material 125 and the sacrificial material 127, leaving the vertical portions of the first spacer material 125 and the sacrificial material 127. The remaining vertical portions of the first spacer material 125 and the sacrificial material 127 are referred to as the first spacer layers 125a, 125b, 125c, 125d and the sacrificial layers 127a, 127b, 127c, 127d. In some embodiments, the etching process is an anisotropic etching process.

[0202] In some embodiments, the first spacer layer 125a is disposed on the sidewall SW1 of the bit line structure 113a and the sidewall SW5 of the bit line mask layer 115a, the first spacer layer 125b is disposed on the sidewall SW2 of the bit line structure 113a and the sidewall SW6 of the bit line mask layer 115a, the first spacer layer 125c is disposed on the sidewall SW3 of the bit line structure 113b and the sidewall SW7 of the bit line mask layer 115b, and the first spacer layer 125d is disposed on the sidewall SW4 of the bit line structure 113b and the sidewall SW8 of the bit line mask layer 115b. In addition, in some embodiments, the sacrificial layer 127a is disposed on the sidewall SW9 of the first spacer layer 125a, the sacrificial layer 127b is disposed on the sidewall SW10 of the first spacer layer 125b, the sacrificial layer 127c is disposed on the sidewall SW11 of the first spacer layer 125c, and the sacrificial layer 127d is disposed on the sidewall SW12 of the first spacer layer 125d. According to some embodiments, after the etching process, the top surfaces T1 of the bit line mask layer 115a and T2 of the bit line mask layer 115b are exposed.

[0203] Subsequently, as Figure 10 shown, according to some embodiments, a second spacer material 129 is formed over the Figure 9 structure, and a dielectric layer 131 is formed over the second spacer material 129. In some embodiments, the second spacer material 129 is formed to cover the bit line mask layers 115a, 115b, the first spacer layers 125a, 125b, 125c, 125d, and the sacrificial layers 127a, 127b, 127c, 127d, and to line the openings 122a, 122b and 122c (refer to Figure 9)。In some embodiments, the remaining portions of the openings 122a, 122b, and 122c are filled with the dielectric layer 131, and the dielectric layer 131 extends over the bit line mask layers 115a and 115b.

[0204] In some embodiments, the second spacer material 129 and the sacrificial material 127 comprise different materials. In some embodiments, the second spacer material 129 comprises silicon nitride, while the sacrificial material 127 comprises silicon oxide. In some embodiments, the dielectric layer 131 comprises silicon oxide, silicon nitride, silicon oxynitride, or another applicable dielectric material. In some embodiments, the fabrication techniques for the second spacer material 129 and the dielectric layer 131 include deposition processes such as CVD, PVD, ALD, spin coating, or another suitable process.

[0205] Then, as Figure 11 shown, according to some embodiments, a planarization process is performed to expose the bit line mask layers 115a and 115b. In some embodiments, the dielectric layer 131 and the second spacer material 129 are partially removed by the planarization process, and the remaining portions of the second spacer material 129 are referred to as the second spacer layers 129a, 129b, and 129c. In some embodiments, the planarization process includes a chemical mechanical polishing (CMP) process.

[0206] After the planarization process is performed, the top surface T1 of the bit line mask layer 115a and the top surface T2 of the bit line mask layer 115b are exposed. In some embodiments, the first spacer layer 125a, the sacrificial layer 127a, and the second spacer layer 129a are disposed on the sidewall SW1 of the bit line structure 113a and the sidewall SW5 of the bit line mask layer 115a. In some embodiments, a portion of the first spacer layer 125b, the sacrificial layer 127b, and the second spacer layer 129b is disposed on the sidewall SW2 of the bit line structure 113a and the sidewall SW6 of the bit line mask layer 115a. In some embodiments, a portion of the first spacer layer 125c, the sacrificial layer 127c, and the second spacer layer 129b is disposed on the sidewall SW3 of the bit line structure 113b and the sidewall SW7 of the bit line mask layer 115b. In some embodiments, the first spacer layer 125d, the sacrificial layer 127d, and the second spacer layer 129c are disposed on the sidewall SW4 of the bit line structure 113b and the sidewall SW8 of the bit line mask layer 115b. The corresponding steps are shown as step S13 in the Figure 2 method 10 shown.

[0207] Next, as Figure 12As shown, according to some embodiments, the sacrificial layers 127a, 127b, 127c, and 127d are removed to form air gaps 134a, 134b, 134c, and 134d. The corresponding steps are shown as step S15 in the method 10 shown in Figure 2 In some embodiments, the dielectric layer 131 includes a material different from that of the sacrificial layers 127a, 127b, 127c, and 127d, such that there is an etching selectivity between them. For example, the sacrificial layers 127a, 127b, 127c, and 127d include doped oxide materials such as borophosphosilicate glass (BPSG), while the dielectric layer 131 includes a CVD oxide material that is denser than the doped oxide material. In some embodiments, the sacrificial layers 127a, 127b, 127c, and 127d are removed by an etching process such as a dry etching process or a wet etching process.

[0208] As Figure 13 shown, according to some embodiments, after removing the sacrificial layers 127a, 127b, 127c, and 127d, the dielectric layer 131 is removed. In some embodiments, the dielectric layer 131 is removed by an etching process such as a wet etching process. After removing the dielectric layer 131, the openings 122a, 122b, and 122c expose the second spacer layers 129a, 129b, and 129c, respectively.

[0209] Subsequently, as Figure 14 shown, according to some embodiments, an etching process is performed to remove the horizontal portions of the second spacer layers 129a, 129b, and 129c, thereby exposing the semiconductor substrate 101, and openings 136a, 136b, and 136c are formed in the semiconductor substrate 101 by further etching the semiconductor substrate 101. In some embodiments, the openings 136a, 136b, and 136c are formed adjacent to the bit line structures 113a and 113b and below the openings 122a, 122b, and 122c. The corresponding steps are shown as step S17 in the method 10 shown in Figure 2 shown.

[0210] In some embodiments, the horizontal portions of the second spacer layers 129a, 129b, and 129c are removed by a dry etching process. In some embodiments, the semiconductor substrate 101 is etched by an etching process that includes a dry etching process or a wet etching process. The remaining portions of the second spacer layers 129a, 129b, and 129c are referred to as the second spacer layers 129a, 129b1, 129b2, and 129c, as Figure 14 shown.

[0211] Then, as Figure 15 shown, according to some embodiments, a lower capacitor contact layer 141 is formed inFigure 14 on the structure of, and fill the openings 122a, 122b, 122c, 136a, 136b and 136c with a lower capacitor contact layer 141. In some embodiments, the bit line mask layers 115a, 115b, the first spacer layers 125a, 125b, 125c, 125d, and the second spacer layers 129a, 129b1, 129b2, 129c are covered by the lower capacitor contact layer 141, and the air gaps 134a, 134b, 134c and 134d are sealed by the lower capacitor contact layer 141. The corresponding steps are shown as step S19 in Figure 2 the method 10 shown in. In some embodiments, the lower capacitor contact layer 141 includes polysilicon, and its manufacturing technology includes deposition processes such as CVD process, PVD process, ALD process, spin coating process, or another suitable deposition process.

[0212] Next, as Figure 16 shown, according to some embodiments, a re-etching process is performed on the lower capacitor contact layer 141 to expose the sidewalls SW13, SW14, SW15 and SW16 of the second spacer layers 129a, 129b1, 129b2 and 129c. The remaining portions of the lower capacitor contact layer 141 are referred to as lower capacitor contacts 141a, 141b and 141c. The corresponding steps are shown as step S21 in Figure 2 the method 10 shown in. In some embodiments, the re-etching process includes a dry etching process, a wet etching process, or a combination of the foregoing.

[0213] As Figure 17 shown, according to some embodiments, after forming the lower capacitor contacts 141a, 141b and 141c, a higher capacitor contact layer 143 is formed on Figure 16 the structure of, and fill the openings 122a, 122b, 122c with the higher capacitor contact layer 143. In some embodiments, the lower capacitor contacts 141a, 141b, 141c, the bit line mask layers 115a, 115b, the first spacer layers 125a, 125b, 125c, 125d, and the second spacer layers 129a, 129b1, 129b2, 129c are covered by the higher capacitor contact layer 143, and the air gaps 134a, 134b, 134c and 134d are sealed by the higher capacitor contact layer 143. The corresponding steps are shown as step S23 in Figure 2 the method 10 shown in. In some embodiments, the higher capacitor contact layer 143 includes titanium nitride (TiN), and its manufacturing technology includes deposition processes such as CVD process, PVD process, ALD process, spin coating process, or another suitable deposition process.

[0214] Subsequently, as Figure 18As shown, according to some embodiments, a re-etching process is performed on the higher capacitor contact layer 143 to expose the sidewalls SW13, SW14, SW15, and SW16 of the second spacer layers 129a, 129b1, 129b2, and 129c. The remaining portions of the higher capacitor contact layer 143 are referred to as the higher capacitors contacts 143a, 143b, and 143c. The corresponding steps are shown as step S25 in the method 10 shown in Figure 2 In some embodiments, the re-etching process includes a dry etching process, a wet etching process, or a combination of the foregoing. According to some embodiments, after forming the higher capacitors contacts 143a, 143b, and 143c, the top surfaces T1 and T2 of the bit line mask layers 115a and 115b are higher than the top surfaces T3, T4, and T5 of the higher capacitors contacts 143a, 143b, and 143c.

[0215] According to some embodiments, after forming the higher capacitors contacts 143a, 143b, and 143c, a third spacer material 145 is formed on top of the Figure 18 structure. In some embodiments, as Figure 19 shown, the top surfaces T1, T2 of the bit line mask layers 115a, 115b and the top surfaces T3, T4, T5 of the higher capacitors contacts 143a, 143b, 143c are covered by the third spacer material 145. In some embodiments, the first spacer layers 125a, 125b, 125c, 125d and the second spacer layers 129a, 129b1, 129b2, 129c are covered by the third spacer material 145, and the air gaps 134a, 134b, 134c, 134d are sealed by the third spacer material 145. In some embodiments, the third spacer material 145 includes silicon nitride, and its fabrication technique includes a deposition process, such as a CVD process, a PVD process, an ALD process, a spin coating process, or a combination of the foregoing.

[0216] Then, as Figure 20 shown, according to some embodiments, an etching process is performed on top of the third spacer material 145 to expose the top surfaces T3, T4, T5 of the higher capacitors contacts 143a, 143b, 143c. In some embodiments, the remaining portions of the third spacer material 145 are referred to as the third spacer layers 145a and 145b. In some embodiments, the etching process includes a dry etching process, a wet etching process, or a combination of the foregoing.

[0217] In some embodiments, the bit line mask layer 115a, the first spacer layers 125a, 125b, and the second spacer layers 129a, 129b1 are covered by a third spacer layer 145a, and the air gaps 134a, 134b are sealed by the third spacer layer 145a. In some embodiments, the bit line mask layer 115b, the first spacer layers 125c, 125d, and the second spacer layers 129b2, 129c are covered by a third spacer layer 145b, and the air gaps 134c, 134d are sealed by the third spacer layer 145b. The corresponding steps are shown as step S27 in Figure 2 method 10 shown.

[0218] Next, as Figure 21 shown, according to some embodiments, a landing pad layer 147 is formed over the third spacer layers 145a, 145b and the higher capacitor contacts 143a, 143b, 143c. The corresponding steps are shown as step S29 in Figure 2 method 10 shown. In some embodiments, the landing pad layer 147 includes a conductive material such as copper (Cu), tungsten (W), aluminum (Al), titanium (Ti), tantalum (Ta), gold (Au), silver (Ag). Fabrication techniques for the landing pad layer 147 may include deposition processes such as CVD processes, PVD processes, sputtering processes, electroplating processes, or another suitable deposition process.

[0219] Subsequently, as Figure 22 shown, according to some embodiments, an etching process is performed to form openings 150a and 150b. In some embodiments, portions of the landing pad layer 147, the first spacer layers 125a, 125c, the second spacer layers 129a, 129b2, the third spacer layers 145a, 145b, and the bit line mask layers 115a, 115b are removed. The remaining portions of the landing pad layer 147 are referred to as landing pads 147a, 147b, and 147c. In some embodiments, the etching process includes a wet etching process, a dry etching process, or a combination of the foregoing. The corresponding steps are shown as step S31 in Figure 2 method 10 shown.

[0220] Then, referring to Figure 1 shown, according to some embodiments, capacitors 159a and 159b are formed in the openings 150a and 150b. In some embodiments, the air gaps 134a and 134c are respectively sealed by the capacitors 159a and 159b. The corresponding steps are shown as step S33 in Figure 2 method 10 shown.

[0221] As described above, capacitor 159a includes a bottom electrode 153a, a top electrode 157a, and a capacitor dielectric layer 155a sandwiched between the bottom electrode 153a and the top electrode 157a, while capacitor 159b includes a bottom electrode 153b, a top electrode 157b, and a capacitor dielectric layer 155b sandwiched between the bottom electrode 153b and the top electrode 157b. The formation of capacitors 159a and 159b may include sequentially depositing a conductive material, a dielectric material, and another conductive material into openings 150a and 150b (refer to Figure 22 ) and extending over landing pads 147a, 147b, and 147c, and performing a planarization process (e.g., CMP process) to remove excess portions of the two conductive materials and the dielectric material.

[0222] In some embodiments, bottom electrodes 153a and 153b include titanium nitride (TiN), capacitor dielectric layers 155a and 155b include a dielectric material such as silicon dioxide (SiO2), hafnium dioxide (HfO2), aluminum oxide (Al2O3), zirconium dioxide (ZrO2), or a combination of the foregoing, and top electrodes 157a and 157b include titanium nitride (TiN), low-stress silicon germanium (SiGe), or a combination of the foregoing. After forming capacitors 159a and 159b, a memory element 100 including capacitor contacts having different materials (e.g., polysilicon and titanium nitride (TiN)) is obtained. In some embodiments, memory element 100 is part of a DRAM.

[0223] Figures 23 to 27 An intermediate stage cross-sectional view showing the formation of memory element 100 is shown according to some alternative embodiments. It should be noted that the operations prior to the structure shown in Figure 23 are substantially the same as the operations shown in Figures 4 to 11 (steps S41 and S43 in method 20 shown in Figure 3 are the same as steps S11 and S13 in method 10 shown in Figure 2 ), and the relevant detailed description can be referred to the foregoing paragraphs and will not be discussed here.

[0224] As Figure 23 shown, according to some embodiments, after performing the planarization process, dielectric layer 131 is removed, and an etching process is performed to remove the horizontal portions of second spacer layers 129a, 129b, and 129c, thereby exposing semiconductor substrate 101, and openings 136a, 136b, and 136c are formed in semiconductor substrate 101 by further etching semiconductor substrate 101. Figure 23 The structure of Figure 14has a similar structure, except that in this embodiment, when forming the openings 136a, 136b, and 136c, the sacrificial layers 127a, 127b, 127c, and 127d are not removed. The corresponding steps are shown as step S45 in Figure 3 the method 20 shown.

[0225] In some embodiments, the horizontal portions of the second spacer layers 129a, 129b, and 129c are removed by a dry etching process. In some embodiments, the semiconductor substrate 101 is etched by an etching process that includes a dry etching process or a wet etching process. The remaining portions of the second spacer layers 129a, 129b, and 129c are referred to as the second spacer layers 129a, 129b1, 129b2, and 129c, as Figure 23 shown.

[0226] Next, as Figure 24 shown, according to some embodiments, lower capacitor contacts 141a, 141b, and 141c are formed in the openings 136a, 136b, and 136c and extend over the semiconductor substrate 101. Some of the materials and processes for forming the Figure 24 lower capacitor contacts 141a, 141b, and 141c in Figure 15 and Figure 16 are similar or the same as those for forming the lower capacitor contacts 141a, 141b, and 141c in Figure 3 shown, and the details thereof are not repeated herein. The corresponding steps are shown as steps S47 and S49 in the method 20 shown in

[0227] Subsequently, as Figure 25 shown, according to some embodiments, upper capacitor contacts 143a, 143b, and 143c are formed in the openings 122a, 122b, and 122c and on top of the lower capacitor contacts 141a, 141b, and 141c. Some of the materials and processes for forming the Figure 25 upper capacitor contacts 143a, 143b, and 143c in Figure 17 and Figure 18 are similar or the same as those for forming the upper capacitor contacts 143a, 143b, and 143c in

[0228] The corresponding steps are shown as steps S51 and step S53 in the method 20 shown in Figure 3 shown. According to some embodiments, after forming the upper capacitor contacts 143a, 143b, and 143c, the top surfaces T1 and T2 of the bit line mask layers 115a and 115b are higher than the top surfaces T3, T4, and T5 of the upper capacitor contacts 143a, 143b, and 143b.

[0229] Then, asFigure 26 As shown, according to some embodiments, third spacer layers 145a and 145b are formed. In some embodiments, the third spacer layer 145a is formed to cover the bit line mask layer 115a, the first spacer layers 125a, 125b, the sacrificial layers 127a, 127b, and the second spacer layers 129a, 129b1, and the third spacer layer 145a extends to contact the higher capacitor contacts 143a and 143b. In some embodiments, the third spacer layer 145b is formed to cover the bit line mask layer 115b, the first spacer layers 125c, 125d, the sacrificial layers 127c, 127d, and the second spacer layers 129b2, 129c, and the third spacer layer 145b extends to contact the higher capacitor contacts 143b and 143c.

[0230] For forming Figure 26 the third spacer layers 145a and 145b in Figure 19 and Figure 20 the materials and processes for forming the third spacer layers 145a and 145b in Figure 3 are similar or the same as those for forming the third spacer layers 145a and 145b in

[0231] Next, as Figure 27 shown, according to some embodiments, landing pads 147a, 147b, 147c and openings 150a, 150b are formed. For forming Figure 27 the landing pads 147a, 147b, 147c and openings 150a, 150b in Figure 21 and Figure 22 the materials and processes for forming the landing pads 147a, 147b and 147c in Figure 3 are similar or the same as those for forming the landing pads 147a, 147b and 147c in

[0232] Subsequently, as Figure 1 shown, according to some embodiments, the sacrificial layers 127a, 127b, 127c and 127d are removed through the openings 150a and 150b, and capacitors 159a and 159b are formed in the openings 150a and 150b. In some embodiments, an etching process is performed to remove the sacrificial layers 127a, 127b, 127c and 127d, thereby forming air gaps 134a, 134b, 134c and 134d. In some embodiments, the etching process includes a dry etching process, a wet etching process, or a combination of the foregoing.

[0233] According to some embodiments, after forming capacitors 159a and 159b, air gaps 134a and 134b are sealed by capacitors 159a and 159b. The corresponding steps are shown as step S61 and step S63 in Figure 3 method 20 shown. Some of the materials and processes used to form capacitors 159a and 159b in this embodiment are similar to or the same as those used to form capacitors 159a and 159b in the previous embodiment, and the details thereof will not be repeated here.

[0234] The present disclosure provides embodiments of a memory element 100 and a method for manufacturing the same. In some embodiments, the lower capacitor contacts 141a, 141b, 141c and the higher capacitor contacts 143a, 143b, 143c include different materials. For example, the lower capacitor contacts 141a, 141b, 141c include polysilicon, while the higher capacitor contacts 143a, 143b, 143c include titanium nitride (TiN). In some embodiments, the lower capacitor contacts 141a, 141b, 141c have a height H1, the higher capacitor contacts 143a, 143b, 143c have a height H2, and the height H2 is greater than or equal to the height H1. For example, the ratio of the height H2 to the height H1 is in the range of about 1 to about 1.5. Therefore, the sheet resistance of the capacitor contacts can be reduced while eliminating or suppressing junction leakage current. In addition, the air gaps 134a, 134b, 134c and 134d can help reduce parasitic capacitance and accordingly improve device performance (e.g., by reducing signal noise). As a result, the performance of the memory element 100 can be improved.

[0235] In an embodiment of the present disclosure, a memory element is provided. The memory element includes: a bit line structure disposed on a semiconductor substrate, and a lower capacitor contact disposed in the semiconductor substrate and extending above the semiconductor substrate. The lower capacitor contact includes polysilicon. The memory element also includes a higher capacitor contact disposed on the lower capacitor contact. The higher capacitor contact includes titanium nitride (TiN). The memory element further includes a first spacer layer disposed between the lower capacitor contact and the bit line structure and between the higher capacitor contact and the bit line structure. In addition, the memory element includes a capacitor disposed on the first spacer layer.

[0236] In another embodiment of the present disclosure, a memory element is provided. The memory element includes: a bit line structure disposed on a semiconductor substrate, and a lower capacitor contact disposed in the semiconductor substrate and extending above the semiconductor substrate. The memory element also includes a higher capacitor contact disposed on the lower capacitor contact. The higher capacitor contact and the lower capacitor contact include different materials. The memory element further includes a first spacer layer disposed between the lower capacitor contact and the bit line structure and between the higher capacitor contact and the bit line structure. In addition, the memory element includes a capacitor disposed on the first spacer layer, and a landing pad disposed on and in direct contact with the higher capacitor contact.

[0237] In another embodiment of the present disclosure, a method for manufacturing a memory element is provided. The method includes: forming a bit line structure on a semiconductor substrate, and forming a first spacer layer and a second spacer layer on a sidewall of the bit line structure. The method also includes etching the second spacer layer and the semiconductor substrate to form a first opening adjacent to the bit line structure, and filling the first opening with a lower capacitor contact. The lower capacitor contact protrudes above the semiconductor substrate. The method further includes forming a higher capacitor contact on the lower capacitor contact. The higher capacitor contact and the lower capacitor contact include different materials. In addition, the method includes forming a landing pad on the higher capacitor contact, etching the landing pad, the first spacer layer and the second spacer layer to form a second opening, and forming a capacitor in the second opening.

[0238] Embodiments of the present disclosure have some advantageous features. By forming the lower capacitor contact and the higher capacitor contact with different materials (for example, the lower capacitor contact includes polysilicon while the higher capacitor contact includes titanium nitride), the sheet resistance of the capacitor contact can be reduced while eliminating or suppressing junction leakage current. As a result, the performance of the memory element can be improved.

[0239] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alterations can be made without departing from the spirit and scope of the present disclosure as defined by the claims. For example, many of the above processes can be implemented in different ways, and many of the above processes can be replaced with other processes or combinations of the foregoing.

[0240] Moreover, the scope of the present application is not limited to the specific embodiments of the processes, machines, manufactures, compositions of matter, means, methods, and steps described in the specification. Those skilled in the art can understand from the disclosure of the present disclosure that existing or future-developed processes, machines, manufactures, compositions of matter, means, methods, or steps that can be used according to the present disclosure and have the same functions or achieve substantially the same results as the corresponding embodiments described herein. Accordingly, these processes, machines, manufactures, compositions of matter, means, methods, or steps are included in the claims of the present application.

Claims

1. A memory element, comprising: A bit line structure disposed on a semiconductor substrate; A lower capacitor contact disposed in the semiconductor substrate and extending above the semiconductor substrate, wherein the lower capacitor contact comprises polysilicon; A higher capacitor contact disposed on the lower capacitor contact, wherein the higher capacitor contact comprises titanium nitride; A first spacer layer disposed between the lower capacitor contact and the bit line structure and between the higher capacitor contact and the bit line structure; And A capacitor disposed on the first spacer layer.

2. The memory element according to claim 1, wherein the higher capacitor contact is in direct contact with the lower capacitor contact.

3. The memory element according to claim 1, wherein a height of the higher capacitor contact is greater than or equal to a height of the lower capacitor contact.

4. The memory element according to claim 1, wherein a ratio of a height of the higher capacitor contact to a height of the lower capacitor contact is in a range of about 1 to about 1.

5.

5. The memory element according to claim 1, further comprising: A second spacer layer disposed between the lower capacitor contact and the first spacer layer and between the higher capacitor contact and the first spacer layer, wherein an air gap is disposed between the first spacer layer and the second spacer layer.

6. The memory element according to claim 1, further comprising: A bit line mask layer disposed on the bit line structure, wherein the capacitor is disposed on the bit line mask layer and in direct contact with the bit line mask layer.

7. The memory element according to claim 6, wherein a top surface of the bit line mask layer is higher than a top surface of the higher capacitor contact.

8. The memory element according to claim 6, further comprising: A third spacer layer covering the bit line mask layer, wherein the third spacer layer extends to contact the higher capacitor contact.

9. The memory element according to claim 8, further comprising: A landing pad disposed on the higher capacitor contact, wherein the landing pad is in direct contact with the third spacer layer.

10. The memory element according to claim 9, wherein the landing pad is in direct contact with the higher capacitor contact.

11. A memory element, comprising: A bit line structure disposed on a semiconductor substrate; A lower capacitor contact disposed in the semiconductor substrate and extending above the semiconductor substrate; A higher capacitor contact disposed on the lower capacitor contact, wherein the higher capacitor contact and the lower capacitor contact comprise different materials; A first spacer layer disposed between the lower capacitor contact and the bit line structure and between the higher capacitor contact and the bit line structure; A capacitor disposed on the first spacer layer; And A landing pad disposed on the higher capacitor contact and in direct contact with the higher capacitor contact.

12. The memory element according to claim 11, wherein the lower capacitor contact comprises polysilicon and the higher capacitor contact comprises titanium nitride.

13. The memory element according to claim 11, wherein a height of the higher capacitor contact is greater than or equal to a height of the lower capacitor contact.

14. The memory element according to claim 13, wherein a ratio of the height of the higher capacitor contact to the height of the lower capacitor contact is in a range of about 1 to about 1.

5.

15. The memory element according to claim 11, wherein the lower capacitor contact is in direct contact with the higher capacitor contact, and the higher capacitor contact is in direct contact with the landing pad.

16. The memory element according to claim 11, further comprising: a second spacer layer separating the lower capacitor contact and the higher capacitor contact from the first spacer layer, wherein an air gap is provided between the first spacer layer and the second spacer layer.

17. The memory element according to claim 16, wherein the second spacer layer is in direct contact with the lower capacitor contact and the higher capacitor contact.

18. The memory element according to claim 16, further comprising: a third spacer layer disposed on the higher capacitor contact and separating the landing pad from the second spacer layer, wherein the third spacer layer is in direct contact with the capacitor and the higher capacitor contact.

19. The memory element according to claim 16, further comprising: a bit line mask layer disposed between the bit line structure and the capacitor, wherein the first spacer layer and the second spacer layer extend between the bit line mask layer and the landing pad.

20. The memory element according to claim 19, wherein a top surface of the bit line mask layer is higher than a top surface of the higher capacitor contact.

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