Semiconductor structure including bit line structure and method of fabricating same

Abstract

The invention provides a semiconductor structure and a preparation method thereof. The semiconductor structure comprises a substrate structure, a first bit line structure and a second bit line structure. The first bit line structure is buried in the substrate structure. The second bit line structure is embedded in the substrate structure. A maximum width of the first bit line structure is smaller than a maximum width of the second bit line structure.

Description

[0001] This application is a divisional of Chinese Patent Application No. 202410434410.0, filed on April 11, 2024, entitled "Semiconductor Structure Including Bit Line Structure and Method of Manufacturing the Same", which claims the priority and benefits of U.S. Provisional Application No. 18 / 421,042, filed on January 24, 2024. The content of the U.S. Provisional Application is incorporated herein by reference in its entirety. Technical Field

[0002] The present disclosure relates to a semiconductor structure and a method of manufacturing the same. In particular, the present disclosure relates to a semiconductor structure including a bit line structure and a method of manufacturing the same. Background Art

[0003] Semiconductor structures are used in various electronic applications, and the size of semiconductor structures is continuously reduced to meet current application requirements. However, various problems occur during the reduction process and affect the final electronic characteristics, quality, cost, and yield. A typical memory element (e.g., a dynamic random access memory (DRAM) element) includes a plurality of signal lines, such as word lines and bit lines that cross the word lines. As the size of the DRAM element is reduced and the size and / or pitch of the signal lines become smaller and smaller, parasitic capacitance will become a critical issue.

[0004] The above description of "prior art" only provides background art and does not admit that the above description of "prior art" discloses the subject matter of the present disclosure, does not constitute the prior art of the present disclosure, and any description of the above "prior art" should not be taken as any part of the present disclosure. Summary of the Invention

[0005] An embodiment of the present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate structure, a first bit line structure, and a second bit line structure. The first bit line structure is buried in the substrate structure. The second bit line structure is buried in the substrate structure. A maximum width of the first bit line structure is less than a maximum width of the second bit line structure.

[0006] Another embodiment of the present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate structure, a unit contact, and a bit line structure. The substrate structure includes a substrate portion and a first active region located in the substrate portion. The unit contact is disposed above the substrate structure and electrically connected to the first active region. The bit line structure is disposed in the substrate portion and below the unit contact. The bit line structure is electrically insulated from the first active region.

[0007] Another embodiment of the present disclosure provides a method for manufacturing a semiconductor structure. The manufacturing method includes providing a substrate structure, where the substrate structure includes a substrate portion and a plurality of active regions located in the substrate portion; forming a plurality of trenches extending in the substrate portion and the plurality of active regions; forming a plurality of bit line structures in the plurality of trenches; and forming a plurality of cell contacts on some of the plurality of active regions.

[0008] The technical features and advantages of the present disclosure have been outlined quite extensively above, so that a better understanding of the following detailed description of the present disclosure can be obtained. Other technical features and advantages constituting the subject matter of the claims of the present disclosure will be described below. Those skilled in the art to which the present disclosure pertains should understand that the concepts disclosed below and the specific embodiments can be quite easily used as a basis for modifying or designing other structures or processes to achieve the same purpose as the present disclosure. Those skilled in the art to which the present disclosure pertains should also understand that such equivalent constructs cannot depart from the spirit and scope of the present disclosure defined by the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] A more complete understanding of the present disclosure can be obtained by referring to the detailed description and the claims. The present disclosure should also be understood as being associated with the reference numerals of the drawings, and the reference numerals of the drawings represent similar elements throughout the description.

[0010] Figure 1 is a cross-sectional schematic diagram illustrating a semiconductor structure according to some embodiments of the present disclosure.

[0011] Figure 2 is an enlarged schematic diagram illustrating Figure 1 region “A” of

[0012] Figure 3 is a cross-sectional schematic diagram illustrating a semiconductor structure according to some embodiments of the present disclosure.

[0013] Figure 4 is a cross-sectional schematic diagram illustrating one or more stages of an example of a method for manufacturing a semiconductor structure according to some embodiments of the present disclosure.

[0014] Figure 5 is a cross-sectional schematic diagram illustrating one or more stages of an example of a method for manufacturing a semiconductor structure according to some embodiments of the present disclosure.

[0015] Figure 6 is a cross-sectional schematic diagram illustrating one or more stages of an example of a method for manufacturing a semiconductor structure according to some embodiments of the present disclosure.

[0016] Figure 7 is a cross-sectional schematic diagram illustrating one or more stages of an example of a method for manufacturing a semiconductor structure according to some embodiments of the present disclosure.

[0017] Figure 8 is a cross-sectional schematic diagram illustrating one or more stages of an example of a method for fabricating a semiconductor structure according to some embodiments of the present disclosure.

[0018] Figure 9 is a cross-sectional schematic diagram illustrating one or more stages of an example of a method for fabricating a semiconductor structure according to some embodiments of the present disclosure.

[0019] Figure 10 is a cross-sectional schematic diagram illustrating one or more stages of an example of a method for fabricating a semiconductor structure according to some embodiments of the present disclosure.

[0020] Figure 11 is a cross-sectional schematic diagram illustrating one or more stages of an example of a method for fabricating a semiconductor structure according to some embodiments of the present disclosure.

[0021] Figure 12 is a cross-sectional schematic diagram illustrating one or more stages of an example of a method for fabricating a semiconductor structure according to some embodiments of the present disclosure.

[0022] Figure 13 is a cross-sectional schematic diagram illustrating one or more stages of an example of a method for fabricating a semiconductor structure according to some embodiments of the present disclosure.

[0023] Figure 14 is a cross-sectional schematic diagram illustrating one or more stages of an example of a method for fabricating a semiconductor structure according to some embodiments of the present disclosure.

[0024] Figure 15 is a cross-sectional schematic diagram illustrating one or more stages of an example of a method for fabricating a semiconductor structure according to some embodiments of the present disclosure.

[0025] Figure 16 is a cross-sectional schematic diagram illustrating one or more stages of an example of a method for fabricating a semiconductor structure according to some embodiments of the present disclosure.

[0026] Figure 17 is a cross-sectional schematic diagram illustrating one or more stages of an example of a method for fabricating a semiconductor structure according to some embodiments of the present disclosure.

[0027] Figure 18 is a flowchart schematic diagram illustrating a method for fabricating a semiconductor structure according to some embodiments of the present disclosure.

[0028] Description of reference numerals:

[0029] 1: Semiconductor structure

[0030] 1a: Semiconductor structure

[0031] 2: First bit line structure

[0032] 2a: Third bit line structure

[0033] 3: Second bit line structure

[0034] 3a: Fourth bit line structure

[0035] 10: Substrate structure

[0036] 11: First active region

[0037] 11a: Fourth active region

[0038] 12: Second active region

[0039] 12a: Fifth active region

[0040] 13: Third active region

[0041] 13a: Sixth active region

[0042] 14: Trench

[0043] 15: Photoresist layer

[0044] 21: Main part

[0045] 22: Cover part

[0046] 23: Spacer

[0047] 23a: Spacer

[0048] 24: Bottom end

[0049] 31: Main part

[0050] 32: Cover part

[0051] 33: Second oxide

[0052] 34: Bottom end

[0053] 52: First insulating layer

[0054] 54: Second insulating layer

[0055] 55: Contact area

[0056] 56: Contact area

[0057] 62: First cell contact

[0058] 62a: Third cell contact

[0059] 64: Second cell contact

[0060] 64a: Fourth cell contact

[0061] 66: First landing pad

[0062] 66a: Third landing pad

[0063] 68: Second landing pad

[0064] 68a: Fourth landing pad

[0065] 72: First conductive structure

[0066] 72a: Third conductive structure

[0067] 74: Second conductive structure

[0068] 74a: Fourth conductive structure

[0069] 80: Conductive material

[0070] 82: Insulating material

[0071] 100: Substrate portion

[0072] 101: Upper surface

[0073] 103: Active region

[0074] 111: Upper surface

[0075] 112: Side surface

[0076] 113: Notch

[0077] 113': Notch

[0078] 121: Upper surface

[0079] 122: Side surface

[0080] 123: Notch

[0081] 123': Notch

[0082] 131: Upper surface

[0083] 131': Upper surface

[0084] 141: First groove

[0085] 141a: Third groove

[0086] 142: Second groove

[0087] 142a: Fourth groove

[0088] 143: Second groove

[0089] 143a: Fourth groove

[0090] 221: Lower part

[0091] 222: Upper part

[0092] 231: Upper surface

[0093] 321: Lower part

[0094] 322: Upper part

[0095] 520: Opening

[0096] 523: Draped part

[0097] 524: First opening

[0098] 525: Second opening

[0099] 900: Preparation method

[0100] 1001: Upper surface

[0101] 1411: Lower part

[0102] 1412: Upper part

[0103] 1421: Lower part

[0104] 1422: Upper part

[0105] 1431: Lower part

[0106] 1432: Upper part

[0107] L1: Plane

[0108] L2: Plane

[0109] S901: Step

[0110] S902: Step

[0111] S903: Step

[0112] S904: Step

[0113] t: Thickness

[0114] T2: Maximum thickness

[0115] T3: Maximum thickness

[0116] T4: Thickness

[0117] T5: Thickness

[0118] T6: Thickness

[0119] T7: Thickness

[0120] W2: Maximum width

[0121] W3: Maximum width

[0122] W4: Width

[0123] W5: Width

[0124] W6: Width

[0125] W7: Width Detailed Implementation Manner

[0126] Specific examples of components and configurations are described below to simplify the embodiments of the present disclosure. Of course, these embodiments are only for illustration and are not intended to limit the scope of the present disclosure. For example, when it is described that the first component is formed on the second component, it may include embodiments where the first and second components are in direct contact, or it may include embodiments where additional components are formed between the first and second components such that the first and second components are not in direct contact. Additionally, the embodiments of the present disclosure may repeat reference numerals and / or letters in many examples. The purpose of these repetitions is to simplify and clarify, and unless otherwise specifically stated in the text, they do not themselves represent a specific relationship between various embodiments and / or the configurations being discussed.

[0127] It should be understood that although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers, or sections, these elements, components, regions, layers, or sections are not limited by these terms. On the contrary, these terms are only used to distinguish one element, component, region, layer, or section from another region, layer, or section. Therefore, without departing from the teachings of the progressive concept of the present disclosure, the first element, component, region, layer, or section discussed below may be referred to as the second element, component, region, layer, or section.

[0128] The terms used herein are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "a", "an", and "the" are also intended to include the plural forms unless the context clearly indicates otherwise. It will be further understood that when the terms "comprises" and / or "comprising" are used in this specification, these terms specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups of the above.

[0129] Figure 1 is a cross-sectional schematic diagram illustrating the semiconductor structure 1 of some embodiments of the present disclosure. Figure 2 is an enlarged schematic diagram illustrating Figure 1Region “A”. In some embodiments, the semiconductor structure 1 can be a semiconductor device including a circuit, such as a memory cell. In some embodiments, the memory cell can include a dynamic random access memory cell (DRAM cell).

[0130] Alternatively, the semiconductor structure 1 can be a part of an integrated circuit (IC) chip that includes various passive and active microelectronic components, such as resistors, capacitors, inductors, diodes, p-type field effect transistors (pFETs), n-type field effect transistors (nFETs), metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused MOS (LDMOS) transistors, high voltage transistors, high frequency transistors, fin field effect transistors (FinFETs), other suitable IC components, or combinations thereof.

[0131] The semiconductor structure 1 can include a substrate structure 10, at least one bit line structure (e.g., a first bit line structure 2, a second bit line structure 3, a third bit line structure 2a, and a fourth bit line structure 3a), at least one spacer 23, 23a, a first insulating layer 52, at least one cell contact (e.g., a first cell contact 62, a second cell contact 64, a third cell contact 62a, and a fourth cell contact 64a), a second insulating layer 54, at least one landing pad (e.g., a first landing pad 66, a second landing pad 68, a third landing pad 66a, and a fourth landing pad 68a), and at least one conductive structure (e.g., a first conductive structure 72, a second conductive structure 74, a third conductive structure 72a, and a fourth conductive structure 74a).

[0132] The substrate structure 10 can be a substrate and can include a dielectric material, such as an oxide material or a nitride material. Alternatively, for example, the substrate structure 10 can be a substrate and can include silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), gallium (Ga), gallium arsenide (GaAs), indium (In), indium arsenide (InAs), indium phosphide (InP), or other Group IV-IV, III-V, or II-VI semiconductor materials. In some embodiments, the substrate structure 10 can include a substrate portion 100 and a plurality of active regions 103 (e.g., a first active region 11, a second active region 12, a third active region 13, a fourth active region 11a, a fifth active region 12a, and a sixth active region 13a) disposed in or embedded in the substrate portion 100.

[0133] The base portion 100 may include a dielectric oxide material and may have an upper surface 1001 (e.g., a first surface). Each active region 103 (e.g., the first active region 11, the second active region 12, the third active region 13, the fourth active region 11a, the fifth active region 12a, and the sixth active region 13a) may include a silicon (Si) material and may have a width W4. A portion of the base portion 100 disposed between the active regions 103 may have a width W5. The width W4 of the active region may be greater than or equal to the width W5 of the portion of the base portion 100 disposed between the active regions 103.

[0134] In some embodiments, each of the third active region 13 and the sixth active region 13a may be a drain electrode. Each of the first active region 11, the second active region 12, the fourth active region 11a, and the fifth active region 12a may be a source electrode.

[0135] In some embodiments, as Figure 1 shown, the base structure 10 may have an upper surface 101 (e.g., a first surface). The active regions 103 (e.g., the first active region 11, the second active region 12, the fourth active region 11a, and the fifth active region 12a) may be exposed from the upper surface 101 (e.g., the first surface) of the base structure 10. In some embodiments, the first active region 11 may have an upper surface 111 and a side surface 112. The upper surface 111 of the first active region 11 may be aligned or coplanar with the upper surface 1001 of the base portion 100 and may be a part of the upper surface 101 of the base structure 10. The upper surface 111 of the first active region 11 may be exposed from the upper surface 101 of the base structure 10. In addition, a notch 113 may be defined at a corner of the first active region 11. The notch 113 may be recessed from the upper surface 111 and the side surface 112 of the first active region 11. The notch 113 may be configured to accommodate a portion of the first bit line structure 2 and a portion of the spacer 23. The notch 113 may have a curved sidewall. The first active region 11 may not be a symmetric structure.

[0136] In some embodiments, the second active region 12 may have an upper surface 121 and a side surface 122. The side surface 122 of the second active region 12 may face the side surface 112 of the first active region 11. The upper surface 121 of the second active region 12 may be aligned or coplanar with the upper surface 1001 of the base portion 100 and may be part of the upper surface 101 of the base structure 10. The upper surface 121 of the second active region 12 may be exposed from the upper surface 101 of the base structure 10. In addition, a notch 123 may be defined at a corner of the second active region 12. The notch 123 may be recessed from the upper surface 121 and the side surface 122 of the second active region 12. The notch 123 of the second active region 12 may face the notch 113 of the first active region 11. The notch 123 may be configured to accommodate a portion of the first bit line structure 2 and a portion of the spacer 23. The notch 123 may have a curved sidewall. The second active region 12 may not be a symmetric structure.

[0137] In some embodiments, the third active region 13 may have an upper surface 131. The upper surface 131 may be concave and may be configured to accommodate a portion of the second bit line structure 3. The third active region 13 may be a symmetric structure. The third active region 13 may be spaced apart from the upper surface 101 of the base structure 10. Thus, the upper surfaces 111, 121, 131 of the active regions 103 (e.g., the first active region 11, the second active region 12, and the third active region 13) are not aligned with each other.

[0138] At least one bit line structure may include a plurality of bit line structures (e.g., the first bit line structure 2, the second bit line structure 3, the third bit line structure 2a, and the fourth bit line structure 3a) and may be buried or embedded in the base structure 10. The first bit line structure 2 may include a main portion 21 and a capping portion 22 disposed on the main portion 21. The main portion 21 may include a metal such as tungsten (W), and the capping portion 22 may include an insulating material such as silicon nitride (SiN). The main portion 21 may also be referred to as a "bit line structure" or a "bit line". The main portion 21 may be disposed below the upper surface 101 (e.g., the first surface) of the base structure 10 and below the first unit contact 62 and the second unit contact 64. The capping portion 22 may extend through the upper surface 101 (e.g., the first surface) of the base structure 10. The capping portion 22 may include a lower portion 221 and an upper portion 222. The capping portion 22 may be an integral structure. The lower portion 221 is below the upper surface 101 of the base structure 10. That is, the lower portion 221 is located below the upper surface 101 of the base structure 10. The upper portion 222 is above the upper surface 101 of the base structure 10. That is, the upper portion 222 may protrude beyond the upper surface 101 of the base structure 10.

[0139] The first bit line structure 2 can be disposed between multiple active regions 103 and can be electrically insulated from the active regions 103. For example, the first bit line structure 2 can be disposed between the first active region 11 and the second active region 12 and can be electrically insulated from the first active region 11 and the second active region 12. The first bit line structure 2 can laterally overlap with the active regions 103 such as the first active region 11 and the second active region 12. The first bit line structure 2 can include a bottom end 24. The bottom end 24 can be a bottom end of the main portion 21.

[0140] The spacer 23 can be disposed around the first bit line structure 2. The spacer 23 can include an insulating material such as an oxide material. The spacer 23 can be disposed between the first bit line structure 2 and the first active region 11 such that the first bit line structure 2 can be electrically insulated from the first active region 11 through the spacer 23. The spacer 23 can be disposed between the first bit line structure 2 and the second active region 12 such that the first bit line structure 2 is electrically insulated from the second active region 12 through the spacer 23. The spacer 23 can have an upper surface 231. The upper surface 231 of the spacer 23 can be aligned or coplanar with the upper surface 101 of the substrate structure 10 (including the upper surface 1001 of the substrate portion 100, the upper surface 111 of the first active region 11, and the upper surface 121 of the second active region 12).

[0141] In some embodiments, the first bit line structure 2 and the spacer 23 can be disposed in the notch 113 of the first active region 11 and the notch 123 of the second active region 12. Accordingly, the first bit line structure 2 and the spacer 23 can extend beyond the side surface 112 of the first active region 11 and the side surface 122 of the second active region 12.

[0142] The shapes of the notch 113 of the first active region 11 and the notch 123 of the second active region 12 can be conformal to the spacer 23. In some embodiments, the spacer 23 can have a non-uniform thickness t. The spacer 23 can taper towards the bottom end 24 of the first bit line structure 2. That is, the thickness t of the spacer 23 can gradually decrease towards the bottom end 24 of the first bit line structure 2.

[0143] The first bit line structure 2 may be a through bit line structure. The first bit line structure 2 may have a maximum width W2, which may be equal to the maximum width of the main portion 21 and the maximum width of the capping portion 22. The maximum width W2 of the first bit line structure 2 may be greater than the width W4 of the first active region 11 and the width W5 of the portion of the base portion 100 disposed between the plurality of active regions 103. Additionally, the main portion 21 may have a maximum thickness T2. The lower portion 221 of the capping portion 22 may have a thickness T4. For example, the thickness T4 may be in the range of 30 nm to 50 nm. The upper portion 222 of the capping portion 22 may have a thickness T5.

[0144] The second bit line structure 3 may include a main portion 31 and a capping portion 32 disposed on the main portion 31. The main portion 31 may include a metal such as tungsten (W), and the capping portion 32 may include an insulating material such as silicon nitride (SiN). The main portion 31 may also be referred to as a "bit line structure" or a "bit line". The main portion 31 may be disposed below the upper surface 101 (e.g., the first surface) of the base structure 10, and below the first unit contact 62 and the second unit contact 64. The capping portion 32 may extend through the upper surface 101 (e.g., the first surface) of the base structure 10. The capping portion 32 may include a lower portion 321 and an upper portion 322. The lower portion 321 is below the upper surface 101 of the base structure 10. That is, the lower portion 321 is located below the upper surface 101 of the base structure 10. The upper portion 322 is above the upper surface 101 of the base structure 10. That is, the upper portion 322 may protrude beyond the upper surface 101 of the base structure 10.

[0145] The second bit line structure 3 may be disposed above or on the third active region 13, and may be electrically connected to the plurality of active regions 103, such as the third active region 13. For example, the main portion 31 of the second bit line structure 3 may directly contact the upper surface 131 of the third active region 13. Additionally, the second bit line structure 3 may laterally overlap the active regions 103 such as the first active region 11 and the second active region 12. The second bit line structure 3 may include a bottom end 34. The bottom end 34 may be a bottom end of the main portion 31.

[0146] The second bit line structure 3 may not be surrounded by a spacer. That is, no spacer is disposed around the second bit line structure 3. No spacer is disposed between the second bit line structure 3 and the third active region 13, such that the second bit line structure 3 can be electrically connected to the third active region 13. In some embodiments, the second bit line structure 3 may extend beyond two opposite side surfaces of the third active region 13. The shape of the upper surface 131 of the third active region 13 may be conformal to the second bit line structure 3.

[0147] The second bit line structure 3 may be an active bit line structure. The second bit line structure 3 may have a maximum width W3, which may be equal to the maximum width of the main portion 31 and the maximum width of the cover portion 32. The maximum width W3 of the second bit line structure 3 may be greater than the width W4 of the third active region 13 and the width W5 of the portion of the base portion 100 disposed between the plurality of active regions 103. The maximum width W2 of the first bit line structure 2 is less than the maximum width W3 of the second bit line structure 3. Additionally, the main portion 31 may have a maximum thickness T3. The maximum thickness T3 of the main portion 31 of the second bit line structure 3 may be greater than the maximum thickness T2 of the main portion 21 of the first bit line structure 2. The thickness of the cover portion 32 of the second bit line structure 3 may be equal to the thickness of the cover portion 22 of the first bit line structure 2. In some embodiments, the bottom end 24 of the first bit line structure 2 may not be flush with the bottom end 34 of the second bit line structure 3. For example, a plane L1 (or height) of the bottom end 24 of the first bit line structure 2 may be higher than a plane L2 (or height) of the bottom end 34 of the second bit line structure 3.

[0148] The first insulating layer 52 may be disposed on the upper surface 101 of the base structure 10. The material of the first insulating layer 52 may be the same as or different from the materials of the cover portion 22 of the first bit line structure 2 and the cover portion 32 of the second bit line structure 3. For example, the first insulating layer 52 may include an insulating material such as silicon nitride (SiN), silicon oxynitride (SiON), or other suitable materials. The cover portion 22 of the first bit line structure 2 and the cover portion 32 of the second bit line structure 3 may extend through the first insulating layer 52. Thus, the thickness of the first insulating layer 52 may be equal to the thickness T5 of the upper portion 222 of the cover portion 22 of the first bit line structure 2.

[0149] The first unit contact 62 may be disposed above the base structure 10 and may be electrically connected to the first active region 11. The material of the first unit contact 62 may include a conductive material such as titanium (Ti), tungsten (W), or other suitable materials. The first unit contact 62 may cover and contact the first active region 11. Thus, a contact region 55 may be formed between the first unit contact 62 and the upper surface 111 of the first active region 11. A width W6 of the contact region 55 may be greater than half of the width W4 of the first active region 11. Additionally, the first unit contact 62 may cover and contact the upper surface 231 of the spacer 23.

[0150] The first unit contact 62 can extend through the first insulating layer 52. Accordingly, the thickness T6 of the first unit contact 62 can be equal to the thickness of the first insulating layer 52 and the thickness T5 of the upper portion 222 of the cover portion 22 of the first bit line structure 2. One side surface of the first unit contact 62 can contact one side surface of the upper portion 222 of the cover portion 22 of the first bit line structure 2. In some embodiments, the main portion 21 of the first bit line structure 2 can be spaced apart from the first unit contact 62 by the lower portion 221 of the cover portion 22 of the first bit line structure 2 and a portion of the spacer 23.

[0151] The second unit contact 64 can be disposed above the substrate structure 10 and can be electrically connected to the second active region 12. A material of the second unit contact 64 can include a conductive material, such as titanium (Ti), tungsten (W), or other suitable materials. The second unit contact 64 can cover and contact the second active region 12. Accordingly, a contact region 56 can be formed between the upper surface 121 of the second unit contact 64 and the second active region 12. A width W7 of the contact region 56 can be greater than half of the width W4 of the second active region 12. In addition, the second unit contact 64 can cover and contact the upper surface 231 of the spacer 23.

[0152] The second unit contact 64 can extend through the first insulating layer 52. Accordingly, the thickness T7 of the second unit contact 64 can be equal to the thickness of the first insulating layer 52 and the thickness T5 of the upper portion 222 of the cover portion 22 of the first bit line structure 2. One side surface of the second unit contact 64 can contact one side surface of the upper portion 222 of the cover portion 22 of the first bit line structure 2. In some embodiments, the main portion 21 of the first bit line structure 2 can be spaced apart from the second unit contact 64 by the lower portion 221 of the cover portion 22 of the first bit line structure 2 and a portion of the spacer 23.

[0153] The second insulating layer 54 can be disposed on the first insulating layer 52. A material of the second insulating layer 54 can be the same as or different from the material of the first insulating layer 52. For example, the second insulating layer 54 can include an insulating material, such as silicon nitride (SiN), silicon oxynitride (SiON), or other suitable materials.

[0154] The first landing pad 66 can be disposed on the first insulating layer 52 and can be electrically connected to the first unit contact 62. A material of the first landing pad 66 can include a conductive material, such as titanium (Ti), tungsten (W), or other suitable materials. The first landing pad 66 can cover and contact the first unit contact 62. The first landing pad 66 can extend through the second insulating layer 54. Accordingly, the thickness of the first landing pad 66 can be equal to the thickness of the second insulating layer 54.

[0155] The second landing pad 68 can be disposed on the first insulating layer 52 and can be electrically connected to the second unit contact 64. A material of the second landing pad 68 can include a conductive material such as titanium (Ti), tungsten (W), or other suitable materials. The second landing pad 68 can cover and contact the upper portion 222 of the second unit contact 64 and the cover portion 22 of the first bit line structure 2. The second landing pad 68 can extend through the second insulating layer 54. Accordingly, the thickness of the second landing pad 68 can be equal to the thickness of the second insulating layer 54.

[0156] The first conductive structure 72 can be disposed on the first landing pad 66 and can be electrically connected to the first landing pad 66. The first conductive structure 72 can be a three-layer structure. The first conductive structure 72 can be a capacitive structure. Additionally, the second conductive structure 74 can be disposed on the second landing pad 68 and can be electrically connected to the second landing pad 68. The second conductive structure 74 can be a three-layer structure. The second conductive structure 74 can be a capacitive structure.

[0157] The third bit line structure 2a can be the same as or similar to the first bit line structure 2, and can be disposed between the fourth active region 11a and the fifth active region 12a. The spacer 23a can be the same as or similar to the spacer 23, and can be disposed around the third bit line structure 2a. The fourth bit line structure 3a can be the same as or similar to the second bit line structure 3, and can be disposed on the sixth active region 13a.

[0158] The third unit contact 62a can be the same as or similar to the first unit contact 62. The third unit contact 62a can be disposed above the base structure 10 and can cover and contact the fourth active region 11a. The third unit contact 62a can extend through the first insulating layer 52. Additionally, the fourth unit contact 64a can be the same as or similar to the second unit contact 64. The fourth unit contact 64a can be disposed above the base structure 10 and can cover and contact the fifth active region 12a. The fourth unit contact 64a can extend through the first insulating layer 52.

[0159] The third landing pad 66a can be the same as or similar to the first landing pad 66. The third landing pad 66a can be disposed on the first insulating layer 52 and can cover and contact the third unit contact 62a. The third landing pad 66a can extend through the second insulating layer 54. Additionally, the fourth landing pad 68a can be the same as or similar to the second landing pad 68. The fourth landing pad 68a can be disposed on the first insulating layer 52 and can cover and contact the fourth unit contact 64a. The fourth landing pad 68a can extend through the second insulating layer 54.

[0160] The third conductive structure 72a may be the same as or similar to the first conductive structure 72. The third conductive structure 72a may be disposed on the third landing pad 66a and electrically connected to the third landing pad 66a. Additionally, the fourth conductive structure 74a may be the same as or similar to the second conductive structure 74. The fourth conductive structure 74a may be disposed on the fourth landing pad 68a and electrically connected to the fourth landing pad 68a.

[0161] In Figure 1 and Figure 2 In the illustrated embodiment, bit line structures (e.g., the first bit line structure 2, the second bit line structure 3, the third bit line structure 2a, and the fourth bit line structure 3a) are buried or disposed in the substrate structure 10. Thus, bit line contacts between the bit line structures (e.g., the second bit line structure 3 and the fourth bit line structure 3a) and the active regions 103 (e.g., the third active region 13 and the sixth active region 13a) can be omitted. Further, the thickness of the unit contacts (e.g., the first unit contact 62, the second unit contact 64, the third unit contact 62a, and the fourth unit contact 64a) can be reduced. Accordingly, an electronic path between the bit line structures (e.g., the second bit line structure 3 and the fourth bit line structure 3a) and the conductive structures (e.g., the first conductive structure 72, the second conductive structure 74, the third conductive structure 72a, and the fourth conductive structure 74a) can be reduced. Thus, the resistance value between the bit line structures and the conductive structures is reduced, and a signal margin is improved. The overall height of the semiconductor structure 1 is reduced.

[0162] Moreover, the bit line structures (e.g., the first bit line structure 2, the second bit line structure 3, the third bit line structure 2a, and the fourth bit line structure 3a) are buried or disposed in the substrate structure 10, and the unit contacts (e.g., the first unit contact 62, the second unit contact 64, the third unit contact 62a, and the fourth unit contact 64a) are disposed above the substrate structure 10. That is, the unit contacts are not arranged side by side beside the bit line structures. A main portion (e.g., the main portion 21) of the first bit line structure 2 may be spaced apart from the unit contacts (e.g., the first unit contact 62 and the second unit contact 64) by a part (e.g., the lower portion 221) of the cover portion (e.g., the cover portion 22). The long distance between the main portion (e.g., the main portion 21) of the first bit line structure 2 and the unit contact (e.g., the first unit contact 62) can reduce the parasitic capacitance and can further improve the signal margin.

[0163] In addition, the width W6 of the contact region 55 may be greater than half of the width W4 of the first active region 11. The large contact region 55 between the first unit contact 62 and the first active region 11 can further improve the signal margin.

[0164] Figure 3 is a cross-sectional schematic diagram illustrating a semiconductor structure 1a according to some embodiments of the present disclosure. Figure 3 The semiconductor structure 1a of Figure 1 is similar to the semiconductor structure 1 of Figure 3 except that the width of the upper portion 222 of the capping portion 22 of the first bit line structure 2 of Figure 1 can be greater than the width of the upper portion 222 of the capping portion 22 of the first bit line structure 2 of Figure 3 As shown, the width of the upper portion 222 of the capping portion 22 of the first bit line structure 2 can be greater than the width of the lower portion 221 of the capping portion 22 of the first bit line structure 2. The upper portion 222 of the capping portion 22 can cover and contact the upper surface 231 of the spacer 23. The first unit contact 62 may not cover and contact the upper surface 231 of the spacer 23.

[0165] Figures 4 to 17 Illustrates a method for manufacturing a semiconductor structure 1 according to some embodiments of the present disclosure.

[0166] Referring to Figure 4 , a substrate structure 10 and a first insulating layer 52 disposed thereon can be provided. Figure 4 The substrate structure 10 and the first insulating layer 52 of Figure 1 can be the same as or similar to the substrate structure 10 and the first insulating layer 52 of

[0167] In some embodiments, the substrate structure 10 can include a substrate portion 100 and a plurality of active regions 103 (e.g., a first active region 11, a second active region 12, a third active region 13, a fourth active region 11a, a fifth active region 12a, and a sixth active region 13a) disposed in or embedded in the substrate portion 100. The substrate portion 100 can have an upper surface 1001 (e.g., a first surface).

[0168] The substrate structure 10 can have an upper surface 101 (e.g., a first surface). In some embodiments, the first active region 11 can have an upper surface 111 and a side surface 112. The upper surface 111 of the first active region 11 can be aligned with or coplanar with the upper surface 1001 of the substrate portion 100 and can be a part of the upper surface 101 of the substrate structure 10. The upper surface 111 of the first active region 11 can be exposed from the upper surface 101 of the substrate structure 10.

[0169] In some embodiments, the second active region 12 may have an upper surface 121 and a side surface 122. The side surface 122 of the second active region 12 may face the side surface 112 of the first active region 11. The upper surface 121 of the second active region 12 may be aligned or coplanar with the upper surface 1001 of the base portion 100 and may be a part of the upper surface 101 of the base structure 10. The upper surface 121 of the second active region 12 may be exposed from the upper surface 101 of the base structure 10.

[0170] In some embodiments, the third active region 13 may have an upper surface 131. The upper surfaces 111, 121, 131 of the active regions 103 (e.g., the first active region 11, the second active region 12, and the third active region 13) are aligned with each other. The first insulating layer 52 may be disposed on the upper surface 101 of the base structure 10 to cover the active regions 103 (e.g., the first active region 11, the second active region 12, and the third active region 13).

[0171] Please refer to Figure 5 , a plurality of trenches 14 may be formed to extend through the first insulating layer 52 and extend in the base portion 100 and the plurality of active regions 103. The sizes and shapes of the trenches 14 may be substantially the same as each other. The manufacturing technique of the trenches 14 may include applying a photoresist layer and performing an etching process.

[0172] The trench 14 may include a first trench 141, a second trench 142, a third trench 141a, and a fourth trench 142a. The first trench 141 may include a lower portion 1411 and an upper portion 1412. The lower portion 1411 is located within the base structure 10. The upper portion 1412 extends through the first insulating layer 52. The first trench 141 may have a maximum width W2. The first active region 11 may define a notch 113' at a corner. The notch 113' may be recessed from the upper surface 111 and the side surface 112 of the first active region 11. The second active region 12 may define a notch 123' at a corner. The notch 123' may be recessed from the upper surface 121 and the side surface 122 of the second active region 12. The notch 113' and the notch 123' may define multiple portions of the lower portion 1411 of the first trench 141. Accordingly, the first trench 141 exposes some portions of the first active region 11 and the second active region 12.

[0173] The second trench 142 may include a lower portion 1421 and an upper portion 1422. The lower portion 1421 is located in the base structure 10. The upper portion 1422 extends through the first insulating layer 52. The second trench 142 may have a maximum width W2. The third active region 13 may have an upper surface 131'. The upper surface 131' may be concave and may define a part of the lower portion 1421 of the second trench 142. Accordingly, a part of the third active region 13 is exposed by the second trench 142. The third trench 141a may be the same as the first trench 141. The fourth trench 142a may be the same as the second trench 142.

[0174] Please refer to Figure 6 , oxidation may be performed on multiple portions of the active region 103 exposed in the trench 14 to form multiple oxides on the active region 103 exposed in the trench 14. For example, a first oxide 23 (e.g., an interstitial 23) may be formed on the notch 113' of the first active region 11 and the notch 123' of the second active region 12. Accordingly, a notch 113 of the first active region 11 may be formed. The oxidation reaction may proceed from the notch 113' to the notch 113. The shape of the notch 113 may be similar to the shape of the notch 113'. The notch 113 may be an interface between the first oxide 23 and the first active region 11. The distance between the notch 113' and the notch 113 may be the thickness of the first oxide 23.

[0175] Meanwhile, a notch 123 of the second active region 12 may be formed. The oxidation reaction may proceed from the notch 123' to the notch 123. The shape of the notch 123 may be similar to the shape of the notch 123'. The notch 123 may be an interface between the first oxide 23 and the second active region 12. The distance between the notch 123' and the notch 123 may be the thickness of the first oxide 23.

[0176] For example, a second oxide 33 may be formed on the upper surface 131' of the third active region 13. Accordingly, an upper surface 131 of the third active region 13 may be formed. The oxidation reaction may proceed from the upper surface 131' to the upper surface 131. The shape of the upper surface 131 may be similar to the shape of the upper surface 131'. The upper surface 131 may be an interface between the second oxide 33 and the third active region 13. The distance between the upper surface 131' and the upper surface 131 may be the thickness of the second oxide 33.

[0177] Please refer to Figure 7, a photoresist layer 15 can be formed. The photoresist layer 15 can be formed to cover and fill the first trench 141 and the third trench 141a to protect the spacer 23 (e.g., the first oxide 23) and the spacer 23a during the etching process. The photoresist layer 15 may not cover the second trench 142 and the fourth trench 142a. That is, the second trench 142 and the fourth trench 142a are exposed.

[0178] Please refer to Figure 8 , the second oxide 33 in the second trench 142 and the fourth trench 142a can be completely removed by, for example, an etching process. At the same time, a part of the substrate portion 100 can also be removed simultaneously. However, the first insulating layer 52 may not be removed. Therefore, the second trench 142 and the fourth trench 142a become a second trench 143 and a fourth trench 143a.

[0179] The second trench 143 may include a lower portion 1431 and an upper portion 1432. The lower portion 1431 is located in the substrate structure 10. The upper portion 1432 extends through the first insulating layer 52. The lower portion 1431 may have a maximum width W3. That is, the lower portion 1431 is enlarged after the etching process. The width of the upper portion 1432 is equal to the width of the upper portion 1422. Therefore, the first insulating layer 52 may include an overhanging portion 523 located above the lower portion 1431. The lower portion of the fourth trench 143a is also enlarged after the etching process.

[0180] Please refer to Figure 9 , the photoresist layer 15 can be removed to expose the first trench 141 (with the spacer 23) and the third trench 141a (with the spacer 23a).

[0181] Please refer to Figure 10 , a conductive material 80 can be formed to fill the trenches 14 (e.g., the first trench 141, the second trench 143, the third trench 141a, and the fourth trench 143a) and cover the upper surface of the first insulating layer 52. A material of the conductive material 80 may include a metal such as tungsten (W).

[0182] Please refer to Figure 11 , an upper portion of the conductive material 80 can be removed by, for example, an etching process. For example, a part of the conductive material 80 can be retained in the first trench 141 to become a main portion 21. Another part of the conductive material 80 can be retained in the second trench 143 to become a main portion 31. The upper surface of the main portion 21 and the upper surface of the main portion 31 can be lower than the upper surface 101 of the substrate structure 10. In addition, the overhanging portion 523 of the first insulating layer 52 located above the lower portion 1431 of the second trench 143 ( Figure 10) can be removed simultaneously during the etching process. Accordingly, the upper portion 1432 of the second trench 143 can be enlarged to have a maximum width W3.

[0183] In addition, a portion of the first insulating layer 52 located above the spacer 23 can be removed simultaneously during the etching process. Accordingly, the upper portion 1412 of the first trench 141 can be enlarged to have a width greater than the maximum width W2. That is, the upper portion 1412 is enlarged after the etching process. The upper surface 231 of the spacer 23 can be exposed ( Figure 2 ). The upper portion of the third trench 141a is also enlarged after the etching process. The upper surface of the spacer 23a can be exposed.

[0184] Please refer to Figure 12 , an insulating material 82 can be formed to fill the trenches 14 (e.g., the first trench 141, the second trench 142, the third trench 141a, and the fourth trench 142a) so as to contact the main portions 21, 31 and cover the upper surface of the first insulating layer 52. A material of the insulating material 82 can include silicon nitride (SiN). The material of the insulating material 82 can be the same as or different from the material of the first insulating layer 52.

[0185] Please refer to Figure 13 , a grinding or polishing process (e.g., chemical mechanical planarization (CMP)) can be performed on the upper surface of the insulating material 82 to remove an upper portion of the insulating material 82 and expose the first insulating layer 52. For example, a portion of the insulating material 82 can be retained in the first trench 141 to become a capping portion 22. Another portion of the insulating material 82 can be retained in the second trench 142 to become a capping portion 32. Accordingly, the upper surface of the first insulating layer 52 and the upper surfaces of the capping portions 22, 32 can be coplanar with each other.

[0186] Meanwhile, a plurality of bit line structures (e.g., the first bit line structure 2, the second bit line structure 3, the third bit line structure 2a, and the fourth bit line structure 3a) can be respectively formed in the plurality of trenches 14 (e.g., the first trench 141, the second trench 143, the third trench 141a, and the fourth trench 143a). The first bit line structure 2 and the third bit line structure 2a can be formed on the spacers 23, 23a.

[0187] The first bit line structure 2 may include a main portion 21 and a cover portion 22 disposed on the main portion 21. The cover portion 22 may include a lower portion 221 and an upper portion 222. The lower portion 221 is lower than the upper surface 101 of the base structure 10. That is, the lower portion 221 is located below the upper surface 101 of the base structure 10. The upper portion 222 is higher than the upper surface 101 of the base structure 10. That is, the upper portion 222 may protrude beyond the upper surface 101 of the base structure 10. The first bit line structure 2 may be disposed between the first active region 11 and the second active region 12, and may be electrically insulated from the first active region 11 and the second active region 12.

[0188] The second bit line structure 3 may include a main portion 31 and a cover portion 32 disposed on the main portion 31. The cover portion 32 may extend through the upper surface 101 (e.g., the first surface) of the base structure 10. The cover portion 32 may include a lower portion 321 and an upper portion 322. The lower portion 321 is lower than the upper surface 101 of the base structure 10. That is, the lower portion 321 is located below the upper surface 101 of the base structure 10. The upper portion 322 is higher than the upper surface 101 of the base structure 10. That is, the upper portion 322 may protrude beyond the upper surface 101 of the base structure 10.

[0189] The second bit line structure 3 may be disposed above or on the third active region 13, and may be electrically connected to the third active region 13. For example, the main portion 31 of the second bit line structure 3 may directly contact the upper surface 131 of the third active region 13. The second bit line structure 3 may not be surrounded by a spacer. No spacer is disposed between the second bit line structure 3 and the third active region 13, such that the second bit line structure 3 may be electrically connected to the third active region 13.

[0190] The maximum width W3 of the second bit line structure 3 may be greater than the width W4 of the third active region 13 and the width W5 of the portion of the base portion 100 disposed between the active regions 103. The maximum width W2 of the first bit line structure 2 is less than the maximum width W3 of the second bit line structure 3. In some embodiments, the bottom end 24 of the first bit line structure 2 may not be flush with the bottom end 34 of the second bit line structure 3. For example, a plane L1 ( Figure 2 ) of the bottom end 24 of the first bit line structure 2 may be higher than a plane L2 ( Figure 2 ) of the bottom end 34 of the second bit line structure 3.

[0191] Please refer to Figure 14, a plurality of openings 520 can be formed to extend through the first insulating layer 52 and expose the upper surfaces of some of the active regions 103. In some embodiments, the openings 520 can include a first opening 524 and a second opening 525. The first opening 524 can expose the upper surface 111 of the first active region 11 and the upper surface 231 of the spacer 23. The second opening 525 can expose the upper surface 121 of the second active region 12 and the upper surface 231 of the spacer 23.

[0192] Please refer to Figure 15 , a conductive material can be formed or disposed in the openings 520 to form a plurality of unit contacts (e.g., a first unit contact 62, a second unit contact 64, a third unit contact 62a, and a fourth unit contact 64a) on some of the plurality of active regions 103. The first unit contact 62 can cover and contact the upper surface 111 of the first active region 11 and the upper surface 231 of the spacer 23. The first unit contact 62 can extend through the first insulating layer 52. One side surface of the first unit contact 62 can contact one side surface of the upper portion 222 of the cover portion 22 of the first bit line structure 2.

[0193] The second unit contact 64 can cover and contact the upper surface 121 of the second active region 12 and the upper surface 231 of the spacer 23. The second unit contact 64 can extend through the first insulating layer 52. One side surface of the second unit contact 64 can contact one side surface of the upper portion 222 of the cover portion 22 of the first bit line structure 2.

[0194] The third unit contact 62a can be the same as or similar to the first unit contact 62. The third unit contact 62a can cover and contact the fourth active region 11a. The third unit contact 62a can extend through the first insulating layer 52. Additionally, the fourth unit contact 64a can be the same as or similar to the second unit contact 64. The fourth unit contact 64a can cover and contact the fifth active region 12a. The fourth unit contact 64a can extend through the first insulating layer 52.

[0195] Please refer to Figure 16 , a second insulating layer 54 can be formed or disposed on the first insulating layer 52 to cover the cover portions 22, 32, and the unit contacts (e.g., the first unit contact 62, the second unit contact 64, the third unit contact 62a, and the fourth unit contact 64a).

[0196] Please refer to Figure 17, a plurality of landing pads (e.g., a first landing pad 66, a second landing pad 68, a third landing pad 66a, and a fourth landing pad 68a) can be formed in the second insulating layer 54 to respectively contact unit contacts (e.g., a first unit contact 62, a second unit contact 64, a third unit contact 62a, and a fourth unit contact 64a).

[0197] Then, a plurality of conductive structures (e.g., a first conductive structure 72, a second conductive structure 74, a third conductive structure 72a, and a fourth conductive structure 74a) can be formed or disposed on the landing pads (e.g., the first landing pad 66, the second landing pad 68, the third landing pad 66a, and the fourth landing pad 68a) to obtain Figure 1 and Figure 2 the semiconductor structure 1.

[0198] Figure 18 is a process schematic diagram illustrating a method 900 for fabricating a semiconductor structure according to some embodiments of the present disclosure.

[0199] In some embodiments, the fabrication method 900 may include step S901 of providing a substrate structure, where the substrate structure includes a substrate portion and at least one active region located in the substrate base portion. For example, as Figure 4 shown, a substrate structure 10 is provided. The substrate structure 10 includes a substrate portion 100 and at least one active region 103, 11, 12, 13, 11a, 12a, 13a in the substrate portion 100.

[0200] In some embodiments, the fabrication method 900 may include step S902 of forming a plurality of trenches to extend in the substrate portion and the plurality of active regions. For example, as Figure 5 shown, trenches 14 can be formed to extend in the substrate portion 100 and the active regions 103, 11, 12, 13, 11a, 12a, 13a.

[0201] In some embodiments, the fabrication method 900 may include step S903 of forming a plurality of bit line structures in the plurality of trenches. For example, as Figure 13 shown, bit line structures 2, 3, 2a, 3a can be formed in the trenches 14.

[0202] In some embodiments, the fabrication method 900 may include step S904 of forming a plurality of unit contacts on some of the plurality of active regions. For example, as Figure 15 shown, unit contacts 62, 64, 62a, 64a can be formed on the first active region 11, the second active region 12, the fourth active region 11a, and the fifth active region 12a.

[0203] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alterations can be made without departing from the spirit and scope of the present disclosure as defined by the claims. For example, many of the processes described above can be implemented in different ways, and many of the processes described above can be replaced by other processes or combinations thereof.

[0204] Furthermore, the scope of the present application is not limited to the specific embodiments of the processes, machines, manufactures, compositions of matter, means, methods, and steps described in the specification. Those skilled in the art can understand from the disclosure of the present disclosure that existing or future-developed processes, machines, manufactures, compositions of matter, means, methods, or steps that have the same function or achieve substantially the same result as the corresponding embodiments described herein can be used in accordance with the present disclosure. Accordingly, these processes, machines, manufactures, compositions of matter, means, methods, or steps are included in the claims of the present application.

Claims

1. A semiconductor structure, comprising: a substrate structure including a substrate portion and a first active region located in the substrate portion; a cell contact disposed above the substrate structure and electrically connected to the first active region; and a bit line structure disposed in the substrate portion and under the cell contact, wherein the bit line structure is electrically insulated from the first active region.

2. The semiconductor structure according to claim 1, wherein the cell contact contacts the first active region.

3. The semiconductor structure according to claim 1, wherein a width of a contact region between the cell contact and the first active region is greater than half of a width of the first active region.

4. The semiconductor structure according to claim 1, wherein the bit line structure includes a main portion and a capping portion disposed on the main portion, wherein the capping portion extends through an upper surface of the substrate structure.

5. The semiconductor structure according to claim 4, wherein the main portion of the bit line structure and the cell contact are separated by a lower portion of the capping portion, wherein the lower portion of the capping portion is located below the upper surface of the substrate structure.

6. The semiconductor structure according to claim 4, wherein a thickness of the cell contact is substantially equal to a thickness of an upper portion of the capping portion.

7. The semiconductor structure according to claim 6, wherein the cell contact contacts the upper portion of the capping portion.

8. The semiconductor structure according to claim 4, wherein the capping portion is a single-piece structure.

9. The semiconductor structure according to claim 1, further comprising a spacer disposed around the bit line structure, wherein the spacer is disposed between the bit line structure and the first active region.

10. The semiconductor structure according to claim 9, wherein the spacer has a non-uniform thickness.

11. The semiconductor structure according to claim 9, wherein the spacer tapers towards a bottom end of the bit line structure.

12. The semiconductor structure according to claim 9, wherein the cell contact contacts an upper surface of the spacer.

13. The semiconductor structure according to claim 1, wherein the substrate structure further includes a second active region in the substrate portion, wherein the bit line structure is disposed between the first active region and the second active region.

14. The semiconductor structure according to claim 13, wherein the bit line structure extends over a side surface of the first active region and a side surface of the second active region.

15. The semiconductor structure according to claim 1, wherein the first active region defines a notch that indents from an upper surface in the first active region and a side surface in the first active region.

16. The semiconductor structure according to claim 15, wherein the bit line structure is disposed in the notch.

17. A method for fabricating a semiconductor structure, comprising: providing a substrate structure, wherein the substrate structure includes a substrate portion and a plurality of active regions located in the substrate portion; forming a plurality of trenches to extend in the substrate portion and the plurality of active regions; forming a plurality of bit line structures in the plurality of trenches; Form a plurality of unit contacts on some of the plurality of active regions; And Form a plurality of oxides on the plurality of active regions exposed in the plurality of trenches.

18. The manufacturing method according to claim 17, wherein providing the substrate structure comprises: Providing the substrate structure and an insulating layer thereon, wherein the plurality of trenches extend through the insulating layer.

19. The manufacturing method according to claim 17, further comprising: Forming a spacer in some of the plurality of trenches.

20. The manufacturing method according to claim 17, wherein some of the plurality of unit contacts contact some of the plurality of active regions, and a width of a contact region between one of the plurality of unit contacts and one of the plurality of active regions is greater than half of a width of the one of the plurality of active regions, and the plurality of unit contacts contact an upper surface of a spacer.

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