Semiconductor device and method for manufacturing the same

Abstract

The present disclosure relates to the field of semiconductor technology, and provides a semiconductor device and a manufacturing method thereof, which are used to solve the technical problem of how to increase the capacitance of a capacitor structure. The semiconductor device includes: a transistor structure, the transistor structure includes a semiconductor body extending along a first direction; a capacitor structure, located on one side of the transistor structure along the first direction, the capacitor structure includes a first electrode layer, a second electrode layer, and a dielectric layer located between the first electrode layer and the second electrode layer, and the first electrode layer and the semiconductor body are coupled; wherein the first electrode layer includes a first sub-electrode and a second sub-electrode surrounding the first sub-electrode, the axial directions of the first sub-electrode and the second sub-electrode are both in the first direction, and the dielectric layer covers the inner sidewall and outer sidewall of the first sub-electrode and the inner sidewall and outer sidewall of the second sub-electrode. In this way, it is beneficial to increase the facing area between the first electrode layer and the second electrode layer, thereby increasing the capacitance of the capacitor structure.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, including but not limited to a semiconductor device and a method for manufacturing the same. Background Art

[0002] With the continuous advancement of semiconductor technology, dynamic random access memory (DRAM) is moving towards higher integration and smaller size. Typically, each DRAM memory cell consists of a 1-transistor-1-capacitor (1T1C) structure, with the transistor's gate coupled to the word line (WL), the transistor's source (or drain) coupled to the bit line (BL), and the transistor's drain (or source) coupled to the capacitor.

[0003] However, as the demand for capacitor structures with larger capacitance increases, new challenges are also posed to the development of DRAM. Summary of the Invention

[0004] In view of this, embodiments of the present disclosure provide a semiconductor device and a method for manufacturing the same.

[0005] In a first aspect, an embodiment of the present disclosure provides a semiconductor device, comprising: a transistor structure, the transistor structure comprising a semiconductor body extending along a first direction; a capacitor structure, located on one side of the transistor structure along the first direction, the capacitor structure comprising a first electrode layer, a second electrode layer, and a dielectric layer located between the first electrode layer and the second electrode layer, the first electrode layer and the semiconductor body being coupled; wherein the first electrode layer comprises a first sub-electrode and a second sub-electrode surrounding the first sub-electrode, the first sub-electrode comprises a first annular structure, the second sub-electrode comprises a second annular structure, the axial directions of the first annular structure and the second annular structure are both the first direction, and the dielectric layer covers the inner and outer side walls of the first sub-electrode and the inner and outer side walls of the second sub-electrode.

[0006] In some embodiments, along the first direction, the first sub-electrode includes a first end relatively close to the semiconductor body and a second end relatively far away from the semiconductor body, and the second sub-electrode includes a third end relatively close to the semiconductor body and a fourth end relatively far away from the semiconductor body; the first electrode layer also includes: a third sub-electrode, the third sub-electrode is respectively connected to the first end and the third end, and the third sub-electrode and the semiconductor body are coupled.

[0007] In some embodiments, the third sub-electrode includes a third annular structure, an outer contour of the third annular structure is connected to the second sub-electrode, and an inner contour of the third annular structure is connected to the first sub-electrode.

[0008] In some embodiments, the dielectric layer includes: a first sub-dielectric layer, covering the inner side wall of the first sub-electrode; a second sub-dielectric layer, covering the outer side wall of the first sub-electrode; a third sub-dielectric layer, covering the inner side wall of the second sub-electrode; a fourth sub-dielectric layer, covering the outer side wall of the second sub-electrode; a fifth sub-dielectric layer, covering the second end and connecting the first sub-dielectric layer and the second sub-dielectric layer respectively; a sixth sub-dielectric layer, covering the fourth end and connecting the third sub-dielectric layer and the fourth sub-dielectric layer respectively; and a seventh sub-dielectric layer, covering the third sub-electrode and connecting the second sub-dielectric layer and the third sub-dielectric layer respectively.

[0009] In some embodiments, the second electrode layer includes: a first portion covering the inner sidewall of the first sub-dielectric layer; a second portion covering the outer sidewall of the second sub-dielectric layer, the inner sidewall of the third sub-dielectric layer, and the seventh sub-dielectric layer; a third portion covering the outer sidewall of the fourth sub-dielectric layer; a fourth portion covering the fifth sub-dielectric layer and connecting the first portion and the second portion, respectively; and a fifth portion covering the sixth sub-dielectric layer and connecting the second portion and the third portion, respectively.

[0010] In some embodiments, along the first direction, a size of the first sub-electrode is smaller than a size of the second sub-electrode.

[0011] In some embodiments, the semiconductor device further includes: a plurality of the transistor structures, the plurality of the transistor structures are arranged along the second direction and the third direction, and the transistor structure further includes a gate structure coupled to the side wall of the semiconductor body; wherein the gate structures in the plurality of the transistor structures arranged along the third direction are coupled to each other, and any two of the first direction, the second direction and the third direction intersect.

[0012] In some embodiments, the semiconductor device further includes: a plurality of the capacitor structures, and the plurality of the capacitor structures are arranged along the second direction and the third direction; wherein the dielectric layers in the plurality of the capacitor structures arranged along the second direction are connected to each other, and the second electrode layers in the plurality of the capacitor structures arranged along the second direction are connected to each other.

[0013] In some embodiments, the semiconductor body includes a fifth end and a sixth end arranged opposite to each other along the first direction; the semiconductor device also includes: a bit line structure, located on one side of the transistor structure along the first direction, the capacitor structure and the fifth end are coupled, and the bit line structure and the sixth end are coupled; wherein, the multiple transistor structures arranged along the second direction are coupled to the same bit line structure.

[0014] In a second aspect, an embodiment of the present disclosure provides a method for manufacturing a semiconductor device, the method comprising: forming a transistor structure, the transistor structure comprising a semiconductor body extending along a first direction; forming a capacitor structure on one side of the transistor structure along the first direction; the capacitor structure comprising a first electrode layer, a second electrode layer, and a dielectric layer located between the first electrode layer and the second electrode layer, the first electrode layer and the semiconductor body being coupled; wherein the first electrode layer comprises a first sub-electrode and a second sub-electrode surrounding the first sub-electrode, the first sub-electrode comprises a first annular structure, the second sub-electrode comprises a second annular structure, the axial directions of the first annular structure and the second annular structure are both the first direction, and the dielectric layer covers the inner and outer side walls of the first sub-electrode and the inner and outer side walls of the second sub-electrode.

[0015] In some embodiments, the capacitor structure is formed on one side of the transistor structure along the first direction, including: providing an initial stacking structure, the initial stacking structure including semiconductor layers and sacrificial layers alternately stacked along a second direction; the first direction and the second direction intersect; etching the initial stacking structure to form a capacitor hole; removing the sacrificial layer through the capacitor hole to form a gap; forming a first filling layer and a second filling layer in the gap in sequence to form a stacking structure; wherein the first filling layer surrounds the semiconductor layer, and the capacitor hole exposes the first filling layer and the second filling layer alternately stacked along the second direction.

[0016] In some embodiments, the capacitor structure is formed on one side of the transistor structure along the first direction, and further includes: removing the first filling layer to form a first groove; wherein the first groove includes an annular groove, the inner sidewall of the first groove exposes the semiconductor layer, the outer sidewall of the first groove exposes the second filling layer, and the bottom of the first groove exposes the semiconductor body; forming an initial first electrode layer covering the bottom, outer sidewall and inner sidewall of the first groove, covering the end of the semiconductor layer and covering the end of the second filling layer; forming a third filling layer in the first groove; removing the initial first electrode layer covering the end of the semiconductor layer and covering the end of the second filling layer to form a first electrode layer; wherein the first electrode layer includes a first sub-electrode covering the inner sidewall of the first groove, a second sub-electrode covering the outer sidewall of the first groove and a third sub-electrode covering the bottom of the first groove.

[0017] In some embodiments, forming a capacitor structure on one side of the transistor structure along the first direction further includes: removing the semiconductor layer, the second filling layer and the third filling layer to form a second groove, a third groove and a fourth groove, respectively; wherein the second groove exposes the inner side wall of the first sub-electrode, and the third groove exposes the outer side wall of the second sub-electrode; the fourth groove includes an annular groove, and the fourth groove exposes the outer side wall of the first sub-electrode and the inner side wall of the second sub-electrode; forming a dielectric layer in the second groove, the third groove and the fourth groove; wherein the dielectric layer includes a first sub-dielectric layer covering the inner side wall of the first sub-electrode, a second sub-dielectric layer covering the outer side wall of the first sub-electrode, a third sub-dielectric layer covering the inner side wall of the second sub-electrode, and a fourth sub-dielectric layer covering the outer side wall of the second sub-electrode.

[0018] In some embodiments, the capacitor structure is formed on one side of the transistor structure along the first direction, and further includes: forming a second electrode layer in the second groove, the third groove, the fourth groove and the capacitor hole; wherein the second electrode layer includes a first portion covering the inner sidewall of the first sub-dielectric layer, a second portion covering the outer sidewall of the second sub-dielectric layer and the inner sidewall of the third sub-dielectric layer, and a third portion covering the outer sidewall of the fourth sub-dielectric layer.

[0019] In some embodiments, the forming of the transistor structure includes: forming a plurality of the transistor structures, the plurality of the transistor structures are arranged along a second direction and a third direction, the transistor structure further including a gate structure coupled to the side wall of the semiconductor body; wherein the gate structures in the plurality of the transistor structures arranged along the third direction are coupled to each other, and any two of the first direction, the second direction and the third direction intersect.

[0020] In some embodiments, the semiconductor body includes a fifth end and a sixth end arranged opposite to each other along the first direction; the method also includes: forming a bit line structure on one side of the transistor structure along the first direction, the capacitor structure and the fifth end are coupled, and the bit line structure and the sixth end are coupled; wherein, the multiple transistor structures arranged along the second direction are coupled to the same bit line structure.

[0021] The present disclosure provides a semiconductor device and a method for manufacturing the same. In the present disclosure, a first electrode layer coupled to a semiconductor body includes a first sub-electrode and a second sub-electrode surrounding the first sub-electrode. The first sub-electrode and the second sub-electrode are both annular structures, and a dielectric layer covers the inner and outer sidewalls of the first sub-electrode and the inner and outer sidewalls of the second sub-electrode. This is advantageous in reducing the length of the first electrode layer along the first direction while increasing the facing area between the first electrode layer and the second electrode layer, thereby increasing the capacitance of the capacitor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 Schematic diagram of the three-dimensional structure of the memory provided for some examples;

[0023] Figure 2 Schematic diagram of the YZ cross-section structure of the capacitor structure provided for some examples;

[0024] Figure 3 Schematic diagrams of enlarged structures of XZ and YZ cross sections of capacitor structures provided for some examples;

[0025] Figure 4 A schematic diagram of a three-dimensional structure of a semiconductor device provided in an embodiment of the present disclosure;

[0026] Figure 5 A schematic diagram of the YZ cross-sectional structure of a capacitor structure provided by an embodiment of the present disclosure;

[0027] Figure 6 Schematic diagram of an enlarged structure of an XZ cross section and a YZ cross section of a capacitor structure provided by an embodiment of the present disclosure;

[0028] Figure 7 An enlarged schematic diagram of the XZ cross section of a semiconductor device is provided for an embodiment of the present disclosure;

[0029] Figure 8 A schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure;

[0030] Figure 9 A schematic diagram of a partial cross-sectional structure of a semiconductor device during the manufacturing process is provided for some embodiments;

[0031] Figure 10Provides a schematic diagram of the three-dimensional structure of a semiconductor device during the manufacturing process for some embodiments Figure 1 ;

[0032] Figure 11 Provides a schematic diagram of the three-dimensional structure of a semiconductor device during the manufacturing process for some embodiments Figure 2 ;

[0033] Figure 12 Provides a schematic diagram of the three-dimensional structure of a semiconductor device during the manufacturing process for some embodiments Figure 3 ;

[0034] Figure 13 Provides a schematic diagram of the three-dimensional structure of a semiconductor device during the manufacturing process for some embodiments Figure 4 ;

[0035] Figure 14 Provides a schematic diagram of the three-dimensional structure of a semiconductor device during the manufacturing process for some embodiments Figure 5 ;

[0036] Figure 15 Provides a schematic diagram of the three-dimensional structure of a semiconductor device during the manufacturing process for some embodiments Figure 6 ;

[0037] Figure 16 Provides a schematic diagram of the three-dimensional structure of a semiconductor device during the manufacturing process for some embodiments Figure 7 ;

[0038] Figure 17 Provides a schematic diagram of the three-dimensional structure of a semiconductor device during the manufacturing process for some embodiments Figure 8 ;

[0039] Figure 18 Provides a schematic diagram of the three-dimensional structure of a semiconductor device during the manufacturing process for some embodiments Figure 9 ;

[0040] Figure 19 Provides a schematic diagram of the three-dimensional structure of a semiconductor device during the manufacturing process for some embodiments Figure 10 ;

[0041] Figure 20 Provides a schematic diagram of the three-dimensional structure of a semiconductor device during the manufacturing process for some embodiments Figure 10 one;

[0042] Figure 21 Provides a schematic diagram of the three-dimensional structure of a semiconductor device during the manufacturing process for some embodiments Figure 10 two;

[0043] Figure 22 Provides a schematic diagram of the three-dimensional structure of a semiconductor device during the manufacturing process for some embodiments Figure 10 three;

[0044] Figure 23 Provides a schematic diagram of the three-dimensional structure of a semiconductor device during the manufacturing process for some embodiments Figure 10 Four;

[0045] Figure 24 Provides a schematic diagram of the three-dimensional structure of a semiconductor device during the manufacturing process for some embodiments Figure 10 five;

[0046] Figure 25 Provides a schematic diagram of the three-dimensional structure of a semiconductor device during the manufacturing process for some embodiments Figure 10 six;

[0047] Figure 26 Provides a schematic diagram of the three-dimensional structure of a semiconductor device during the manufacturing process for some embodiments Figure 10 seven;

[0048] Figure 27 for Figure 10 A schematic diagram of the partially enlarged structure in the middle dotted circle;

[0049] Figure 28 for Figure 11 A schematic diagram of the partially enlarged structure of the dotted circle and dotted square;

[0050] Figure 29 for Figure 12 A schematic diagram of the partially enlarged structure of the dotted circle and dotted square;

[0051] Figure 30 for Figure 13 A schematic diagram of the partially enlarged structure of the dotted circle and dotted square;

[0052] Figure 31 for Figure 14 A schematic diagram of the partially enlarged structure of the dotted circle and dotted square;

[0053] Figure 32 for Figure 15 A schematic diagram of the partially enlarged structure of the dotted circle and dotted square;

[0054] Figure 33 for Figure 16 A schematic diagram of the partially enlarged structure of the dotted circle and dotted square;

[0055] Figure 34 for Figure 17 A schematic diagram of the partially enlarged structure of the dotted circle and dotted square;

[0056] Figure 35 for Figure 18 A schematic diagram of the partially enlarged structure of the dotted circle and dotted square;

[0057] Figure 36 for Figure 19 A schematic diagram of the partially enlarged structure of the dotted circle and dotted square;

[0058] Figure 37 for Figure 20 A schematic diagram of the partially enlarged structure of the dotted circle and dotted square;

[0059] Figure 38 for Figure 21 A schematic diagram of the partially enlarged structure of the dotted circle and dotted square;

[0060] Figure 39 for Figure 22 A schematic diagram of the partially enlarged structure of the dotted circle and dotted square;

[0061] Figure 40 for Figure 23 A schematic diagram of the partially enlarged structure of the dotted circle and dotted square;

[0062] Figure 41 for Figure 24 A schematic diagram of the partially enlarged structure of the dotted circle and dotted square;

[0063] Figure 42 for Figure 25 A schematic diagram of the partially enlarged structure of the dotted circle and dotted square;

[0064] Figure 43 for Figure 26 Schematic diagram of the local enlarged structure in the middle dotted circle and dotted square. DETAILED DESCRIPTION

[0065] The following will clearly and completely describe the technical solutions in the embodiments of the present disclosure in conjunction with the embodiments of the present disclosure and the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present disclosure.

[0066] In the following description, numerous specific details are provided to provide a more thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present disclosure; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0067] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0068] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to, or coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to, or directly coupled to" another element or layer, there may be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part. However, when the second element, component, region, layer, or part is discussed, it does not necessarily mean that the first element, component, region, layer, or part exists in the present disclosure.

[0069] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, then the elements or features described as "under" or "beneath" or "beneath" the other elements will be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can include both the above and below orientations. The device can be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0070] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0071] In order to fully understand the present disclosure, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present disclosure. The preferred embodiments of the present disclosure are described in detail below. However, in addition to these detailed descriptions, the present disclosure may also have other implementation methods.

[0072] Before introducing the embodiments of the present disclosure, the various directions that may be involved below are defined. The extension direction of the semiconductor body is defined as the first direction, the extension direction of the bit line structure is defined as the second direction, and the extension direction of the word line structure is defined as the third direction. In some embodiments, any two of the first direction, the second direction, and the third direction intersect. In a specific embodiment, any two of the first direction (i.e., the X direction), the second direction (i.e., the Z direction), and the third direction (i.e., the Y direction) are perpendicular to each other. The following three-dimensional structure schematic diagram will be explained as an example in which any two of the X direction, the Y direction, and the Z direction are perpendicular to each other.

[0073] refer to Figures 1 to 3 , Figure 1 Schematic diagram of the three-dimensional structure of the memory provided for some examples, Figure 2 and Figure 3 The cross-sectional structure diagram of the capacitor structure provided for some examples. Figures 1 to 3 , describing the structure of the memory provided by some examples.

[0074] like Figure 1 As shown, the memory 100 includes: a plurality of semiconductor bodies 102 extending along the X direction, the plurality of semiconductor bodies 102 being arranged at intervals along the Y direction and the Z direction; a word line structure 104 extending along the Y direction, the sidewalls of the plurality of semiconductor bodies 102 arranged along the Y direction being coupled to the same word line structure 104; a bit line structure 106 extending along the Z direction, the ends of the plurality of semiconductor bodies 102 arranged along the Z direction being coupled to the same bit line structure 106; a capacitor structure 108 (such as Figure 1 The semiconductor body 102 is connected to the capacitor structure 108 at its end (as shown in the dotted line box).

[0075] right Figure 2 The capacitor structure 108 shown in the dotted circle is enlarged and combined with Figure 3 As shown, the capacitor structure 108 includes: a lower electrode structure 110, an upper electrode structure 116, and a dielectric structure 126 located between the lower electrode structure 110 and the upper electrode structure 116. The lower electrode structure 110 is coupled to an end of the semiconductor body 102. The lower electrode structure 110 includes a first sub-lower electrode 112 and a second sub-lower electrode 114. The first sub-lower electrode 112 is an annular structure with an axis oriented in the X direction. The second sub-lower electrode 114 is located between the first sub-lower electrode 112 and the semiconductor body 102 and is coupled to the end of the semiconductor body 102.

[0076] The upper electrode structure 116 includes a first upper sub-electrode 118, a second upper sub-electrode 120, a third upper sub-electrode 122, and a fourth upper sub-electrode 124. Both the first upper sub-electrode 118 and the second upper sub-electrode 120 are annular structures, with the axes of the annular structures oriented in the X direction. The second upper sub-electrode 120 surrounds the first upper sub-electrode 118. The third upper sub-electrode 122 connects the first upper sub-electrode 118 and the second upper sub-electrode 120, respectively. The fourth upper sub-electrode 124 is located between the first upper sub-electrode 118 and the semiconductor body 102.

[0077] The dielectric structure 126 includes a first sub-dielectric layer 128, a second sub-dielectric layer 130, a third sub-dielectric layer 132, and a fourth sub-dielectric layer 134. Both the first sub-dielectric layer 128 and the second sub-dielectric layer 130 are annular structures, with the axes of the annular structures both oriented in the X direction. The second sub-dielectric layer 130 surrounds the first sub-dielectric layer 128. The third sub-dielectric layer 132 connects the first sub-dielectric layer 128 and the second sub-dielectric layer 130. The fourth sub-dielectric layer 134 is located between the first sub-dielectric layer 128 and the semiconductor body 102.

[0078] In summary, combined with Figure 3 As shown in the YZ cross-sectional structural diagram, from radially outward direction, there are the first sub-upper electrode 118, the first sub-dielectric layer 128, the first sub-lower electrode 112, the second sub-dielectric layer 130, and the second sub-upper electrode 120. It should be noted that the capacitance of the capacitor structure 108 is affected by factors such as the dielectric constant of the dielectric structure 126, the facing area between the lower electrode structure 110 and the upper electrode structure 116, and the distance between the lower electrode structure 110 and the upper electrode structure 116. The greater the dielectric constant of the dielectric structure 126, the larger the facing area between the lower electrode structure 110 and the upper electrode structure 116, and the smaller the distance between the lower electrode structure 110 and the upper electrode structure 116, the greater the capacitance of the capacitor structure 108.

[0079] In some examples, the size of the capacitor structure 108 along the X direction can be increased to increase the facing area between the lower electrode structure 110 and the upper electrode structure 116, thereby increasing the capacitance of the capacitor structure 108. However, increasing the size of the capacitor structure 108 along the X direction may result in a decrease in the integration density of the memory 100, which is not conducive to the miniaturization of the memory 100.

[0080] It should be noted that single-crystal silicon can be used as the active structure in three-dimensional DRAM, and lateral wet etching of single-crystal silicon is also a common process in three-dimensional DRAM. However, because both the substrate and the active structure are made of silicon, the lateral wet etching of single-crystal silicon can also cause severe damage to the substrate, leading to device failure. In other words, increasing the size of capacitor structure 108 along the X direction increases the difficulty of performing the lateral wet etching process on the active structure and increases the difficulty of protecting the substrate.

[0081] In view of this, in order to solve at least one of the above technical problems, an embodiment of the present disclosure provides a semiconductor device and a method for manufacturing the same.

[0082] refer to Figures 4 to 7 , Figure 4 A schematic diagram of a three-dimensional structure of a semiconductor device provided in an embodiment of the present disclosure, Figure 5 and Figure 6 A schematic cross-sectional view of a capacitor structure provided in an embodiment of the present disclosure is shown. Figure 7 The cross-sectional structure diagram of the semiconductor device is provided for the embodiment of the present disclosure. Figures 4 to 7 , the structure of the semiconductor device provided by the embodiment of the present disclosure is described.

[0083] like Figures 4 to 7 As shown, in a first aspect, an embodiment of the present disclosure provides a semiconductor device, the semiconductor device 200 comprising: a transistor structure 202 (such as Figure 4 As shown in the dashed box, the transistor structure 202 includes a semiconductor body 204 extending along the X direction; a capacitor structure 210 (as shown in the dashed box Figure 4 As shown in the dotted box, the capacitor structure 210 is located on one side of the transistor structure 202 along the X direction. The capacitor structure 210 includes a first electrode layer 212, a second electrode layer 228, and a dielectric layer 240 located between the first electrode layer 212 and the second electrode layer 228. The first electrode layer 212 is coupled to the semiconductor body 204. The first electrode layer 212 includes a first sub-electrode 214 and a second sub-electrode 220 surrounding the first sub-electrode 214. The first sub-electrode 214 includes a first annular structure, and the second sub-electrode includes a second annular structure. The axial directions of the first annular structure and the second annular structure are both in the X direction. The dielectric layer 240 covers the inner and outer side walls of the first sub-electrode 214 and the inner and outer side walls of the second sub-electrode 220.

[0084] In the disclosed embodiment, the first electrode layer 212 coupled to the semiconductor body 204 includes a first sub-electrode 214 and a second sub-electrode 220 surrounding the first sub-electrode 214. The first sub-electrode 214 and the second sub-electrode 220 are both annular structures. The dielectric layer 240 covers the inner and outer sidewalls of the first sub-electrode 214 and the inner and outer sidewalls of the second sub-electrode 220. This arrangement helps to reduce the length of the first electrode layer 212 in the X direction while increasing the facing area between the first electrode layer 212 and the second electrode layer 228, thereby increasing the capacitance of the capacitor structure 210.

[0085] In addition, the layout space of the capacitor structure 210 in the semiconductor device 200 mainly depends on the length of the first electrode layer 212 in the X direction. Under the condition of the same capacitance, reducing the length of the first electrode layer 212 in the X direction is conducive to reducing the layout length of the capacitor structure 210 in the X direction, thereby facilitating the integration of more capacitor structures 210 in a unit area of ​​the semiconductor device 200, thereby improving the integration density of the semiconductor device 200. Therefore, the semiconductor device 200 provided by the embodiment of the present disclosure is conducive to improving the integration density of the semiconductor device 200 while increasing the capacitance of the capacitor structure 210.

[0086] The term "coupling" herein refers to the operative connection of multiple conductive structures, which may include but is not limited to the following situations, depending on actual needs: (1) two conductive structures are directly electrically connected; (2) two conductive structures are indirectly electrically connected, for example, through other conductive structures; (3) although the two conductive structures are not electrically connected, one conductive structure can control the electrical properties of the other conductive structure in response to an electrical signal, for example, a gate dielectric layer is provided between the sidewall of the semiconductor body and the gate conductive layer.

[0087] right Figure 5 The capacitor structure 210 shown in the dotted circle is enlarged and combined with Figure 6 As shown in the XZ cross-sectional structural diagram, the capacitor structure 210 includes a first electrode layer 212, a second electrode layer 228 and a dielectric layer 240, and the first electrode layer 212, the second electrode layer 228 and the dielectric layer 240 are schematically shown. Figure 6 Shown in the dotted box.

[0088] Here, the first electrode layer 212 includes a first sub-electrode 214 in a ring structure and a second sub-electrode 220 surrounding the first sub-electrode 214. Along the X direction, the first sub-electrode 214 includes a first end 216 relatively close to the semiconductor body 204 and a second end 218 relatively far away from the semiconductor body 204. The second sub-electrode 220 includes a third end 222 relatively close to the semiconductor body 204 and a fourth end 224 relatively far away from the semiconductor body 204. Figure 6The dotted circle illustrates the first end 216, the second end 218, the third end 222, and the fourth end 224. That is, the radial dimension of the first sub-electrode 214 (ie, the first annular structure) is smaller than the radial dimension of the second sub-electrode 220 (ie, the second annular structure).

[0089] In some embodiments, along the X direction, the size of the first sub-electrode 214 is smaller than the size of the second sub-electrode 220 . In other words, the axial size of the first sub-electrode 214 is smaller than the axial size of the second sub-electrode 220 .

[0090] In some embodiments, the first electrode layer 212 further includes a third sub-electrode 226, wherein the third sub-electrode 226 is connected to the first end 216 and the third end 222, respectively, and the third sub-electrode 226 is coupled to the semiconductor body 204. In other words, the third sub-electrode 226 is located between the first sub-electrode 214 and the semiconductor body 204, and the third sub-electrode 226 is also located between the second sub-electrode 220 and the semiconductor body 204.

[0091] In some embodiments, the plane where the third sub-electrode 226 is located intersects the X direction. For example, the plane where the third sub-electrode 226 is located and the X direction are perpendicular to each other.

[0092] In some embodiments, the third sub-electrode 226 includes a third annular structure, the outer contour of the third annular structure is connected to the second sub-electrode 220, and the inner contour of the third annular structure is connected to the first sub-electrode 214. In other words, the radial dimension of the outer contour of the third annular structure is substantially the same as the radial dimension of the second sub-electrode 220 (i.e., the second annular structure), and the radial dimension of the inner contour of the third annular structure is substantially the same as the radial dimension of the first sub-electrode 214 (i.e., the first annular structure).

[0093] It should be noted that, to facilitate description of the structure of the first electrode layer 212, the first electrode layer 212 is divided into a first sub-electrode 214, a second sub-electrode 220, and a third sub-electrode 226. In practice, the first sub-electrode 214, the second sub-electrode 220, and the third sub-electrode 226 can be formed in the same process, forming an integrally formed structure.

[0094] In some embodiments, the dielectric layer 240 includes: a first sub-dielectric layer 242, covering the inner wall of the first sub-electrode 214, the first sub-electrode 214 surrounds the first sub-dielectric layer 242, and the first sub-dielectric layer 242 also covers the end of the semiconductor body 204, that is, the first sub-dielectric layer 242 is cup-shaped; a second sub-dielectric layer 244, covering the outer wall of the first sub-electrode 214, that is, the second sub-dielectric layer 244 is a ring structure, the second sub-dielectric layer 244 surrounds the first sub-electrode 214; a third sub-dielectric layer 246, covering the inner wall of the second sub-electrode 220, that is, the third sub-dielectric layer 246 is a ring structure, the second sub-electrode 220 surrounds the third sub-dielectric layer 246; a fourth sub-dielectric layer 248, covering the outer wall of the second sub-electrode 220, that is, the fourth sub-dielectric layer 248 is a ring structure, the fourth sub-dielectric layer 248 surrounds the second sub-electrode 220.

[0095] Here, the first sub-dielectric layer 242 is an annular structure, the radial dimension of which is smaller than the radial dimension of the first sub-electrode 214; the second sub-dielectric layer 244 is an annular structure, the radial dimension of which is larger than the radial dimension of the first sub-electrode 214; the third sub-dielectric layer 246 is an annular structure, the radial dimension of which is smaller than the radial dimension of the second sub-electrode 220; and the fourth sub-dielectric layer 248 is an annular structure, the radial dimension of which is larger than the radial dimension of the second sub-electrode 220.

[0096] In some embodiments, the dielectric layer 240 further includes: a fifth sub-dielectric layer 250, covering the second end portion 218 and respectively connecting the first sub-dielectric layer 242 and the second sub-dielectric layer 244; a sixth sub-dielectric layer 252, covering the fourth end portion 224 and respectively connecting the third sub-dielectric layer 246 and the fourth sub-dielectric layer 248; and a seventh sub-dielectric layer 254, covering the third sub-electrode 226 and respectively connecting the second sub-dielectric layer 244 and the third sub-dielectric layer 246.

[0097] In some embodiments, the plane of the fifth sub-dielectric layer 250 intersects the X-direction, for example, the plane of the fifth sub-dielectric layer 250 and the X-direction are mutually perpendicular. The plane of the sixth sub-dielectric layer 252 intersects the X-direction, for example, the plane of the sixth sub-dielectric layer 252 and the X-direction are mutually perpendicular. The plane of the seventh sub-dielectric layer 254 intersects the X-direction, for example, the plane of the seventh sub-dielectric layer 254 and the X-direction are mutually perpendicular.

[0098] It should be noted that, to facilitate description of the structure of the dielectric layer 240, the dielectric layer 240 is divided into a first sub-dielectric layer 242, a second sub-dielectric layer 244, a third sub-dielectric layer 246, a fourth sub-dielectric layer 248, a fifth sub-dielectric layer 250, a sixth sub-dielectric layer 252, and a seventh sub-dielectric layer 254. In practice, the first sub-dielectric layer 242, the second sub-dielectric layer 244, the third sub-dielectric layer 246, the fourth sub-dielectric layer 248, the fifth sub-dielectric layer 250, the sixth sub-dielectric layer 252, and the seventh sub-dielectric layer 254 can be formed in the same process, i.e., they form an integrally formed structure.

[0099] In some embodiments, the second electrode layer 228 includes: a first portion 230 covering the inner sidewall of the first sub-dielectric layer 242, where the first portion 230 can fill the space enclosed by the first sub-dielectric layer 242; a second portion 232 covering the outer sidewall of the second sub-dielectric layer 244, the inner sidewall of the third sub-dielectric layer 246, and the seventh sub-dielectric layer 254, where the second portion 232 can fill the space enclosed by the second sub-dielectric layer 244, the third sub-dielectric layer 246, and the seventh sub-dielectric layer 254; a third portion 234 covering the outer sidewall of the fourth sub-dielectric layer 248; a fourth portion 236 covering the fifth sub-dielectric layer 250 and connecting the first portion 230 and the second portion 232, respectively; and a fifth portion 238 covering the sixth sub-dielectric layer 252 and connecting the second portion 232 and the third portion 234, respectively.

[0100] It should be noted that, to facilitate description of the structure of the second electrode layer 228, the second electrode layer 228 is divided into a first portion 230, a second portion 232, a third portion 234, a fourth portion 236, and a fifth portion 238. In practice, the first portion 230, the second portion 232, the third portion 234, the fourth portion 236, and the fifth portion 238 can be formed in the same process, i.e., an integrally formed structure.

[0101] In summary, combined with Figure 6As shown in the YZ cross-sectional structural diagram, from radially outward, the first portion 230, first sub-dielectric layer 242, first sub-electrode 214, second sub-dielectric layer 244, second portion 232, third sub-dielectric layer 246, second sub-electrode 220, fourth sub-dielectric layer 248, and third portion 234 are sequentially arranged. The first sub-dielectric layer 242 is located between the first portion 230 and the first sub-electrode 214, the second sub-dielectric layer 244 is located between the first sub-electrode 214 and the second portion 232, the third sub-dielectric layer 246 is located between the second portion 232 and the second sub-electrode 220, and the fourth sub-dielectric layer 248 is located between the second sub-electrode 220 and the third portion 234. In other words, the sum of the areas of the first sub-dielectric layer 242, the second sub-dielectric layer 244, the third sub-dielectric layer 246, and the fourth sub-dielectric layer 248 can be considered the area of ​​the capacitor structure 210 facing each other between the first electrode layer 212 and the second electrode layer 228.

[0102] It should be noted that Figure 6 The YZ cross-sectional structural diagram includes cross sections A1A2 and B1B2. The enlarged XZ cross-sectional structural diagram, shown in the dashed box, is obtained along cross section A1A2. This diagram illustrates the cup-shaped first sub-dielectric layer 242. The space enclosed by the first sub-dielectric layer 242 can subsequently be filled to form the first portion 230 of the second electrode layer 228. The XZ cross-sectional structural diagram is obtained along cross section B1B2. This cross-sectional location passes right through the first sub-dielectric layer 242, preventing the cup-shaped first sub-dielectric layer 242 from being clearly visible.

[0103] In the embodiment of the present disclosure, the dielectric layer 240 is located between the first electrode layer 212 and the second electrode layer 228, and the area facing each other between the first electrode layer 212 and the second electrode layer 228 can be determined based on the area of ​​the dielectric layer 240. The first electrode layer 212 includes a double-layer lower electrode (i.e., a first sub-electrode 214 and a second sub-electrode 220), and the dielectric layer 240 includes four circles of dielectric layers (i.e., a first sub-dielectric layer 242, a second sub-dielectric layer 244, a third sub-dielectric layer 246, and a fourth sub-dielectric layer 248) surrounding the double-layer lower electrode, thereby improving the utilization of the YZ space. While ensuring the capacitance of the capacitor structure 210, the length of the capacitor structure 210 in the X direction can be reduced, thereby reducing the difficulty of performing a lateral wet etching process on the active structure and reducing the difficulty of protecting the substrate.

[0104] In addition, the fifth sub-dielectric layer 250 is located between the second end 218 of the first sub-electrode 214 and the fourth portion 236, the sixth sub-dielectric layer 252 is located between the fourth end 224 of the second sub-electrode 220 and the fifth portion 238, and the seventh sub-dielectric layer 254 is located between the third sub-electrode 226 and the second portion 232. In this way, the facing area between the first electrode layer 212 and the second electrode layer 228 can be further increased, thereby increasing the capacitance of the capacitor structure 210.

[0105] The term "annular structure" herein includes a circular annular structure, a square annular structure or any other annular structure. Figure 6 The YZ cross-sectional structural diagram uses a square ring structure as an example, which does not constitute a limitation on the scope of protection of the present disclosure.

[0106] In some embodiments, the semiconductor body 204 may include any suitable semiconductor material, including but not limited to silicon material and metal oxide semiconductor material, etc. In this embodiment, the semiconductor body 204 may include, for example, single crystal silicon.

[0107] In some embodiments, the materials of the first electrode layer 212 and the second electrode layer 228 may be the same or different, including conductive materials. The materials of the first electrode layer 212 and the second electrode layer 228 may include, but are not limited to, at least one of titanium nitride (TiN), tantalum nitride (TaN), polysilicon (Poly), tungsten (W), copper (Cu), and metal silicide.

[0108] In some embodiments, dielectric layer 240 may include any suitable dielectric material, such as silicon oxide, silicon nitride, a high-k dielectric material, or any combination thereof. The high-k dielectric material may include, but is not limited to, at least one of strontium titanate, hafnium oxide, chromium oxide, and zirconium oxide. Using a high-k dielectric material as dielectric layer 240 may further increase the capacitance of capacitor structure 210.

[0109] like Figure 7 As shown, in some embodiments, the semiconductor device 200 further includes: a plurality of transistor structures 202, the plurality of transistor structures 202 are arranged along the Y direction and the Z direction, the transistor structure 202 further includes a gate structure 256 coupled to the side wall of the semiconductor body 204; wherein the gate structures 256 in the plurality of transistor structures 202 arranged along the Y direction are coupled to each other.

[0110] Here, the gate structures 256 can be coupled to each other to form a wordline structure. The gate structure 256 and the wordline structure can refer to the same structure, and the portion of the wordline structure located on the sidewall of the semiconductor body 204 can serve as the gate structure in the transistor structure. In other words, multiple semiconductor bodies 204 arranged along the Y direction can be coupled to the same wordline structure. Depending on the amount of sidewalls of the semiconductor body 204 covered by the gate structure 256, the gate structure 256 can be classified as a single-gate structure, a double-gate structure, a triple-gate structure, or a full-surround gate structure.

[0111] In some embodiments, the gate structure 256 includes a gate conductive layer 258 and a gate dielectric layer 260 . The gate dielectric layer 260 is located between the sidewalls of the semiconductor body 204 and the gate conductive layer 258 .

[0112] In some embodiments, the gate conductive layer 258 may include a conductive material, such as at least one of titanium nitride (TiN), tungsten (W), and silver (Ag). The gate dielectric layer 260 may include a dielectric material, such as at least one of silicon oxide, silicon nitride, or silicon oxynitride.

[0113] It should be noted that since the semiconductor device 200 may include multiple memory cells arranged along the X, Y, and Z directions, each memory cell includes a transistor structure 202 and a coupled capacitor structure 210. To simplify the description, the semiconductor device 200 is divided into multiple layers stacked along the Z direction. The memory cells in each layer are arranged in the same manner, and each layer includes multiple memory cells arranged along the X and Y directions. The technical characteristics of the semiconductor device 200 can be determined by defining the technical characteristics of each layer and the relationship between different layers.

[0114] Here, in each level, multiple transistor structures 202 are arranged along the X and Y directions, and correspondingly, multiple semiconductor bodies 204 included in the multiple transistor structures 202 are arranged along the X and Y directions. Thus, in the semiconductor device 200, multiple transistor structures 202 are arranged along the X, Y, and Z directions, and multiple semiconductor bodies 204 are arranged along the X, Y, and Z directions.

[0115] Here, in each level, the word line structure extends along the Y direction, and multiple word line structures are arranged along the X direction. Thus, in the semiconductor device 200 , multiple word line structures are arranged along the X direction and the Z direction.

[0116] In some embodiments, in each level, the multiple word line structures can be divided into multiple word line groups, each word line group including two word line structures adjacent along the X direction. Thus, in the semiconductor device 200, each word line group includes two word line sub-groups adjacent along the X direction, and each word line sub-group includes multiple word line structures arranged along the Z direction.

[0117] In some embodiments, the semiconductor body 204 includes a fifth end 206 and a sixth end 208 disposed opposite each other along a first direction. The semiconductor device 200 further includes a bitline structure 262 located on one side of the transistor structure 202 along the X direction. The capacitor structure 210 is coupled to the fifth end 206, and the bitline structure 262 is coupled to the sixth end 208. Multiple transistor structures 202 arranged along the Z direction are coupled to the same bitline structure 262. In the semiconductor device 200, the bitline structure 262 extends along the Z direction, and the multiple bitline structures 262 are arranged along the X and Y directions.

[0118] In some embodiments, the plurality of bit line structures 262 may be divided into a plurality of bit line groups 264 (eg, Figure 7 Each bit line group 264 includes two bit line sub-groups adjacent to each other along the X direction, and each bit line sub-group includes a plurality of bit line structures 262 arranged along the Y direction. The bit line group 264 is located between two word line sub-groups in the same word line group.

[0119] In some embodiments, the bit line structure 262 may include a conductive material. In some embodiments, the bit line structure may include a single-layer structure, or a multi-layer structure.

[0120] In some embodiments, the semiconductor device 200 further includes: a plurality of capacitor structures 210, the plurality of capacitor structures 210 being arranged along the Y direction and the Z direction; wherein the dielectric layers 240 in the plurality of capacitor structures 210 arranged along the Z direction are interconnected, and the second electrode layers 228 in the plurality of capacitor structures 210 arranged along the Z direction are interconnected. In other words, the second electrode layers 228 in the plurality of capacitor structures 210 arranged along the Z direction can be commonly coupled to a common terminal.

[0121] Figure 7The dashed box in the middle illustrates two adjacent memory cells along the X-direction, namely, a first memory cell 266 and a second memory cell 268. The first memory cell 266 and the second memory cell 268 are located on the same level. The first memory cell 266 includes a first transistor structure and a first capacitor structure, which are coupled to a first bitline structure. The second memory cell 268 includes a second transistor structure and a second capacitor structure, which are coupled to a second bitline structure. The positional relationship between the first transistor structure, the first capacitor structure, and the first bitline structure is mirror-symmetrical to the positional relationship between the second transistor structure, the second capacitor structure, and the second bitline structure. For the first memory cell 266, the first capacitor structure is located on the negative side of the first transistor structure along the X-direction (i.e., the left side), and the first bitline structure is located on the positive side of the first transistor structure along the X-direction (i.e., the right side). For the second memory cell 268, the second bitline structure is located on the negative side of the second transistor structure along the X-direction (i.e., the left side), and the second capacitor structure is located on the positive side of the second transistor structure along the X-direction (i.e., the right side). That is, the first memory cell 266 and the second memory cell 268 are mirror-symmetric about the YZ plane between the bit line structures 262. It is understood that the first memory cell 266 and the second memory cell 268 can be any two memory cells in a plurality of memory cells that meet the above coupling relationship.

[0122] Here, the first semiconductor body in the first memory cell 266 is coupled to a first word line structure, and the second semiconductor body in the second memory cell 268 is coupled to a second word line structure. The first word line structure and the second word line structure belong to the same word line group.

[0123] Here, the first transistor structure in the first memory cell 266 is coupled to the first bitline structure, and the second transistor structure in the second memory cell 268 is coupled to the second bitline structure. The first bitline structure and the second bitline structure belong to the same bitline group. In other words, the first bitline structure and the second bitline structure can be formed in the same bitline hole.

[0124] Here, the first capacitor structure coupled to the first transistor structure in the first storage unit 266 and the second capacitor structure coupled to the second transistor structure in the second storage unit 268 may be formed in different capacitor holes.

[0125] Figure 7The dotted box illustrates two adjacent memory cells along the X-direction, namely, the third memory cell 270 and the fourth memory cell 272. The third memory cell 270 and the fourth memory cell 272 are located on the same level. The third memory cell 270 includes a third transistor structure and a third capacitor structure, which are coupled to the third bitline structure. The fourth memory cell 272 includes a fourth transistor structure and a fourth capacitor structure, which are coupled to the fourth bitline structure. The positional relationship between the third transistor structure, the third capacitor structure, and the third bitline structure is mirror-symmetrical to the positional relationship between the fourth transistor structure, the fourth capacitor structure, and the fourth bitline structure. For the third memory cell 270, the third bitline structure is located on the negative side of the third transistor structure along the X-direction (i.e., the left side), and the third capacitor structure is located on the positive side of the third transistor structure along the X-direction (i.e., the right side). For the fourth memory cell 272, the fourth capacitor structure is located on the negative side of the fourth transistor structure along the X-direction (i.e., the left side), and the fourth bitline structure is located on the positive side of the fourth transistor structure along the X-direction (i.e., the right side). That is, the third storage unit 270 and the fourth storage unit 272 are mirror-symmetrical with respect to the capacitor structure 210. It is understandable that the third storage unit 270 and the fourth storage unit 272 can be any two storage units among the plurality of storage units that satisfy the above coupling relationship.

[0126] Here, the third semiconductor body in the third memory cell 270 is coupled to the third word line structure, and the fourth semiconductor body in the fourth memory cell 272 is coupled to the fourth word line structure. The third word line structure and the fourth word line structure belong to different word line groups.

[0127] Here, the third bit line structure coupled to the third transistor structure in the third storage unit 270 and the fourth bit line structure coupled to the fourth transistor structure in the fourth storage unit 272 can be formed in different bit line holes, that is, the third bit line structure and the fourth bit line structure belong to different bit line groups.

[0128] Here, the third capacitor structure in the third storage unit 270 and the fourth capacitor structure in the fourth storage unit 272 may share the second electrode layer. In other words, the third capacitor structure in the third storage unit 270 and the fourth capacitor structure in the fourth storage unit 272 may be formed in the same capacitor hole.

[0129] refer to Figure 8 , Figure 8 Schematic diagram of the process of manufacturing a semiconductor device according to an embodiment of the present disclosure. Figure 8 As shown, in a second aspect, an embodiment of the present disclosure provides a method for manufacturing a semiconductor device, the method comprising:

[0130] Step S310: forming a transistor structure, where the transistor structure includes a semiconductor body extending along a first direction;

[0131] Step S320: forming a capacitor structure on one side of the transistor structure along the first direction; the capacitor structure includes a first electrode layer, a second electrode layer, and a dielectric layer located between the first electrode layer and the second electrode layer, and the first electrode layer is coupled to the semiconductor body; wherein, the first electrode layer includes a first sub-electrode and a second sub-electrode surrounding the first sub-electrode, the first sub-electrode includes a first annular structure, the second sub-electrode includes a second annular structure, the axial directions of the first annular structure and the second annular structure are both the first direction, and the dielectric layer covers the inner side wall and the outer side wall of the first sub-electrode and the inner side wall and the outer side wall of the second sub-electrode.

[0132] Figures 10 to 26 These are schematic diagrams of the three-dimensional structure of semiconductor devices during the manufacturing process. Figure 9 、 Figures 27 to 43 All of them are schematic diagrams of partial cross-sectional structures of semiconductor devices during the manufacturing process. Figure 8 、 Figures 9 to 43 , which provides a detailed description of the manufacturing process of semiconductor devices. Figures 10 to 26 The dotted circle in the middle shows the XZ cross-sectional structure diagram of the capacitor structure 210. Figures 11 to 26 The dotted box in the middle shows a YZ cross-sectional structural diagram of the capacitor structure 210 .

[0133] like Figure 9 As shown, in some embodiments, step S310 includes: providing an initial stacked structure 402, the initial stacked structure 402 including semiconductor layers 404 and sacrificial layers 406 alternately stacked along the Z direction; etching the initial stacked structure 402 along the Z direction to form capacitor holes 408, the capacitor holes 408 exposing the semiconductor layers 404 and sacrificial layers 406 alternately stacked along the Z direction. Here, the semiconductor layer 404 can be subsequently used to form the semiconductor body 204. The semiconductor body 204 extends along the X direction and includes a source, a drain, and a channel located between the source and the drain.

[0134] In some embodiments, the process of forming the semiconductor layer 404 and the sacrificial layer 406 may include, but is not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0135] In some embodiments, semiconductor layer 404 may include, for example, single crystal silicon, and sacrificial layer 406 may include, for example, silicon germanium (SiGe). For example, SiGe may be epitaxially grown on a surface of single crystal silicon, and SiGe may be selectively and directionally grown on the surface of single crystal silicon, resulting in a simple and controllable process.

[0136] Return Reference Figure 7 As shown, in some embodiments, step S310 includes: forming a plurality of transistor structures 202, the transistor structure 202 including a semiconductor body 204 and a gate structure 256 coupled to the sidewall of the semiconductor body 204; wherein the gate structures 256 in the plurality of transistor structures 202 arranged along the Y direction are coupled to each other.

[0137] In some embodiments, the method further includes: forming a bit line structure 262 on one side of the transistor structure 202 along the X direction, coupling the capacitor structure 210 to the fifth end 206, and coupling the bit line structure 262 to the sixth end 208; wherein, multiple transistor structures 202 arranged along the Z direction are coupled to the same bit line structure 262.

[0138] In some embodiments, the method further includes: etching the initial stack structure 402 along the Z direction to form bit line holes, wherein the bit line holes and capacitor holes 408 are alternately arranged along the X direction. The transistor structure 202 (such as Figure 10 The transistor structure 202, the word line structure, and the bit line structure 262 are formed in the bit line hole. The present disclosure does not specifically limit the specific steps for forming the transistor structure 202, the word line structure, and the bit line structure 262. The following example illustrates the formation of the transistor structure 202, the word line structure, and the bit line structure 262 in sequence, followed by the formation of the capacitor structure.

[0139] In some embodiments, the process of etching to form the capacitor hole 408 and the bit line hole may include, for example, a dry etching process.

[0140] like Figure 10 and Figure 27 As shown, in some embodiments, step S310 includes: removing the sacrificial layer 406 through the capacitor hole 408 to form a gap; forming an isolation layer 410 in the gap, and isolating adjacent semiconductor layers 404 along the Z direction by the isolation layer 410. Here, the transistor structure includes a semiconductor body 204, which is formed by the semiconductor layer 404 in the initial stacked structure. Therefore, the semiconductor layer 404 and the semiconductor body 204 are in contact at their ends, that is, the semiconductor layer 404 and the semiconductor body 204 are located at the same height.

[0141] Exemplarily, an isolation layer 410 , a silicon nitride layer, and a polysilicon layer are sequentially formed in the space formed by the gap and the capacitor hole 408 ; wherein the isolation layer 410 is located in the gap, and the silicon nitride layer and the polysilicon layer are located in the capacitor hole 408 .

[0142] In some embodiments, the process of forming the isolation layer 410 , the silicon nitride layer, and the polysilicon layer may include, but is not limited to, CVD, PVD, ALD, or any combination thereof.

[0143] In some embodiments, the isolation layer 410 may include, for example, silicon oxide.

[0144] like Figure 11 and Figure 28 As shown, the method further includes: removing the silicon nitride layer, the polysilicon layer and the isolation layer 410 in the capacitor hole 408, so that the capacitor hole 408 exposes the semiconductor layer 404 and the isolation layer 410 alternately stacked along the Z direction.

[0145] like Figure 12 and Figure 29 As shown, the method further includes: removing the isolation layer 410 by lateral etching to form a gap 412. The semiconductor layers 404 stacked along the Z direction are separated by the gap 412, and the gap 412 is connected to the capacitor hole 408. Here, the sidewalls of the semiconductor layer 404 extend along the X direction. For example, the semiconductor layer 404 may include two sidewalls arranged oppositely along the Y direction and two sidewalls arranged oppositely along the Z direction. The gap 412 exposes the four sidewalls of the semiconductor layer 404. The semiconductor layer 404 may also include two end portions arranged oppositely along the X direction. One of the two end portions of the semiconductor layer 404 is coupled to an end portion of the semiconductor body 204. The capacitor hole 408 exposes the other end portion of the two end portions of the semiconductor layer 404.

[0146] In some embodiments, the process of etching and removing the isolation layer 410 may include, for example, a wet etching process.

[0147] like Figure 13 and Figure 30As shown, in some embodiments, step S310 further includes: forming a first filling layer 414 in the space formed by the gap 412 and the capacitor hole 408. Here, the sidewalls of the first filling layer 414 extend along the X direction. For example, the first filling layer 414 may include two sidewalls arranged oppositely along the Y direction and two sidewalls arranged oppositely along the Z direction. The gap 412 exposes the four sidewalls of the first filling layer 414. The first filling layer 414 may also include two ends arranged oppositely along the X direction. One of the two ends of the first filling layer 414 is relatively close to the semiconductor body 204, and the other end of the two ends of the first filling layer 414 is relatively far away from the semiconductor body 204. The capacitor hole 408 exposes the other end of the two ends of the first filling layer 414.

[0148] In some embodiments, the first filling layer 414 may include, for example, silicon oxide. For example, the semiconductor layer 404 may be subjected to an in-situ oxidation process so that an oxide layer is formed on the surface of the semiconductor layer 404 exposed by the gap 412 and the capacitor hole 408, serving as the first filling layer 414. Figure 17 As shown, the first filling layer 414 surrounds the sidewalls of the semiconductor layer 404 and also covers the end of the semiconductor layer 404 , where the gap 412 and the capacitor hole 408 are not fully filled.

[0149] like Figure 14 and Figure 31 As shown, in some embodiments, step S310 further includes: forming an initial second filling layer 416S in the space formed by the gap 412 and the capacitor hole 408; wherein the capacitor hole 408 exposes the initial second filling layer 416S.

[0150] In some embodiments, the initial second filler layer 416S may include, for example, polysilicon. Figure 31 As shown, the initial second filling layer 416S surrounds the sidewalls of the first filling layer 414 and the initial second filling layer 416S also covers the end of the first filling layer 414 where the gap 412 has been fully filled.

[0151] In some embodiments, the process of forming the initial second filling layer 416S may include, but is not limited to, CVD, PVD, ALD, or any combination thereof.

[0152] like Figure 15 and Figure 32 As shown, in some embodiments, step S310 also includes: etching away a portion of the initial second filling layer 416S through the capacitor hole 408 to form a second filling layer 416; wherein the capacitor hole 408 exposes the first filling layer 414 and the second filling layer 416 alternately stacked along the Z direction, that is, the capacitor hole 408 exposes the end of the first filling layer 414 and the end of the second filling layer 416.

[0153] Here, the stacked structure 418 includes a semiconductor layer 404, a first filling layer 414, and a second filling layer 416. Figure 32 As shown in the YZ cross-sectional structural diagram, the first filling layer 414 surrounds the semiconductor layer 404 , and the second filling layer 416 surrounds the first filling layer 414 .

[0154] In some embodiments, the process of etching and removing a portion of the initial second filling layer 416S may include, for example, a dry etching process.

[0155] In the disclosed embodiment, by oxidizing the semiconductor layer 404, the stacked structure 418 in the YZ space is configured as a three-layer space consisting of the semiconductor layer 404, the first filling layer 414, and the second filling layer 416, thereby fully utilizing the YZ space. In other words, by fully utilizing the YZ space, the capacitance of the capacitor structure 210 can be increased, eliminating the need to increase or even reducing the length of the capacitor structure 210 in the X direction. This reduces the difficulty of performing a lateral wet etching process on the active structure and the difficulty of protecting the substrate.

[0156] like Figure 16 and Figure 33 As shown, in some embodiments, step S320 further includes: removing the first filling layer 414 by lateral etching to form a first groove 420; wherein the first groove 420 comprises an annular groove, wherein the inner sidewall of the first groove 420 exposes the sidewall of the semiconductor layer 404, the outer sidewall of the first groove 420 exposes the sidewall of the second filling layer 416, and the bottom of the first groove 420 exposes the end of the semiconductor body 204. More specifically, the first groove 420 is connected to the capacitor hole 408, and the capacitor hole 408 exposes the end of the semiconductor layer 404 and the end of the second filling layer 416.

[0157] In some embodiments, the process of etching and removing the first filling layer 414 may include, for example, a wet etching process.

[0158] like Figure 17 and Figure 34 As shown, in some embodiments, step S320 further includes: forming an initial first electrode layer 212S covering the bottom, outer and inner sidewalls of the first groove 420, covering the end of the semiconductor layer 404, and covering the end of the second filling layer 416. Here, the initial first electrode layer 212S covers the sidewalls and ends of the semiconductor layer 404, covers the sidewalls and ends of the third filling layer 422, and covers the end of the semiconductor body 204.

[0159] like Figure 18 and Figure 35As shown, in some embodiments, step S320 further includes: forming an initial third filling layer 422S covering the surface of the initial first electrode layer 212S.

[0160] In some embodiments, the process of forming the initial first electrode layer 212S and the initial third filling layer 422S may include, but is not limited to, CVD, PVD, ALD, or any combination thereof.

[0161] In some embodiments, the material of the initial first electrode layer 212S may include, for example, titanium nitride, and the material of the initial third filling layer 422S may include, for example, polysilicon.

[0162] like Figure 19 and Figure 36 As shown, in some embodiments, step S320 further includes: etching and removing a portion of the initial third filling layer 422S to form a third filling layer 422. Here, the capacitor hole 408 exposes the initial first electrode layer 212S covering the end of the semiconductor layer 404 and the initial first electrode layer 212S covering the end of the third filling layer 422. The capacitor hole 408 exposes the initial first electrode layer 212S and the third filling layer 422 alternately stacked along the Z direction.

[0163] like Figure 20 and Figure 37 As shown, in some embodiments, step S320 further includes removing the initial first electrode layer 212S covering the end of the semiconductor layer 404 and the end of the second filling layer 416 to form the first electrode layer 212. The capacitor hole 408 exposes the second filling layer 416, the third filling layer 422 and the semiconductor layer 404.

[0164] Here, the first electrode layer 212 includes a first sub-electrode 214 covering the inner sidewall of the first groove 420 , a second sub-electrode 220 covering the outer sidewall of the first groove 420 , and a third sub-electrode 226 covering the bottom of the first groove 420 .

[0165] like Figure 21 and Figure 38 As shown, in some embodiments, step S320 further includes: removing the semiconductor layer 404, the second filling layer 416, and the third filling layer 422 by lateral etching to form a second groove 424, a third groove 426, and a fourth groove 428, respectively. The second groove 424 exposes the inner sidewall of the first sub-electrode 214 and the third sub-electrode 226, and the third groove 426 exposes the outer sidewall of the second sub-electrode 220. The fourth groove 428 comprises an annular groove, exposing the outer sidewall of the first sub-electrode 214 and the inner sidewall of the second sub-electrode 220. The capacitor hole 408 also exposes the end of the first sub-electrode 214 and the end of the second sub-electrode 220.

[0166] Return Reference Figure 32 and Figure 33 As shown, the first filling layer 414 covers the sidewalls and ends of the semiconductor layer 404. After removing the first filling layer 414, the end of the second filling layer 416 protrudes from the end of the semiconductor layer 404 along the X direction. Figure 38 As shown, the first sub-electrode 214 is formed on the sidewall of the semiconductor layer 404 , and the second sub-electrode 220 covers the sidewall of the second filling layer 416 . Therefore, along the X direction, the size of the first sub-electrode 214 is smaller than that of the second sub-electrode 220 .

[0167] In some embodiments, the process of removing the semiconductor layer 404, the second filling layer 416, and the third filling layer 422 may include a wet etching process. In this embodiment, the semiconductor layer 404 may include, for example, single crystal silicon, and the second filling layer 416 and the third filling layer 422 may include, for example, polycrystalline silicon.

[0168] like Figure 22 and Figure 39 As shown, in some embodiments, step S320 further includes: forming a dielectric layer 240 in the second groove 424, the third groove 426 and the fourth groove 428. Return to reference Figure 6 As shown, the dielectric layer 240 includes a first sub-dielectric layer 242 covering the inner wall of the first sub-electrode 214, a second sub-dielectric layer 244 covering the outer wall of the first sub-electrode 214, a third sub-dielectric layer 246 covering the inner wall of the second sub-electrode 220, and a fourth sub-dielectric layer 248 covering the outer wall of the second sub-electrode 220.

[0169] The dielectric layer 240 further includes a fifth dielectric layer 250 covering the end of the first sub-electrode 214 and respectively connecting the first and second dielectric layers 242 and 244; a sixth dielectric layer 252 covering the end of the second sub-electrode 220 and respectively connecting the third and fourth dielectric layers 246 and 248; and a seventh dielectric layer 254 covering the third sub-electrode 226. The dielectric layers 240 in the plurality of capacitor structures 210 arranged along the Z direction are interconnected.

[0170] In some embodiments, the process of forming the dielectric layer 240 may include, but is not limited to, CVD, PVD, ALD, or any combination thereof.

[0171] like Figure 23 and Figure 40 As shown, in some embodiments, step S320 further includes: forming a second electrode layer 228 in the second groove 424, the third groove 426, the fourth groove 428 and the capacitor hole 408. Return to reference Figure 6As shown, the second electrode layer 228 includes a first portion 230 covering the inner sidewall of the first sub-dielectric layer 242 , a second portion 232 covering the outer sidewalls of the second sub-dielectric layer 244 and the inner sidewalls of the third sub-dielectric layer 246 , and a third portion 234 covering the outer sidewall of the fourth sub-dielectric layer 248 .

[0172] The second electrode layer 228 further includes a fourth portion 236 covering the fifth dielectric sub-layer 250 and connecting the first portion 230 and the second portion 232, and a sixth dielectric sub-layer 252 covering the second portion 232 and connecting the third portion 234. The dielectric layers 240 in the plurality of capacitor structures 210 arranged along the Z direction are interconnected.

[0173] like Figure 24 and Figure 41 As shown, the method further includes: forming a first conductive layer 430 in the capacitor hole 408. In some embodiments, the material of the first conductive layer 430 may include, for example, silicon germanium (SiGe).

[0174] like Figure 25 and Figure 42 As shown, the method further includes: forming a second conductive layer 432 in the capacitor hole 408 .

[0175] In some embodiments, the material of the second conductive layer 432 may include, for example, titanium nitride (TiN).

[0176] like Figure 26 and Figure 43 As shown, the method further includes: forming a third conductive layer 434 in the capacitor hole 408.

[0177] In some embodiments, the material of the third conductive layer 434 may include, for example, tungsten (W).

[0178] In some embodiments, the process of forming the second electrode layer 228 , the first conductive layer 430 , the second conductive layer 432 , and the third conductive layer 434 may include, but is not limited to, CVD, PVD, ALD, or any combination thereof.

[0179] Here, the capacitor hole 408 is filled with the first conductive layer 430 , the second conductive layer 432 and the third conductive layer 434 , and the first conductive layer 430 , the second conductive layer 432 and the third conductive layer 434 are coupled to the second electrode layer 228 in sequence to lead out the electrical signal of the second electrode layer 228 .

[0180] The present disclosure provides a semiconductor device and a method for manufacturing the same. In the present disclosure, a first electrode layer coupled to a semiconductor body includes a first sub-electrode and a second sub-electrode surrounding the first sub-electrode. The first sub-electrode and the second sub-electrode are both annular structures, and a dielectric layer covers the inner and outer sidewalls of the first sub-electrode and the inner and outer sidewalls of the second sub-electrode. This is advantageous in reducing the length of the first electrode layer along the first direction while increasing the facing area between the first electrode layer and the second electrode layer, thereby increasing the capacitance of the capacitor structure.

[0181] It should be understood that “one embodiment” or “an embodiment” mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, “in one embodiment” or “in an embodiment” appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0182] The above description is only a preferred embodiment of the present disclosure and does not limit the patent scope of the present disclosure. All equivalent structural transformations made by using the contents of the present disclosure and the drawings under the inventive concept of the present disclosure, or direct / indirect application in other related technical fields are included in the patent protection scope of the present disclosure.

Claims

1. A semiconductor device, characterized in that: The semiconductor device comprises: a transistor structure comprising a semiconductor body extending along a first direction; a capacitor structure located on one side of the transistor structure along the first direction, the capacitor structure comprising a first electrode layer, a second electrode layer, and a dielectric layer located between the first electrode layer and the second electrode layer, wherein the first electrode layer is coupled to the semiconductor body; wherein the first electrode layer comprises a first sub-electrode and a second sub-electrode surrounding the first sub-electrode, the first sub-electrode comprises a first annular structure, the second sub-electrode comprises a second annular structure, and the axial directions of the first annular structure and the second annular structure are both in the first direction; the dielectric layer comprises a first sub-dielectric layer covering an inner sidewall of the first sub-electrode, a second sub-dielectric layer covering an outer sidewall of the first sub-electrode, a third sub-dielectric layer covering an inner sidewall of the second sub-electrode, and a fourth sub-dielectric layer covering an outer sidewall of the second sub-electrode; and the second electrode layer comprises a first portion covering the inner sidewall of the first sub-dielectric layer, a second portion covering the outer sidewall of the second sub-dielectric layer and the inner wall of the third sub-dielectric layer, and a third portion covering the outer sidewall of the fourth sub-dielectric layer; The first sub-electrode includes a first end relatively close to the semiconductor body and a second end relatively far away from the semiconductor body, and the second sub-electrode includes a third end relatively close to the semiconductor body and a fourth end relatively far away from the semiconductor body; the first electrode layer also includes: a third sub-electrode, the third sub-electrode is respectively connected to the first end and the third end, and the third sub-electrode is coupled to the semiconductor body; the dielectric layer also includes: a seventh sub-dielectric layer covering the third sub-electrode, and the seventh sub-dielectric layer is respectively connected to the second sub-dielectric layer and the third sub-dielectric layer; the second part also covers the seventh sub-dielectric layer.

2. The semiconductor device according to claim 1, wherein The third sub-electrode includes a third annular structure, an outer contour of the third annular structure is connected to the second sub-electrode, and an inner contour of the third annular structure is connected to the first sub-electrode.

3. The semiconductor device according to claim 1, wherein The dielectric layer further comprises: a fifth sub-dielectric layer, covering the second end portion and respectively connecting the first sub-dielectric layer and the second sub-dielectric layer; The sixth sub-dielectric layer covers the fourth end portion and is respectively connected to the third sub-dielectric layer and the fourth sub-dielectric layer.

4. The semiconductor device according to claim 3, wherein The second electrode layer further includes: a fourth portion, covering the fifth sub-dielectric layer and respectively connecting the first portion and the second portion; The fifth portion covers the sixth sub-dielectric layer and is respectively connected to the second portion and the third portion.

5. The semiconductor device according to claim 1, wherein Along the first direction, a size of the first sub-electrode is smaller than a size of the second sub-electrode. The semiconductor device according to claim 1 , wherein: The semiconductor device further includes: A plurality of the transistor structures are arranged along a second direction and a third direction, and the transistor structure further includes a gate structure coupled to a side wall of the semiconductor body; wherein the gate structures in the plurality of the transistor structures arranged along the third direction are coupled to each other, and any two of the first direction, the second direction and the third direction intersect.

7. The semiconductor device according to claim 6, wherein: The semiconductor device further includes: Multiple capacitor structures are arranged along the second direction and the third direction; wherein the dielectric layers in the multiple capacitor structures arranged along the second direction are connected to each other, and the second electrode layers in the multiple capacitor structures arranged along the second direction are connected to each other.

8. The semiconductor device according to claim 6, wherein: The semiconductor body includes a fifth end and a sixth end disposed opposite to each other along the first direction; the semiconductor device further includes: A bit line structure is located on one side of the transistor structure along the first direction, the capacitor structure is coupled to the fifth end, and the bit line structure is coupled to the sixth end; wherein, multiple transistor structures arranged along the second direction are coupled to the same bit line structure.

9. A method for manufacturing a semiconductor device, characterized in that: The manufacturing method comprises: forming a transistor structure comprising a semiconductor body extending along a first direction; A capacitor structure is formed on one side of the transistor structure along the first direction; the capacitor structure includes a first electrode layer, a second electrode layer and a dielectric layer located between the first electrode layer and the second electrode layer, and the first electrode layer is coupled to the semiconductor body; wherein the first electrode layer includes a first sub-electrode and a second sub-electrode surrounding the first sub-electrode, the first sub-electrode includes a first annular structure, the second sub-electrode includes a second annular structure, and the axial directions of the first annular structure and the second annular structure are both the first direction, the dielectric layer includes a first sub-dielectric layer covering the inner side wall of the first sub-electrode, a second sub-dielectric layer covering the outer side wall of the first sub-electrode, a third sub-dielectric layer covering the inner side wall of the second sub-electrode and a fourth sub-dielectric layer covering the outer side wall of the second sub-electrode, the second electrode layer includes a first sub-dielectric layer covering the first sub-electrode A first portion of the inner sidewall of a sub-dielectric layer, a second portion covering the outer sidewall of the second sub-dielectric layer and the inner sidewall of the third sub-dielectric layer, and a third portion covering the outer sidewall of the fourth sub-dielectric layer; the first sub-electrode includes a first end relatively close to the semiconductor body and a second end relatively far away from the semiconductor body, and the second sub-electrode includes a third end relatively close to the semiconductor body and a fourth end relatively far away from the semiconductor body; the first electrode layer also includes: a third sub-electrode, the third sub-electrode is respectively connected to the first end and the third end, and the third sub-electrode is coupled to the semiconductor body; the dielectric layer also includes: a seventh sub-dielectric layer covering the third sub-electrode, and the seventh sub-dielectric layer is respectively connected to the second sub-dielectric layer and the third sub-dielectric layer; the second portion also covers the seventh sub-dielectric layer.

10. The method for manufacturing a semiconductor device according to claim 9, wherein: The forming of a capacitor structure on one side of the transistor structure along the first direction comprises: Providing an initial stacking structure, the initial stacking structure comprising semiconductor layers and sacrificial layers alternately stacked along a second direction; the first direction and the second direction intersect; Etching the initial stacked structure to form a capacitor hole; removing the sacrificial layer through the capacitor hole to form a gap; A first filling layer and a second filling layer are sequentially formed in the gap to form a stacked structure; wherein the first filling layer surrounds the semiconductor layer, and the capacitor hole exposes the first filling layer and the second filling layer alternately stacked along the second direction.

11. The method for manufacturing a semiconductor device according to claim 10, wherein: The capacitor structure is formed on one side of the transistor structure along the first direction, further comprising: Removing the first filling layer to form a first groove; wherein the first groove comprises an annular groove, an inner sidewall of the first groove exposes the semiconductor layer, an outer sidewall of the first groove exposes the second filling layer, and a bottom of the first groove exposes the semiconductor body; forming an initial first electrode layer covering the bottom, outer sidewall and inner sidewall of the first groove, covering the end of the semiconductor layer and covering the end of the second filling layer; forming a third filling layer in the first groove; The initial first electrode layer covering the end of the semiconductor layer and the end of the second filling layer is removed to form a first electrode layer; wherein the first electrode layer includes a first sub-electrode covering the inner side wall of the first groove, a second sub-electrode covering the outer side wall of the first groove, and a third sub-electrode covering the bottom of the first groove.

12. The method for manufacturing a semiconductor device according to claim 11, wherein: The capacitor structure is formed on one side of the transistor structure along the first direction, further comprising: The semiconductor layer, the second filling layer, and the third filling layer are removed to form a second groove, a third groove, and a fourth groove, respectively; wherein the second groove exposes the inner sidewall of the first sub-electrode, the third groove exposes the outer sidewall of the second sub-electrode; and the fourth groove includes an annular groove, and the fourth groove exposes the outer sidewall of the first sub-electrode and the inner sidewall of the second sub-electrode; A dielectric layer is formed in the second groove, the third groove, and the fourth groove.

13. The method for manufacturing a semiconductor device according to claim 12, wherein: The capacitor structure is formed on one side of the transistor structure along the first direction, further comprising: A second electrode layer is formed in the second groove, the third groove, the fourth groove and the capacitor hole.

14. The method for manufacturing a semiconductor device according to claim 9, wherein: The forming of the transistor structure includes: A plurality of transistor structures are formed, and the plurality of transistor structures are arranged along a second direction and a third direction, and the transistor structure further includes a gate structure coupled to a side wall of the semiconductor body; wherein the gate structures in the plurality of transistor structures arranged along the third direction are coupled to each other, and any two of the first direction, the second direction and the third direction intersect.

15. The method for manufacturing a semiconductor device according to claim 14, wherein: The semiconductor body includes a fifth end and a sixth end disposed opposite to each other along the first direction; the manufacturing method further includes: A bit line structure is formed on one side of the transistor structure along the first direction, the capacitor structure is coupled to the fifth end, and the bit line structure is coupled to the sixth end; wherein, the multiple transistor structures arranged along the second direction are coupled to the same bit line structure.

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