Integrated circuit device supporting chip scale package

Abstract

An integrated circuit device includes a lower circuit pattern on a substrate, a bit line on the lower circuit pattern, a gate electrode structure on the bit line, and a memory channel structure extending through the gate electrode structure. The memory channel structure includes a first cap pattern on the bit line, a channel on the first cap pattern, a second cap pattern on the channel, and a charge storage structure at outer sidewalls of the first cap pattern, the channel, and the second cap pattern. A common source plate (CSP) is provided on the memory channel structure.

Description

Technical Field

[0001] The inventive concept relates to integrated circuit devices, and more particularly, to an integrated circuit memory device that is vertically integrated and compatible with chip-level packaging. Background Art

[0002] In electronic systems that require data storage, high-capacity semiconductor memory devices capable of storing high-capacity data are desired. Accordingly, methods for increasing the data storage capacity of semiconductor memory devices have been studied. For example, semiconductor memory devices including memory cells that can be three-dimensionally stacked have been proposed.

[0003] Methods for highly integrating memory cells in semiconductor memory devices need to be studied. Summary of the Invention

[0004] Example embodiments provide an integrated circuit semiconductor device having improved electrical characteristics.

[0005] According to an example embodiment, an integrated circuit semiconductor device is provided. The semiconductor device may include a lower circuit pattern, a bit line structure, a gate electrode structure, a memory channel structure, and a common source plate (CSP). The lower circuit pattern may be disposed on a substrate. The bit line may be disposed on the lower circuit pattern. The gate electrode structure may be disposed on the bit line and include gate electrodes spaced apart from each other in a first direction, wherein a length of the gate electrodes in a second direction may gradually decrease from bottom to top along the first direction, wherein the first direction is substantially perpendicular to an upper surface of the substrate, and the second direction is substantially parallel to the upper surface of the substrate. In addition, the memory channel structure may extend through the gate electrode structure and include a first capping pattern on the bit line, a channel on the first capping pattern, a second capping pattern on the channel, and a charge storage structure at outer sidewalls of the first capping pattern, the channel, and the second capping pattern. The CSP may be disposed on the memory channel structure.

[0006] According to an exemplary embodiment, an integrated circuit semiconductor device is provided. The semiconductor device may include a lower circuit pattern, a gate electrode structure, an insulating pattern structure, a storage channel structure, a via, and a common source plate (CSP). The lower circuit pattern may be disposed on a substrate. The gate electrode structure may include gate electrodes spaced apart from each other in a first direction, wherein a length of the gate electrodes in a second direction may gradually decrease from bottom to top along the first direction, the first direction being substantially perpendicular to an upper surface of the substrate, and the second direction being substantially parallel to the upper surface of the substrate. The insulating pattern structure may extend through the gate electrode structure and include a first insulating pattern disposed at a height corresponding to the gate electrodes respectively and a second insulating pattern disposed between the first insulating patterns adjacent to each other in the first direction in the first insulating pattern. The storage channel structure may extend through the gate electrode structure and include a first capping pattern on a bit line, a channel on the first capping pattern, a second capping pattern on the channel, and a charge storage structure at outer sidewalls of the first capping pattern, the channel, and the second capping pattern. The via may extend through the insulating pattern structure. The CSP may be disposed on the storage channel structure.

[0007] According to another embodiment, an integrated circuit semiconductor device is provided. The semiconductor device may include a lower circuit pattern, a first bonding structure, a first bit line, a first gate electrode structure, a first storage channel structure, a first common source plate (CSP), a second bonding structure, a second CSP, a second gate electrode structure, a second storage channel structure, and a second bit line. The lower circuit pattern may extend on a substrate. The first bonding structure may be disposed on the lower circuit pattern. The first bit line may be disposed on the first bonding structure. The first gate electrode structure may include first gate electrodes spaced apart from each other in a first direction. In addition, a length of the first gate electrodes in a second direction may gradually decrease from bottom to top along the first direction, the first direction being substantially perpendicular to an upper surface of the substrate, and the second direction being substantially parallel to the upper surface of the substrate. The first storage channel structure may extend through the first gate electrode structure and include a first capping pattern on the first bit line, a first channel on the first capping pattern, a second capping pattern on the first channel, and a first charge storage structure at outer sidewalls of the first capping pattern, the first channel, and the second capping pattern. The first CSP may be disposed on the first storage channel structure. The second bonding structure may be disposed on the first CSP. The second CSP may be disposed on the second bonding structure. The second gate electrode structure may include second gate electrodes spaced apart from each other in a first direction, wherein a length of the second gate electrodes in the second direction may gradually increase from bottom to top along the first direction. The second storage channel structure may extend through the second gate electrode structure and include a third capping pattern, a second channel on the third capping pattern, a fourth capping pattern on the second channel, and a second charge storage structure at outer sidewalls of the third capping pattern, the second channel, and the fourth capping pattern. The second bit line may be disposed on the second storage channel structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figures 1 to 5 FIGS. show a plan view and a cross-sectional view of an integrated circuit semiconductor device according to an exemplary embodiment.

[0009] Figures 6 to 55 FIGS. show a plan view and a cross-sectional view of a method of manufacturing an integrated circuit semiconductor device according to an exemplary embodiment.

[0010] Figure 56 FIG. shows a cross-sectional view of an integrated circuit semiconductor device according to an exemplary embodiment.

[0011] Figure 57 FIG. shows a cross-sectional view of an integrated circuit semiconductor device according to an exemplary embodiment.

[0012] Figures 58 to 59 FIG. is a cross-sectional view illustrating a method of manufacturing an integrated circuit semiconductor device according to an exemplary embodiment.

[0013] Figure 60 FIG. shows a cross-sectional view of an integrated circuit semiconductor device according to an exemplary embodiment. DETAILED DESCRIPTION

[0014] The above and other aspects and features of a capacitor structure according to an exemplary embodiment, a method of manufacturing the same, a semiconductor device including the capacitor structure, and a method of manufacturing the same will become readily apparent from the following detailed description with reference to the accompanying drawings. It should be understood that although the terms "first", "second", and / or "third" may be used herein to describe various materials, layers, regions, pads, electrodes, patterns, structures, and / or processes, these various materials, layers, regions, pads, electrodes, patterns, structures, and / or processes should not be limited by these terms. These terms are only used to distinguish one material, layer, region, pad, electrode, pattern, structure, or process from another material, layer, region, pad, electrode, pattern, structure, or process. Thus, "first", "second", and / or "third" may be selectively or interchangeably used for each material, layer, region, electrode, pad, pattern, structure, or process.

[0015] Hereinafter, a vertical direction substantially perpendicular to the upper surface of the substrate may be referred to as a first direction D1, and two mutually intersecting horizontal directions substantially parallel to the upper surface of the substrate may be respectively referred to as a second direction D2 and a third direction D3. In an exemplary embodiment, the second direction D2 and the third direction D3 may be substantially perpendicular to each other.

[0016] Figures 1 to 5 FIGS. illustrate a plan view and a cross-sectional view of an integrated circuit semiconductor device according to an exemplary embodiment.

[0017] Specifically, Figure 1 is a plan view, and Figures 2 to 5 is a view of the region W with respect to Figure 1 . Figure 2 is a plan view, Figure 3 is a cross-sectional view taken along the line A-A' of Figure 2 , Figure 4 including cross-sectional views taken along the lines B-B' and C-C' of Figure 2 , and Figure 5 including enlarged cross-sectional views of the regions X and Y of Figure 4 .

[0018] Figure 2 Some of the upper wirings, upper vias, and upper contact plugs are not shown to avoid complicating the drawings.

[0019] Referring to Figures 1 to 5 , the integrated circuit semiconductor device may include a lower circuit pattern, an eleventh insulating intermediate layer 40, a first bonding structure, and a first structure on a third substrate 30.

[0020] The first structure may include a fourth wiring 783, an etch stop layer 760, a landing structure 23, a gate electrode structure, first to third split patterns 620, 625, and 440, a storage channel structure 460, a support structure 688, first to third upper contact plugs 701, 703, and 705, a through via 709, and a common source plate (CSP) 713. The first structure may further include first to fourteenth vias 723, 725, 727, 763, 773, 775, 767, 777, 813, 833, 815, 835, 817, and 837, first to third and fifth to ninth wirings 733, 735, 737, 785, 787, 823, 825, and 827, first to third and fifth to ninth insulating intermediate layers 340, 350, 660, 710, 720, 730, 750, 790, and 840.

[0021] The third substrate 30 may include a semiconductor material such as silicon, germanium, silicon germanium, etc., or a III-V compound semiconductor such as GaP, GaAs, GaSb, etc. In some exemplary embodiments, the third substrate 30 may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0022] The third substrate 30 may include a first region I and a second region II surrounding the first region I. In an exemplary embodiment, the first region I may be a cell array region, and the second region II may be a pad region or an extended region. The first region I and the second region II of the third substrate 30 may together form a cell region.

[0023] In particular, memory cells each including a gate electrode, a channel, and a charge storage structure may be formed on a first region I of a third substrate 30, and an upper contact plug for transmitting an electrical signal to the memory cell and a pad for contacting the gate electrode of the upper contact plug may be formed on a second region II of the third substrate 30. Figure 1 It is shown that the second region II of the third substrate 30 completely surrounds the first region I of the third substrate 30. However, the inventive concept is not limited thereto, and for example, the second region II of the third substrate 30 may be formed only at a side opposite to the first region I of the third substrate 30 in a second direction D2.

[0024] The third substrate 30 may further include a third region surrounding the second region II, and an upper circuit pattern for applying an electrical signal to the memory cell through the upper contact plug may be formed on the third region of the third substrate 30.

[0025] The third substrate 30 may include a field region on which an isolation pattern 33 is formed, and an active region 31 on which the isolation pattern 33 is not formed. The isolation pattern 33 may include an oxide, such as silicon oxide.

[0026] In an exemplary embodiment, the integrated circuit semiconductor device may have a cell-on-periphery (COP) structure. That is, a lower circuit pattern may be disposed on the third substrate 30, and the memory cell, the upper contact plug, and the upper circuit pattern may be disposed above the lower circuit pattern. The lower circuit pattern may include, for example, transistors, lower contact plugs 35, first lower wirings 36, second lower wirings 38, lower vias 37, and the like.

[0027] The transistor may include a lower gate structure 43 disposed on the third substrate 30, and an impurity region 32 that may serve as a source / drain and is disposed in an upper portion of the active region 31 adjacent to the lower gate structure 43.

[0028] The lower gate structure 43 may include a lower gate insulating pattern 41 and a lower gate electrode 42 sequentially stacked on the third substrate 30.

[0029] The lower contact plug 35 may also contact the impurity region 32. A lower contact plug for contacting the lower gate electrode 42 may be additionally formed.

[0030] The first lower wiring 36, the lower via 37, and the second lower wiring 38 may be sequentially stacked on the lower contact plug 35.

[0031] An eleventh insulating interlayer 40 may cover the transistor, the lower contact plug 35, the first lower wiring 36, the second lower wiring 38, and the lower via 37.

[0032] The first bonding structure may be formed on the eleventh insulating intermediate layer 40 and the lower circuit pattern. The first bonding structure may include a first bonding layer 910 and a second bonding layer 50, as well as a first bonding pattern 900 and a second bonding pattern 55.

[0033] The second bonding layer 50 may be formed on the eleventh insulating intermediate layer 40, and the second bonding pattern 55 may extend through the second bonding layer 50 to contact one of the lower wirings or lower vias of the lower circuit pattern. In an exemplary embodiment, a plurality of second bonding patterns 55 may be spaced apart from each other in a second direction D2 and a third direction D2.

[0034] The first bonding layer 910 may be formed on the second bonding layer 50, and the first bonding pattern 900 may extend through the first bonding layer 910 to contact the second bonding pattern 55. In an exemplary embodiment, a plurality of first bonding patterns 900 may be spaced apart from each other in a second direction D2 and a third direction D3 corresponding to the second bonding pattern 55.

[0035] In an exemplary embodiment, the first bonding pattern 900 may have a cross-section in the shape of "╩", and the second bonding pattern 55 may have a cross-section in the shape of "╦".

[0036] In an exemplary embodiment, each of the first bonding layer 910 and the second bonding layer 50 may include, for example, silicon carbonitride (SiCN), and each of the first bonding pattern 900 and the second bonding pattern 55 may include a metal, such as copper (Cu).

[0037] The tenth via 833, the seventh wiring 823, and the ninth via 813 may be sequentially stacked on a corresponding one of the first bonding patterns 900. The twelfth via 835, the eighth wiring 825, and the eleventh via 815 may be sequentially stacked on a corresponding one of the first bonding patterns 900. The fourteenth via 837, the ninth wiring 827, and the thirteenth via 817 may be sequentially stacked on a corresponding one of the first bonding patterns 900.

[0038] The tenth insulating intermediate layer 840 may cover the ninth to fourteenth vias 813, 833, 815, 835, 817, and 837, as well as the seventh to ninth wirings 823, 825, and 827.

[0039] The fourth wiring 783, as well as the fifth via 773 and the fourth via 763, may be sequentially stacked on the ninth via 813. The fourth wiring 783 may be electrically connected to the transistor through the ninth via 813, the seventh wiring 823, the tenth via 833, and the corresponding bonding pattern in the first bonding pattern 900 and the second bonding pattern 55. The fourth wiring 783 may be used as a bit line.

[0040] In an exemplary embodiment, the fourth wiring 783 may extend in a third direction D3 over a first region I of the third substrate 30, and a plurality of the fourth wirings may be spaced apart from each other in a second direction D2.

[0041] In an exemplary embodiment, the width of the upper surface of the fourth via 763 in a horizontal direction may be greater than the width of the lower surface of the first cap pattern 412 in a horizontal direction. When the fourth via 763 is not formed such that the fifth via 773 is in direct contact with the first cap pattern 412, the width of the upper surface of the fifth via 773 in a horizontal direction may be greater than the width of the lower surface of the first cap pattern 412 in a horizontal direction.

[0042] The fifth wiring 785 and the sixth via 775 may be sequentially stacked on the eleventh via 815. The fifth wiring 785 may be electrically connected to the transistor through the eleventh via 815, the eighth wiring 825, the twelfth via 835, and corresponding ones of the first bonding pattern 900 and the second bonding pattern 55.

[0043] The sixth wiring 787, and the eighth via 777 and the seventh via 767 may be sequentially stacked on the thirteenth via 817. The sixth wiring 787 may be electrically connected to the transistor through the thirteenth via 817, the ninth wiring 827, the fourteenth via 837, and corresponding ones of the first bonding pattern 900 and the second bonding pattern 55.

[0044] In an exemplary embodiment, the width of the upper surface of the seventh via 767 in a horizontal direction may be less than the width of the lower surface of the landing pad 22 in a horizontal direction.

[0045] The ninth insulating interlayer 790 may cover the fourth to eighth vias 763, 773, 775, 767, and 777 and the fourth to sixth wirings 783, 785, and 787.

[0046] The etch stop layer 760 may be formed over the ninth insulating interlayer 790 and may cover upper sidewalls of the fourth via 763, the sixth via 775, and the seventh via 767. The upper surface of the etch stop layer 760 may be substantially coplanar with the upper surface of each of the fourth via 763, the sixth via 775, and the seventh via 767. In an exemplary embodiment, the etch stop layer 760 may include a nitride, such as silicon nitride.

[0047] The eighth insulating interlayer 750 may be formed over the etch stop layer 760.

[0048] The gate electrode structure may include a plurality of gate electrodes spaced apart from each other in a first direction D1 over the eighth insulating interlayer 750. Each of the gate electrodes may extend in a second direction D2.

[0049] In an exemplary embodiment, the gate electrode structure may include first to third gate electrodes 751, 753, and 755 sequentially stacked along a first direction D1. Each of the first gate electrode 751 and the third gate electrode 755 may be disposed at one or more layers, and the second gate electrode 753 may be disposed at a plurality of layers, respectively. Figures 1 to 6 Each of the first gate electrode 751 and the third gate electrode 755 disposed at two layers is shown, but the concept of the present invention is not limited thereto.

[0050] In an exemplary embodiment, the first gate electrode 751 may serve as a string select line (SSL), the second gate electrode 753 may serve as a word line, and the third gate electrode 755 may serve as a ground select line (GSL).

[0051] However, the first gate electrode 751 may additionally be formed at one or more layers below the SSL and / or above the GSL to serve as a GIDL gate electrode, which realizes bulk erasure by utilizing the gate-induced drain leakage (GIDL) phenomenon. Some of the second gate electrodes 753 disposed between the SSL and the GSL may serve as dummy word lines.

[0052] Each of the first to third gate electrodes 751 to 753 and 755 may include a gate conductive pattern and a gate blocking pattern covering the surface of the gate conductive pattern. The gate conductive pattern may include a metal having a low resistance, such as tungsten, titanium, tantalum, platinum, etc., and the gate blocking pattern may include a metal nitride, such as titanium nitride, tantalum nitride, etc.

[0053] The first insulating pattern 315 may be formed between adjacent gate electrodes among the first to third gate electrodes 751, 753, and 755 in the first direction D1, on the upper surface of the uppermost one of the third gate electrodes 755, and between the first gate electrode 751 and the eighth insulating intermediate layer 750. The first insulating pattern 315 may include an oxide, such as silicon oxide.

[0054] In an exemplary embodiment, the gate electrode structure may have a stepped shape, in which the length in a second direction D2 decreases stepwise from the lowermost level to the uppermost level in the first direction D1, and may include steps disposed in the second direction D2 on a second region II of the third substrate 30. In some embodiments, the gate electrode structure may further include steps disposed in a third direction D3 on the second region II of the third substrate 30.

[0055] Hereinafter, a portion of the gate electrode corresponding to the step of the gate electrode structure, that is, an end portion of each of the gate electrodes that may not overlap with the upper gate electrode in the gate electrode, may be referred to as a pad. Accordingly, pads of each of the gate electrodes may be disposed on the second region II of the third substrate 30. In an exemplary embodiment, pads of each of the first to third gate electrodes 751, 753, and 755 may have a greater thickness than other portions of the same gate electrode.

[0056] In an exemplary embodiment, a plurality of gate electrode structures may be spaced apart from each other in the third direction D3. A first division pattern 620 extending in the second direction D2 on the first region I and the second region II of the third substrate 30 may be disposed between and separate the first to third gate electrodes 751, 753, and 755 included in adjacent gate structures in the third direction D3. In an exemplary embodiment, the first division pattern 620 may extend through the first insulating intermediate layer to the third insulating intermediate layers 340, 350, and 660, the first to third gate electrodes 751, 753, and 755, and the eighth insulating intermediate layer 750.

[0057] In an exemplary embodiment, each of the gate electrode structures separated by the first division pattern 620 and the storage channel structure 460 extending through the corresponding one of the gate electrode structures may together form a storage block. A plurality of storage blocks may be disposed in the third direction D3.

[0058] However, one of the storage blocks on which the storage channel structure 460 is not formed may be referred to as a dummy storage block. Hereinafter, storage blocks other than the dummy storage block may be referred to as active memory blocks. In addition, a part of the first region I of the third substrate 30 on which the active storage blocks are formed may be referred to as an active storage block region, and a part of the first region I of the third substrate 30 on which the dummy storage blocks are formed may be referred to as a dummy storage block region.

[0059] The insulating pattern structure 600 may extend through a part of the gate electrode structure on the dummy storage block region of the third substrate 30. In a plan view, the insulating pattern structure 600 may have a shape such as a rectangle, an ellipse, a circle, etc. In an exemplary embodiment, the insulating pattern structure 600 may include a fourth insulating pattern 317 and a fifth insulating pattern 327 stacked alternately and repeatedly along the first direction D1.

[0060] A third division pattern 440 may extend through the lower portions of each of the gate structures on the first region I and the second region II of the third substrate 30, that is, the lower two layers in which the first gate electrode 751 is formed. Accordingly, each of the first gate electrodes 751 may be further separated in the third direction D3.

[0061] The second division pattern 625 may extend in a second direction D2 through the first to third insulating intermediate layers 340, 350, and 660, the first to third gate electrodes 751, 753, and 755, and the eighth insulating intermediate layer 750.

[0062] Each of the first to third division patterns 620, 625, and 440 may include, for example, an oxide such as silicon oxide.

[0063] The storage channel structure 460 may be formed on a first region I of the third substrate 30. The storage channel structure 460 may extend through the second insulating intermediate layer 350 and the third insulating intermediate layer 660, the first to third gate electrodes 751, 753, and 755, the first insulating pattern 315, and the eighth insulating intermediate layer 750 to contact the upper surface of the fourth via 763.

[0064] In an exemplary embodiment, the storage channel structure 460 may include a first capping pattern 412 that may be disposed on the fourth via 763, a channel 422 having a cup shape that may be disposed on the first capping pattern 412, a filling pattern 442 that may fill a space formed by an upper portion of the channel 422 and extend in a first direction D1, a second capping pattern 452 that may contact the upper surfaces of the filling pattern 442 and the channel 422, and a charge storage structure 402 that may be disposed at outer sidewalls of the first capping pattern 412, the channel 422, and the second capping pattern 452.

[0065] The upper surface of the first capping pattern 412 may be higher than the lower surface of the lowermost one of the first insulating patterns 315, but the concept of the present invention is not limited thereto. That is, the upper surface of the first capping pattern 412 may be lower than the lower surface of the lowermost one of the first insulating patterns 315.

[0066] The charge storage structure 402 may include a tunnel insulating pattern 392, a charge storage pattern 382, and a first blocking pattern 372 that are sequentially stacked in a horizontal direction from an outer sidewall of the channel 422.

[0067] In an exemplary embodiment, the lower surface of the storage channel structure 460 may be substantially coplanar with the upper surface of the etch stop layer 760.

[0068] In an exemplary embodiment, a plurality of storage channel structures 460 may be spaced apart from each other in a second direction D2 and a third direction D3 in each active storage block on the first region I of the third substrate 30 to form an array of storage channel structures.

[0069] The CSP 713 may extend through the fifth insulating intermediate layer 710 and commonly contact the upper surfaces of the storage channel structures 460 of each active storage block. Accordingly, the storage channel structures 460 of each active storage block may be electrically connected to each other through the CSP 713. Accordingly, a plurality of CSPs 713 may be spaced apart from each other in the third direction D3 corresponding to the active storage blocks.

[0070] The channel 422 may include, for example, undoped polysilicon, the filling pattern 442 may include an oxide, such as silicon oxide, and the first capping pattern 412 and the second capping pattern 452 may include, for example, doped polysilicon.

[0071] The tunnel insulating pattern 392 and the first blocking pattern 372 may include an oxide, such as silicon oxide, and the charge storage pattern 382 may include a nitride, such as silicon nitride.

[0072] The oxidation pattern 362 may be disposed between the lower sidewalls of the storage channel structure 460 and the eighth insulating intermediate layer 750. The oxidation pattern 362 may include, for example, silicon oxide.

[0073] Referring to Figure 34 Together with Figures 1 to 5 , the support structure 688 may be formed on the second region II of the third substrate 30 and may extend through the second insulating intermediate layer 350 and the third insulating intermediate layer 660, the first gate electrode to the third gate electrodes 751, 753, and 755, the first insulating pattern 315, and the eighth insulating intermediate layer 750. In an exemplary embodiment, a plurality of support structures 688 may be spaced apart from each other on the second region II of the third substrate 30 in the second direction D2 and the third direction D3.

[0074] In an exemplary embodiment, the support structure 688 may include an extension portion having a column shape extending in the first direction D1, and protruding portions protruding in a horizontal direction from the sidewalls of the extension portion and spaced apart from each other in the first direction D1. The protruding portions may be respectively formed at portions of the sidewalls of the extension portion facing the first gate electrode to the third gate electrodes 751, 753, and 755. In an exemplary embodiment, the width of the uppermost protruding portion in the horizontal direction may be greater than the width of each of the protruding portions below the uppermost protruding portion in the horizontal direction. The support structure 688 may include an oxide, such as silicon oxide.

[0075] The second blocking pattern 615 may cover the upper and lower surfaces of each of the first to third gate electrodes 751, 753, and 755, and the sidewalls of each of the first to third gate electrodes 751, 753, and 755 facing the memory channel structure 460, the support structure 688, and the first to third upper contact plugs 701, 703, and 705. The second blocking pattern 615 may include a metal oxide, such as aluminum oxide or hafnium oxide.

[0076] Each of the first to third upper contact plugs 701, 703, and 705 may extend through the first to third insulating intermediate layers 340, 350, and 660, the gate electrode structure, and the first insulating pattern 315 to contact the upper surface of a corresponding one of the sixth vias 775.

[0077] Each of the first to third upper contact plugs 701, 703, and 705 may be disposed on the second region II of the third substrate 30.

[0078] In an exemplary embodiment, the first upper contact plug 701 may extend through the pad of the first gate electrode 751, the second upper contact plug 703 may extend through the pad of the second gate electrode 753 and the first gate electrode 751 thereunder, and the third upper contact plug 705 may extend through the pad of the third gate electrode 755 and the first gate electrode 751 and the second gate electrode 753 thereunder.

[0079] In an exemplary embodiment, the fourth insulating pattern 686 may be disposed at each sidewall of the first to third upper contact plugs 701, 703, and 705 facing each of the first to third gate electrodes 751, 753, and 755. However, the fourth insulating pattern 686 may not be formed at the portion of each sidewall of the first to third upper contact plugs 701, 703, and 705 facing the gate electrode including the pad.

[0080] In an exemplary embodiment, each of the first to third upper contact plugs 701, 703, and 705 may include a protruding portion protruding horizontally from the portion of each sidewall of the first to third upper contact plugs 701, 703, and 705 facing the uppermost one of the gate electrodes. The protruding portion of each of the first to third upper contact plugs 701, 703, and 705 may directly contact the gate electrode including the pad.

[0081] The fourth insulating pattern 686 may include an oxide, such as silicon oxide.

[0082] The through-via 709 may be formed on the dummy memory block region of the first region I of the third substrate 30. The through-via 709 may extend through the first to third insulating intermediate layers 340, 350, and 660 to contact the upper surface of the landing structure 23 on the seventh via 767.

[0083] The landing structure 23 may include a landing pad 22 and a buffer pattern 21 covering the sidewall of the landing pad 22. The buffer pattern 21 may include an oxide, such as silicon oxide, and the landing pad 22 may include a metal, such as tungsten.

[0084] In an exemplary embodiment, the landing structure 23 may have a shape such as a rectangle, an ellipse, a circle, etc. in a plan view.

[0085] In an exemplary embodiment, a plurality of landing structures 23 may be spaced apart from each other in a second direction D2 and a third direction D3.

[0086] In an exemplary embodiment, the upper surface of the etch stop layer 760, the lower surface of the storage channel structure 460, the lower surface of each of the first to third upper contact plugs 701, 703, and 705, and the lower surface of the landing structure 23 may be substantially coplanar with each other.

[0087] The first to third partition patterns 620, 625 and 440, the support structure 688, the first to third upper contact plugs 701, 703, and 705, and the through-passage 709 may be formed in various layouts.

[0088] The first insulating intermediate layer 340 may cover the sidewalls of the first to third gate electrodes 751, 753, and 755 and the first insulating pattern 315. The second insulating intermediate layer 350 may be disposed on the first insulating intermediate layer 340 and the first insulating pattern 315. The third insulating intermediate layer 660 may be disposed on the second insulating intermediate layer 350 and cover the upper outer sidewalls of the storage channel structure 460, the upper outer sidewalls of the support structure 788, the upper outer sidewalls of each of the first to third upper contact plugs 701, 703, and 705, and the upper outer sidewalls of the through-passage 709. The fifth insulating intermediate layer 710 may be disposed on the third insulating intermediate layer 660, the storage channel structure 460, the support structure 788, the first to third upper contact plugs 701, 703, and 705, and the through-passage 709. The sixth insulating intermediate layer 720 and the seventh insulating intermediate layer 730 may be sequentially stacked on the fifth insulating intermediate layer 710.

[0089] The first via 723 may extend through the sixth insulating intermediate layer 720 to contact the upper surface of the CSP 713. The second via 725 may extend through the fifth insulating intermediate layer 710 and the sixth insulating intermediate layer 720 to contact the upper surface of a corresponding one of the first to third upper contact plugs 701, 703, and 705. The third via 727 may extend through the fifth insulating intermediate layer 710 and the sixth insulating intermediate layer 720 to contact the upper surface of the through-passage 709.

[0090] The first through third wirings 733, 735, and 737 may extend through the seventh insulating intermediate layer 730 to contact the upper surfaces of the first through third vias 723, 725, and 727, respectively.

[0091] In an exemplary embodiment, each of the first through fourteenth vias 723, 725, 727, 763, 773, 775, 767, 777, 813, 833, 815, 835, 817, and 837 and each of the first through ninth wirings 733, 735, 737, 783, 785, 787, 823, 825, and 827 may include a conductive pattern and a barrier pattern covering the surface of the conductive pattern. The conductive pattern may include a metal having a low resistance, such as tungsten, titanium, tantalum, platinum, etc., and the barrier pattern may include a metal nitride, such as titanium nitride, tantalum nitride, etc.

[0092] The first through fourteenth vias 723, 725, 727, 763, 773, 775, 767, 777, 813, 833, 815, 835, 817, and 837 and the first through ninth wirings 733, 735, 737, 783, 785, 787, 823, 825, and 827 may be formed in various layouts.

[0093] Each of the first through third insulating intermediate layers 340, 350, and 660 and each of the fifth through eleventh insulating intermediate layers 710, 720, 730, 750, 790, 840, and 40 may include an oxide, such as silicon oxide.

[0094] In an integrated circuit semiconductor device, the width of the upper surface of the fourth via 763 (if the fourth via 763 is not formed, the upper surface of the fifth via 773) in the horizontal direction may be greater than the width of the lower surface of the first cap pattern 412 in the horizontal direction. Accordingly, misalignment between the fourth wiring 783 and the fourth via 763 may be reduced.

[0095] Figures 6 to 55 are a plan view and a cross-sectional view showing a method of manufacturing an integrated circuit semiconductor device. In particular, Figure 6 、 Figure 8 、 Figure 11 、 Figure 14 、 Figure 21 、 Figures 30 - 31 and Figure 35 are plan views, while Figure 7 、 Figures 9 - 10 、 Figures 12 - 13 、 Figures 15 - 20 、 Figures 22 - 29 、 Figures 32 - 34 and Figures 36 - 55 are cross-sectional views.

[0096] Figure 12 、Figure 13 , Figure 15 , Figures 24 - 25 , Figures 27 - 28 , Figure 32 , Figures 36 - 37 , Figure 39 , Figure 41 , Figure 49 , Figure 52 and Figures 54 - 55 are cross-sectional views taken along line A - A' of the corresponding plan view, and among them, Figure 25 , Figure 28 and Figure 37 are enlarged cross-sectional views of region W of the corresponding cross-sectional views, respectively. Figures 16 - 17 , Figure 19 , Figure 20 , Figures 22 - 23 , Figure 33 , Figure 38 , Figure 40 , Figures 42 - 48 , Figures 50 - 51 and Figure 53 include cross-sectional views taken along lines B - B' and C - C' of the corresponding plan view, respectively, and among them, Figure 17 , Figure 23 , Figures 43 - 46 , Figure 48 and Figure 51 include enlarged cross-sectional views of region X and region Y of the corresponding cross-sectional views, respectively. Figure 7 and Figure 10 are cross-sectional views taken along line C - C' of the corresponding plan view, respectively. Figure 18 , Figure 26 , Figure 29 and Figure 34 are cross-sectional views taken along line D - D' of the corresponding plan view, respectively.

[0097] Referring to Figure 6 and Figure 7 , a landing structure 23 including a landing pad 22 and a buffer pattern 21 covering the lower surface and side walls of the landing pad 22 can be formed on the first region I of the first substrate 10.

[0098] In an exemplary embodiment, the landing structure 23 can have a shape such as a rectangle, an ellipse, a circle, etc. in a plan view.

[0099] In an exemplary embodiment, the landing structure 23 can be formed at a position corresponding to a through via 709 to be formed later. Accordingly, a plurality of landing structures 23 can be formed to be spaced apart from each other in the second direction D2 and the third direction D3.

[0100] Referring to Figures 8 to 10, the first insulating layer 310 and the first sacrificial layer 320 may be alternately and repeatedly stacked on the first substrate 10 and the landing structure 23 in the first direction D1. Thus, a molded layer including the first insulating layer 310 and the first sacrificial layer 320 may be formed. The first insulating layer 310 may include an oxide, such as silicon oxide, and the first sacrificial layer 320 may include a material having an etching selectivity with respect to the first insulating layer 310, such as a nitride, such as silicon nitride.

[0101] Referring to Figure 11 and Figure 12 , a photoresist pattern may be formed to partially cover the uppermost one in the first insulating layer 310, and the uppermost one in the first insulating layer 310 and the uppermost one in the first sacrificial layer 320 may be etched using the photoresist pattern as an etching mask. Thus, a part of one of the first insulating layers 310 directly below the uppermost one in the first sacrificial layer 320 may be exposed.

[0102] After performing a trimming process for reducing the area of the photoresist pattern, the uppermost one in the first insulating layer 310, the uppermost one in the first sacrificial layer 320, the exposed one in the first insulating layer 310, and the one in the first sacrificial layer 320 directly below the exposed one in the first insulating layer 310 may be etched by an etching process using the reduced photoresist pattern as an etching mask. The trimming process and the etching process may be repeatedly performed to form a mold, and the mold may have a stepped shape and include a plurality of stepped layers, and each stepped layer may include one first sacrificial layer 320 and one first insulating layer 310 stacked in sequence.

[0103] Hereinafter, a "stepped layer" may refer to all parts of the first sacrificial layer 320 and the first insulating layer 310 at the same level, which may include unexposed parts and exposed parts of the first sacrificial layer 320 and the first insulating layer 310, and a "step" may refer only to the exposed part of the "stepped layer". In an exemplary embodiment, the steps may be arranged in the second direction D2. Alternatively, the steps may be arranged in the third direction D3.

[0104] Each of the steps of the mold may be formed on the second region II of the first substrate 10.

[0105] Referring to Figure 13 , an insulating pad layer may be formed, and the insulating pad layer may be partially removed to form a first insulating pad 322 and a second insulating pad 324.

[0106] In an embodiment, the insulating pad layer may include the same material as the first sacrificial layer 320, however, may have an etching rate different from that of the first sacrificial layer 320.

[0107] After forming the insulating pad layer, portions of the insulating pad layer adjacent to the sidewalls of the steps of the mold can be removed respectively to form a first insulating pad 322 on the upper surface of the uppermost one of the first insulating layers 310, and a second insulating pad 324 can be formed on the upper surface of each of the first sacrificial layers 320 on which the steps of the mold can be formed. In an exemplary embodiment, each of the first insulating pad 322 and the second insulating pad 324 can extend along a third direction D3.

[0108] Referring Figures 14 to 18 , a first insulating intermediate layer 340 can be formed to cover the mold and the first insulating pad 322 and the second insulating pad 324, and can be planarized until the upper surface of one of the first insulating layers 310 on the step layer on which the second insulating pad 324 is formed is exposed.

[0109] During planarization, the first insulating pad 322 and one of the first insulating layers 310 and one of the first sacrificial layers 320 in the uppermost step layer included in the mold can be removed, and the sidewalls of the mold can be covered by the first insulating intermediate layer 340.

[0110] A second insulating intermediate layer 350 can be formed on the upper surfaces of the mold and the first insulating intermediate layer 340.

[0111] An etching process can be performed to form a first hole extending in a first direction D1 through the second insulating intermediate layer 350, the mold, and the upper portion of the first substrate 10 on a first region I of the first substrate 10, and a second hole extending in the first direction D1 through the first insulating intermediate layer 340 and the second insulating intermediate layer 350, a portion of the mold, and the upper portion of the first substrate 10 on a second region II of the first substrate 10. In an exemplary embodiment, a plurality of first holes can be spaced apart from each other in a second direction D2 and a third direction D3 on the first region I of the first substrate 10, and a plurality of second holes can be spaced apart from each other in the second direction D2 and the third direction D3 on the second region II of the first substrate 10.

[0112] In addition, a third hole to a fifth hole extending in the first direction D1 through the first insulating intermediate layer 340 and the second insulating intermediate layer 350, the mold, and the upper portion of the first substrate 10 can be formed on the second region II of the first substrate 10. In an exemplary embodiment, each of the third hole to the fifth hole can be formed in a region defined by the second holes adjacent to each other in a plan view.

[0113] The sixth hole that extends through the second insulating intermediate layer 350 and the mold in the first direction D1 can be formed to expose the upper surface of the landing pad 22 on the first region I of the third substrate 30. In an exemplary embodiment, a plurality of sixth holes can be spaced apart from each other in the first direction D1 and the second direction D2 corresponding to the landing structures 23.

[0114] In an exemplary embodiment, the first through sixth holes can be formed simultaneously by a single etching process, or can be formed sequentially by independent processes.

[0115] The second through seventh sacrificial patterns 362, 366, 632, 634, 636, and 640 can be formed in the first through sixth holes, respectively.

[0116] The second through seventh sacrificial patterns 362, 366, 632, 634, 636, and 640 can be formed by forming a second sacrificial layer on the second insulating intermediate layer 350 to fill the first through sixth holes, and planarizing the second sacrificial layer until the upper surface of the second insulating intermediate layer 350 is exposed.

[0117] In an embodiment, the second sacrificial layer can include, for example, an insulating material containing carbon, a metal, undoped polysilicon, etc.

[0118] Referring to Figure 19 , a third insulating intermediate layer 660 can be formed on the second insulating intermediate layer 350 and the second through seventh sacrificial patterns 362, 366, 632, 634, 636, and 640. The third insulating intermediate layer 660 can be patterned by an etching process to expose the second sacrificial pattern 362, and the exposed second sacrificial pattern 362 can be removed to reform the first hole that exposes the upper surface of the first substrate 10.

[0119] An oxidation process can be performed on the exposed upper surface of the first substrate 10 to form an oxide layer 360.

[0120] Referring to Figure 20 , a charge storage structure layer 400 can be formed on the surface of the oxide layer 360, the sidewalls of the first hole, and the upper surface of the third insulating intermediate layer 660. The charge storage structure layer 400 can include a first blocking layer 370, a charge storage layer 380, and a tunnel insulating layer 390 stacked in sequence.

[0121] A first capping layer 410 can be conformally formed on the charge storage structure layer 400, for example. The diameter of the lower portion of the first hole can be smaller than the diameter of the upper portion of the first hole. Thus, the lower portion of the first hole can be filled with the first capping layer 410, while the upper portion of the first hole can be unfilled with the first capping layer 410 and have an empty space at the center.

[0122] Referring to Figures 21 to 23, an etching process can be performed on the upper portion of the first capping layer 410. A large surface area can be exposed during the etching process as compared to the lower portion of the first capping layer 410 that partially fills the lower portion of the first hole. Accordingly, the upper portion of the first capping layer 410 can be removed by the etching process, and the lower portion of the first capping layer 410 can be retained. In an exemplary embodiment, the upper surface of the first capping layer 410 can be formed to be lower than the lower surface of the lowermost one of the first sacrificial layers 320.

[0123] In an exemplary embodiment, the etching process can be performed by a wet etching process.

[0124] An annealing process can be performed to activate the first capping layer 410.

[0125] A channel layer can be formed on the charge storage structure layer 400 and the first capping layer 410, and a fill layer can be formed on the channel layer to fill the remaining portion of the first hole. The fill layer, the channel layer, and the charge storage structure layer 400 can be planarized until the upper surface of the third insulating intermediate layer 660 is exposed. Accordingly, an oxide layer 360, a charge storage structure 402, a first capping layer 410, a channel 422, and a fill pattern 442 can be formed in the first hole. The charge storage structure 402 can include a first blocking pattern 372, a charge storage pattern 382, and a tunnel insulating pattern 392 stacked in sequence.

[0126] The upper portions of the fill pattern 442 and the channel 422 can be removed to form a first recess, and a second capping pattern 452 can be formed to fill the first recess.

[0127] The charge storage structure 402, the first capping layer 410, the channel 422, the fill pattern 442, and the second capping pattern 452 in the first hole can together form a preliminary storage channel structure 460a.

[0128] In an exemplary embodiment, the preliminary storage channel structure 460a can have a column shape extending in a first direction D1. In an exemplary embodiment, a plurality of preliminary storage channel structures 460a can be spaced apart from each other in a second direction D2 and a third direction D3 on a first region I of the first substrate 10.

[0129] Referring to Figures 24 to 26 , the third insulating intermediate layer 660 can be patterned by an etching process to expose the third to sixth sacrificial patterns 366, 632, 634, and 636, and the third to sixth sacrificial patterns 366, 632, 634, and 636 can be removed to re-form second to fifth holes exposing the upper surface of the first substrate 10.

[0130] An additional etching process can be performed on portions of the first sacrificial layer 320 adjacent to each of the second to fifth holes to form a second recess 672 and a third recess 674.

[0131] In an exemplary embodiment, during the formation of the second recess 672, not only the first sacrificial layer 320 can be removed, but also the second insulating pad 324 that can be formed on the first sacrificial layer 320 and includes substantially the same material as the first sacrificial layer 320 can be removed. Therefore, the width of the second recess 672 in the horizontal direction can be formed to be greater than the width of the third recess 674 in the horizontal direction.

[0132] Referring to Figures 27 to 29 , a second insulating layer can be formed on the inner walls of the second to fifth holes, the second recess 672 and the third recess 674, and the upper surface of the third insulating intermediate layer 660 to fill the second recess 672 and the third recess 674. A sacrificial cushion layer can be formed on the second insulating layer. A second sacrificial layer can be formed on the sacrificial cushion layer to fill the remaining portions of the second to fifth holes, and the second sacrificial layer, the sacrificial cushion layer, and the second insulating layer can be planarized until the upper surface of the third insulating intermediate layer 660 is exposed.

[0133] In an exemplary embodiment, the second insulating layer can include an oxide, such as silicon oxide, and the sacrificial cushion layer can include an insulating nitride, such as silicon nitride, and the second sacrificial layer can include, for example, polysilicon.

[0134] Through a planarization process, sacrificial pillars including a second insulating pattern 681, a sacrificial cushion 683, and an eighth sacrificial pattern 685 can be formed in each of the second to fifth holes. Specifically, a first sacrificial pillar and second to fourth sacrificial pillars 691, 693, and 695 can be formed in the second to fifth holes, respectively.

[0135] After removing the sacrificial cushion 683 and the eighth sacrificial pattern 685 included in the first sacrificial pillar, a third insulating pattern can be formed to fill the remaining portion of the second hole. The third insulating pattern can include substantially the same material as the second insulating pattern 681, for example, an oxide such as silicon oxide, and can be merged with the second insulating pattern 681.

[0136] Hereinafter, the second insulating pattern 681 and the third insulating pattern in the second hole can be collectively referred to as a support structure 688.

[0137] Referring to Figure 30 , a fourth insulating intermediate layer 700 can be formed on the third insulating intermediate layer 660, the preliminary storage channel structure 460a, the support structure 688, and the second to fourth sacrificial pillars 691, 693, and 695, and an etching process can be performed to form a first opening 493 that extends in the second direction D2 through the first to fourth insulating intermediate layers 340, 350, 660, and 700, the mold, and the upper portion of the first substrate 10 in the first region I and the second region II of the first substrate 10.

[0138] In an exemplary embodiment, the first opening 493 may extend in a second direction D2 over a first region I and a second region II of the first substrate 10 to two opposite ends in the second direction D2 of a mold having a stepped shape, and a plurality of first openings 493 may be spaced apart from each other in a third direction D3. Accordingly, the mold may be divided by the first openings 493 into a plurality of parts spaced apart from each other in the third direction D3, and each of the parts in the mold may form an active storage block or a dummy storage block. By forming the first opening 493, a first insulating layer 310 and a first sacrificial layer 320 included in the mold may be divided into a plurality of first insulating patterns 315 and a plurality of first sacrificial patterns 325, respectively, and each of the first insulating patterns 315 and each of the first sacrificial patterns 325 may extend in the second direction D2.

[0139] A part of the first region I of the third substrate 30 on which an active storage block is formed may be referred to as an active storage block region, and a part of the first region I of the third substrate 30 on which a dummy storage block is formed may be referred to as a dummy storage block region.

[0140] The second opening 497 may be formed to extend in the second direction D2 through first insulating intermediate layers 340, 350, 660, and 700 over the first region I and the second region II of the first substrate 10, the mold, and an upper portion of the first substrate 10.

[0141] In the exemplary embodiment, the first opening 493 and the second opening 497 may not be formed over the dummy storage block region.

[0142] Even though the mold is divided into a plurality of parts, each part may extend in the second direction D2 and be spaced apart from each other in the third direction D3 by a wet etching process for forming the first opening 493 and the second opening 497, and the mold may not collapse due to a preliminary storage channel structure 460a, a support structure 688, second to fourth sacrificial posts 691, 693, and 695, and a seventh sacrificial pattern 640 extending through the mold.

[0143] Referring to Figure 31 and Figure 34 , the first sacrificial pattern 325 and a second insulating pad 324 exposed by the first opening 493 and the second opening 497 may be removed to form a first gap in a first direction D1 between adjacent first insulating patterns 315, and a part of an outer sidewall of a charge storage structure 402 included in the preliminary storage channel structure 460a, a part of a sidewall of the support structure 688, and a part of a sidewall of each of the second to fourth sacrificial posts 691, 693, and 695 may be exposed by the first gap.

[0144] In an exemplary embodiment, a wet etching process may be performed using, for example, phosphoric acid (H3PO4) or sulfuric acid (H2SO4) to remove the first sacrificial pattern 325.

[0145] The wet etching process may be performed through the first opening 493 and the second opening 497, and a portion of the first sacrificial pattern 325 between the first opening 493 and the second opening 497 may be removed by an etching solution provided from the first opening 493 and the second opening 497 in two directions, respectively.

[0146] However, the first opening 493 and the second opening 497 may not be formed within the dummy memory block region. Thus, within the dummy memory block region, the etching solution may be provided only from one side of each of the first opening 493 and the second opening 497 adjacent to the dummy memory block region. Accordingly, the first sacrificial pattern 325 may not be completely removed and may be partially retained on the dummy memory block region, and the remaining portion of the first sacrificial pattern 325 may be referred to as the fifth insulating pattern 327. A portion of the first insulating pattern 315 that may overlap the fifth insulating pattern 327 in the first direction D1 may be referred to as the fourth insulating pattern 317. The fourth insulating pattern 317 and the fifth insulating pattern 327 stacked alternately and repeatedly in the first direction D1 may together form the insulating pattern structure 600.

[0147] The insulating pattern structure 600 may extend through a portion of the die over the dummy memory region of the first substrate 10 and may have a shape such as a rectangle, an ellipse, a circle, etc. in a plan view.

[0148] The second blocking layer may be formed on the outer sidewalls of the charge storage structure 402, the sidewalls of the support structure 688, the sidewalls of each of the second to fourth sacrificial posts 691, 693, and 695 exposed by the first gap, the inner walls of each of the first gaps 590, the surface of the first insulating pattern 315, the sidewalls of the second to fourth insulating intermediate layers 350, 660, and 700, and the upper surface of the fourth insulating intermediate layer 700, and the gate electrode layer may be formed on the second blocking layer.

[0149] The gate electrode layer may be partially removed to form gate electrodes in each of the first gaps. In an exemplary embodiment, the gate electrode layer may be partially removed by a wet etching process. As a result, the first sacrificial pattern 325 of the die may be replaced with the gate electrodes and the second blocking layer covering the lower and upper surfaces of the gate electrodes.

[0150] In an exemplary embodiment, the gate electrodes may extend in the second direction D2, and a plurality of gate electrodes may be respectively disposed at a plurality of levels spaced apart from each other in the first direction D1 to form a gate electrode structure. The gate electrode structure may have a stepped shape including the gate electrodes as stepped layers. An end portion of each of the gate electrodes in the second direction D2, that is, a portion corresponding to a step of the stepped layer having a relatively large thickness in each of the gate electrodes may be referred to as a pad.

[0151] In an exemplary embodiment, a plurality of gate electrode structures may be spaced apart from each other in the third direction D3 through a first opening 493 and a second opening 497.

[0152] The gate electrode structure may include first to third gate electrodes 751, 753, and 755 sequentially formed along the first direction D1.

[0153] A second dividing layer may be formed on the second barrier layer to fill the first opening 493 and the second opening 497, and may be planarized until the upper surface of the fourth insulating intermediate layer 700 is exposed.

[0154] Accordingly, the second barrier layer may be transformed into a second barrier pattern 615, and a first dividing pattern 620 and a second dividing pattern 625 may be respectively formed in the first opening 493 and the second opening 497.

[0155] Referring to Figures 35 to 37 , a planarization process may be performed on the fourth insulating intermediate layer 700 until the upper surface of the third insulating intermediate layer 660 is exposed, and an upper portion of the first dividing pattern 620 and the second dividing pattern 625 may also be removed through the planarization process. Accordingly, the upper surfaces of a preliminary storage channel structure 460a and second to fourth sacrificial posts 691, 693, and 695 may be exposed.

[0156] The exposed second to fourth sacrificial posts 691, 693, and 695 may be partially removed to re-form third to fifth holes, respectively.

[0157] Specifically, an eighth sacrificial pattern 685 and a sacrificial liner 683 included in each of the second to fourth sacrificial posts 691, 693, and 695 may be removed. A portion of the second insulating pattern 681 formed in the second recess 672 having a relatively large width in the first direction D1 may be removed, while a portion of the second insulating pattern 681 formed in the third recess 674 having a relatively small width in the first direction D1 may be retained to form a fourth insulating pattern 686.

[0158] A portion of the second barrier pattern 615 exposed by the second recess 672 may be removed, thereby exposing sidewalls of the uppermost one of the gate electrodes penetrated by each of the third to fifth holes.

[0159] The first to third upper contact plugs 701, 703, and 705 may be formed in the third to fifth holes, respectively.

[0160] Referring to Figure 38 , the third insulating intermediate layer 660 may be patterned to expose the seventh sacrificial pattern 640. The exposed seventh sacrificial pattern 640 may be removed to re-form the sixth hole, and thus, the upper surface of the landing pad 22 may be exposed.

[0161] A through via 709 contacting the landing pad 22 may be formed within the sixth hole.

[0162] Referring to Figure 39 and Figure 40 , a fifth insulating intermediate layer 710 may be formed on the preliminary storage channel structure 460a, the first to third upper contact plugs 701, 703, and 705, the through via 709, and the third insulating intermediate layer 660.

[0163] A common source plate (CSP) 713 may be formed to extend through the fifth insulating intermediate layer 710 and contact the upper surface of the preliminary storage channel structure 460a.

[0164] In an exemplary embodiment, the CSP 713 may commonly contact the upper surfaces of the preliminary storage channel structures 460a of the active storage blocks, and thus, the preliminary storage channel structures 460a of the active storage blocks may be electrically connected to each other. In an exemplary embodiment, a plurality of CSPs 713 may be formed to be spaced apart from each other in the third direction D3 corresponding to the active storage blocks.

[0165] A sixth insulating intermediate layer 720 may be formed on the CSP 713 and the fifth insulating intermediate layer 710. A first via 723 may be formed through the sixth insulating intermediate layer 720 to contact the upper surface of the CSP 713. A second via 725 may be formed through the fifth insulating intermediate layer 710 and the sixth insulating intermediate layer 720 to contact the upper surfaces of the first to third upper contact plugs 701, 703, and 705, respectively. A third via 727 may be formed through the fifth insulating intermediate layer 710 and the sixth insulating intermediate layer 720 to contact the upper surface of the through via 709.

[0166] A seventh insulating intermediate layer 730 may be formed on the first to third vias 723, 725, and 727 and the sixth insulating intermediate layer 720. First to third wirings 733, 735, and 737 may be formed to pass through the fifth insulating intermediate layer 710 to contact the upper surfaces of the first to third vias 723, 725, and 727, respectively.

[0167] In an exemplary embodiment, each of the first wiring 733 and the third wiring 737 may extend in the third direction D3.

[0168] The second substrate 20 may be formed on the first to third wirings 733, 735, and 737 and the seventh insulating intermediate layer 730.

[0169] Referring Figures 41 to 43 to [Figure], various structures formed on the first substrate 10 may be inverted using the second substrate 20.

[0170] Hereinafter, the following description may be based on the state where the top and bottom of the structure on the first substrate 10 are inverted.

[0171] Referring Figure 44 to [Figure], the first substrate 10 may be removed. Accordingly, the upper surface of the first insulating pattern 315, the upper surface and outer sidewalls of the oxide layer 360, and the upper surface and outer sidewalls of the buffer pattern 21 may be exposed.

[0172] In an exemplary embodiment, the first substrate 10 may be removed by a wet etching process.

[0173] Referring Figure 45 to [Figure], an eighth insulating intermediate layer 750 may be formed on the upper surface of the first insulating pattern 315, the upper surface and outer sidewalls of the oxide layer 360, and the upper surface and outer sidewalls of the buffer pattern 21 to a sufficient height.

[0174] Referring Figure 46 to [Figure], a planarization process may be performed until the upper surface of the landing structure 23 is exposed. Accordingly, the upper portions of the oxide layer 360, the charge storage structure 402, and the first capping layer 410 may be removed.

[0175] The oxide layer 360 may be transformed into an oxide pattern 362, the first capping layer 410 may be transformed into a first capping pattern 412, and the preliminary storage channel structure 460a may be transformed into a storage channel structure 460 including a charge storage structure 402, a first capping pattern 412, a channel 422, a filling pattern 442, and a second capping pattern 452.

[0176] The upper surfaces of the first blocking pattern 372, the charge storage pattern 382, and the tunnel insulating pattern 392 of the charge storage structure 402 and the upper surface of the landing structure 23 may be exposed by the planarization process.

[0177] Referring Figure 47 to [Figure], a third opening may be formed by etching the eighth insulating intermediate layer 750, a part of the first insulating pattern 315, a part of the second blocking pattern 615, and the first gate electrode 751, and a third dividing pattern 440 may be formed to fill the third opening.

[0178] In an exemplary embodiment, the third division pattern 440 may partially extend through the upper portion of the storage channel structure 460. The third division pattern 440 may not only extend through the upper portion of the storage channel structure 460, but also extend through the first gate electrode 751 formed on the upper two layers, the first insulating pattern 315 formed on the upper two layers, and a portion of the first insulating pattern 315 at a layer below the upper two layers. The third division pattern 440 may extend in the second direction D2 on the first region I and the second region II of the first substrate 10 through the upper two step layers of the gate electrode structure. Accordingly, each of the first gate electrodes 751 at the upper two step layers may be separated in the third direction D3 by the third division pattern 440.

[0179] Referring Figure 48 , an etch stop layer 760 may be formed on the upper surfaces of the first blocking pattern 372, the charge storage pattern 382, and the tunnel insulating pattern 392 of the charge storage structure 402, the upper surface of the landing structure 23, the upper surface of the oxide pattern 362, the upper surface of the third division pattern 440, and the upper surface of the eighth insulating intermediate layer 750.

[0180] In an exemplary embodiment, the etch stop layer 760 may include a material having an etch selectivity with respect to a ninth insulating intermediate layer 790 to be formed later.

[0181] Referring Figures 49 to 51 , a fourth via 763, a fifth via 773, and a fourth wiring 783 may be sequentially formed on the storage channel structure 460. The fourth wiring 783 may extend in the third direction D3 and a plurality of fourth wirings 783 may be spaced apart from each other in the second direction D2. The fourth wiring 783 may be used as a bit line. A sixth via 775 and a fifth wiring 785 may be sequentially formed on each of the first to third upper contact plugs 701, 703, and 705. A seventh via 767, an eighth via 777, and a sixth wiring 787 may be sequentially formed on the through via 709.

[0182] The ninth insulating intermediate layer 790 may cover the fourth to eighth vias 763, 773, 775, 767, and 777 and the fourth to sixth wirings 783, 785, and 787.

[0183] In an exemplary embodiment, the width of the lower surface of the fourth via 763 in the horizontal direction may be greater than the width of the upper surface of the first capping pattern 412 of the storage channel structure 460 in the horizontal direction. The width of the storage channel structure 460 may decrease from the bottom to the top. If the fifth via 773, which electrically connects the fourth wiring 783 serving as a bit line to the storage channel structure 460, is directly formed on the upper surface of the storage channel structure 460 having a relatively small width, misalignment may increase. However, in an exemplary embodiment, the fourth via 763 having a relatively large width may be directly formed on the storage channel structure 460, and thus, misalignment may be reduced.

[0184] If the fifth via 773 is formed to directly contact the storage channel structure 460 instead of the fourth via 763, the width of the lower surface of the fifth via 773 in the horizontal direction may be greater than the width of the upper surface of the first capping pattern 412 in the horizontal direction.

[0185] Referring to Figure 52 and Figure 53 , the ninth via 813, the seventh wiring 823, and the tenth via 833 may be sequentially formed on the fourth wiring 783. The seventh wiring 823 may handle the routing of the fourth wiring 783 serving as a bit line. The eleventh via 815, the eighth wiring 825, and the twelfth via 835 may be sequentially formed on the fifth wiring 785. The thirteenth via 817, the ninth wiring 827, and the fourteenth via 837 may be sequentially formed on the sixth wiring 787.

[0186] The tenth insulating interlayer 840 may cover the ninth to fourteenth vias 813, 833, 815, 835, 817, and 837 and the seventh to ninth wirings 823, 825, and 827.

[0187] Hereinafter, for convenience of explanation, various structures formed on the second substrate 20 are collectively referred to as the first structure.

[0188] A first bonding pattern 900 that contacts one of the seventh to ninth wirings 823, 825, and 827 and a first bonding layer 910 that covers the first bonding pattern 900 may be formed on the first structure. In an exemplary embodiment, a plurality of first bonding patterns 900 may be formed to be spaced apart from each other in the second direction D2 and the third direction D3.

[0189] Referring to Figure 54 , a lower circuit pattern and an eleventh insulating interlayer 40 that covers the lower circuit pattern may be formed on the third substrate 30.

[0190] The third substrate 30 may include a first region I and a second region II surrounding the first region I, corresponding to the first substrate 10.

[0191] The lower circuit pattern may include, for example, transistors, lower contact plugs 35, first lower wirings 36, second lower wirings 38, and lower vias 37. Each component constituting the lower circuit pattern may be formed by a lithographic patterning method or an inlay process.

[0192] For example, the transistor may include a lower gate structure 43 disposed on the third substrate 30, and impurity regions 32 that may be disposed on an upper portion of the active region 31 adjacent to the lower gate structure 43 and serve as source / drains.

[0193] The lower gate structure 43 may include a lower gate insulating pattern 41 and a lower gate electrode 42 sequentially stacked on the third substrate 30. The lower contact plug 35 may also be in contact with the impurity region 32. A lower contact plug that contacts the lower gate electrode 42 may be additionally formed. The first lower wiring 36, the lower via 37, and the second lower wiring 38 may be sequentially formed on the lower contact plug 35. The second bonding pattern 55 and the second bonding layer 50 covering the second bonding pattern 55 may be formed on the eleventh insulating intermediate layer 40 and the lower circuit pattern.

[0194] In an exemplary embodiment, a plurality of second bonding patterns 55 may be formed to be spaced apart from each other in the second direction D2 and the third direction D3. The second bonding pattern 55 may be formed at a position corresponding to the first bonding pattern 900.

[0195] Referring to Figure 55 , the second substrate 20 may be flipped and the first bonding layer 910 may be bonded to the second bonding layer 50, and the first bonding pattern 900 may be bonded to the second bonding pattern 55. The first bonding pattern 900 and the second bonding pattern 55, and the first bonding layer 910 and the second bonding layer 50 may jointly form a first bonding structure.

[0196] Referring again to Figures 1 to 4 , the manufacturing of the integrated circuit semiconductor device may be completed by removing the second substrate 20.

[0197] As shown above, the first hole may be formed to extend through the mold on the first substrate 10, the first capping layer 410 may be formed at a lower portion of the first hole, and an annealing process may be performed to activate the first capping layer 410. The structure on the first substrate 10 may be inverted, and the first bonding pattern 900 may be formed on the inverted structure on the first substrate 10. The second bonding pattern 55 may be formed on the lower circuit pattern on the third substrate 30, and the structure on the first substrate 10 may be inverted again to be bonded to the lower circuit pattern on the third substrate.

[0198] After forming the first bonding pattern 900 including, for example, copper and the second bonding pattern 55, there may be limitations in sufficiently performing an annealing process on the first capping layer 410. However, in a method of manufacturing an integrated circuit semiconductor device, the first bonding pattern 900 may be formed after performing the annealing process on the first capping layer 410, and thus, the annealing process may be sufficiently performed.

[0199] In addition, the CSP 713 that connects the storage channel structures 460 of the active storage blocks to each other may be formed above the storage channel structures 460. Accordingly, compared to when the CSP 713 is formed to contact the lower sidewalls of the storage channel structures 460, the overall process complexity may be reduced.

[0200] Figure 56 is a cross-sectional view of an integrated circuit semiconductor device according to an exemplary embodiment, which may correspond to Figure 3 . Except for the shape of the storage channel structure 460, the semiconductor device may be substantially the same as or similar to the Figures 1 to 5 semiconductor device.

[0201] Referring to Figure 56 , the storage channel structure 460 may include a lower portion and an upper portion sequentially stacked in a first direction D1, and each of the lower portion and the upper portion may have a width that gradually decreases from its top toward its bottom. In an exemplary embodiment, the upper surface of the lower portion of the storage channel structure 460 may have a width greater than the lower surface of the upper portion of the storage channel structure 460.

[0202] Figure 56 shows that the storage channel structure 460 includes two portions stacked in the first direction D1. However, the inventive concept is not limited thereto and may include more than two portions stacked in the first direction D1. Each portion of the storage channel structure 460 may have a width that gradually decreases from its top toward its bottom, and the upper surface of a portion of the storage channel structure 460 may have a width greater than the lower surface of a portion of the storage channel structure 460 thereabove.

[0203] The support structure 688 may have a shape similar to the shape of the storage channel structure 460. That is, the support structure 688 may include a plurality of portions sequentially stacked in the first direction D1, and each portion may have a width that gradually decreases from its top toward its bottom.

[0204] Figure 57 is a cross-sectional view of an integrated circuit semiconductor device according to an exemplary embodiment, which may correspond to Figure 3 . The semiconductor device may be substantially the same as or similar to the Figures 1 to 5 semiconductor device, except for including a second structure and a second bonding structure corresponding to the first structure, and thus, repeated descriptions are omitted herein.

[0205] Referring to Figure 57 , the second bonding structure may include a third bonding pattern 75 and a fourth bonding pattern 85, as well as a third bonding layer 70 and a fourth bonding layer 80.

[0206] The third bonding layer 70 may be formed on the first structure, and the third bonding pattern 75 may extend through the third bonding layer 70 to contact one of the wirings or vias of the first structure. In an exemplary embodiment, a plurality of third bonding patterns 75 may be formed to be spaced apart from each other in a second direction D2 and a third direction D3.

[0207] The third bonding pattern 75 and the third bonding layer 70 may be substantially the same as or similar to the second bonding pattern 55 and the second bonding layer 50, respectively.

[0208] The fourth bonding layer 80 may be formed on the third bonding layer 70, and the fourth bonding pattern 85 may extend through the fourth bonding layer 80 to contact a corresponding one of the third bonding patterns 75. In an exemplary embodiment, a plurality of fourth bonding patterns 85 may be formed to be spaced apart from each other in the second direction D2 and the third direction D3 corresponding to the third bonding patterns 75.

[0209] In an exemplary embodiment, the fourth bonding pattern 85 and the fourth bonding layer 80 may be substantially the same as or similar to the first bonding pattern 900 and the first bonding layer 910, respectively.

[0210] The second structure may be formed on the second bonding structure. The second structure may be substantially the same as or similar to the first structure, but may be opposite to the first structure. The first structure and the second structure may be electrically connected to each other through the third bonding pattern 75 and the fourth bonding pattern 85. Compared with the first structure, the second structure may not include ninth to fourteenth vias 813, 833, 815, 835, 817 and 837, seventh to ninth wirings 823, 825 and 827, and tenth insulating intermediate layer 840.

[0211] Figures 58 to 59 is a cross-sectional view showing a method of forming an integrated circuit semiconductor device according to an exemplary embodiment. The method may include processes substantially the same as or similar to the processes shown in reference to Figures 1 to 54 and thus repeated explanations thereof are omitted herein.

[0212] Referring to Figure 58 , the first structure may be formed by performing the processes shown in reference to Figures 1 to 54 , and the third bonding layer 70 and the third bonding pattern 75 extending through the third bonding layer 70 to contact one of the wirings or vias of the first structure may be formed on the first structure.

[0213] Referring to Figure 59, the process shown with reference to Figures 6 to 40 can be performed. Hereinafter, for convenience of explanation, the first substrate 10 and the structures formed on the first substrate 10 (e.g., the preliminary storage channel structure 460a) may be collectively referred to as the preliminary second structure. However, different from the process shown with reference to Figure 39 and Figure 40 , instead of forming the second substrate 20 on the preliminary second structure, a fourth bonding layer 80 and a fourth bonding pattern 85 extending through the fourth bonding layer 80 to contact one of the wirings or vias of the preliminary second structure may be formed. The fourth bonding pattern 85 may be formed at a position corresponding to the third bonding pattern 75.

[0214] Referring again to Figure 57 , the preliminary second structure may be flipped and the fourth bonding layer 80 may be bonded to the third bonding layer 70, and each of the fourth bonding patterns 85 may contact a corresponding one of the third bonding patterns 75. The third bonding pattern 75 and the fourth bonding pattern 85, and the third bonding layer 70 and the fourth bonding layer 80 may jointly form a second bonding structure.

[0215] The preliminary storage channel structure 460a of the preliminary second structure may be transformed into a storage channel structure 460 by performing the process shown with reference to Figures 41 to 51 . Accordingly, the preliminary second structure may be transformed into a second structure corresponding to the first structure, and the fabrication of the integrated circuit semiconductor device may be completed.

[0216] Figure 60 is a cross-sectional view showing an integrated circuit semiconductor device according to an example embodiment, which may correspond to Figure 57 . Except for the shape of the storage channel structure 460 of the first and second structures, the semiconductor device may be substantially the same as or similar to the semiconductor device of Figure 57 , and thus repeated descriptions are omitted herein.

[0217] Referring to Figure 60 , the storage channel structure 460 of the first structure may include a lower portion and an upper portion sequentially stacked in a first direction D1, and each of the lower portion and the upper portion may have a width gradually decreasing from its top toward its bottom. In an example embodiment, the upper surface of the lower portion of the storage channel structure 460 may have a width greater than the lower surface of the upper portion of the storage channel structure 460.

[0218] The storage channel structure 460 of the second structure may include a lower portion and an upper portion sequentially stacked in a first direction D1, and each of the lower portion and the upper portion may have a width gradually increasing from its top toward its bottom. In an example embodiment, the upper surface of the lower portion of the storage channel structure 460 may have a width less than the lower surface of the upper portion of the storage channel structure 460.

[0219] Figure 60 The storage channel structure 460 of the first structure is shown to include two parts stacked in the first direction D1. However, the inventive concept is not limited thereto and may include more than two parts stacked in the first direction D1. Each part of the storage channel structure 460 may have a width that gradually decreases from its top to its bottom, and the upper surface of a part of the storage channel structure 460 may have a width greater than the width of the lower surface of a part of the storage channel structure 460 thereon.

[0220] The support structure 688 of the first structure may have a shape similar to the shape of the storage channel structure 460. That is, the support structure 688 may include a plurality of parts sequentially stacked in the first direction D1, and each part may have a width that gradually decreases from its top to its bottom.

[0221] Figure 60 The storage channel structure 460 of the second structure is shown to include two parts stacked in the first direction D1. However, the inventive concept is not limited thereto and may include more than two parts stacked in the first direction D1. Each part of the storage channel structure 460 may have a width that gradually increases from its top to its bottom, and the upper surface of a part of the storage channel structure 460 may have a width less than the width of the lower surface of a part of the storage channel structure 460 thereon.

[0222] The support structure 688 of the second structure may have a shape similar to the shape of the storage channel structure 460. That is, the support structure 688 may include a plurality of parts sequentially stacked in the first direction D1, and each part may have a width that gradually increases from its top to its bottom.

[0223] Although example embodiments have been specifically shown and described, those of ordinary skill in the art will understand that changes in form and detail may be made therein without departing from the spirit and scope of the claims.

[0224] Citation of Priority Application

[0225] This application claims priority to Korean Patent Application No. 10-2024-0010946, filed on January 24, 2024, the disclosure of which is incorporated herein by reference.

Claims

1. An integrated circuit device, comprising: A lower circuit pattern on a substrate; A bit line on the lower circuit pattern; A gate electrode structure on the bit line, the gate electrode structure including gate electrodes spaced apart from each other in a first direction and having a length in a second direction that gradually decreases from bottom to top along the first direction, the first direction being perpendicular to the upper surface of the substrate, and wherein the second direction is parallel to the upper surface of the substrate; A storage channel structure extending through the gate electrode structure, the storage channel structure including: A first capping pattern on the bit line; A channel on the first capping pattern; A second capping pattern on the channel; and A charge storage structure at outer sidewalls of the first capping pattern, the channel, and the second capping pattern; and A common source plate (CSP) on the storage channel structure.

2. The device according to claim 1, wherein a width of at least a portion of the storage channel structure increases from bottom to top in the first direction.

3. The device according to claim 1, further comprising: A via on the bit line; Wherein a lower surface of the first capping pattern contacts an upper surface of the via; Wherein the upper surface of the via has a width in a horizontal direction greater than a width of the lower surface of the first capping pattern in the horizontal direction; and wherein the horizontal direction is parallel to the upper surface of the substrate.

4. The device according to claim 3, wherein, The width of the via decreases from bottom to top.

5. The device according to claim 1, wherein The channel has a cup shape.

6. The device according to claim 1, further comprising: A bonding structure on the lower circuit pattern, the bonding structure including a first bonding layer on the lower circuit pattern, a first bonding pattern extending through the first bonding layer, a second bonding layer on the first bonding layer and the first bonding pattern, and a second bonding pattern extending through the second bonding layer to contact the first bonding pattern; Wherein the gate electrode structure extends on the bonding structure; And Wherein each of the first bonding pattern and the second bonding pattern includes copper.

7. An integrated circuit device, comprising: A lower circuit pattern on a substrate; A gate electrode structure including gate electrodes spaced apart from each other in a first direction, the gate electrode structure having a length in a second direction that gradually decreases from bottom to top along the first direction, the first direction being perpendicular to the upper surface of the substrate, and wherein the second direction is parallel to the upper surface of the substrate; An insulating pattern structure extending through the gate electrode structure, the insulating pattern structure including a first insulating pattern respectively disposed at a height corresponding to the gate electrode, and a second insulating pattern disposed between the first insulating patterns adjacent to each other in the first direction in the first insulating pattern; A storage channel structure extending through the gate electrode structure, the storage channel structure including: A first capping pattern on the bit line; A channel on the first capping pattern; A second capping pattern on the channel; and A charge storage structure at outer sidewalls of the first capping pattern, the channel, and the second capping pattern; A through - via extending through the insulating pattern structure; and A common source plate (CSP) on the storage channel structure.

8. The device according to claim 7, wherein the width of at least a portion of the storage channel structure increases from bottom to top in the first direction, and the width of at least a portion of the through - via increases from bottom to top in the first direction.

9. The device according to claim 7, further comprising a landing structure covering the lower sidewall and the lower surface of the through - via.

10. The device according to claim 9, wherein the lower surface of the storage channel structure is coplanar with the lower surface of the landing structure.

11. The device according to claim 9, further comprising an etch stop layer on the lower circuit pattern, the etch stop layer having an upper surface coplanar with the lower surface of the storage channel structure and the lower surface of the landing structure.

12. The device according to claim 9, wherein, The landing structure includes a landing pad covering the lower sidewall and the lower surface of the through - via, and a buffer pattern covering the outer sidewall of the landing pad.

13. The device according to claim 9, further comprising: A first via contacting the lower surface of the first cover pattern; and A second via contacting the lower surface of the landing structure; and wherein the width of the upper surface of the first via in the horizontal direction is greater than the width of the lower surface of the first cover pattern in the horizontal direction, and the horizontal direction is parallel to the upper surface of the substrate.

14. The device according to claim 13, wherein, The width of each of the first via and the second via decreases from bottom to top.

15. The device according to claim 7, further comprising: A bonding structure on the lower circuit pattern, the bonding structure including a first bonding layer on the lower circuit pattern, a first bonding pattern extending through the first bonding layer, a second bonding layer on the first bonding layer and the first bonding pattern, and a second bonding pattern extending through the second bonding layer to contact the first bonding pattern; wherein the gate electrode structure and the insulating pattern structure extend on the bonding structure; and wherein each of the first bonding pattern and the second bonding pattern includes copper.

16. The device according to claim 7, wherein, The channel has a cup - like shape.

17. An integrated circuit device, comprising: A lower circuit pattern on a substrate; A first bonding structure on the lower circuit pattern; A first bit line on the first bonding structure; A first gate electrode structure including first gate electrodes spaced apart from each other in a first direction, the first gate electrode structure having a length in a second direction that gradually decreases from bottom to top along the first direction, the first direction being perpendicular to the upper surface of the substrate, and wherein the second direction is parallel to the upper surface of the substrate; A first storage channel structure extending through the first gate electrode structure, the first storage channel structure including a first cover pattern on the first bit line, a first channel on the first cover pattern, a second cover pattern on the first channel, and a first charge storage structure at the outer sidewalls of the first cover pattern, the first channel, and the second cover pattern; A first common source plate (CSP) on the first storage channel structure; A second bonding structure on the first common source plate; A second common source plate on the second bonding structure; A second gate electrode structure including second gate electrodes spaced apart from each other in the first direction, the second gate electrode structure having a length in the second direction that increases from bottom to top along the first direction; A second storage channel structure extending through the second gate electrode structure, the second storage channel structure including a third capping pattern, a second channel on the third capping pattern, a fourth capping pattern on the second channel, and a second charge storage structure at outer sidewalls of the third capping pattern, the second channel, and the fourth capping pattern; and A second bit line on the second storage channel structure.

18. The device according to claim 17, wherein a width of at least a portion of the first storage channel structure increases from bottom to top in the first direction, and a width of at least a portion of the second storage channel structure decreases from bottom to top in the first direction.

19. The device according to claim 17, wherein the first bonding structure includes a first bonding layer on the lower circuit pattern, a first bonding pattern extending through the first bonding layer, a second bonding layer on the first bonding layer and the first bonding pattern, and a second bonding pattern extending through the second bonding layer to contact the first bonding pattern, each of the first bonding pattern and the second bonding pattern including copper; and wherein the second bonding structure includes a third bonding layer on the first common source plate, a third bonding pattern extending through the third bonding layer, a fourth bonding layer on the third bonding layer and the third bonding pattern, and a fourth bonding pattern extending through the fourth bonding layer to contact the third bonding pattern, each of the third bonding pattern and the fourth bonding pattern including copper.

20. The device according to claim 17, wherein the first channel has a shape of a cup, and the second channel has a shape of an inverted cup.

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