Memory cell structure and forming method of memory cell structure

Abstract

The invention discloses a memory cell structure and a forming method thereof. The memory cell structure comprises a substrate; the bit line structure and the source line structure are located on the substrate, and a first opening is formed between the bit line structure and the source line structure; the erasing gate structure is located in the first opening, and a second opening is formed between the erasing gate structure and the bit line structure; the floating gate structure is located in the second opening, and a third opening is formed between the floating gate structure and the erasing gate structure; the control gate structure is located in the third opening, and a fourth opening exposing the floating gate structure is formed between the control gate structure and the bit line structure; and the word line grid structure is positioned in the fourth opening. The erasing gate structure, the floating gate structure, the control gate structure and the word line gate structure are located between the bit line structure and the source line structure, a longitudinal electron transmission channel in the storage unit structure is achieved, and the transverse size of the storage unit structure is reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular, to a memory cell structure and a method for forming the memory cell structure. Background Art

[0002] As a non-volatile memory, NOR Flash has characteristics such as non-volatility, high device density, low power consumption, and electrical rewritability, and is widely used in portable electronic products such as mobile phones, digital cameras, smart cards, etc. With the gradual intelligence of the automotive, industrial, etc. and the trend of in-memory computing, higher requirements are put forward for the area of a single cell and the storage density in NOR Flash.

[0003] A relatively large area in NOR Flash comes from the word line structure and the control gate structure. Currently, in order to reduce the area of NOR Flash, on the one hand, the sizes of the word line structure, the control gate structure, and the peripheral control circuit in NOR Flash are compressed, but the size of the floating gate structure cannot be significantly reduced because the total electron storage amount needs to be ensured. Too low a storage amount of the floating gate structure will reduce the data read window and the cycling characteristics of write and erase operations, reducing the performance of the memory; on the other hand, the method of eliminating the word line structure is used to reduce the cell area, but it will exacerbate the interference effect between cells and cannot ensure the reliability of the memory. Summary of the Invention

[0004] The technical problem solved by the present invention is to provide a memory cell structure and a method for forming the memory cell structure to reduce the area of the memory cell while ensuring the storage amount of the floating gate structure.

[0005] To solve the above technical problem, an embodiment of the present invention provides a memory cell structure, including: a substrate; a bit line structure and a source line structure located on the substrate, with a first opening between the bit line structure and the source line structure; an erase gate structure located in the first opening, the erase gate structure being located on the sidewall surface of the source line structure, and having a second opening between the erase gate structure and the bit line structure; a floating gate structure located in the second opening, the floating gate structure being located on the bottom surface of the second opening, a partial sidewall surface of the bit line, and a partial sidewall surface of the erase gate structure, and having a third opening between the floating gate structure and the erase gate structure; a control gate structure located in the third opening, having a fourth opening exposing the floating gate structure between the control gate structure and the bit line structure; a word line gate structure located in the fourth opening.

[0006] Optionally, there is a source line structure on each side of the bit line structure; the erase gate structure, the floating gate structure, the control gate structure, and the word line gate structure are respectively located on both sides of the bit line structure.

[0007] Optionally, the erase gate structure includes: an erase gate dielectric layer located on the sidewall surface of the source line structure and the substrate surface, and an erase gate located on the surface of the erase gate dielectric layer.

[0008] Optionally, the control gate structure includes: a control gate dielectric layer located on the surface of the erase gate structure and the floating gate structure, and a control gate located on the surface of the control gate dielectric layer.

[0009] Optionally, the control gate dielectric layer includes a third dielectric layer located on the sidewall surface and the bottom surface of the control gate, a first dielectric layer located on the surface of the third dielectric layer, and a second dielectric layer located between the first dielectric layer and the third dielectric layer. The material of the second dielectric layer is different from the materials of the first dielectric layer and the third dielectric layer.

[0010] Optionally, the material of the first dielectric layer includes silicon oxide, the material of the second dielectric layer includes silicon nitride, and the material of the third dielectric layer includes silicon oxide.

[0011] Optionally, the floating gate structure includes: a floating gate dielectric layer located on the bottom surface of the second opening, a partial sidewall surface of the bit line, and the sidewall surface of the erase gate structure, and a floating gate located on the surface of the floating gate dielectric layer.

[0012] Optionally, the floating gate structure includes: a part of the floating gate dielectric layer is also located between the control gate structure and the erase gate structure.

[0013] Optionally, the memory cell structure further includes: well regions located within the substrate, within the bit line structure, and within the source line structure.

[0014] Optionally, the memory cell structure further includes: a source line doping region located within the source line structure, and the source line doping region is located on the sidewall surface and the top surface of the source line structure.

[0015] Optionally, the memory cell structure further includes: an interlayer dielectric layer located on the top surface of the erase gate dielectric layer and the top surface of the control gate structure; a conductive plug located within the interlayer dielectric layer, and the conductive plug is located on the top surface of the bit line structure.

[0016] Optionally, the memory cell structure further includes: the interlayer dielectric layer includes a first interlayer dielectric layer and a second interlayer dielectric layer located on the surface of the first interlayer dielectric layer, and the materials of the first interlayer dielectric layer and the second interlayer dielectric layer are different.

[0017] Correspondingly, an embodiment of the present invention further provides a method for forming a storage cell structure, including: providing a substrate; forming a bit line structure and a source line structure on the substrate, with a first opening between the bit line structure and the source line structure; forming an erase gate structure in the first opening, the erase gate structure being located on the sidewall surface of the source line structure, and having a second opening between the erase gate structure and the bit line structure; forming a floating gate structure in the second opening, the floating gate structure being located on the bottom surface of the second opening, a partial sidewall surface of the bit line, and a partial sidewall surface of the erase gate structure, and having a third opening between the floating gate structure and the erase gate structure; forming a control gate structure in the third opening, with a fourth opening exposing the floating gate structure between the control gate structure and the bit line structure; forming a word line gate structure in the fourth opening.

[0018] Optionally, the method for forming the storage cell structure further includes: forming a source line structure on each side of the bit line structure; the erase gate structure, the floating gate structure, the control gate structure, and the word line gate structure are respectively located on both sides of the bit line structure.

[0019] Optionally, the method for forming the bit line structure and the source line structure includes: performing a first ion implantation process on the substrate to form an initial well region in the substrate; etching the initial well region to form a well region, a bit line structure, a source line structure, and a first opening, the first opening being located between the bit line structure and the source line structure.

[0020] Optionally, the method for forming the erase gate structure includes: forming an erase gate dielectric layer on the sidewall surface of the source line structure and the substrate surface; forming an initial erase gate on the surface of the erase gate dielectric layer in the first opening; etching a part of the initial erase gate until the surface of the erase gate dielectric layer is exposed, forming an erase gate and a second opening, the second opening being located between the erase gate and the bit line structure.

[0021] Optionally, the method for forming the floating gate structure, the control gate structure, and the word line gate structure includes: after forming the erase gate structure, forming a floating gate dielectric layer on the bottom surface of the second opening, on partial sidewall surfaces of the bit line, and on the sidewall surface of the erase gate structure, with part of the floating gate dielectric layer also located between the control gate structure and the erase gate structure; forming a first initial floating gate on the surface of the floating gate dielectric layer within the second opening; etching part of the first initial floating gate until part of the floating gate dielectric layer is exposed, forming a second initial floating gate and a third opening; forming a control gate dielectric layer on the bottom surface of the third opening, on partial sidewall surfaces of the second initial floating gate, and on the surface of part of the floating gate dielectric layer; forming a control gate on the surface of the control gate dielectric layer; etching the top surface of the second initial floating gate to form a fourth opening and a floating gate; forming a word line gate dielectric layer at the bottom of the fourth opening; and forming a word line gate on the surface of the word line gate dielectric layer.

[0022] Optionally, the method for forming the control gate dielectric layer includes: forming a first dielectric layer on the bottom surface of the third opening, on partial sidewall surfaces of the second initial floating gate, and on the surface of part of the floating gate dielectric layer; forming a second dielectric layer on the surface of the first dielectric layer; and forming a third dielectric layer on the surface of the second dielectric layer, with the material of the second dielectric layer being different from the materials of the first dielectric layer and the third dielectric layer.

[0023] Optionally, the method for forming the control gate dielectric layer includes: forming a first dielectric layer on the bottom surface of the third opening, on partial sidewall surfaces of the second initial floating gate, and on the surface of part of the floating gate dielectric layer; forming a second dielectric layer on the surface of the first dielectric layer; and forming a third dielectric layer on the surface of the second dielectric layer, with the material of the second dielectric layer being different from the materials of the first dielectric layer and the third dielectric layer.

[0024] Optionally, the method for forming the memory cell structure further includes: after forming the word line gate structure, forming an interlayer dielectric layer on the top surface of the erase gate dielectric layer and on the top surface of the control gate structure; etching the interlayer dielectric layer on the top surface of the bit line structure and the floating gate dielectric layer until the surface of the bit line structure is exposed, forming a fifth opening; and forming a conductive plug within the fifth opening, with the conductive plug located on the top surface of the bit line structure.

[0025] Optionally, the method for forming the interlayer dielectric layer includes: forming a first interlayer dielectric layer on the top surface of the erase gate dielectric layer, on the top surface of the control gate structure, and on the top surface of the word line gate structure; and forming a second interlayer dielectric layer on the surface of the first interlayer dielectric layer, with the materials of the first interlayer dielectric layer and the second interlayer dielectric layer being different.

[0026] Optionally, the method for forming the storage cell structure further includes: after forming the source line structure, performing a second ion implantation process on the sidewall surface and the top surface of the source line structure to form a source line doping region.

[0027] Optionally, the ion type of the first ion implantation process is P-type, and the concentration range of the first ion implantation process is 1E11 ions / cm 3 to 1E14 ions / cm 3 ; the ion type of the second ion implantation process is N-type, and the concentration range of the second ion implantation process is 1E13 ions / cm 3 to 5E15 ions / cm 3 .

[0028] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0029] In the storage cell structure of the technical solution of the present invention, the erase gate structure, the floating gate structure, the control gate structure, and the word line gate structure are located between the bit line structure and the source line structure, realizing a longitudinal electron transmission channel in the storage cell structure, and the word line gate structure is located between the control gate structure and the bit line structure, reducing the lateral size of the storage cell structure; in addition, the increase in the longitudinal thickness of the floating gate structure ensures the storage capacity of the storage cell structure, thereby ensuring the read window of the storage cell and the cycling characteristics of the write and erase operations, and improving the performance of the storage cell.

[0030] Further, a source line structure is respectively disposed on both sides of the bit line structure, that is, adjacent storage cells share a bit line structure, realizing a reduction in the lateral size of the storage cell structure.

[0031] Further, in the storage cell structure of the technical solution of the present invention, both the erase gate structure and the control gate structure are arranged longitudinally, reducing the lateral size of the storage cell structure, and by increasing the height of the longitudinal erase gate structure and the control gate structure, the erase gate structure and the control gate structure can be flexibly adjusted according to the technology node, reducing the lower limit of the size of the storage cell structure.

[0032] Further, the bit line structure in the technical solution of the present invention can be flexibly adjusted according to the technology node. By compressing the size of the bit line structure and controlling the longitudinal channel of the bit line structure, the control ability of the storage cell structure for the channel is improved, charge leakage is reduced, and the performance of the storage cell is further improved.

[0033] In the method for forming the storage cell structure of the technical solution of the present invention, an erase gate structure, a floating gate structure, a control gate structure, and a word line gate structure are formed between the bit line structure and the source line structure to realize a longitudinal electron transfer channel in the storage cell structure, and the word line gate structure is located between the control gate structure and the bit line structure, reducing the lateral size of the storage cell structure; in addition, the increase in the thickness of the floating gate structure in the longitudinal direction ensures the storage capacity of the storage cell structure, thereby ensuring the read window of the storage cell and the cycle characteristics of the write and erase operations, improving the performance of the storage cell.

[0034] Further, in the method for forming the storage cell structure of the technical solution of the present invention, a source line structure is formed on each side of the bit line structure, that is, adjacent storage cells share a bit line structure, realizing a reduction in the lateral size of the storage cell structure.

[0035] Further, in the method for forming the storage cell structure of the technical solution of the present invention, both the erase gate structure and the control gate structure are arranged longitudinally, reducing the lateral size of the storage cell structure, and by increasing the height of the longitudinal erase gate structure and the control gate structure, the erase gate structure and the control gate structure can be flexibly adjusted according to the technology node, reducing the lower limit of the size of the storage cell structure.

[0036] Further, the bit line structure in the technical solution of the present invention can be flexibly adjusted according to the technology node. By compressing the size of the bit line structure and controlling the longitudinal channel of the bit line structure, the control ability of the storage cell structure for the channel is improved, charge leakage is reduced, and thus the performance of the storage cell is improved. Description of the Drawings

[0037] Figure 1 is a schematic structural diagram of a storage cell structure in an embodiment.

[0038] Figure 2 is a schematic structural diagram of a storage cell structure in another embodiment.

[0039] Figures 3 to 18 is a schematic structural diagram of the formation process of the storage cell structure in an embodiment of the present invention.

[0040] Figure 19 is a schematic structural diagram of a storage array structure in an embodiment of the present invention. Detailed Embodiments

[0041] It should be noted that the "surface" and "upper" in this specification are used to describe the relative positional relationship in space and do not limit whether there is direct contact.

[0042] As described in the background art, existing Nor Flash devices need to be further improved. Specific embodiments are now combined for analysis and explanation.

[0043] Figure 1 is a schematic structural diagram of a memory cell structure in an embodiment.

[0044] Please refer to Figure 1 In the memory cell structure, there are: a substrate 100, which includes a plurality of first regions I arranged in a first direction, and a second region II located between adjacent first regions I, and adjacent first regions I are axially symmetrically distributed along the second region II; memory cells located in the first regions I, and each memory cell includes a floating gate structure 105 located on the surface of the substrate 100, a control gate structure 106 located on the surface of the floating gate structure 105, a bit line structure 101 located on the surface of the substrate 100, a word line structure 108 located between the bit line structure 101 and the floating gate structure 105, and a channel region 102 located on the bottom surface of the word line structure 108; an erase gate structure 104 located in the second region II, and a source line structure 103 located on the bottom surface of the erase gate structure 104.

[0045] In this embodiment, the memory cell structure further includes: a conductive plug structure 109 located on the surfaces of the bit line structure 101, the word line structure 108, the control gate structure 106, and the erase gate structure 104.

[0046] The surface of the control gate structure 106 further includes a first dielectric layer 107.

[0047] In this embodiment, the memory cell structure further includes: a second dielectric layer 110 surrounding the memory cells in the first regions I, the erase gate structure 104 in the second region II, and the conductive plug structure 109.

[0048] In the above solution, in order to reduce the area of the memory cell structure, the sizes of the word line structure 108, the control gate structure 106, and the peripheral control circuit in the NOR flash memory are compressed, but the size of the floating gate structure 105 cannot be significantly reduced because the total electron storage capacity needs to be ensured. Too low a storage capacity of the floating gate structure 105 will reduce the data read window and the cycle characteristics of the write and erase operations, thereby reducing the performance of the memory.

[0049] Figure 2 is a schematic structural diagram of a memory cell structure in another embodiment.

[0050] Please refer to Figure 2 , Figure 2The storage cell structure reduces the area of the storage cell structure by removing the word line structure. By using the floating gate structure FG2 in adjacent storage cells as the word line structure to achieve the switching function. Specifically, by applying pressure to the second floating gate structure FG2 in adjacent storage cells, the current flows through the channel region N+ at the bottom of the floating gate structure FG2 to the first floating gate structure FG1, that is, a read operation or a write operation is performed on the first floating gate structure FG1. However, applying pressure to the second floating gate structure FG2 for a long time will also cause interference to the second floating gate structure FG2 itself. Since the second floating gate structure FG2 is also a storage cell, during the read operation or write operation on the first floating gate structure FG1, miswriting or misreading of the second floating gate structure FG2 will occur, reducing the reliability and cycle life of the memory.

[0051] To make the above objects, features and beneficial effects of the present invention more obvious and understandable, the following detailed description of the specific embodiments of the present invention will be given with reference to the accompanying drawings.

[0052] Figures 3 to 18 It is a schematic structural diagram of the formation process of the storage cell structure in the embodiment of the present invention.

[0053] Please refer to Figure 3 , provide a substrate 200; perform a first ion implantation process on the substrate 200 to form an initial well region 201 located in the substrate 200.

[0054] In this embodiment, the material of the substrate 200 is silicon.

[0055] In other embodiments, the material of the substrate includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon on insulator (SOI) or germanium on insulator (GOI). Among them, the multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.

[0056] In this embodiment, the ion implantation type of the first ion implantation process is P-type, and the concentration range of the first ion implantation process is 1E11 ions / cm 3 to 1E14 ions / cm 3 .

[0057] Please refer to Figure 4 , form a bit line structure 203 and a source line structure 204 on the substrate 200, and there is a first opening 202 between the bit line structure 203 and the source line structure 204.

[0058] The method for forming the bit line structure 203 and the source line structure 204 includes: etching the initial well region 201 to form a well region, a bit line structure 203, a source line structure 204, and a first opening 202, where the first opening 202 is located between the bit line structure 203 and the source line structure 204.

[0059] The first opening 202 is used to accommodate an erasing gate structure, a floating gate structure, a control gate structure, and a word line gate structure formed subsequently.

[0060] In this embodiment, the method for forming the first opening 202 includes one or a combination of both a wet etching process and a dry etching process.

[0061] The wet etching process parameters include: the etching solution includes at least two of ammonia water, hydrogen peroxide, acetic acid, and ammonium fluoride, and the mass concentration range of each solution is from 0 wt% to 30 wt%, and the reaction temperature range is from 0 degrees Celsius to 80 degrees Celsius.

[0062] The process parameters of the dry etching process include: the etching gas includes at least three of fluorine gas, hydrogen gas, nitrogen gas, argon gas, and ammonia gas, and the flow rate range of each gas is from 0 mL / min to 2000 mL / min, the reaction pressure range is from 0 mT to 3000 mT, the reaction temperature range is from 0 degrees Celsius to 250 degrees Celsius, and the etching power range is from 0 W to 1000 W.

[0063] In this embodiment, a source line structure 204 is formed on each side of the bit line structure 203; the erasing gate structure, the floating gate structure, the control gate structure, and the word line gate structure are respectively located on both sides of the bit line structure 203.

[0064] In the above solution, a source line structure 204 is respectively provided on both sides of the bit line structure 203, that is, adjacent memory cells share a bit line structure 203, so as to reduce the size of the memory cell structure in the transverse direction.

[0065] In addition, the bit line structure 203 in the technical solution of the present invention can be flexibly adjusted according to the technology node. Taking a node below 14 nanometers as an example, by compressing the size of the bit line structure 203, controlling the longitudinal channel of the bit line structure 203, improving the control ability of the memory cell structure over the channel, reducing charge leakage, and further improving the performance of the memory cell.

[0066] Please refer to Figure 5 , after forming the source line structure 204, a second ion implantation process is performed on the sidewall surface and the top surface of the source line structure 204 to form a source line doped region 205.

[0067] In this embodiment, the ion type of the second ion implantation process is N-type, and the concentration range of the second ion implantation process is 1E13 ions / cm 3 to 5E15 ions / cm 3 .

[0068] Please refer to Figure 6 , an erase gate structure is formed in the first opening 202. The erase gate structure is located on the sidewall surface of the source line structure 204, and there is a second opening 209 between the erase gate structure and the bit line structure 203.

[0069] The method of forming the erase gate structure includes: forming an initial erase gate dielectric layer 206 on the sidewall surface of the source line structure 204 and the surface of the substrate 200.

[0070] The material of the initial erase gate dielectric layer 206 includes silicon oxide, nitrogen-doped silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, titanium oxide, zirconium oxide.

[0071] The method of forming the initial erase gate dielectric layer 206 includes one or more of chemical vapor deposition, physical deposition, atomic layer deposition, and jet vapor deposition. The deposition gases include hydrogen and silane, and the reaction temperature range is 400 degrees Celsius to 800 degrees Celsius.

[0072] Please refer to Figure 7 , an initial erase gate 207 is formed on the surface of the erase gate dielectric layer 210 in the first opening 202.

[0073] The material of the initial erase gate 207 includes: single-crystalline silicon, polycrystalline silicon, amorphous silicon, hafnium oxide, iridium oxide, ruthenium oxide.

[0074] The method of forming the initial erase gate 207 includes one or more of chemical vapor deposition, physical deposition, atomic layer deposition, and jet vapor deposition. The deposition gases include hydrogen and silane, and the reaction temperature range is 400 degrees Celsius to 800 degrees Celsius.

[0075] Please refer to Figure 8 , part of the initial erase gate 207 is etched until the surface of the erase gate dielectric layer 210 is exposed, forming an erase gate 208 and a second opening 209. The second opening 209 is located between the erase gate 208 and the bit line structure 203.

[0076] The longitudinal dimension range of the erase gate 208 is 40 nanometers to 200 nanometers, and the transverse dimension range of the erase gate 208 is 15 nanometers to 200 nanometers.

[0077] In this embodiment, the method for forming the second opening 209 includes one or a combination of wet etching process and dry etching process.

[0078] The wet etching process parameters include: the etching solution includes at least two of ammonia water, hydrogen peroxide, acetic acid, and ammonium fluoride, and the mass concentration range of each solution is 0 wt% to 30 wt%, and the reaction temperature range is 0 °C to 80 °C.

[0079] The process parameters of the dry etching process include: the etching gas includes at least three of fluorine gas, hydrogen gas, nitrogen gas, argon gas, and ammonia gas, and the flow rate range of each gas is 0 mL / min to 2000 mL / min, the reaction pressure range is 0 mT to 3000 mT, the reaction temperature range is 0 °C to 250 °C, and the etching power range is 0 W to 1000 W.

[0080] Please refer to Figure 9 , remove the initial erase gate dielectric layer 206 on the surface of part of the well region and the surface of the bit line structure 203 to form an erase gate dielectric layer 210.

[0081] The erase gate dielectric layer 210 is located on the sidewall surface of the erase gate 208, the surface of the source line doping region 205, and the surface of part of the well region.

[0082] Please refer to Figure 10 , after forming the erase gate structure, form a floating gate dielectric layer 211 on the bottom surface of the second opening 209, part of the sidewall surface of the bit line, and the sidewall surface of the erase gate structure, and part of the floating gate dielectric layer 211 is also located between the control gate structure and the erase gate structure.

[0083] The material of the floating gate dielectric layer 211 includes silicon oxide, nitrogen-doped silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, titanium oxide, and zirconium oxide.

[0084] The method for forming the floating gate dielectric layer 211 includes: one or more of chemical vapor deposition, physical deposition, atomic layer deposition, and jet vapor deposition, and the deposition gas includes: hydrogen gas and silane, and the reaction temperature range is 400 °C to 800 °C.

[0085] Please refer to Figure 11 , form a first initial floating gate 212 on the surface of the floating gate dielectric layer 211 in the second opening 209.

[0086] The method for forming the first initial erase gate 207 includes: one or more of chemical vapor deposition, physical deposition, atomic layer deposition, and jet vapor deposition, and the deposition gas includes: hydrogen gas and silane, and the reaction temperature range is 400 °C to 800 °C.

[0087] Please refer to Figure 12 , etch a part of the first initial floating gate 212 until a part of the floating gate dielectric layer 211 is exposed, forming a second initial floating gate 213 and a third opening 214.

[0088] The third opening 214 is used to accommodate a subsequently formed control gate structure.

[0089] In this embodiment, the second initial floating gate 213 is in an "L" shape.

[0090] In this embodiment, the method for forming the third opening 214 includes one or a combination of both a wet etching process and a dry etching process.

[0091] The wet etching process parameters include: the etching solution includes at least two of ammonia water, hydrogen peroxide, acetic acid, and ammonium fluoride, and the mass concentration range of each solution is 0 wt% to 30 wt%, and the reaction temperature range is 0 degrees Celsius to 80 degrees Celsius.

[0092] The process parameters of the dry etching process include: the etching gas includes at least three of fluorine gas, hydrogen gas, nitrogen gas, argon gas, and ammonia gas, and the flow rate range of each gas is 0 mL / min to 2000 mL / min, the reaction pressure range is 0 mT to 3000 mT, the reaction temperature range is 0 degrees Celsius to 250 degrees Celsius, and the etching power range is 0 W to 1000 W.

[0093] Please refer to Figure 13 , form a control gate dielectric layer on the bottom surface of the third opening 214, the side wall surface of a part of the second initial floating gate 213, and the surface of a part of the floating gate dielectric layer 211.

[0094] The method for forming the control gate dielectric layer includes: forming a first dielectric layer 215 on the bottom surface of the third opening 214, the side wall surface of a part of the second initial floating gate 213, and the surface of a part of the floating gate dielectric layer 211; forming a second dielectric layer 216 on the surface of the first dielectric layer 215; forming a third dielectric layer 217 on the surface of the second dielectric layer 216, and the material of the second dielectric layer 216 is different from the materials of the first dielectric layer 215 and the third dielectric layer 217.

[0095] In this embodiment, the material of the first dielectric layer 215 includes silicon oxide, the material of the second dielectric layer 216 includes silicon nitride, and the material of the third dielectric layer 217 includes silicon oxide.

[0096] Please refer to Figure 14 , form a control gate 218 on the surface of the control gate dielectric layer.

[0097] The longitudinal dimension of the control gate 218 ranges from 40 nanometers to 200 nanometers, and the transverse dimension of the control gate 218 ranges from 20 nanometers to 150 nanometers.

[0098] The material of the control gate 218 includes: single-crystalline silicon, polycrystalline silicon, amorphous silicon, hafnium oxide, iridium oxide, ruthenium oxide.

[0099] The method for forming the control gate 218 includes one or more of chemical vapor deposition, physical deposition, atomic layer deposition, and jet vapor deposition. The deposition gases include hydrogen and silane, and the reaction temperature ranges from 400 degrees Celsius to 800 degrees Celsius.

[0100] Please refer to Figure 15 , etch the top surface of the second initial floating gate 213 to form a fourth opening 220 and a floating gate 227.

[0101] The floating gate 227 is used to store data in the memory cell structure.

[0102] The longitudinal dimension of the floating gate 227 ranges from 40 nanometers to 200 nanometers, and the transverse dimension of the floating gate 227 ranges from 20 nanometers to 150 nanometers.

[0103] The method for forming the fourth opening 220 includes: forming a first mask layer 219 on the surface of the erase gate dielectric layer 210, the floating gate dielectric layer 211, the control gate dielectric layer, and the control gate 218. The first mask layer 219 exposes a part of the surface of the second initial floating gate 213 and a part of the surface of the erase gate dielectric layer 210; use the first mask layer 219 as a mask to etch the surface of the second initial floating gate 213 to form a fourth opening 220 and a floating gate 227.

[0104] In this embodiment, the material of the first mask 219 includes silicon nitride.

[0105] In this embodiment, the method for forming the fourth opening 220 includes one or a combination of a wet etching process and a dry etching process.

[0106] The wet etching process parameters include: the etching solution includes at least two of ammonia water, hydrogen peroxide, acetic acid, and ammonium fluoride, and the mass concentration range of each solution is from 0 wt% to 30 wt%, and the reaction temperature range is from 0 degrees Celsius to 80 degrees Celsius.

[0107] The process parameters of the dry etching process include: the etching gas includes at least three of fluorine gas, hydrogen gas, nitrogen gas, argon gas, and ammonia gas, and the flow rate range of each gas is 0 mL / min to 2000 mL / min, the reaction pressure range is 0 mT to 3000 mT, the reaction temperature range is 0 °C to 250 °C, and the etching power range is 0 W to 1000 W.

[0108] In the above solution, both the erase gate structure and the control gate structure are arranged longitudinally, reducing the size of the memory cell structure in the transverse direction, and by increasing the height of the longitudinal erase gate structure and the control gate structure, the erase gate structure and the control gate structure can be flexibly adjusted according to the technology node, reducing the lower limit of the size of the memory cell structure.

[0109] Please refer to Figure 16 , an etch stop layer 222 is formed on the surface of the erase gate dielectric layer 210, the surface of the floating gate dielectric layer 211, the surface of the control gate dielectric layer, and the surface of the control gate 218; a word line gate dielectric layer 221 is formed at the bottom of the fourth opening 220.

[0110] Please refer to Figure 17 , a word line gate 223 is formed on the surface of the word line gate dielectric layer 221.

[0111] The material of the word line gate 223 is a semiconductor material, and the word line gate 223 is doped with conductive ions.

[0112] In this embodiment, the top of the word line gate 223 is flush with the etch stop layer 222.

[0113] In the above solution, the top surfaces of the bit line structure 203, the source line structure 204, the word line gate structure, the erase gate structure, the control gate structure, and the floating gate structure are flush, realizing the uniformity of the memory cell manufacturing process, and thus reducing the process difficulty.

[0114] Please refer to Figure 18 , after forming the word line gate structure, an interlayer dielectric layer is formed on the top surface of the erase gate dielectric layer 210 and the top surface of the control gate structure; the interlayer dielectric layer on the top surface of the bit line structure 203 and the floating gate dielectric layer 211 are etched until the surface of the bit line structure 203 is exposed, forming a fifth opening (not shown in the figure); a conductive plug 226 is formed in the fifth opening (not shown in the figure), and the conductive plug 226 is located on the top surface of the bit line structure 203.

[0115] The method for forming the interlayer dielectric layer includes: forming a first interlayer dielectric layer 224 on the surface of the etch stop layer 222 and the top surface of the word line gate 223; forming a second interlayer dielectric layer 225 on the surface of the first interlayer dielectric layer 224, and the materials of the first interlayer dielectric layer 224 and the second interlayer dielectric layer 225 are different.

[0116] The materials of the first interlayer dielectric layer 224 and the second interlayer dielectric layer 225 include: silicon oxide, nitrogen-doped silicon oxide, silicon oxynitride, aluminum oxide, hafnium oxide, titanium oxide, zirconium oxide.

[0117] In this embodiment, the materials of the conductive plugs 226 include aluminum and copper.

[0118] In the above solution, the erase gate structure, floating gate structure, control gate structure, and word line gate structure are formed between the bit line structure 203 and the source line structure 204 to realize the longitudinal electron transport channel in the memory cell structure, and the word line gate structure is located between the control gate structure and the bit line structure 203, reducing the lateral size of the memory cell structure. Taking the 55-nanometer node as an example, the area of the memory cell structure can be reduced to 0.04 square micrometers; in addition, the increase in the thickness of the floating gate structure in the longitudinal direction ensures the storage capacity of the memory cell structure, thereby ensuring the read window of the memory cell and the cycle characteristics of the write and erase operations, improving the performance of the memory cell.

[0119] The following will be combined with Figure 18 to illustrate the working principles of the write process and the erase process of the memory cell structure in this embodiment.

[0120] Specifically, during the write process of the memory cell structure, by applying a voltage to the word line gate 223, the underlying channel is turned on, and a high voltage (greater than 10V) is applied to the control gate 218, so that the voltage is coupled to the floating gate, and then the channel under the floating gate 227 is turned on to form a strong vertical electric field. A large pressure difference is applied between the source line structure 204 and the bit line structure 203 to generate a conduction current. And because the pressure difference is large and the carrier energy is large, the strong vertical electric field accelerates the channel hot carriers in the vertical direction, and they are injected into the floating gate through the floating gate dielectric layer 211, thereby realizing signal writing.

[0121] Please continue to refer to Figure 18 , the main writing sites are at the concentrated intersection electric field of the word line gate 223 and the floating gate 227, and the principle of source-side hot electron injection (abbreviated as SSHEI) is used to realize the tunneling of electrons from the channel to the floating gate 227.

[0122] Specifically, during the erasure process of the storage cell structure, by applying a high voltage (greater than 10V) to the erasure gate 208 terminal, due to the coupling capacitance effect, a potential difference is formed on the erasure gate dielectric layer 210, which is sufficient to pull the electrons written in the floating gate 227 to the erasure gate 208 through the tunneling mechanism, thereby emptying the electrons stored in the erasure gate 208.

[0123] Please continue to refer to Figure 18 , the erasure site is mainly at the junction of the floating gate 227 and the erasure gate 208, and the erasure of the electrons in the floating gate 227 is realized by using the tunneling principle.

[0124] Figure 19 It is a schematic structural diagram of a storage array structure in an embodiment of the present invention.

[0125] Please refer to Figure 19 , the storage array structure includes a plurality of storage cell structures 301, the storage cell structures in each row are connected to a bit line, and the storage cell structures in each column are connected to a word line and a source line.

[0126] In this embodiment, the storage cell structure 302 in the second row and the second column is selected for write, read, or erase operations.

[0127] In this embodiment, in Figure 19 , the voltage and current values in the storage cell structures are shown in Table 1, Table 2, Table 3, and Table 4:

[0128]

[0129] Table 1

[0130]

[0131] Table 2

[0132]

[0133] Table 3

[0134]

[0135] Table 4

[0136] Among them, the values in each column of Table 1 represent the voltage or current values at the source line 1 (SL1), source line 2 (SL2), and source line 3 (SL3) terminals under different operation types.

[0137] The values in each column of Table 2 represent the voltage or current values at the word line 1 (WL1), word line 2 (WL2), word line 3 (WL3), and word line 4 (WL4) terminals under different operation types.

[0138] The values in each column of Table 3 represent the voltage or current values at the ends of bit line 1 (BL1), bit line 2 (BL2), bit line 3 (BL3), and bit line 4 (BL4) under different operation types.

[0139] The values in each column of Table 4 represent the voltage or current values at the ends of control gate (CG1), control gate 218 (CG2), and erase gate (EG) under different operation types.

[0140] In the above solution, since the memory cell structure in the second row and second column is the selected memory cell structure, that is, source line 2 (SL2), word line 2 (WL2), bit line 2 (BL2), and control gate (CG1) are the read terminals.

[0141] Correspondingly, an embodiment of the present invention further provides a memory cell structure. Please continue to refer to Figure 18 , including: a substrate 200; a bit line structure 203 and a source line structure 204 located on the substrate 200, with a first opening 202 between the bit line structure 203 and the source line structure 204; an erase gate structure located in the first opening 202, the erase gate structure being located on the sidewall surface of the source line structure 204, and there being a second opening 209 between the erase gate structure and the bit line structure 203; an erase gate structure located in the first opening 202, the erase gate structure being located on the sidewall surface of the source line structure 204, and there being a second opening 209 between the erase gate structure and the bit line structure 203; an erase gate structure located in the first opening 202, the erase gate structure being located on the sidewall surface of the source line structure 204, and there being a second opening 209 between the erase gate structure and the bit line structure 203; a word line gate structure located in the fourth opening 220.

[0142] In this embodiment, there is a source line structure 204 on each side of the bit line structure 203; the erase gate structure, floating gate structure, control gate structure, and word line gate structure are respectively located on both sides of the bit line structure 203.

[0143] In this embodiment, the erase gate structure includes: an erase gate dielectric layer 210 located on the sidewall surface of the source line structure 204 and the surface of the substrate 200, and an erase gate 208 located on the surface of the erase gate dielectric layer 210.

[0144] In this embodiment, the control gate structure includes: a control gate dielectric layer located on the surface of the erase gate structure and the surface of the floating gate structure, and a control gate 218 located on the surface of the control gate dielectric layer.

[0145] In this embodiment, the control gate dielectric layer includes a third dielectric layer 217 located on the sidewall surface and the bottom surface of the control gate 218, a first dielectric layer 215 located on the surface of the third dielectric layer 217, and a second dielectric layer 216 located between the first dielectric layer 215 and the third dielectric layer 217. The material of the second dielectric layer 216 is different from the materials of the first dielectric layer 215 and the third dielectric layer 217.

[0146] In this embodiment, the material of the first dielectric layer 215 includes silicon oxide, the material of the second dielectric layer 216 includes silicon nitride, and the material of the third dielectric layer 217 includes silicon oxide.

[0147] In this embodiment, the floating gate structure includes: a floating gate dielectric layer 211 located on the bottom surface of the second opening 209, a partial sidewall surface of the bit line, and a sidewall surface of the erase gate structure, and a floating gate 227 located on the surface of the floating gate dielectric layer 211.

[0148] In this embodiment, the memory cell structure further includes: well regions located in the substrate 200, the bit line structure 203, and the source line structure 204.

[0149] In this embodiment, the memory cell structure further includes: a source line doping region 205 located in the source line structure 204, and the source line doping region 205 is located on the sidewall surface and the top surface of the source line structure 204.

[0150] In this embodiment, the memory cell structure further includes: an interlayer dielectric layer located on the top surface of the erase gate dielectric layer 210 and the top surface of the control gate structure; a conductive plug 226 located in the interlayer dielectric layer, and the conductive plug 226 is located on the top surface of the bit line structure 203.

[0151] In this embodiment, the memory cell structure further includes: the interlayer dielectric layer includes a first interlayer dielectric layer 224 and a second interlayer dielectric layer 225 located on the surface of the first interlayer dielectric layer 224, and the materials of the first interlayer dielectric layer 224 and the second interlayer dielectric layer 225 are different.

[0152] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. A memory cell structure, characterized in that, Comprising: A substrate; A bit line structure and a source line structure located on the substrate, with a first opening between the bit line structure and the source line structure; An erase gate structure located within the first opening, the erase gate structure being located on the sidewall surface of the source line structure, and having a second opening between the erase gate structure and the bit line structure; A floating gate structure located within the second opening, the floating gate structure being located on the bottom surface of the second opening, a partial sidewall surface of the bit line, and a partial sidewall surface of the erase gate structure, and having a third opening between the floating gate structure and the erase gate structure; A control gate structure located within the third opening, having a fourth opening exposing the floating gate structure between the control gate structure and the bit line structure; A word line gate structure located within the fourth opening.

2. The memory cell structure according to claim 1, wherein There is a source line structure on each side of the bit line structure; the erase gate structure, the floating gate structure, the control gate structure, and the word line gate structure are respectively located on both sides of the bit line structure.

3. The memory cell structure according to claim 1, wherein The erase gate structure includes: an erase gate dielectric layer located on the sidewall surface of the source line structure and the substrate surface, and an erase gate located on the surface of the erase gate dielectric layer.

4. The memory cell structure according to claim 1, characterized in that, The control gate structure includes: a control gate dielectric layer located on the surface of the erase gate structure and the floating gate structure, and a control gate located on the surface of the control gate dielectric layer.

5. The memory cell structure according to claim 4, wherein The control gate dielectric layer includes a third dielectric layer located on the sidewall surface and the bottom surface of the control gate, a first dielectric layer located on the surface of the third dielectric layer, and a second dielectric layer located between the first dielectric layer and the third dielectric layer, the material of the second dielectric layer being different from the materials of the first dielectric layer and the third dielectric layer.

6. The memory cell structure according to claim 5, characterized in that, The material of the first dielectric layer includes silicon oxide, the material of the second dielectric layer includes silicon nitride, and the material of the third dielectric layer includes silicon oxide.

7. The memory cell structure according to claim 1, wherein The floating gate structure includes: a floating gate dielectric layer located on the bottom surface of the second opening, a partial sidewall surface of the bit line, and the sidewall surface of the erase gate structure, and a floating gate located on the surface of the floating gate dielectric layer.

8. The memory cell structure according to claim 7, wherein The floating gate structure includes: a part of the floating gate dielectric layer is also located between the control gate structure and the erase gate structure.

9. The memory cell structure according to claim 1, wherein, Further comprising: Well regions located within the substrate, the bit line structure, and the source line structure.

10. The memory cell structure according to claim 1, wherein Further comprising: A source line doping region located within the source line structure, the source line doping region being located on the sidewall surface and the top surface of the source line structure.

11. The storage cell structure according to claim 1, wherein, Further comprising: An interlayer dielectric layer located on the top surface of the erase gate dielectric layer and the top surface of the control gate structure; A conductive plug located within the interlayer dielectric layer, the conductive plug being located on the top surface of the bit line structure.

12. The memory cell structure according to claim 11, wherein Further comprising: The interlayer dielectric layer includes a first interlayer dielectric layer and a second interlayer dielectric layer located on the surface of the first interlayer dielectric layer, the materials of the first interlayer dielectric layer and the second interlayer dielectric layer being different.

13. A method for forming a memory cell structure, characterized in that, Comprising: Providing a substrate; Forming a bit line structure and a source line structure on the substrate, with a first opening between the bit line structure and the source line structure; Forming an erase gate structure within the first opening, the erase gate structure being located on the sidewall surface of the source line structure, and having a second opening between the erase gate structure and the bit line structure; A floating gate structure is formed within the second opening. The floating gate structure is located on the bottom surface of the second opening, partial sidewall surfaces of the bit line, and partial sidewall surfaces of the erase gate structure, and there is a third opening between the floating gate structure and the erase gate structure; A control gate structure is formed within the third opening, and there is a fourth opening exposing the floating gate structure between the control gate structure and the bit line structure; A word line gate structure is formed within the fourth opening.

14. The method for forming the storage cell structure according to claim 13, wherein It further includes: A source line structure is respectively formed on both sides of the bit line structure; the erase gate structure, the floating gate structure, the control gate structure, and the word line gate structure are respectively located on both sides of the bit line structure.

15. The method for forming the memory cell structure according to claim 14, wherein, The method for forming the bit line structure and the source line structure includes: performing a first ion implantation process on the substrate to form an initial well region within the substrate; etching the initial well region to form a well region, a bit line structure, a source line structure, and a first opening, and the first opening is located between the bit line structure and the source line structure.

16. The method for forming the memory cell structure according to claim 15, wherein The method for forming the erase gate structure includes: forming an erase gate dielectric layer on the sidewall surface of the source line structure and the substrate surface; forming an initial erase gate on the surface of the erase gate dielectric layer within the first opening; etching a part of the initial erase gate until the surface of the erase gate dielectric layer is exposed to form an erase gate and a second opening, and the second opening is located between the erase gate and the bit line structure.

17. The method for forming the memory cell structure according to claim 16, wherein The method for forming the floating gate structure, the control gate structure, and the word line gate structure includes: after forming the erase gate structure, forming a floating gate dielectric layer on the bottom surface of the second opening, partial sidewall surfaces of the bit line, and the sidewall surface of the erase gate structure, and a part of the floating gate dielectric layer is also located between the control gate structure and the erase gate structure; forming a first initial floating gate on the surface of the floating gate dielectric layer within the second opening; etching a part of the first initial floating gate until a part of the floating gate dielectric layer is exposed to form a second initial floating gate and a third opening; forming a control gate dielectric layer on the bottom surface of the third opening, partial sidewall surfaces of the second initial floating gate, and partial surface of the floating gate dielectric layer; forming a control gate on the surface of the control gate dielectric layer; etching the top surface of the second initial floating gate to form a fourth opening and a floating gate; forming a word line gate dielectric layer at the bottom of the fourth opening; forming a word line gate on the surface of the word line gate dielectric layer.

18. The method for forming the storage cell structure according to claim 17, wherein, The method for forming the control gate dielectric layer includes: forming a first dielectric layer on the bottom surface of the third opening, partial sidewall surfaces of the second initial floating gate, and partial surface of the floating gate dielectric layer; forming a second dielectric layer on the surface of the first dielectric layer; forming a third dielectric layer on the surface of the second dielectric layer, and the material of the second dielectric layer is different from that of the first dielectric layer and the third dielectric layer.

19. The method for forming the memory cell structure according to claim 17, wherein The method for forming the word line gate structure further includes: forming a first mask layer on the surfaces of the erase gate dielectric layer, the floating gate dielectric layer, the control gate dielectric layer, and the control gate, and the first mask layer exposes part of the second initial floating gate surface and part of the erase gate dielectric layer surface; etching the second initial floating gate surface using the first mask layer as a mask to form a fourth opening and a floating gate; forming a word line gate dielectric layer at the bottom of the fourth opening; and forming a word line gate on the surface of the word line gate dielectric layer.

20. The method for forming the memory cell structure according to claim 17, wherein, It further includes: After forming the word line gate structure, forming an interlayer dielectric layer on the top surface of the erase gate dielectric layer and the top surface of the control gate structure; Etching the interlayer dielectric layer on the top surface of the bit line structure and the floating gate dielectric layer until the surface of the bit line structure is exposed to form a fifth opening; Forming a conductive plug in the fifth opening, and the conductive plug is located on the top surface of the bit line structure.

21. The method for forming the storage cell structure according to claim 20, wherein The method for forming the interlayer dielectric layer includes: forming a first interlayer dielectric layer on the top surface of the erase gate dielectric layer, the top surface of the control gate structure, and the top surface of the word line gate structure; forming a second interlayer dielectric layer on the surface of the first interlayer dielectric layer, and the materials of the first interlayer dielectric layer and the second interlayer dielectric layer are different.

22. The method for forming the memory cell structure according to claim 15, wherein It further includes: After forming the source line structure, performing a second ion implantation process on the sidewall surface and the top surface of the source line structure to form a source line doped region.

23. The method for forming the memory cell structure according to claim 22, wherein, The ion type of the first ion implantation process is P-type, and the concentration range of the first ion implantation process is 1E11 ions / cm 3 to 1E14 ions / cm 3 ; the ion type of the second ion implantation process is N-type, and the concentration range of the second ion implantation process is 1E13 ions / cm 3 to 5E15 ions / cm 3 .

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