Semiconductor structure and manufacturing method thereof, memory and memory system

Abstract

The invention provides a semiconductor structure and a manufacturing method thereof, a memory and a memory system. The semiconductor structure comprises a laminated structure; the channel structure extends along a first direction in the laminated structure; the conducting layer is located on one side of the laminated structure, and a part of the conducting layer extends to the channel structure in the stacking direction of the laminated structure; wherein the first direction is a direction opposite to the stacking direction.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more particularly, to semiconductor structures, methods of manufacturing semiconductor structures, memories, and storage systems. Background Art

[0002] With the rise and development of the fields of artificial intelligence, big data, Internet of Things, mobile communication, mobile devices, and cloud storage, the requirements for the storage density of semiconductor structures such as three-dimensional semiconductor memory devices are also getting higher and higher. However, as the number of stacked layers in the semiconductor structure increases, the aspect ratio of the channel structure becomes larger and larger, which makes the differences between multiple channel structures larger and larger, and thus easily leads to a decline in the overall performance of the semiconductor structure. Summary of the Invention

[0003] The embodiments proposed in this application can solve or partially solve the deficiencies proposed in the above background art part or other deficiencies in the prior art.

[0004] This application provides a semiconductor structure. The semiconductor structure includes: a stacked structure; a channel structure extending in a first direction in the stacked structure; and a conductive layer located on one side of the stacked structure, wherein a part of the conductive layer extends in the stacking direction of the stacked structure to the channel structure; wherein the first direction is a direction opposite to the stacking direction.

[0005] In one embodiment, the semiconductor structure further includes: a spacer layer located between the conductive layer and the stacked structure in the first direction, wherein a part of the conductive layer penetrates through the spacer layer and extends to the channel structure.

[0006] In one embodiment, the semiconductor structure further includes: a semiconductor layer located between the spacer layer and the stacked structure in the first direction, wherein a part of the conductive layer penetrates through the spacer layer and the semiconductor layer and extends to the channel structure.

[0007] In one embodiment, the channel structure includes: a functional layer extending in the first direction; and a channel layer located on a side of the functional layer away from the stacked structure and extending in the first direction; wherein the channel layer is in contact with the conductive layer.

[0008] In one embodiment, multiple channel structures extend to the same height in the stacked structure in the first direction.

[0009] In one embodiment, the material of the spacer layer includes an insulating material.

[0010] In one embodiment, the stacked structure includes alternately stacked dielectric layers and gate layers.

[0011] On the other hand, the present application provides a method for manufacturing a semiconductor structure. The method includes: forming an epitaxial layer within a sacrificial material layer; forming a channel structure extending in a first direction to the epitaxial layer in an initial stacked structure located on one side of the sacrificial material layer, wherein the channel structure includes a functional layer extending in the first direction and a channel layer located on a side of the functional layer away from the initial stacked structure; removing the sacrificial material layer, the epitaxial layer, and a part of the functional layer to expose the channel layer; and forming a conductive layer covering the channel layer, wherein the conductive layer protrudes toward the channel layer.

[0012] In one embodiment, the semiconductor structure includes a spacer layer and a semiconductor layer adjacent to each other in the first direction, wherein the spacer layer is located between the sacrificial material layer and the semiconductor layer, and forming the epitaxial layer within the sacrificial material layer includes: forming an epitaxial layer extending in the first direction within the sacrificial material layer and the semiconductor layer, wherein a part of the spacer layer opposite to the epitaxial layer forms a groove.

[0013] In one embodiment, forming the epitaxial layer extending in the first direction within the sacrificial material layer and the semiconductor layer includes: forming a channel hole extending in the first direction through the initial stacked structure, the semiconductor layer, and the spacer layer and extending to the sacrificial material layer; and forming the epitaxial layer in parts of the channel hole located in the semiconductor layer and the sacrificial material layer.

[0014] In one embodiment, the method further includes: forming an isolation layer on one side of the epitaxial layer via the channel hole.

[0015] In one embodiment, removing the sacrificial material layer, the epitaxial layer, and a part of the functional layer to expose the channel layer includes: removing parts of the sacrificial material layer and the epitaxial layer located in the sacrificial material layer to expose the groove; and removing parts of the epitaxial layer located in the semiconductor layer, the isolation layer, and a part of the functional layer via the groove to expose the channel layer.

[0016] In one embodiment, forming the channel structure extending in the first direction to the epitaxial layer in the initial stacked structure located on one side of the sacrificial material layer includes: forming the channel structure on one side of the isolation layer via the channel hole.

[0017] In one embodiment, the initial stacked structure includes alternately stacked dielectric layers and sacrificial layers, and wherein the method further includes: after forming the channel structure, replacing the sacrificial layer with a gate layer to form a stacked structure.

[0018] In one embodiment, the channel structure is formed on one side of the isolation layer via the channel holes, including: forming a functional layer on the sidewalls of the channel holes; and forming a channel layer extending in the first direction on the side of the functional layer away from the initial stacked structure.

[0019] On the other hand, this application provides a memory, which includes: a memory cell array including the semiconductor structure as described above; and a peripheral circuit coupled to the memory cell array.

[0020] On the other hand, this application provides a storage system, which includes at least one memory; and a controller coupled to the memory for controlling the memory to store data. Description of the Drawings

[0021] In conjunction with the drawings, through the following detailed description of non-limiting embodiments, other features, objectives, and advantages of this application will become more apparent. In the drawings:

[0022] Figure 1 is a flowchart of a method for manufacturing a semiconductor structure according to an exemplary embodiment of this application;

[0023] Figures 2 to 9 is a process step diagram of manufacturing a semiconductor structure according to an exemplary embodiment of this application;

[0024] Figure 10 is a schematic block diagram of a memory according to an exemplary embodiment of this application;

[0025] Figure 11 is an exemplary block diagram of a system with a storage system according to an exemplary embodiment of this application; and

[0026] Figure 12A and Figure 12B is a schematic diagram of a storage system according to an exemplary embodiment of this application. Detailed Embodiments

[0027] To better understand this application, more detailed descriptions will be made on various aspects of this application with reference to the drawings. It should be understood that these detailed descriptions are only descriptions of the exemplary embodiments of this application and do not limit the scope of this application in any way.

[0028] In the drawings, for ease of illustration, the thickness, dimensions, and shapes of the components have been slightly adjusted. The drawings are only examples and are not drawn strictly to scale. As used herein, terms such as "substantially", "about", and similar terms are used as approximate terms and not as terms of degree, and are intended to account for the inherent deviations in measured or calculated values that would be recognized by those of ordinary skill in the art.

[0029] In addition, in this document, when describing that a part is "on" another part, for example, the meanings of "on...", "above...", and "over..." should be interpreted in the broadest way, such that "on..." not only means "directly on something", but also includes "on something" with intermediate features or layers therebetween, and "above..." or "over..." does not absolutely mean being above with respect to the direction of gravity, nor does it only mean "above something" or "over something", but can also include "above something" or "over something" with no intermediate features or layers therebetween (i.e., directly on something).

[0030] It should also be understood that expressions such as "comprising", "including", "having", "containing", and / or "including having" in this specification are open-ended rather than closed-ended expressions, which mean the presence of the stated features, elements, and / or components, but do not exclude the presence of one or more other features, elements, components, and / or combinations thereof. In addition, when an expression such as "at least one of..." appears after a list of listed features, it modifies the entire list of features, rather than just the individual elements in the list. In addition, when describing embodiments of the present application, the use of "may" means "one or more embodiments of the present application". And the term "exemplarily" is intended to refer to an example or illustration.

[0031] This document is described with reference to schematic diagrams of exemplary embodiments. The exemplary embodiments disclosed herein should not be construed as limited to the specific shapes and dimensions shown, but include various equivalent structures capable of achieving the same functions and shape and size deviations caused, for example, during manufacturing. The positions shown in the drawings are schematic in nature and are not intended to limit the positions of the components.

[0032] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the technical field to which this disclosure belongs. Terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant field, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0033] As used herein, the term "layer" refers to a portion of material that includes a region having a height. A layer can be a region of a uniform or non-uniform continuous structure, the height of which is less than the height of the continuous structure. For example, a layer can be located at the top and bottom surfaces of the continuous structure or between any set of horizontal planes therebetween. A layer can extend horizontally, vertically, and / or along a tapered surface. A substrate can be a layer, can include one or more layers therein, and / or can have one or more layers thereon, above, and / or below it. A layer can include multiple layers.

[0034] In addition, in the present application, when "connected" or "coupled" is used, it can indicate direct or indirect contact between the corresponding components, unless otherwise explicitly defined or derivable from the context.

[0035] It should be noted that, without conflict, the embodiments in the present application and the features in the embodiments can be combined with each other. Additionally, unless explicitly defined or contradictory to the context, the specific steps included in the methods described in the present application do not have to be limited to the described order, but can be executed in any order or in parallel. The present application will be described in detail below with reference to the drawings and in conjunction with the embodiments.

[0036] Figure 1 is a flowchart of a method 1000 for manufacturing a semiconductor structure according to an exemplary embodiment of the present application.

[0037] As Figure 1 shown, the method 1000 for manufacturing a semiconductor structure can include: S1100, forming an epitaxial layer within a sacrificial material layer; S1200, forming a channel structure extending in a first direction to the epitaxial layer in an initial stacked structure located on one side of the sacrificial material layer, where the channel structure includes a functional layer extending in the first direction and a channel layer located on the side of the functional layer away from the initial stacked structure; S1300, removing the sacrificial material layer, the epitaxial layer, and a portion of the functional layer to expose the channel layer; and S1400, forming a conductive layer covering the channel layer, where the conductive layer bulges towards the channel layer. Steps S1100 to S1400 will be described in detail below.

[0038] In an exemplary embodiment of the present application, as Figure 3 shown, an epitaxial layer 1500 can be formed within a sacrificial material layer 1100. Figure 2 And Figure 3 is a process step diagram of a method for forming an epitaxial layer 1500 according to an exemplary embodiment of the present application. It should be understood that the process for forming the epitaxial layer 1500 provided in the present application is only an example and is not specifically limited. In actual processes, the process for forming the epitaxial layer 1500 can be reasonably set according to actual needs.

[0039] Exemplarily, asFigure 2 As shown, a spacer layer 1200, a semiconductor layer 1300, and an initial stacked structure 1400' can be sequentially formed on a sacrificial material layer 1100. The sacrificial material layer 1100, the spacer layer 1200, the semiconductor layer 1300, and the initial stacked structure 1400' can be sequentially distributed along a first direction X or the stacking direction Y of the initial stacked structure 1400', where the first direction X is a direction opposite to the stacking direction Y.

[0040] Exemplarily, the material of the sacrificial material layer 1100 and / or the semiconductor layer 1300 can include elemental semiconductor materials, such as single-crystalline silicon and the like. Of course, it should be understood that in another embodiment, the material of the sacrificial material layer 1100 and / or the semiconductor layer 1300 can include at least one of polycrystalline semiconductor materials or other semiconductor materials known in the art. For example, the material of the sacrificial material layer 1100 can include single-crystalline silicon, and the material of the semiconductor layer 1300 can include polycrystalline silicon and the like. The sacrificial material layer 1100 can not only provide mechanical support for the spacer layer 1200, the semiconductor layer 1300, and the initial stacked structure 1400' thereon, but also provide space for epitaxial growth of the subsequently formed epitaxial layer 1500. The semiconductor layer 1300 can provide space for epitaxial growth of the subsequently formed epitaxial layer.

[0041] Exemplarily, the material of the spacer layer 1200 can include silicon dioxide, silicon nitride, aluminum oxide, or other insulating materials, or a combination of the above insulating materials. In one embodiment of the present application, the material of the spacer layer 1200 can be silicon dioxide. The spacer layer 1200 can be used as a stop layer for subsequently removing the sacrificial material layer 1100. In addition, the spacer layer 1200 is located between the sacrificial material layer 1100 and the semiconductor layer 1300. Due to the material of the spacer layer 1200, epitaxial growth is difficult inside and outside the spacer layer 1200. Therefore, after the epitaxial layer 1500 is formed in the sacrificial material layer 1100 and the semiconductor layer 1300 subsequently, a groove 100 ( Figure 3 ) will be formed in the part of the spacer layer 1200 opposite to the epitaxial layer 1500. The groove 100 can be used as a removal path for subsequent removal processes.

[0042] Exemplarily, the sacrificial material layer 1100, the spacer layer 1200, the semiconductor layer 1300, and the initial stacked structure 1400' can be sequentially formed by thin film deposition processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0043] Exemplarily, an oxidation method can also be used to oxidize the sacrificial material layer 1100 to form the spacer layer 1200. Exemplarily, the semiconductor layer 1300 can also be formed by an epitaxial growth process. The epitaxial growth process can include, but is not limited to: vapor phase epitaxy (VPE), liquid phase epitaxy (LPE), molecular beam epitaxy (MPE), or any combination thereof.

[0044] Exemplarily, a dielectric layer 1410 and a sacrificial layer 1420 can be alternately stacked on the semiconductor layer 1300 to form an initial stacked structure 1400'. Exemplarily, the dielectric layer 1410 and the sacrificial layer 1420 can be sequentially stacked to form the initial stacked structure 1400' by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. It should be understood that the number and thickness of the dielectric layer 1410 and the sacrificial layer 1420 are not limited to Figure 2 the number and thickness shown in. Without departing from the concept of the present application, those skilled in the art can set any number and thickness of the dielectric layer 1410 and the sacrificial layer 1420 according to needs. Additionally, the thickness of the sacrificial layer 1420 can be greater than the thickness of the dielectric layer 1410. The materials of the dielectric layer 1410 and the sacrificial layer 1420 can be selected from suitable materials known in the art. For example, the material of the dielectric layer 1410 can include oxides such as silicon oxide, and the material of the sacrificial layer 1420 can include nitrides such as silicon nitride.

[0045] Exemplarily, forming the epitaxial layer 1500 within the sacrificial material layer 1100 can include: forming a channel hole 200 that penetrates the initial stacked structure 1400', the semiconductor layer 1300, and the spacer layer 1200 along the first direction X and extends into the sacrificial material layer 1100 ( Figure 2 ); and forming the epitaxial layer 1500 in the portions of the channel hole 200 that are located in the semiconductor layer 1300 and the sacrificial material layer 1100 ( Figure 3 ).

[0046] Exemplarily, as Figure 3 shown, the formed epitaxial layer 1500 can extend along the first direction X within the sacrificial material layer 1100 and the semiconductor layer 1300. Limited by the material of the spacer layer 1200, during the process of forming the epitaxial layer 1500 within the sacrificial material layer 1100 and the semiconductor layer 1300, a groove 100 can be formed in the portion of the spacer layer 1200 that is opposite to the epitaxial layer 1500.

[0047] Exemplarily, the channel hole 200 can be formed by, for example, a dry etching process or a combination of dry and wet etching processes; other manufacturing processes can also be performed, such as patterning processes including photolithography, cleaning, and chemical mechanical polishing, etc. The channel hole 200 can have a cylindrical or columnar shape extending in the first direction X in the initial stack structure 1400', semiconductor layer 1300, spacer layer 1200, and sacrificial material layer 1100.

[0048] As the number of stacked layers of the initial stack structure 1400' increases, the aspect ratio of the channel hole 200 penetrating the initial stack structure 1400' becomes larger and larger, and the depth difference of the channel hole 200 extending into the sacrificial material layer 1100 becomes larger and larger.

[0049] Exemplarily, the epitaxial layer 1500 can be formed by filling a part of the channel hole 200 with semiconductor material epitaxially grown from the sacrificial material layer 1100 and semiconductor layer 1300 via the channel hole 200. The material of the epitaxial layer 1500 can include silicon germanium (SiGe). For example, germanium can be added to the epitaxially grown silicon to form silicon germanium. The manufacturing processes for epitaxially growing the epitaxial layer 1500 can include but are not limited to: vapor phase epitaxy (VPE), liquid phase epitaxy (LPE), molecular beam epitaxy (MPE), or any combination thereof.

[0050] In this application, the material of the epitaxial layer 1500 includes silicon germanium, which can effectively achieve high selectivity growth, and thus is conducive to enabling the top surfaces of the multiple epitaxial layers 1500 formed by epitaxial growth via the multiple channel holes 200 to be substantially flush. In other words, the top surfaces of the multiple epitaxial layers 1500 extending to the semiconductor layer 1300 can be relatively flush. This is conducive to enabling the multiple channel structures 1700 subsequently formed on the top surface to have the same height, and thus is conducive to improving the conductivity and structural stability of the semiconductor structure.

[0051] In addition, in this application, by producing and forming the epitaxial layer 1500 on the side of the channel hole 200 away from the initial stack structure 1400' (i.e., the part where the channel hole 200 extends into the sacrificial material layer 1100 and semiconductor layer 1300), it is conducive to making the side of the channel hole 200 away from the stack structure a solid structure, and thus is conducive to improving the structural strength of the semiconductor structure and reducing the risk of deformation or collapse of the channel structure 1700 subsequently formed in the channel hole 200.

[0052] Exemplarily, as Figure 4As shown, the isolation layer 1600 can be formed on one side of the epitaxial layer 1500 via the channel hole 200. The material of the isolation layer 1600 can include silicon dioxide, silicon nitride, aluminum oxide, or other insulating materials, or a combination of the above insulating materials. In one embodiment of the present application, the material of the isolation layer 1600 can be silicon nitride or silicon oxide. The isolation layer 1600 can be used to provide electrical insulation between the epitaxial layer 1500 and the subsequently formed channel structure 1700.

[0053] Exemplarily, the isolation layer 1600 can be formed by a thin film deposition process such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof. Exemplarily, the epitaxial layer 1500 can also be oxidized by methods such as dry oxidation process, wet oxidation process, or in-situ steam oxidation process to form the isolation layer 1600.

[0054] In an exemplary embodiment of the present application, as Figure 5 shown, the channel structure 1700 extending along the first direction X to the isolation layer 1600 can be formed in the initial stack structure 1400' located on one side of the sacrificial material layer 1100, where the channel structure 1700 includes a functional layer 1710 extending along the first direction X and a channel layer 1720 located on the side of the functional layer 1710 away from the initial stack structure 1400'. Exemplarily, the channel structure 1700 can be formed on one side of the isolation layer 1600 via the channel hole 200. Specifically, the functional layer 1710 can be formed on the sidewall of the channel hole 200; and the channel layer 1720 extending along the first direction X can be formed on the side of the functional layer 1710 away from the initial stack structure 1400'.

[0055] Exemplarily, after the isolation layer 1600 is formed, the channel structure 1700 can be formed on the isolation layer 1600 by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. Specifically, the functional layer 1710 and the channel layer 1720 can be sequentially formed from the outside to the inside in the remaining space of the channel hole 200; and the channel filling dielectric layer 1730 and the channel plug (not shown) can be formed. It should be understood that the channel structure 1700 extends along the first direction X to the isolation layer 1600.

[0056] The functional layer 1710 can include a blocking layer 1740 formed on the inner wall of the channel hole 200 to block the outflow of charges, a charge trapping layer 1750 formed on the surface of the blocking layer 1740 to store charges during the operation of the semiconductor structure, and a tunneling layer 1760 formed on the surface of the charge trapping layer 1750.

[0057] The blocking layer 1740 may include one or more layers, and the one or more layers may include one or more materials. The materials for the blocking layer 1740 may include silicon oxide, silicon nitride, silicon oxynitride, high-k dielectric materials such as aluminum oxide or hafnium oxide, another wide-bandgap material, etc. The charge trapping layer 1750 may include one or more layers, and the one or more layers may include one or more materials. The materials for the charge trapping layer 1750 may include polysilicon, silicon nitride, silicon oxynitride, nanocrystalline silicon, another wide-bandgap material, etc. The tunneling layer 1760 may include one or more layers, and the one or more layers may include one or more materials. The materials for the tunneling layer 1760 may include silicon oxide, silicon nitride, silicon oxynitride, high-k dielectric materials such as aluminum oxide or hafnium oxide, another wide-bandgap material, etc. Exemplarily, the functional layer 1710 may include an oxide-nitride-oxide (ONO) structure. Of course, it should be understood that the functional layer 1710 may also have a structure different from the ONO configuration. For example, the functional layer 1710 may include a silicon oxide layer, a silicon nitride layer, and another silicon oxide layer.

[0058] The channel layer 1720 may include silicon, such as amorphous silicon, polysilicon, or single-crystalline silicon. The material of the channel layer 1720 includes but is not limited to P-type doped polysilicon. Specifically, a semiconductor material may be used to fill the channel holes 200 to form the channel layer 1720. The filling dielectric layer 1730 may include an oxide dielectric layer, such as silicon oxide, etc. Exemplarily, during the filling process, multiple insulating gaps may be formed in the filling dielectric layer 1730 by controlling the channel filling process to relieve the structural stress. The channel layer 1720 may be used to transport the required charges (electrons or holes). Exemplarily, the channel layer 1720 may be formed on the surface of the tunneling layer 1760 by a thin-film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0059] In addition, the channel structure 1700 further includes a channel plug formed at one end of the channel layer 1720 away from the semiconductor layer 1300 (which can be understood as the top end of the channel structure 1700). Specifically, the channel plug may be formed in the portion of the channel filling dielectric layer 1730 located at the top of the channel holes 200. The material of the channel plug may be selected to be the same as that of the channel layer 1720, such as N-type doped or P-type doped polysilicon, etc. The channel plug is connected to the channel layer 1720.

[0060] In the exemplary embodiment of the present application, as Figure 6As shown, after the formation of the channel structure 1700, the sacrificial layer 1420 can be replaced with the gate layer 1430 to form the stacked structure 1400, where the stacked structure 1400 can include dielectric layers 1410 and gate layers 1430 stacked alternately. The material of the gate layer 1430 can be a conductive material, such as tungsten metal, etc. Exemplarily, the sacrificial layer 1420 can be replaced with the gate layer 1430 via a gate replacement process. Specifically, a gate gap (not shown) can be formed through the initial stacked structure 1400'; then, the sacrificial layer 1420 can be removed via the gate gap, and a conductive material can be filled in the removed space to form the gate layer 1430. After the formation of the gate layer 1430, the gate gap can be filled to form a gate gap structure (not shown).

[0061] Figure 7 and Figure 8 For flipping the Figure 6 structure by 180° and then thinning it is a schematic structural diagram. Exemplarily, as Figure 8 shown, the sacrificial material layer 1100, the epitaxial layer 1500, and part of the functional layer 1710 can be removed to expose the channel layer 1720.

[0062] Exemplarily, the part of the sacrificial material layer 1100 and the epitaxial layer 1500 located in the sacrificial material layer 1100 can be removed to expose the groove 100 ( Figure 7 ); and through the groove 100, the part of the epitaxial layer 1500 located in the semiconductor layer 1300, the isolation layer 1600, and part of the functional layer 1710 can be removed to expose the channel layer 1720 ( Figure 8 ).

[0063] Exemplarily, as Figure 7 shown, the part of the sacrificial material layer 1100 and the epitaxial layer 1500 located in the sacrificial material layer 1100 can be removed from one side of the sacrificial material layer 1100 by a planarization process to expose the spacer layer 1200 and the groove 100. The spacer layer 1200 can be used as a stop layer for removing the sacrificial material layer 1100. For example, the Chemical Mechanical Polishing (CMP) process can be used to remove the part of the sacrificial material layer 1100 and the epitaxial layer 1500 located in the sacrificial material layer 1100 to expose the spacer layer 1200 and the groove 100.

[0064] Exemplarily, as Figure 8As shown, the groove 100 can serve as a removal path for removing the portion of the epitaxial layer 1500 located in the semiconductor layer 1300, the isolation layer 1600, and a portion of the functional layer 1710. Exemplarily, processes such as dry etching can be used to remove, via the groove 100, the portion of the epitaxial layer 1500 located in the semiconductor layer 1300, the isolation layer 1600, and a portion of the functional layer 1710 until the channel layer 1720 is exposed.

[0065] In the present application, a planarization process can be used to remove the sacrificial material layer 1100 and the portion of the epitaxial layer 1500 located in the sacrificial material layer 1100 until the spacer layer 1200 and the groove 100 are exposed; then, processes such as dry etching can be used to remove, via the groove 100, the portion of the epitaxial layer 1500 located in the semiconductor layer 1300, the isolation layer 1600, and a portion of the functional layer 1710 until the channel layer 1720 is exposed. It can be seen that the present application can expose the channel layer 1720 through fewer and simpler removal processes, which is beneficial for reducing process steps and production costs. In addition, by exposing the channel layer 1720 through the groove 100 in the present application, the exposed surface of the channel layer 1720 can be made concave, reducing the risk of damage to the exposed surface. Using processes such as dry etching to expose the channel layer 1720 in the present application is beneficial for increasing the selectivity, which in turn is beneficial for improving the flatness of the exposed surface of the channel layer 1720, and further beneficial for improving the overall performance of the semiconductor structure.

[0066] In an exemplary embodiment of the present application, as Figure 9 shown, a conductive layer 1800 covering the channel layer 1720 can be formed, where the conductive layer 1800 protrudes towards the channel layer 1820. In other words, a portion of the conductive layer 1800 extends along the stacking direction Y of the stacked structure 1400 to the channel layer 1820. It should be understood that since the exposed surface of the channel layer 1720 is concave, the formed conductive layer 1800 protrudes towards the channel layer 1820.

[0067] Exemplarily, a conductive material can be filled in the concave gap, for example, by a deposition process, so that the conductive layer 1800 can be formed at the end of the channel layer 1720 close to the semiconductor layer 1300, realizing the connection between the conductive layer 1800 and the channel layers 1720 of multiple channel structures 1700. Exemplarily, a planarization process, such as a chemical mechanical polishing (CMP) process, can be used to perform planarization on the formed conductive layer 1800. The material of the conductive layer 1800 can be a conductive material, such as polysilicon or doped polysilicon, etc. The conductive layer 1800 can be used as a common source structure for multiple channel structures 1700.

[0068] Figure 9 is a schematic structural diagram of a semiconductor structure according to an exemplary embodiment of the present application.

[0069] The semiconductor structure may include a stacked structure 1400, a channel structure 1700, and a conductive layer 1800.

[0070] The stacked structure 1400 may include dielectric layers 1410 and gate layers 1430 that are alternately stacked. It should be understood that the number and thickness of the dielectric layers 1410 and gate layers 1430 are not limited to Figure 9 the number and thickness shown therein. Those skilled in the art can set any number and thickness of the dielectric layers 1410 and gate layers 1430 as needed without departing from the concept of the present application. Additionally, the thickness of the gate layer 1430 may be greater than the thickness of the dielectric layer 1410. The materials of the dielectric layer 1410 and the gate layer 1430 can be selected from suitable materials known in the art. For example, the material of the dielectric layer 1410 may include oxides such as silicon oxide, and the material of the gate layer 1430 may include conductive materials such as tungsten metal.

[0071] The channel structure 1700 may extend in a first direction X in the stacked structure 1400. The channel structure 1700 may include a functional layer 1710 extending in the first direction X and a channel layer 1720 located on a side of the functional layer 1710 away from the stacked structure 1400 and extending in the first direction X. Exemplarily, the channel layer 1720 may have a U-shaped structure and may be in contact with the conductive layer 1800. The functional layer 1710 may be located on both sidewalls of the channel layer 1720.

[0072] The functional layer 1710 may include a blocking layer 1740 extending in the first direction X to block charge outflow, a charge trapping layer 1750 formed on the surface of the blocking layer 1740 to store charge during the operation of the semiconductor structure, and a tunneling layer 1760 formed on the surface of the charge trapping layer 1750.

[0073] The blocking layer 1740 may include one or more layers, and the one or more layers may include one or more materials. The materials for the blocking layer 1740 may include silicon oxide, silicon nitride, silicon oxynitride, high-k dielectric materials such as aluminum oxide or hafnium oxide, another wide-bandgap material, etc. The charge trapping layer 1750 may include one or more layers, and the one or more layers may include one or more materials. The materials for the charge trapping layer 1750 may include polysilicon, silicon nitride, silicon oxynitride, nanocrystalline silicon, another wide-bandgap material, etc. The tunneling layer 1760 may include one or more layers, and the one or more layers may include one or more materials. The materials for the tunneling layer 1760 may include silicon oxide, silicon nitride, silicon oxynitride, high-k dielectric materials such as aluminum oxide or hafnium oxide, another wide-bandgap material, etc. Exemplarily, the functional layer 1710 may include an oxide-nitride-oxide (ONO) structure. Of course, it should be understood that the functional layer 1710 may also have a structure different from the ONO configuration. For example, the functional layer 1710 may include a silicon oxide layer, a silicon nitride layer, and another silicon oxide layer. The channel layer 1720 may include silicon, such as amorphous silicon, polysilicon, or single-crystalline silicon. The material of the channel layer 1720 includes but is not limited to P-type doped polysilicon.

[0074] Exemplarily, the channel structure 1700 may further include a channel filling dielectric layer 1730 located on a side of the channel layer 1720 away from the functional layer 1710 and extending along a first direction X. In addition, the channel structure 1700 may further include a channel plug (not shown) connected to the channel layer 1720.

[0075] The filling dielectric layer 1730 may include an oxide dielectric layer, such as silicon oxide, etc. The material of the channel plug may be selected to be the same as that of the channel layer 1720, such as N-type doped or P-type doped polysilicon, etc. The channel plug is connected to the channel layer 1720. Exemplarily, a plurality of insulating gaps may be formed in the filling dielectric layer 1730 to relieve structural stress. The channel layer 1720 may be used to transport the required charges (electrons or holes).

[0076] Exemplarily, a plurality of channel structures 1700 may extend to the same height in the first direction X in the stacked structure 1400. In other words, a plurality of channel layers 1720 may extend to the same height in the first direction X in the stacked structure 1400. The plurality of channel structures 1700 provided in the present application having the same height is beneficial to improving the conductive performance and structural stability of the semiconductor structure.

[0077] The conductive layer 1800 may be located on one side of the stacked structure 1400, and a part of the conductive layer 1800 may extend along the stacking direction Y of the stacked structure 1400 to the channel structure 1700, where the first direction X may be a direction opposite to the stacking direction Y.

[0078] Exemplarily, the conductive layer 1800 may extend to the channel layer 1720 in the channel structure 1700. That is, the conductive layer 1800 may be located on one side of the stacked structure 1400 and protrude towards the channel layer 1820. Exemplarily, the material of the conductive layer 1800 may be selected from conductive materials such as polysilicon or doped polysilicon. The conductive layer 1800 may be used as a common source structure for a plurality of channel structures 1700.

[0079] The plurality of channel structures 1700 provided in the present application have the same height, which is beneficial to making the plurality of channel structures 1700 have high structural strength and not easily prone to risks such as deformation or collapse, and is also beneficial to improving the conductive performance and structural stability of the semiconductor structure. In addition, the plurality of channel layers 1720 provided in the present application can extend to the same height and the conductive layer 1800 protrudes towards the channel layer 1820, which is beneficial to improving the flatness of the surface of the plurality of channel layers 1720, and thus beneficial to improving the overall performance of the semiconductor structure.

[0080] In an exemplary embodiment of the present application, the semiconductor structure may further include a spacer layer 1200. The spacer layer 1200 may be located between the conductive layer 1800 and the stacked structure 1400 along the first direction X, and a part of the conductive layer 1800 may penetrate through the spacer layer 1200 and extend to the channel structure 1700.

[0081] Exemplarily, the material of the spacer layer 1200 may include silicon dioxide, silicon nitride, aluminum oxide or other insulating materials, or a combination of the above insulating materials. In an embodiment of the present application, the material of the spacer layer 1200 may be silicon dioxide.

[0082] In an exemplary embodiment of the present application, the semiconductor structure may further include a semiconductor layer 1300. The semiconductor layer 1300 may be located between the spacer layer 1200 and the stacked structure 1400 along the first direction X, and a part of the conductive layer 1800 may penetrate through the spacer layer 1200 and the semiconductor layer 1300 and extend to the channel structure 1700.

[0083] Exemplarily, the material of the semiconductor layer 1300 may include at least one of polysilicon semiconductor materials or other semiconductor materials known in the art. For example, the material of the semiconductor layer 1300 may include polysilicon. Of course, it should be understood that in another embodiment, the material of the semiconductor layer 1300 may include elemental semiconductor materials, such as single crystal silicon.

[0084] Since the content and structure involved in describing the method 1000 for manufacturing a semiconductor structure above may be fully or partially applicable to the semiconductor structure described here, the related or similar content will not be repeated here.

[0085] Although exemplary structures and fabrication methods of semiconductor structures are described herein, it is understood that one or more features may be omitted, substituted, or added from the fabrication methods of the semiconductor structures. Additionally, the exemplified layers and their materials are merely exemplary.

[0086] Figure 10 is a schematic block diagram of a memory according to an exemplary embodiment of the present application. The memory 2000 may include a memory cell array 2100 and a peripheral circuit 2200.

[0087] The memory cell array 2100 and the peripheral circuit 2200 may be separately formed on different substrates and then bonded to form the memory 2000.

[0088] The peripheral circuit 2200 may be coupled to the memory cell array 2100. The peripheral circuit 2200 (also referred to as a control and sensing circuit) may include any suitable digital, analog, and / or mixed-signal circuits for facilitating the operation of the memory cell array 2100. For example, the peripheral circuit 2200 may include a page buffer, a decoder (e.g., a row decoder and a column decoder), a sense amplifier, a driver (e.g., a word line driver), an input / output (I / O) circuit, a charge pump, a voltage source or generator, a current or voltage reference, any part of the above functional circuits (e.g., a sub-circuit), or any active or passive components of the circuit (e.g., a transistor, a diode, a resistor, or a capacitor).

[0089] The memory cell array 2100 may include the semiconductor structures described in any embodiment of the present application. For example, the memory cell array 2100 may include a plurality of memory cells such as NAND memory cells. The NAND memory cells are capable of holding continuous analog values, e.g., voltage or charge, which depends on the number of electrons captured within the memory cell region. Each memory cell may be a floating-gate type memory cell including a floating-gate transistor, or may be a charge-trapping type memory cell including a charge-trapping transistor.

[0090] Figure 11 is a block diagram of a system 10 having a storage system 12 according to an exemplary embodiment of the present application.

[0091] The system 10 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, an in-vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device (the electronic device having a storage system 12 therein). As Figure 11As shown, the system 10 may include a host 18 and a storage system 12. The storage system 12 has one or more memories such as a three-dimensional memory 14 and a controller 17. The host 18 may be a processor of an electronic device, such as a central processing unit (CPU), or may be a system-on-chip (SoC), such as an application processor (AP). The host 18 may be configured to send or receive data to and from the three-dimensional memory 14.

[0092] The three-dimensional memory 14 may include semiconductor structures described in any embodiment of the present application. According to some embodiments, the controller 17 is coupled to the three-dimensional memory 14 and the host 18 and is configured to control the three-dimensional memory 14. The controller 17 may manage data stored in the three-dimensional memory 14 and communicate with the host 18. In some embodiments, the controller 17 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compactFlash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, the controller 17 is designed to operate in a high duty cycle environment, such as a solid state drive (SSD) or an embedded multi-media-card (eMMC) used as a data storage device for a mobile device, and enterprise storage arrays, where the mobile device is such as a smart phone, a tablet computer, a laptop computer, etc. The controller 17 may be configured to control operations of the three-dimensional memory 14, such as read, erase, and program operations. The controller 17 may also be configured to manage various functions related to data stored in or to be stored in the three-dimensional memory 14, the various functions including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the controller 17 is further configured to process an error correction code (ECC) related to data read from or written to the three-dimensional memory 14. Any other suitable functions may also be performed by the controller 17, for example, formatting the three-dimensional memory 14. The controller 17 may communicate with external devices (e.g., the host 18) according to a specific communication protocol. For example, the controller 17 may communicate with external devices through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a high-speed PCI (PCI-express, PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer system interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, etc.

[0093] The controller 17 and one or more three-dimensional memories 14 may be integrated into various types of memory systems, for example, included in the same package (such as a universal flash storage (UFS) package or an eMMC package). That is, the memory system 12 may be implemented and packaged into different types of end electronic products. In as Figure 12AIn one example shown, the controller 17 and the single three-dimensional memory 14 can be integrated into the memory card 22. The memory card 22 can include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a Memory Stick, a Multimedia Card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, etc. The memory card 22 can further include a memory card connector 24 that couples the memory card 22 to a host (e.g., Figure 11 the host 18 in Figure 12B ). In another example shown in Figure 11 , the controller 17 and multiple three-dimensional memories 14 can be integrated into the SSD 26. The SSD 26 can further include an SSD connector 28 that couples the SSD 26 to a host (e.g., Figure 11 the host 18 in

[0094] ). In some embodiments, the storage capacity and / or operating speed of the SSD 26 are higher than those of the memory card 22.

[0094] The above description is only for the preferred embodiments of the present application and the explanation of the applied technical principles. Those skilled in the art should understand that the scope of disclosure involved in the present application is not limited to the technical solutions formed by the specific combination of the above technical features, and should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept. For example, the technical solutions formed by mutually replacing the above features with the (but not limited to) technical features with similar functions disclosed in the present application.

Claims

1. A semiconductor structure, wherein, The semiconductor structure includes: a stacked structure; a channel structure extending in a first direction in the stacked structure; and a conductive layer located on one side of the stacked structure, wherein a part of the conductive layer extends in the stacking direction of the stacked structure to the channel structure; wherein the first direction is a direction opposite to the stacking direction.

2. The semiconductor structure according to claim 1, wherein, The semiconductor structure further includes: a spacer layer located between the conductive layer and the stacked structure along the first direction, wherein a part of the conductive layer penetrates through the spacer layer and extends to the channel structure.

3. The semiconductor structure according to claim 2, wherein, The semiconductor structure further includes: a semiconductor layer located between the spacer layer and the stacked structure along the first direction, wherein a part of the conductive layer penetrates through the spacer layer and the semiconductor layer and extends to the channel structure.

4. The semiconductor structure according to claim 1, wherein, The channel structure includes: a functional layer extending in the first direction; and a channel layer located on a side of the functional layer away from the stacked structure and extending in the first direction; wherein the channel layer is in contact with the conductive layer.

5. The semiconductor structure according to claim 1, wherein, A plurality of the channel structures extend to the same height in the stacked structure in the first direction.

6. The semiconductor structure according to claim 3, wherein, The material of the spacer layer includes an insulating material.

7. The semiconductor structure according to any one of claims 1-6, wherein, The stacked structure includes alternately stacked dielectric layers and gate layers.

8. A method of manufacturing a semiconductor structure, wherein, The method includes: forming an epitaxial layer in a sacrificial material layer; forming a channel structure extending in a first direction to the epitaxial layer in an initial stacked structure located on one side of the sacrificial material layer, wherein the channel structure includes a functional layer extending in the first direction and a channel layer located on a side of the functional layer away from the initial stacked structure; removing the sacrificial material layer, the epitaxial layer, and a part of the functional layer to expose the channel layer; and forming a conductive layer covering the channel layer, wherein the conductive layer bulges towards the channel layer.

9. The method according to claim 8, wherein The semiconductor structure includes a spacer layer and a semiconductor layer adjacent to each other along the first direction, wherein the spacer layer is located between the sacrificial material layer and the semiconductor layer, The forming an epitaxial layer in the sacrificial material layer includes: forming an epitaxial layer extending in the first direction in the sacrificial material layer and the semiconductor layer, wherein a part of the spacer layer opposite to the epitaxial layer forms a groove.

10. The method according to claim 9, wherein, The forming an epitaxial layer extending in the first direction in the sacrificial material layer and the semiconductor layer includes: forming a channel hole extending in the first direction through the initial stacked structure, the semiconductor layer, and the spacer layer and extending to the sacrificial material layer; and forming the epitaxial layer in a part of the channel hole located in the semiconductor layer and the sacrificial material layer.

11. The method according to claim 10, wherein, The method further includes: forming an isolation layer on one side of the epitaxial layer via the channel hole.

12. The method according to claim 11, wherein, Removing the sacrificial material layer, the epitaxial layer, and a part of the functional layer to expose the channel layer includes: removing a part of the sacrificial material layer and the epitaxial layer located in the sacrificial material layer to expose the groove; and removing a part of the epitaxial layer located in the semiconductor layer, the isolation layer, and a part of the functional layer via the groove to expose the channel layer.

13. The method according to claim 11, wherein, Forming a channel structure extending along a first direction to the epitaxial layer in an initial stacked structure on one side of the sacrificial material layer, comprising: Forming the channel structure on one side of the isolation layer via the channel holes.

14. The method according to any one of claims 8-13, wherein, The initial stacked structure includes dielectric layers and sacrificial layers stacked alternately, wherein the method further comprises: After forming the channel structure, replacing the sacrificial layer with a gate layer to form a stacked structure.

15. The method according to claim 13, wherein, Forming the channel structure on one side of the isolation layer via the channel holes, comprising: Forming a functional layer on the sidewalls of the channel holes; and Forming a channel layer extending along the first direction on the side of the functional layer away from the initial stacked structure.

16. A memory, wherein, Comprising: A memory cell array including the semiconductor structure according to any one of claims 1 to 7; And A peripheral circuit coupled to the memory cell array.

17. A storage system, wherein, Comprising: Including the memory according to claim 16; And A controller coupled to the memory for controlling the memory to store data.

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