Semiconductor memory device and electronic system including the same

Abstract

A semiconductor memory device and an electronic system including the same are provided. The semiconductor memory device includes: a source layer; a stacked structure on the source layer including a plurality of gate electrodes sequentially stacked spaced apart from each other; a channel structure extending in the first direction, penetrating the gate electrode, and connected to the source layer; a cutting pattern extending in a second direction crossing the first direction and cutting the stacked structure; a cell wiring structure on the stack structure; a channel contact between the stack structure and the cell wiring structure, connecting the channel structure and the cell wiring structure; and a line pattern between the stack structure and the cell wiring structure, extending in the second direction, and overlapping the cutting pattern in the first direction, in which the line pattern is at the same level as the channel contact.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor memory device, a method of manufacturing a semiconductor memory device, and an electronic system including the semiconductor memory device. More particularly, the present disclosure relates to a semiconductor memory device including memory cells arranged in a three-dimensional manner, a method of manufacturing a semiconductor memory device, and an electronic system including the semiconductor memory device. Background Art

[0002] As semiconductor memory devices capable of storing a large amount of data are required in electronic systems, methods of increasing the data storage capacity of semiconductor memory devices are being studied. One of the methods of increasing the data storage capacity of semiconductor memory devices proposes a semiconductor memory device including memory cells arranged in a three-dimensional manner instead of a two-dimensional manner. Summary of the Invention

[0003] Aspects of the present disclosure provide a semiconductor memory device having improved reliability.

[0004] Aspects of the present disclosure also provide a method of manufacturing a semiconductor memory device, the method being capable of producing a semiconductor memory device having improved reliability.

[0005] Aspects of the present invention also provide an electronic system including a semiconductor memory device having improved reliability.

[0006] According to some aspects of the present disclosure, there is provided a semiconductor memory device including: a source layer; a stacked structure on the source layer, including a plurality of gate electrodes sequentially stacked with spaces therebetween; a channel structure extending through the gate electrodes in a first direction and connected to the source layer; a cutting pattern extending in a second direction intersecting the first direction and cutting the stacked structure; a cell wiring structure on the stacked structure; a channel contact connecting the channel structure and the cell wiring structure between the stacked structure and the cell wiring structure; and a line pattern extending in the second direction between the stacked structure and the cell wiring structure and overlapping the cutting pattern in the first direction, the line pattern being at the same level as the channel contact.

[0007] According to some aspects of the present disclosure, a semiconductor memory device is provided. The semiconductor memory device includes: a peripheral circuit structure including a peripheral circuit substrate and peripheral circuit elements on the peripheral circuit substrate; and a memory cell structure stacked on the peripheral circuit structure. The memory cell structure includes: a source layer including a first surface facing the peripheral circuit structure and a second surface opposite to the first surface; a stacked structure on the source layer including a plurality of gate electrodes sequentially stacked with spaces therebetween; a channel structure extending in a first direction through the gate electrodes and connected to the source layer; a cutting pattern extending in a second direction intersecting the first direction and cutting the stacked structure; a wire extending in a third direction intersecting the first and second directions and between the stacked structure and the peripheral circuit structure; a channel contact connecting the channel structure and the wire and between the stacked structure and the wire; and a line pattern extending in the second direction, between the stacked structure and the wire, and overlapping the cutting pattern in the first direction.

[0008] According to some example embodiments of the present disclosure, an electronic system is provided. The electronic system includes: a main substrate; a semiconductor memory device on the main substrate including a peripheral circuit structure and a sequentially stacked memory cell structure; and a controller on the main substrate electrically connected to the semiconductor memory device. The memory cell structure includes: a source layer including a first surface facing the peripheral circuit structure and a second surface opposite to the first surface; a stacked structure on the source layer including a plurality of gate electrodes sequentially stacked with spaces therebetween; a channel structure extending in a first direction, penetrating the gate electrodes and connected to the source layer; a cutting pattern extending in a second direction intersecting the first direction and cutting the stacked structure; a wire extending in a third direction intersecting the first and second directions and between the stacked structure and the peripheral circuit structure; a channel contact connecting the channel structure and the wire and between the stacked structure and the wire; and a line pattern extending in the second direction, between the stacked structure and the wire, and overlapping the cutting pattern in the first direction.

[0009] It should be noted that the effects of the present disclosure are not limited to those described above, and other effects of the present disclosure will be clear from the following description.

[0010] However, the aspects of the present disclosure are not limited to those set forth herein. The above and other aspects of the present disclosure will become more apparent to those of ordinary skill in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure given below. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other aspects and features of the present disclosure will become more apparent by referring to the example embodiments of the present disclosure described in detail with reference to the accompanying drawings.

[0012] Figure 1It is a block diagram for explaining a semiconductor memory device according to some example embodiments of the present disclosure.

[0013] Figure 2 It is a circuit diagram for explaining a semiconductor memory device according to some example embodiments of the present disclosure.

[0014] Figure 3 It is a layout diagram for explaining a semiconductor memory device according to some example embodiments of the present disclosure.

[0015] Figure 4 It is a Figure 3 cross-sectional view taken along line A-A.

[0016] Figure 5 It is a Figure 4 magnified cross-sectional view of region Z1.

[0017] Figure 6 It is a Figure 3 magnified cross-sectional view of region R.

[0018] Figure 7 It is a Figure 6 cross-sectional view taken along line B-B.

[0019] Figure 8 It is a Figure 7 magnified cross-sectional view of region Z2.

[0020] Figures 9 to 11 It is a cross-sectional view for explaining a semiconductor memory device according to some example embodiments of the present disclosure.

[0021] Figure 12 It is a layout diagram for explaining a semiconductor memory device according to some example embodiments of the present disclosure.

[0022] Figure 13 It is a layout diagram for explaining a semiconductor memory device according to some example embodiments of the present disclosure.

[0023] Figure 14 It is a Figure 13 cross-sectional view taken along line C-C.

[0024] Figure 15 It is a Figure 14 magnified cross-sectional view of region Z3.

[0025] Figures 16 to 31 It is a cross-sectional view showing intermediate steps of a method for manufacturing a semiconductor memory device according to some example embodiments of the present disclosure.

[0026] Figures 32 to 42It is a cross-sectional view showing an intermediate step of a method of manufacturing a semiconductor memory device according to some example embodiments of the present disclosure.

[0027] Figure 43 It is a block diagram for explaining an electronic system according to some example embodiments of the present disclosure.

[0028] Figure 44 It is a perspective view for explaining an electronic system according to some example embodiments of the present disclosure.

[0029] Figure 45 It is along Figure 44 a cross-sectional view taken along line I-I. Detailed Description

[0030] In this specification, although terms such as "first", "second", etc. are used to describe various elements or components, these elements or components are not limited by these terms. These terms are only used to distinguish one element or component from another. Therefore, the first element or component mentioned below may also be the second element or component within the spirit of the disclosed technology.

[0031] Hereinafter, a semiconductor memory device according to some example embodiments of the present disclosure will be described with reference to Figures 1 to 15 a semiconductor memory device according to some example embodiments of the present disclosure will be described.

[0032] Figure 1 It is a block diagram for explaining a semiconductor memory device according to some example embodiments of the present disclosure.

[0033] Referring to Figure 1 , the memory cell array 20 of the semiconductor memory device 10 may include a plurality of memory cell blocks BLK1 to BLKn. Each of the memory cell blocks BLK1 to BLKn may include a plurality of memory cells. The memory cell array 20 may be connected to the peripheral circuit 30 through bit lines BL, word lines WL, one or more string selection lines SSL, and one or more ground selection lines GSL. For example, the memory cell blocks BLK1 to BLKn may be connected to the row decoder 33 through word lines WL, string selection lines SSL, and ground selection lines GSL. In addition, the memory cell blocks BLK1 to BLKn may be connected to the page buffer 35 through bit lines BL.

[0034] The peripheral circuit 30 can receive an address ADDR, a command CMD, and a control signal CTRL from outside the semiconductor memory device 10, and can exchange data DATA with an external device outside the semiconductor memory device 10. The peripheral circuit 30 can include a control logic 37, a row decoder 33, and a page buffer 35. Although not shown, the peripheral circuit 30 may further include various sub-circuits, such as an input / output circuit, a voltage generation circuit that generates various voltages required for the operation of the semiconductor memory device 10, and an error correction circuit that corrects errors in the data DATA read from the memory cell array 20.

[0035] The control logic 37 can be connected to the row decoder 33, the page buffer 35, the input / output circuit, and the voltage generation circuit. The control logic 37 can control the overall operation of the semiconductor memory device 10. The control logic 37 can generate various internal control signals for use in the semiconductor memory device 10 in response to the control signal CTRL. For example, during a memory operation (such as programming or erasing), the control logic 37 can adjust the voltage levels to be provided to the word line WL and the bit line BL.

[0036] In response to the address ADDR, the row decoder 33 can select at least one of the memory cell blocks BLK1 to BLKn, and can select at least one word line WL, at least one string selection line SSL, and at least one ground selection line GSL according to the selected memory cell block(s). In addition, the row decoder 33 can transfer a voltage to the word line WL of the selected memory cell block(s) to perform a memory operation.

[0037] The page buffer 35 can be connected to the memory cell array 20 through the bit line BL. The page buffer 35 can operate as a write driver or a sense amplifier. For example, during a programming operation, the page buffer 35 operates as a write driver and applies a voltage corresponding to the data DATA to be stored in the memory cell array 20 to the bit line BL. Conversely, during a read operation, the page buffer 35 operates as a sense amplifier and detects the data DATA stored in the memory cell array 20.

[0038] Figure 2 is a circuit diagram for explaining a semiconductor memory device according to some example embodiments of the present disclosure.

[0039] Referring to Figure 2 According to some example embodiments of the present disclosure, a memory cell array of a semiconductor memory device (e.g., Figure 1 the memory cell array 20) includes a common source line CSL, a plurality of bit lines BL, and a plurality of cell strings CSTR.

[0040] The bit lines BL can be arranged two-dimensionally in a plane including a first direction X and a second direction Y. For example, the bit lines BL can extend in the second direction Y and can be spaced apart from each other along the first direction X. The cell strings CSTR can be connected in parallel to the bit lines BL. The cell strings CSTR can be commonly connected to a common source line CSL. That is, the cell strings CSTR can be disposed between the bit lines BL and the common source line CSL.

[0041] Each of the cell strings CSTR can include a ground selection transistor GST connected to the common source line CSL, a string selection transistor SST connected to the bit line BL, and a plurality of memory cell transistors MCT disposed between the ground selection transistor GST and the string selection transistor SST. Each of the memory cell transistors MCT can include a data storage element. The ground selection transistor GST, the string selection transistor SST, and the memory cell transistors MCT can be connected in series in a third direction Z intersecting the first direction X and the second direction Y.

[0042] The common source line CSL can be commonly connected to the source of the ground selection transistor GST. In addition, a ground selection line GSL, a plurality of word lines (WL11 to WL1n and WL21 to WL2m), and a string selection line SSL can be disposed between the common source line CSL and the bit line BL. The ground selection line GSL can be used as a gate electrode of the ground selection transistor GST, the word lines WL1 to WLn can be used as gate electrodes of the memory cell transistors MCT, and the string selection line SSL can be used as a gate electrode of the string selection transistor SST.

[0043] Figure 3 is a layout diagram for explaining a semiconductor memory device according to some example embodiments of the present disclosure. Figure 4 is along Figure 3 a cross-sectional view taken along line A-A of Figure 5 is Figure 4 an enlarged cross-sectional view of region Z1 of Figure 6 is Figure 3 an enlarged cross-sectional view of region R of Figure 7 is along Figure 6 a cross-sectional view taken along line B-B of Figure 8 is Figure 7 an enlarged cross-sectional view of region Z2 of

[0044] Referring to Figures 3 to 8 , a semiconductor memory device according to some example embodiments of the present disclosure includes a memory cell structure CELL, a peripheral circuit structure PERI, and a conductive pad 390.

[0045] The memory cell structure CELL can include a cell array region CA, an extended region EA, and an external region PA.

[0046] In the cell array region CA, a memory cell array including a plurality of memory cells may be formed (e.g., Figure 1 the memory cell array 20). For example, the source layer 102, the channel structure CH, the gate electrodes (112 and 117), and the bit line BL, which will be described later, may be disposed in the cell array region CA.

[0047] The extension region EA may be disposed around the cell array region CA. For example, the extension region EA may be adjacent to the cell array region CA in the first direction X. In each of the extension regions EA, the gate electrodes (112 and 117), which will be described later, may be stacked in a stepped manner.

[0048] The outer region PA may be an enclosing region surrounding the cell array region CA and the extension region EA. For example, the outer region PA may be adjacent to the cell array region CA and / or the extension region EA in the first direction X and / or the second direction Y. The conductive pad 390, which will be described later, may be disposed in the outer region PA.

[0049] The memory cell structure CELL may include a source layer 102, an insulating substrate 104, a stacked structure (SS1 and SS2), a channel structure CH, a cut pattern WC, a gate contact 162, a source contact 164, through vias 166, a channel contact CC, a blocking pattern BC, a first contact pattern 170, and a cell wiring structure 180.

[0050] The source layer 102 may include a conductive material (such as doped polysilicon, metal, or metal silicide) or a film of a conductive material, but the present disclosure is not limited thereto. For example, the source layer 102 may include polysilicon doped with an n-type impurity (such as phosphorus (P) or arsenic (As)). The source layer 102 may be configured as a common source line for a semiconductor memory device according to some example embodiments of the present disclosure (e.g., Figure 2 the common source line CSL).

[0051] The source layer 102 may include a first surface 102a and a second surface 102b that face each other. The first surface 102a may also be referred to as the front side of the source layer 102, and the second surface 102b may also be referred to as the back side of the source layer 102.

[0052] The insulating substrate 104 may be formed near the source layer 102. The insulating substrate 104 may form an insulating region around the source layer 102 across the cell array region CA and / or the outer region PA. The insulating substrate 104 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide, but the present disclosure is not limited thereto.

[0053] Stacked structures (SS1 and SS2) may be formed on a first surface 102a of a source layer 102. The stacked structures (SS1 and SS2) may include a plurality of gate electrodes (112 and 117) and a plurality of molded insulating films (110 and 115) stacked on the source layer 102 together with the gate electrodes (112 and 117). Each of the gate electrodes (112 and 117) and the molded insulating films (110 and 115) may have a layered structure extending in a horizontal direction (e.g., a first direction X or a second direction Y). The gate electrodes (112 and 117) may be sequentially stacked by being spaced apart from each other by the molded insulating films (110 and 115).

[0054] The gate electrodes (112 and 117) in the extension region EA may be stacked on the source layer 102 in a stepped manner. For example, in the extension region EA, the length of the gate electrodes (112 and 117) extending in the first direction X may decrease away from the source layer 102.

[0055] In some example embodiments, the stacked structures (SS1 and SS2) may include a plurality of stacked elements (here, for example, a first stacked element SS1 and a second stacked element SS2) sequentially stacked on the source layer 102. The stacked structures (SS1 and SS2) are shown to include two stacked elements, but the present disclosure is not limited thereto. Optionally, the stacked structures (SS1 and SS2) may include three or more stacked elements.

[0056] The first stacked element SS1 may include a first molded insulating film 110 and a first gate electrode 112 alternately stacked on the source layer 102. In some example embodiments, the first gate electrode 112 may include one or more ground selection lines (e.g., Figure 2 the ground selection line GSL) and a plurality of first word lines (e.g., Figure 2 the word lines WL11 to WL1n) sequentially stacked on the source layer 102. The number and shape of the first molded insulating film 110 and the first gate electrode 112 are only examples and are not particularly limited.

[0057] A first interlayer insulating film 141 covering the first stacked element SS1 may be formed on the source layer 102 and the insulating substrate 104. The first interlayer insulating film 141 may include, for example, at least one of silicon oxide, silicon oxynitride, and a low-k material having a dielectric constant smaller than that of silicon oxide, but the present disclosure is not limited thereto.

[0058] The second stacked element SS2 may include a second molded insulating film 115 and a second gate electrode 117 alternately stacked on the first stacked element SS1. In some example embodiments, the second gate electrode 117 may include a plurality of second word lines (e.g., Figure 2word lines WL21 to WL2m) and one or more string selection lines (e.g., Figure 2 string selection line SSL) of. The number and shape of the second molded insulating film 115 and the second gate electrode 117 are merely examples and are not particularly limited.

[0059] The interlayer insulating film 142 covering the second stack SS2 may be formed on the first interlayer insulating film 141. The second interlayer insulating film 142 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low-k material having a dielectric constant smaller than that of silicon oxide, but the present disclosure is not limited thereto.

[0060] The gate electrodes (112 and 117) may include a conductive material, for example, a metal (such as tungsten (W), molybdenum (Mo), ruthenium (Ru), cobalt (Co), or nickel (Ni)) or a semiconductor material (such as silicon (Si)), but the present disclosure is not limited thereto. For example, the gate electrodes (112 and 117) may include at least one of W, Mo, and Ru. In another example, the gate electrodes (112 and 117) may include polysilicon.

[0061] The molded insulating films (110 and 115) may include, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride, but the present disclosure is not limited thereto. For example, the molded insulating films (110 and 115) may include silicon oxide.

[0062] The channel structure CH may be disposed in the cell array region CA. The channel structure CH may be formed on the source layer 102. The channel structure CH may extend in a third direction Z that intersects the first direction X and the second direction Y, and may thereby penetrate the stack structures (SS1 and SS2). For example, the channel structure CH may be in the shape of a pillar (e.g., a cylinder) extending in the third direction Z. The channel structure CH may intersect the gate electrodes (112 and 117).

[0063] The channel structure CH may be electrically connected to the source layer 102. For example, the upper surface of the channel structure CH may be formed coplanar with the first surface 102a of the source layer 102 or higher than the first surface 102a of the source layer 102.

[0064] In some example embodiments, the channel structure CH may be arranged in a zigzag manner. As Figure 3 and Figure 6 shown, the channel structure CH may be staggered in the first direction X and the second direction Y. According to some example embodiments of the present disclosure, the channel structure CH may enhance the integration density of the semiconductor memory device. The number and arrangement of the channel structure CH are merely examples and are not particularly limited.

[0065] In some example embodiments, each of the channel structures CH may have a step difference between the first stack SS1 and the second stack SS2. For example, as Figure 4 shown in, the side portions of each of the channel structures CH may have a bent portion at the boundary between the first interlayer insulating film 141 and the second stack SS2.

[0066] The channel structure CH may include a semiconductor film 130 and a data storage film 132.

[0067] The semiconductor film 130 may extend in the third direction Z and may cross the gate electrodes (112 and 117). The semiconductor film 130 is shown as cup-shaped, but the present disclosure is not limited thereto. Alternatively, the semiconductor film 130 may have various other shapes (such as, cylindrical, rectangular prism, or filled column shape). The semiconductor film 130 may include, for example, single-crystalline silicon, polycrystalline silicon, organic semiconductors, and carbon nanostructures, but the present disclosure is not limited thereto.

[0068] The semiconductor film 130 may be connected to the source layer 102. For example, an end portion (e.g., the upper end) of the semiconductor film 130 may be exposed from the data storage film 132 and may be connected to the source layer 102. In some example embodiments, the semiconductor film 130 may penetrate the first surface 102a of the source layer 102. For example, an end portion (e.g., the upper end) of the semiconductor film 130 may protrude above the data storage film 132. The semiconductor film 130 may enhance the contact area with the source layer 102, thereby reducing the contact resistance.

[0069] The data storage film 132 may be disposed between the semiconductor film 130 and the gate electrodes (112 and 117). For example, the data storage film 132 may extend along the outer surface of the semiconductor film 130. The data storage film 132 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a high-k material having a dielectric constant larger than that of silicon oxide, but the present disclosure is not limited thereto. The high-k material may include, for example, at least one of aluminum oxide, hafnium oxide, lanthanum oxide, tantalum oxide, titanium oxide, lanthanum hafnium oxide, lanthanum aluminum oxide, dysprosium scandium oxide, and combinations thereof.

[0070] In some example embodiments, the data storage film 132 may be formed as a multilayer. For example, as Figure 5 and Figure 8 shown in, each of the data storage films 132 may include a tunnel insulating film 132a, a charge storage film 132b, and a blocking insulating film 132c sequentially stacked on the outer surface of the corresponding semiconductor film 130.

[0071] The tunnel insulating film 132a may include, for example, silicon oxide or a high-k material having a dielectric constant greater than that of silicon oxide (e.g., aluminum oxide (Al2O3) or hafnium oxide (HfO2)). The charge storage film 132b may include, for example, silicon nitride. The blocking insulating film 132c may include, for example, silicon oxide or a high-k material having a dielectric constant greater than that of silicon oxide (e.g., Al2O3 or HfO2).

[0072] In some example embodiments, the channel structure CH may further include a fill insulating film 134. The fill insulating film 134 may be formed to fill the interior of the cup-shaped semiconductor film 130. The fill insulating film 134 may include, for example, an insulating material such as silicon oxide, but the present disclosure is not limited thereto. For example, the fill insulating film 134 may extend beyond the data storage film 132 at an end (e.g., the upper end).

[0073] In some example embodiments, the channel structure CH may further include a channel pad 136. The channel pad 136 may be formed to connect to the other end (e.g., the lower end) of the semiconductor film 130. The channel pad 136 may include a conductive material such as doped polysilicon, metal, or metal silicide, but the present disclosure is not limited thereto.

[0074] In some example embodiments, a dummy channel structure DCH may be formed in the extension region EA. The dummy channel structure DCH may extend in the third direction Z and penetrate at least a portion of the stacked structures (SS1 and SS2).

[0075] The dummy channel structure DCH may be formed at the same level or a different level from the channel structure CH. For example, if formed at the same level as the channel structure CH, the dummy channel structure DCH may also include the semiconductor film 130, the data storage film 132, the fill insulating film 134, and the channel pad 136. Alternatively, if formed at a different level from the channel structure CH, the dummy channel structure DCH may be filled with an insulating material and / or a conductive material. The size (here, e.g., width) of the dummy channel structure DCH may be the same as or different from the size of the channel structure CH. In some example embodiments, the size of the dummy channel structure DCH may be greater than the size of the channel structure CH.

[0076] The cutting pattern WC may be disposed across the cell array region CA and the extension region EA. The cutting pattern WC may extend longitudinally in the first direction X, thereby cutting the stacked structures (SS1 and SS2). Additionally, the cutting patterns WC may be spaced apart from each other and extend parallel in the first direction X. The stacked structures (SS1 and SS2) may be divided by the cutting pattern WC, thereby forming a plurality of memory cell blocks (e.g., Figure 1memory cell blocks BLK1 to BLKn). For example, two adjacent cutting patterns WC may define a single memory cell block therebetween. A plurality of channel structures CH may be disposed in each of the memory cell blocks defined by the cutting patterns WC.

[0077] In some example embodiments, the cutting pattern WC may include an insulating material, such as at least one of silicon oxide, silicon nitride, and silicon oxynitride, but the present disclosure is not limited thereto. For example, the cutting pattern WC may include a silicon oxide film.

[0078] In some example embodiments, a separation pattern (or isolation pattern) SC may be formed within the second stack SS2. The separation pattern SC may extend in a first direction X, cutting a string selection line (e.g., Figure 2 the string selection line SSL) of the second stack SS2 (e.g., the bottommost second gate electrode 117). Each of the memory cell blocks defined by the cutting patterns WC may be divided by the separation pattern SC to form a plurality of string regions. For example, one separation pattern SC may define two string regions within a single memory cell block. The separation pattern SC may include an insulating material, such as at least one of silicon oxide, silicon nitride, and silicon oxynitride, but the present disclosure is not limited thereto.

[0079] The gate contact 162 may be disposed in the extension region EA. The gate contact 162 may be electrically connected to the gate electrodes (112 and 117). For example, a third interlayer insulating film 143 may be formed to cover the channel structure CH and the second interlayer insulating film 142. A plurality of gate contacts 162 may extend in a third direction Z to penetrate the third interlayer insulating film 143 and the second interlayer insulating film 142, and may be connected to the corresponding gate electrodes (112 and 117). In some example embodiments, the width of the gate contact 162 may decrease closer to the corresponding gate electrodes (112 and 117).

[0080] The source contact 164 may be disposed in the external region PA. The source contact 164 may be electrically connected to the source layer 102. For example, the source contact 164 may extend in a third direction Z to penetrate the third interlayer insulating film 143 and the second interlayer insulating film 142, and may be connected to the source layer 102 exposed from the stack structures (SS1 and SS2). In some example embodiments, the width of the source contact 164 may decrease closer to the source layer 102.

[0081] The through - via 166 may be disposed in the external region PA. The through - via 166 may be stacked with the insulating substrate 104 in the third direction Z. For example, the through - via 166 may extend in the third direction Z to penetrate the third interlayer insulating film 143 and the second interlayer insulating film 142, and may be connected to the insulating substrate 104. In some exemplary embodiments, the width of the through - via 166 may decrease closer to the insulating substrate 104. In some exemplary embodiments, the upper surface of the through - via 166 may be formed coplanar with or higher than the lower surface of the insulating substrate 104.

[0082] The channel contact CC may be formed on the channel structure CH. The channel contact CC may be electrically connected to the channel structure CH. For example, the channel contact CC may penetrate the third interlayer insulating film 143, and thus may be connected to the end of the channel structure CH (e.g., the lower end of the channel pad 136). In some exemplary embodiments, the width of the channel contact CC may decrease closer to the channel structure CH.

[0083] In some exemplary embodiments, the channel contact CC may have a width smaller than that of the channel structure CH. For example, at the interface between the channel structure CH and the channel contact CC (or at the interface between the second interlayer insulating film 142 and the third interlayer insulating film 143), the width W12 of the channel contact CC may be smaller than the width W11 of the channel structure CH.

[0084] The barrier pattern BC may be formed on the cutting pattern WC. The barrier pattern BC may be stacked with the cutting pattern WC in the third direction Z. For example, the barrier pattern BC may extend longitudinally in the first direction X within the third interlayer insulating film 143. The barrier pattern BC may also be referred to as a line pattern. In some exemplary embodiments, the barrier pattern BC may directly contact the cutting pattern WC. In some exemplary embodiments, the width of the barrier pattern BC may decrease closer to the cutting pattern WC.

[0085] In some exemplary embodiments, the barrier pattern BC may have a width larger than that of the cutting pattern WC. Here, the term "width" refers to the width in the second direction Y. For example, at the interface between the cutting pattern WC and the barrier pattern BC (or at the interface between the second interlayer insulating film 142 and the third interlayer insulating film 143), the width W22 of the barrier pattern BC may be larger than the width W21 of the cutting pattern WC.

[0086] In some example embodiments, the blocking pattern BC may be disposed at the same level as the channel contact CC. The expression "disposed at the same level" means being disposed at the same height in the vertical direction (e.g., the third direction Z). The lower surface of the blocking pattern BC may be disposed coplanar with the lower surface of the channel contact CC. Similarly, the upper surface of the blocking pattern BC may be disposed coplanar with the upper surface of the channel contact CC. Additionally, the expression "same" not only means exactly the same, but also encompasses the existence of minor differences that may arise due to process margins and the like.

[0087] In some example embodiments, the blocking pattern BC may be formed at the same level as the channel contact CC. Here, the expression "formed at the same level" means being formed by the same manufacturing process. For example, the blocking pattern BC may include the same material as the channel contact CC. Optionally, the blocking pattern BC may have the same material composition as the channel contact CC.

[0088] In some example embodiments, each of the channel contact CC and the blocking pattern BC may include a first barrier conductive film 160b and a first filling conductive film 160f sequentially stacked on the second interlayer insulating film 142.

[0089] The first barrier conductive film 160b may contain a metal or a metal nitride to prevent or reduce the diffusion of the first filling conductive film 160f. The first barrier conductive film 160b may include at least one of, for example, titanium (Ti), tantalum (Ta), tungsten (W), Ni, Co, platinum (Pt), their alloys, and their nitrides, but the present disclosure is not limited thereto. For example, the first barrier conductive film 160b may include a titanium nitride film.

[0090] The first filling conductive film 160f may be formed to fill the region on the first barrier conductive film 160b. The first filling conductive film 160f may include at least one of, for example, aluminum (Al), copper (Cu), W, Mo, Co, Ru, and their alloys, but the present disclosure is not limited thereto. For example, the first filling conductive film 160f may include a W film.

[0091] The first contact pattern 170 may be formed on the third interlayer insulating film 143. The first contact pattern 170 may be electrically connected to the gate contact 162, the source contact 164, the via hole 166, and / or the channel contact CC. For example, a fourth interlayer insulating film 144 may be formed to cover the third interlayer insulating film 143, the gate contact 162, the source contact 164, the via hole 166, the channel contact CC, and the barrier pattern BC. The first contact pattern 170 may be connected to the gate contact 162, the source contact 164, the via hole 166, and / or the channel contact CC by penetrating the fourth interlayer insulating film 144. In some example embodiments, the width of the first contact pattern 170 may decrease closer to the third interlayer insulating film 143.

[0092] In some example embodiments, each of the first contact patterns 170 may include a second barrier conductive film 170b and a second fill conductive film 170f sequentially stacked on the third interlayer insulating film 143.

[0093] The second barrier conductive film 170b may include a metal or a metal nitride to prevent or reduce the diffusion of the second fill conductive film 170f. The second barrier conductive film 170b may include at least one of, for example, Ti, Ta, W, Ni, Co, Pt, their alloys, and their nitrides, but the present disclosure is not limited thereto. For example, the second barrier conductive film 170b may include a titanium nitride film.

[0094] The second fill conductive film 170f may be formed to fill the region on the second barrier conductive film 170b. The second fill conductive film 170f may include at least one of, for example, Al, Cu, W, Mo, Co, Ru, and their alloys, but the present disclosure is not limited thereto. For example, the second fill conductive film 170f may include a W film.

[0095] The unit wiring structure 180 may be formed on the fourth interlayer insulating film 144. The unit wiring structure 180 may be electrically connected to the first contact pattern 170. For example, a first inter-wiring insulating film 145 may be formed to cover the fourth interlayer insulating film 144 and the first contact pattern 170. The unit wiring structure 180 may be formed within the first inter-wiring insulating film 145 so as to be connected to the first contact pattern 170. The number of layers and the arrangement of the unit wiring structure 180 are merely examples and are not particularly limited.

[0096] The unit wiring structure 180 may include a conductive material such as Al, Cu, W, Mo, Co, Ru, or their alloys, but the present disclosure is not limited thereto. For example, the unit wiring structure 180 may include Cu wiring.

[0097] In some example embodiments, the cell wiring structure 180 may include wires 185 disposed in the cell array region CA. The wires 185 may extend longitudinally in the second direction Y. Additionally, the wires 185 may be spaced apart from each other so as to extend in parallel in the second direction Y.

[0098] The wires 185 may be electrically connected to the channel structures CH arranged along the second direction Y. For example, as Figure 6 shown, the wires 185 may be stacked with the channel structures CH arranged along the second direction Y in the third direction Z. The wires 185 may be electrically connected to the channel structures CH through the first contact pattern 170 and the channel contacts CC. In a semiconductor memory device according to some example embodiments of the present disclosure, the wires 185 may be provided as bit lines (e.g., Figure 2 bit lines BL).

[0099] In some example embodiments, the wire 185 may include a first bit line 185a and a second bit line 185b adjacent to each other in the first direction X. The first bit line 185a and the second bit line 185b may be alternately arranged along the first direction X. Further, the channel structures CH may be stacked with both the first bit line 185a and the second bit line 185b. For example, one of two adjacent channel structures CH in the second direction Y may be connected to the first bit line 185a, and the other channel structure CH may be connected to the second bit line 185b. According to some example embodiments of the present disclosure, the wire 185 may further enhance the density of the semiconductor memory device.

[0100] The peripheral circuit structure PERI may include a peripheral circuit substrate 200, peripheral circuit elements PT, and a peripheral circuit wiring structure 280.

[0101] The peripheral circuit substrate 200 may include a semiconductor substrate (such as an Si, germanium (Ge), or silicon germanium (SiGe) substrate). Optionally, the peripheral circuit substrate 200 may include a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0102] The peripheral circuit elements PT may be formed on the peripheral circuit substrate 200. The peripheral circuit elements PT may form a peripheral circuit (e.g., Figure 1 peripheral circuit 30) for controlling the operation of the semiconductor memory device according to some example embodiments of the present disclosure. For example, the peripheral circuit elements PT may include control logic (e.g., Figure 1 control logic 37), a row decoder (e.g., Figure 1 row decoder 33), and a page buffer (e.g., Figure 1of the page buffer 35). The surface of the peripheral circuit substrate 200 where the peripheral circuit elements PT are disposed may be referred to as the front side of the peripheral circuit substrate 200. In contrast, the surface of the peripheral circuit substrate 200 opposite to the front side of the peripheral circuit substrate 200 may be referred to as the back side of the peripheral circuit substrate 200.

[0103] The peripheral circuit elements PT may include, for example, transistors, but the present disclosure is not limited thereto. The peripheral circuit elements PT may include not only active devices (such as transistors) but also passive devices (such as capacitors, resistors, or inductors).

[0104] The peripheral circuit wiring structure 280 may be formed on the peripheral circuit elements PT. For example, the second inter-wiring insulating film 242 may be formed on the front side of the peripheral circuit substrate 200. The peripheral circuit wiring structure 280 may be formed in the second inter-wiring insulating film 242 and may be electrically connected to the peripheral circuit elements PT. The number of layers and the arrangement of the peripheral circuit wiring structure 280 are merely examples and are not particularly limited.

[0105] In some example embodiments, the memory cell structure CELL may be stacked on the peripheral circuit structure PERI. For example, the memory cell structure CELL may be stacked on the second inter-wiring insulating film 242.

[0106] In some example embodiments, the first surface 102a of the source electrode layer 102 may face the peripheral circuit structure PERI. For example, a stacked structure (SS1 and SS2) may be disposed between the source electrode layer 102 and the peripheral circuit structure PERI.

[0107] A semiconductor memory device according to some example embodiments of the present disclosure may have a chip-to-chip (C2C) structure. The C2C structure involves: fabricating an upper chip including the memory cell structure CELL on a first wafer, fabricating a lower chip including the peripheral circuit structure PERI on a second wafer different from the first wafer, and bonding the upper chip and the lower chip together.

[0108] For example, the upper chip and the lower chip may be bonded together by electrically connecting a first bonding metal 190 (and / or a first bonding insulating film 146) formed in the uppermost metal layer of the upper chip and a second bonding metal 290 (and / or a second bonding insulating film 244) formed in the uppermost metal layer of the lower chip. For example, if the first bonding metal 190 and the second bonding metal 290 are formed of Cu, the upper chip and the lower chip may be bonded by a Cu-Cu bonding method, but the present disclosure is not limited thereto. The first bonding metal 190 and the second bonding metal 290 may be formed of various other metals (such as Al or W).

[0109] When the first bonding metal 190 and the second bonding metal 290 are bonded together, the cell wiring structure 180 can be electrically connected to the peripheral circuit wiring structure 280. Accordingly, the memory cells formed in the cell array region CA can be electrically connected to the peripheral circuit elements PT.

[0110] The conductive pad 390 can be formed on the second surface 102b of the source layer 102. For example, an upper insulating film 340 covering the second surface 102b of the source layer 102 and the insulating substrate 104 can be formed. The conductive pad 390 can be formed on the upper surface of the upper insulating film 340.

[0111] In some example embodiments, the conductive pad 390 can be disposed within the external region PA. The conductive pad 390 can be electrically connected to the memory cell structure CELL and / or the peripheral circuit structure PERI. For example, a second contact pattern 360 connected to the via-through hole 166 by penetrating the upper insulating film 340 can be formed. The conductive pad 390 can be electrically connected to the peripheral circuit structure PERI through the second contact pattern 360 and the via-through hole 166.

[0112] To improve the integration density of a semiconductor memory device, a semiconductor memory device having a C2C structure is being studied. In the C2C structure, since the upper chip and the lower chip are connected by bonding, the common source line (e.g., the source layer 102) of the upper chip can be disposed at the top of the semiconductor memory device.

[0113] Meanwhile, a laser annealing process can be performed on the common source line to activate impurities included in the common source line. However, the laser used in the laser annealing process may irradiate wirings (e.g., the wire 185) formed of a material having a high transmittance and penetration structures (e.g., the cut pattern WC) below the common source line. As a result, wiring defects that may be caused by copper migration may occur.

[0114] In contrast, a semiconductor memory device according to some example embodiments of the present disclosure can use a blocking pattern BC to prevent or reduce wiring defects. For example, as described above, the blocking pattern BC can be disposed between the cut pattern WC and the cell wiring structure 180 and can be stacked with the cut pattern WC in the third direction Z. The blocking pattern BC can prevent or reduce defects in the cell wiring structure 180 by blocking the laser passing through the cut pattern WC during the laser annealing process. In this way, a semiconductor memory device having improved reliability can be provided.

[0115] In addition, in a semiconductor memory device according to some example embodiments of the present disclosure, a blocking pattern BC may be disposed at the same level as a channel contact CC. For example, as mentioned above, the blocking pattern BC may be formed at the same level as the channel contact CC. Accordingly, a semiconductor memory device having improved reliability may be provided without additional cost.

[0116] Figures 9 to 11 is a cross-sectional view for explaining a semiconductor memory device according to some example embodiments of the present disclosure. For convenience, descriptions of content overlapping with that already described above will be simplified or omitted. Figures 1 to 8 The description of the content overlapping with that already described above will be simplified or omitted.

[0117] Referring to Figure 7 and Figure 9 , a semiconductor memory device according to some example embodiments of the present disclosure may further include a conductive plate 103.

[0118] The conductive plate 103 may be formed on the back side of the source layer 102. The conductive plate 103 may be disposed between the source layer 102 and the upper insulating film 340. The conductive plate 103 may be electrically connected to the source layer 102. For example, the conductive plate 103 may contact the back side of the source layer 102. The conductive plate 103 may include a conductive material, for example, a metal (such as W, Co, or Ni) or a metal silicide, but the present disclosure is not limited thereto. The conductive plate 103 may be used to reduce the resistance of a common source line including the source layer 102 (for example, Figure 2 the common source line CSL of

[0119] Referring to Figure 7 and Figure 10 , a semiconductor memory device according to some example embodiments of the present disclosure may include a first cutting pattern WC1 and a second cutting pattern WC2.

[0120] The first cutting pattern WC1 may extend in a first direction X, thereby cutting the first stack SS1. The second cutting pattern WC2 may extend in the first direction X, thereby cutting the second stack SS2. The first cutting pattern WC1 and the second cutting pattern WC2 may be connected to each other in a third direction Z.

[0121] The first cutting pattern WC1 may have a tapered shape toward the source layer 102. For example, the width of the first cutting pattern WC1 may decrease closer to the source layer 102. This may be because an etching process for forming the first cutting pattern WC1 is performed in a direction toward the source layer 102 (for example, in the third direction Z).

[0122] The second cutting pattern WC2 may have a tapered shape toward the first cutting pattern WC1. For example, the width of the second cutting pattern WC2 may decrease closer to the first cutting pattern WC1. This may be because the etching process for forming the second cutting pattern WC2 is performed in a direction toward the first cutting pattern WC1 (e.g., in the third direction Z).

[0123] Referring Figure 7 and Figure 11 , in a semiconductor memory device according to some example embodiments of the present disclosure, a blocking pattern BC (or a line pattern) may be disposed at the same level as the first contact pattern 170.

[0124] For example, the lower surface of the blocking pattern BC may be disposed coplanar with the lower surface of the first contact pattern 170. Similarly, the upper surface of the blocking pattern BC may be disposed coplanar with the upper surface of the first contact pattern 170.

[0125] Figure 12 is a layout diagram for explaining a semiconductor memory device according to some example embodiments of the present disclosure. For convenience, descriptions of content overlapping with that already described above with reference to Figures 1 to 11 will be simplified or omitted.

[0126] Referring Figure 3 and Figure 12 , in a semiconductor memory device according to some example embodiments of the present disclosure, the side portion of the cutting pattern WC may include a curved surface.

[0127] For example, as Figure 12 shown, from a planar perspective, the side portion of the cutting pattern WC may have a shape formed by connecting a plurality of arcs along the first direction X. This may be because the etching process for forming the cutting pattern WC connects a plurality of holes arranged along the first direction X. The formation of the cutting pattern WC will be described in more detail later with reference to Figures 32 to 42 .

[0128] Figure 13 is a layout diagram for explaining a semiconductor memory device according to some example embodiments of the present disclosure. Figure 14 is a cross-sectional view taken along line C-C of Figure 13 . Figure 15 is Figure 14 an enlarged cross-sectional view of region Z3 of Figures 1 to 12 . For convenience, descriptions of content overlapping with that already described above with reference to

[0129] Referring Figures 13 to 15 , a semiconductor memory device according to some example embodiments of the present disclosure may further include a gate pattern 119.

[0130] The gate pattern 119 may be disposed between the stacked structures (SS1 and SS2) and the cell wiring structure 180, and between the cut pattern WC and the cell wiring structure 180. The gate pattern 119 may have a layered structure extending in a horizontal direction (e.g., the first direction X or the second direction Y). The gate pattern 119 may be spaced apart from the gate electrodes (112 and 117). For example, the gate pattern 119 may be stacked on the second interlayer insulating film 142. The channel structure CH may extend in the third direction Z and penetrate the gate pattern 119.

[0131] The gate pattern 119 may include a conductive material, e.g., polysilicon doped with impurities, metal, or metal silicide, but the present disclosure is not limited thereto. In some example embodiments, the gate pattern 119 may be provided as one or more string selection lines (e.g., Figure 2 the string selection line SSL) in a semiconductor memory device according to some example embodiments of the present disclosure.

[0132] In some example embodiments, the blocking pattern BC may be in direct contact with the gate pattern 119. For example, the third interlayer insulating film 143 may cover the gate pattern 119, and the blocking pattern BC may be formed within the third interlayer insulating film 143 to contact the lower surface of the gate pattern 119. The width of the blocking pattern BC may decrease closer to the gate pattern 119.

[0133] In some example embodiments, the channel pad 136 may be formed within the gate pattern 119. The gate pattern 119 may be spaced apart from the channel pad 136. For example, as Figure 15 shown, a gate dielectric film 137 surrounding the outer surface of the channel pad 136 may be formed between the channel pad 136 and the gate pattern 119. The gate dielectric film 137 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a high-k material having a dielectric constant greater than that of silicon oxide, but the present disclosure is not limited thereto.

[0134] In some example embodiments, the isolation pattern SC may be formed within the gate pattern 119. The isolation pattern SC may extend in the first direction X, thereby cutting the gate pattern 119. The memory cell block defined by the cut pattern WC may be divided by the isolation pattern SC to form a plurality of string regions.

[0135] In some example embodiments, the gate pattern 119 may include a first portion 119b and a second portion 119a. The first portion 119b may be the portion of the gate pattern 119 that intersects the channel structure CH, i.e., the first portion 119b may be penetrated by the channel structure CH. For example, the channel pad 136 may be disposed in the first portion 119b. The second portion 119a may be the portion of the gate pattern 119 that overlaps with the cutting pattern WC. For example, the second portion 119a may be disposed between the cutting pattern WC and the blocking pattern BC. The first portion 119b and the second portion 119a may be separated from each other by an isolation pattern SC extending in the first direction X. Accordingly, the first portion 119b of the gate pattern 119 may be configured as a string selection line for a memory cell block defined by the cutting pattern WC (e.g., Figure 2 the string selection line SSL).

[0136] In some example embodiments, the second portion 119a of the gate pattern 119 may have a width greater than that of the blocking pattern BC. Here, the term "width" refers to the width in the second direction Y. For example, at the interface between the blocking pattern BC and the gate pattern 119 (or the interface between the third interlayer insulating film 143 and the gate pattern 119), the width W23 of the second portion 119a of the gate pattern 119 may be greater than the width W22 of the blocking pattern BC.

[0137] Hereinafter, a method of manufacturing a semiconductor memory device according to some example embodiments of the present disclosure will be described with reference to Figures 1 to 42 FIGS.

[0138] Figures 16 to 31 FIG. Figures 1 to 15 is a cross-sectional view showing an intermediate step of a method of manufacturing a semiconductor memory device according to some example embodiments of the present disclosure. For convenience, descriptions of content overlapping with that already described above with reference to

[0139] will be simplified or omitted. Figure 16 and Figure 17 FIG. Figure 17 a first preliminary stack pSS1 and a first preliminary channel pCH1 are formed on a substrate base 100. Figure 16 FIG.

[0140] The substrate base 100 may include, for example, a semiconductor substrate (such as an Si substrate, a Ge substrate, or an SiGe substrate). Alternatively, the substrate base 100 may include an SOI substrate or a GOI substrate.

[0141] The substrate base 100 may include a third surface 100a and a fourth surface 100b that face each other. The third surface 100a may also be referred to as the front side of the substrate base 100, and the fourth surface 100b may also be referred to as the back side of the substrate base 100.

[0142] A first preliminary stack pSS1 may be formed on a third surface 100a of a substrate base 100. The first preliminary stack pSS1 may include a plurality of first molded insulating films 110 and a plurality of first molded sacrificial films 111 that are alternately stacked on the substrate base 100 together with the first molded insulating films 110. The first molded sacrificial films 111 may include a material having an etching selectivity with respect to the first molded insulating films 110. For example, each of the first molded insulating films 110 may include a silicon oxide film, and each of the first molded sacrificial films 111 may include a silicon nitride film.

[0143] A first preliminary channel pCH1 may extend in a third direction Z so as to penetrate the first preliminary stack pSS1. The first preliminary channel pCH1 may be connected to the substrate base 100. For example, a first interlayer insulating film 141 covering the first preliminary stack pSS1 may be formed on the substrate base 100. The first preliminary channel pCH1 may penetrate the first interlayer insulating film 141 and the first preliminary stack pSS1 so as to be connected to the substrate base 100.

[0144] The first preliminary channel pCH1 may include a material having an etching selectivity with respect to the first molded insulating films 110 and the first molded sacrificial films 111. For example, the first preliminary channel pCH1 may include polycrystalline Si.

[0145] Refer to Figure 18 , a second preliminary stack pSS2 and a second preliminary channel pCH2 are formed on the first preliminary stack pSS1 and the first preliminary channel pCH1.

[0146] The second preliminary stack pSS2 may include a plurality of second molded insulating films 115 and a plurality of second molded sacrificial films 116 that are alternately stacked on the first preliminary stack pSS1 together with the second molded insulating films 115. The formation of the second preliminary stack pSS2 may be similar to the formation of the first preliminary stack pSS1, and thus, its detailed description will be omitted.

[0147] The second preliminary channel pCH2 may extend in the third direction Z so as to penetrate the second preliminary stack pSS2. In addition, the second preliminary channel pCH2 may be connected to the first preliminary channel pCH1. The formation of the second preliminary channel pCH2 may be similar to the formation of the first preliminary channel pCH1, and thus, its detailed description will be omitted.

[0148] Refer to Figure 19 , a channel structure CH is formed.

[0149] For example, the first preliminary channel pCH1 and the second preliminary channel pCH2 may be selectively removed. Thereafter, a channel structure CH may be formed in the regions from which the first preliminary channel pCH1 and the second preliminary channel pCH2 have been removed. In this way, a channel structure CH may be formed that extends in a third direction Z to penetrate the first preliminary stack pSS1 and the second preliminary stack pSS2 and is connected to the substrate base 100. In some example embodiments, the channel structure CH may include a semiconductor film 130, a data storage film 132, a filling insulating film 134, and a channel pad 136.

[0150] Referring to Figure 20 and Figure 21 , a cutting region WCh is formed. Figure 21 is a cross-sectional view taken along line B-B of Figure 20 .

[0151] The cutting region WCh may extend in a first direction X and may cut the first preliminary stack pSS1 and the second preliminary stack pSS2.

[0152] Referring to Figure 22 , a plurality of gate electrodes (112 and 117) are formed.

[0153] For example, the molded sacrificial layers (111 and 116) exposed by the cutting region (WCh) may be selectively removed. Thereafter, gate electrodes (112 and 117) may be formed in the regions from which the molded sacrificial layers (111 and 116) have been removed. Accordingly, a stacked structure (SS1 and SS2) including molded insulating films (110 and 115) and gate electrodes (112 and 117) may be formed. In some example embodiments, after the stacked structure (SS1 and SS2) is formed, the cutting region WCh may be filled with an insulating material. As a result, a cutting pattern WC that extends in the first direction X to cut the stacked structure (SS1 and SS2) may be formed.

[0154] Referring to Figure 23 and Figure 24 , a channel contact CC and a blocking pattern BC (or line pattern) are formed. Figure 24 is a cross-sectional view taken along line B-B of Figure 23 .

[0155] For example, a third interlayer insulating film 143 covering the channel structure CH and the second interlayer insulating film 142 may be formed. The channel contact CC may penetrate the third interlayer insulating film 143 so as to be connected to the channel structure CH. The blocking pattern BC may extend longitudinally in the first direction X within the third interlayer insulating film 143 and may be superimposed on the cutting pattern WC in the third direction Z. In some example embodiments, the blocking pattern BC may be formed at the same level as the channel contact CC.

[0156] Refer to Figure 25 and Figure 26 , a first contact pattern 170 and a cell wiring structure 180 are formed. Figure 26 is a cross-sectional view taken along line B-B of Figure 25 .

[0157] For example, a fourth interlayer insulating film 144 covering the third interlayer insulating film 143, the channel contact CC, and the barrier pattern BC may be formed. The first contact pattern 170 may penetrate the fourth interlayer insulating film 144 so as to be connected to the channel contact CC. The cell wiring structure 180 may be formed on the fourth interlayer insulating film 144. The cell wiring structure 180 may be electrically connected to the first contact pattern 170. In some example embodiments, the cell wiring structure 180 may extend longitudinally in the second direction Y and may include a wire 185 connected to the first contact pattern 170.

[0158] Refer to Figure 27 , a memory cell structure CELL is stacked on the peripheral circuit structure PERI.

[0159] In some example embodiments, the memory cell structure CELL may be stacked such that the third surface 100a of the base substrate 100 may face the peripheral circuit structure PERI. For example, the first bonding metal 190 and / or the first bonding insulating film 146 formed in the uppermost metal layer of the memory cell structure CELL may be bonded to the second bonding metal 290 and / or the second bonding insulating film 246 formed in the uppermost metal layer of the peripheral circuit structure PERI.

[0160] Refer to Figure 28 , at least a part of the base substrate 100 is removed.

[0161] For example, a planarization process or a recess process may be performed on the fourth surface 100b of the base substrate 100. As a result, the end portion (e.g., the upper end) of the channel structure CH may be exposed.

[0162] Refer to Figure 29 , the upper portion of the data storage film 132 is removed.

[0163] For example, an etching process may be performed on the data storage film 132 of the exposed channel structure CH. As a result, the end portion (e.g., the upper end) of the semiconductor film 130 of the channel structure CH may be exposed.

[0164] Refer to Figure 30 , a source electrode layer 102 is formed on the stacked structures (SS1 and SS2) and the channel structure CH.

[0165] A source layer 102 may be formed in a region from which the substrate base 100 has been removed. Accordingly, the source layer 102 connected to the channel structure CH of the semiconductor film 130 may be formed. The source layer 102 may include a conductive material, for example, doped polysilicon, metal, or metal silicide, but the present disclosure is not limited thereto. For example, the source layer 102 may include polycrystalline Si doped with an N-type impurity such as P or As.

[0166] Referring to Figure 31 , a laser annealing process LA is performed on the source layer 102.

[0167] When the laser annealing process LA is performed, impurities included in the source layer 102 may be activated. Different from a typical general annealing process, the laser annealing process LA may be performed locally on the source layer 102, thereby minimizing damage to the semiconductor memory device.

[0168] In addition, as described above, the blocking pattern BC may prevent or reduce defects in the cell wiring structure 180 by blocking the laser passing through the cutting pattern WC during the laser annealing process LA. Accordingly, a method of manufacturing a semiconductor memory device having improved reliability may be provided.

[0169] Thereafter, referring to Figure 7 , an upper insulating film 340 is formed on the source layer 102. In this manner, a Figures 3 to 8 semiconductor memory device may be obtained.

[0170] Figures 32 to 42 is a cross-sectional view showing an intermediate step of a method of manufacturing a semiconductor memory device according to some example embodiments of the present disclosure. For convenience, descriptions of content overlapping with what has been described above with reference to Figures 1 to 31 will be simplified or omitted.

[0171] Referring to Figure 32 and Figure 33 , a first preliminary stack pSS1, a first preliminary channel pCH1, and a first preliminary cutting pattern pWC1 are formed on the substrate base 100. Figure 33 is a cross-sectional view taken along the line C-C of Figure 32 .

[0172] The first preliminary cutting pattern pWC1 may extend in the third direction Z and penetrate the first preliminary stack pSS1. A plurality of first preliminary cutting patterns pWC1 may be arranged in the first direction X. In some example embodiments, the first preliminary cutting pattern pWC1 may be formed at the same level as the first preliminary channel pCH1.

[0173] Referring to Figure 34, a second preliminary stack pSS2, a second preliminary channel pCH2, and a second preliminary cutting pattern pWC2 are respectively formed on a first preliminary stack pSS1, a first preliminary channel pCH1, and a first preliminary cutting pattern pWC1.

[0174] The second preliminary cutting pattern pWC2 can extend in a third direction Z and penetrate the second preliminary stack pSS2. In addition, the second preliminary cutting pattern pWC2 can be connected to the first preliminary cutting pattern pWC1. A plurality of second preliminary cutting patterns pWC2 can be arranged in a first direction X. In some example embodiments, the second preliminary cutting pattern pWC2 can be formed at the same level as the second preliminary channel pCH2.

[0175] Referring to Figure 35 , a channel structure CH is formed. The formation of the channel structure CH can be almost as described above with reference to Figure 19 , and thus, its detailed description will be omitted.

[0176] Referring to Figure 36 and Figure 37 , a cutting region WCh is formed. Figure 37 is a cross-sectional view taken along line C-C of Figure 36 .

[0177] For example, the first preliminary cutting pattern pWC1 and the second preliminary cutting pattern pWC2 can be selectively removed. Thereafter, a recess process can be performed on the regions from which the first preliminary cutting pattern pWC1 and the second preliminary cutting pattern pWC2 have been removed. Thus, a cutting region WCh that extends in the first direction X and cuts the first preliminary stack pSS1 and the second preliminary stack pSS2 can be formed.

[0178] Referring to Figure 38 , a plurality of gate electrodes (112 and 117) and a cutting pattern WC are formed. The formation of the gate electrodes (112 and 117) and the cutting pattern WC can be almost as described above with reference to Figure 22 , and thus, their detailed description will be omitted.

[0179] Referring to Figure 39 and Figure 40 , a gate pattern 119 and a channel pad 136 are formed. Figure 40 is a cross-sectional view taken along line C-C of Figure 39 .

[0180] The gate pattern 119 can be formed on the stack structures (SS1 and SS2) and the cutting pattern WC. The gate pattern 119 can be spaced apart from the gate electrodes (112 and 117). The gate pattern 119 can include a conductive material, for example, polysilicon doped with impurities, a metal, or a metal silicide, but the present disclosure is not limited thereto.

[0181] In some example embodiments, an isolation pattern SC may be formed within the gate pattern 119. The isolation pattern SC may extend in a first direction X, thereby cutting the gate pattern 119.

[0182] A channel pad 136 may be formed within the gate pattern 119. The channel pad 136 may be connected to the semiconductor film 130 in the channel structure CH. The channel structure CH including the channel pad 136 may extend in a third direction Z, thereby penetrating the gate pattern 119. The channel pad 136 may be formed at the same level as the gate pattern 119, but the present disclosure is not limited thereto.

[0183] Referring to Figure 41 and Figure 42 , a channel contact CC and a blocking pattern BC are formed. Figure 42 is a cross-sectional view taken along line C-C of Figure 41 . The formation of the channel contact CC and the blocking pattern BC may be substantially as described above with reference to Figure 23 and Figure 24 , and thus, a detailed description thereof will be omitted.

[0184] Thereafter, the process described above with reference to Figures 25 to 31 may be performed. In this manner, a semiconductor memory device of Figures 13 to 15 may be obtained.

[0185] Hereinafter, an electronic system including a semiconductor memory device according to some example embodiments of the present disclosure will be described with reference to Figures 1 to 45 .

[0186] Figure 43 is a block diagram for explaining an electronic system according to some example embodiments of the present disclosure. Figure 44 is a perspective view for explaining an electronic system according to some example embodiments of the present disclosure. Figure 45 is a cross-sectional view taken along line I-I of Figure 44 .

[0187] Referring to Figure 43 , the electronic system 1000 may include a semiconductor memory device 1100 and a controller 1200 electrically connected to the semiconductor memory device 1100. The electronic system 1000 may be a storage device including at least one semiconductor memory device 1100 or an electronic device including a storage device. For example, the electronic system 1000 may be a solid state drive (SSD) device, a universal serial bus (USB), a computing system, a medical device, or a communication device including at least one semiconductor memory device 1100.

[0188] The semiconductor memory device 1100 may be a non-volatile memory device (e.g., a NAND (negative AND) flash memory device), and may include, for example, inFigures 1 to 16 at least one of the semiconductor memory devices depicted. The semiconductor memory device 1100 may include a first structure 1100F and a second structure 1100S on the first structure 1100F.

[0189] The first structure 1100F may be a peripheral circuit structure including a decoder circuit (or decoder) 1110 (e.g., Figure 1 row decoder 33), page buffers 1120 (e.g., Figure 1 page buffer 35), and logic circuits 1130 (e.g., Figure 1 control logic 37). The first structure 1100F may correspond to a peripheral circuit structure PERI of any one of, for example, Figures 1 to 16 the like.

[0190] The second structure 1100S may include a common source line CSL, a plurality of bit lines BL, and a plurality of cell strings CSTR as described above with reference to Figure 2 . The cell strings CSTR may be connected to the decoder circuit 1110 through word lines WL, one or more string selection lines SSL, and one or more ground selection lines GSL. Additionally, the cell strings CSTR may be connected to the page buffers 1120 through the bit lines BL. The second structure 1100S may correspond to a memory cell structure CELL of any one of, for example, Figures 1 to 16 the like.

[0191] In some example embodiments, the common source line CSL and the cell strings CSTR may be electrically connected to the decoder circuit 1110 through a first connection wiring 1115 extending from the first structure 1100F to the second structure 1100S.

[0192] In some example embodiments, the bit lines BL may be electrically connected to the page buffers 1120 through a second connection wiring 1125.

[0193] The semiconductor memory device 1100 may communicate with a controller 1200 through an input / output pad 1101 electrically connected to the logic circuits 1130 (e.g., Figure 1 control logic 37). The input / output pad 1101 may correspond to a conductive pad 390 of any one of Figures 1 to 16 the like. The input / output pad 1101 may be electrically connected to the logic circuits 1130 through an input / output connection wiring 1135 extending from the first structure 1100F to the second structure 1100S. The input / output connection wiring 1135 may correspond to a via hole 166 of any one of, for example, Figures 1 to 16 the like.

[0194] The controller 1200 may include a processor 1210, a NAND controller 1220, and a host interface (I / F) 1230. In some example embodiments, the electronic system 1000 may include a plurality of semiconductor memory devices 1100, and in this case, the controller 1200 may control the plurality of semiconductor memory devices 1100.

[0195] The processor 1210 may control the operation of the entire electronic system 1000 including the controller 1200. The processor 1210 may operate according to specific or desired firmware, and may control the NAND controller 1220 to access the semiconductor memory device 1100. The NAND controller 1220 may include a NAND interface 1221 that processes communication with the semiconductor memory device 1100. Control commands for controlling the semiconductor memory device 1100, data to be written to the memory cell transistors MCTs of the semiconductor memory device 1100, and data to be read from the memory cell transistors MCTs of the semiconductor memory device 1100 may be transmitted through the NAND interface 1221. The host interface 1230 may provide communication capabilities between the electronic system 1000 and an external host. In response to a control command received from the external host through the host interface 1230, the processor 1210 may control the semiconductor memory device 1100.

[0196] Referring Figure 44 and Figure 45 , the electronic system 2000 may include a main substrate 2001, a main controller 2002 mounted on the main substrate 2001, one or more semiconductor packages 2003, and a dynamic random access memory (DRAM) 2004. The semiconductor packages 2003 and the DRAM 2004 may be connected to the main controller 2002 via a wiring pattern 2005 formed on the main substrate 2001.

[0197] The main substrate 2001 may include a connector 2006 that includes a plurality of pins to be coupled to an external host. The number and arrangement of the pins in the connector 2006 may vary according to the communication interface between the electronic system 2000 and the external host. In some example embodiments, the electronic system 2000 may communicate with an external host according to one of the following interfaces: USB, Peripheral Component Interconnect (PCI)-Express, Serial Advanced Technology Attachment (SATA), and M-Phy for Universal Flash Storage (UFS). In some example embodiments, the electronic system 2000 may operate using power supplied by an external host through the connector 2006. The electronic system 2000 may also include a power management integrated circuit (PMIC) that distributes the power supplied from the external host to the main controller 2002 and the semiconductor packages 2003.

[0198] The main controller 2002 can write data into the semiconductor package 2003 or read data from the semiconductor package 2003. The main controller 2002 can improve the operation speed of the electronic system 2000.

[0199] The DRAM 2004 can be used as a buffer memory to reduce the speed difference between the semiconductor package 2003 serving as a data storage space and an external host. The DRAM 2004 included in the electronic system 2000 can be used as a cache memory and can provide a temporary storage space for the control operation of the semiconductor package 2003. If the electronic system 2000 includes the DRAM 2004, in addition to the NAND controller for controlling the semiconductor package 2003, the main controller 2002 can also include a DRAM controller for controlling the DRAM 2004.

[0200] The semiconductor package 2003 can include a first semiconductor package 2003a and a second semiconductor package 2003b spaced apart from each other. Both the first semiconductor package 2003a and the second semiconductor package 2003b can be semiconductor packages including a plurality of semiconductor chips 2200. Each of the first semiconductor package 2003a and the second semiconductor package 2003b can include a package substrate 2100, semiconductor chips 2200 on the package substrate 2100, an adhesive layer 2300 disposed on the lower surface of the semiconductor chips 2200, a connection structure 2400 electrically connecting the semiconductor chips 2200 and the package substrate 2100, and a molding layer 2500 covering the semiconductor chips 2200 and the connection structure 2400 on the package substrate 2100.

[0201] The package substrate 2100 can be a printed circuit board (PCB) including package upper pads 2130. Each of the semiconductor chips 2200 can include input / output pads 2210. The input / output pads 2210 can correspond to Figure 43 the input / output pads 1101.

[0202] In some example embodiments, the connection structure 2400 can be bonding wirings that electrically connect the input / output pads 2210 and the package upper pads 2130. Thus, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 can be electrically connected to each other through the bonding wirings and can also be electrically connected to the package upper pads 2130 of the package substrate 2100. Optionally, in some example embodiments, the semiconductor chips 2200 in each of the first semiconductor package 2003a and the second semiconductor package 2003b can be electrically connected to each other through a connection structure including through-silicon vias (TSVs, also known as "vias through silicon") instead of the connection structure 2400 being bonding wirings.

[0203] In some example embodiments, the host controller 2002 and the semiconductor chip 2200 may be included within a single package. In some example embodiments, the host controller 2002 and the semiconductor chip 2200 may be mounted on an interposer substrate separate from the main substrate 2001 and may be connected to each other through wirings formed on the interposer substrate.

[0204] In some example embodiments, the package substrate 2100 may be a PCB. The package substrate 2100 may include a package substrate body 2120, package upper pads 2130 disposed on the upper surface of the package substrate body 2120, package lower pads 2125 disposed on the lower surface of the package substrate body 2120 or exposed through the lower surface of the package substrate body 2120, and internal wirings 2135 within the package substrate body 2120 that electrically connect the package upper pads 2130 and the package lower pads 2125. As Figure 45 shown, the package upper pads 2130 may be electrically connected to the connection structure 2400. The package lower pads 2125 may be connected to the wiring pattern 2005 of the main substrate 2001 of the electronic system 2000 through the conductive connector 2800.

[0205] In the electronic system 2000, each of the semiconductor chips 2200 may include Figures 1 to 16 any one of the semiconductor memory devices depicted in. For example, each of the semiconductor chips 2200 may include a memory cell structure CELL and a peripheral circuit structure PERI. For example, as Figures 3 to 8 described, the memory cell structure CELL may include a source layer 102, a stack structure (SS1 and SS2), a channel structure CH, a cut pattern WC, a through hole 166, a channel contact CC, a blocking pattern BC, a first contact pattern 170, and a cell wiring structure 180. The peripheral circuit structure PERI may include a peripheral circuit substrate 200 and a peripheral circuit wiring structure 280. The memory cell structure CELL and the peripheral circuit structure PERI may be joined to each other through a first bonding metal 190 and a second bonding metal 290.

[0206] When the terms "about" or "substantially" are used in conjunction with a numerical value in this specification, it is intended that the associated numerical value include manufacturing or operating tolerances around the stated numerical value (e.g., ±10%). Additionally, when the words "generally" and "substantially" are used in conjunction with a geometry, it is intended that the precision of the geometry is not required, but rather the tolerance of the shape is within the disclosed range. Further, whether the numerical value or shape is modified by "about" or "substantially", it will be understood that these numerical values and shapes should be interpreted as including manufacturing or operating tolerances around the stated numerical value or shape (e.g., ±10%).

[0207] As described herein, any electronic device and / or part thereof according to any example embodiment may include one or more instances of a processing circuit, may be included in one or more instances of a processing circuit, and / or may be implemented by one or more instances of a processing circuit, the processing circuit being hardware such as including logic circuits; a hardware / software combination (such as a processor executing software); or any combination thereof. For example, the processing circuit may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a graphics processing unit (GPU), an application processor (AP), a digital signal processor (DSP), a microcomputer, a field programmable gate array (FPGA), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), a neural network processor (NPU), an electronic control unit (ECU), an image signal processor (ISP), etc. In some example embodiments, the processing circuit may include: a non-transitory computer-readable storage device (e.g., a memory) storing an instruction program, by way of example a DRAM device, and a processor (e.g., a CPU) configured to execute the instruction program to implement functions and / or methods performed by some or all of any device, system, module, unit, controller, circuit, architecture, and / or part thereof according to any example embodiment and / or any part thereof.

[0208] In summarizing the detailed description, those skilled in the art will understand that many variations and modifications can be made to the example embodiments without substantially departing from the principles of the inventive concept. Therefore, the example embodiments of the disclosed invention are for general and descriptive purposes only and not for purposes of limitation.

Claims

1. A semiconductor memory device, comprising: A source layer; A stacked structure including a plurality of gate electrodes sequentially stacked with spaces therebetween and on the source layer; A channel structure extending in a first direction, penetrating the plurality of gate electrodes, and connected to the source layer; A cutting pattern extending in a second direction intersecting the first direction and cutting the stacked structure; A cell wiring structure on the stacked structure; A channel contact connecting the channel structure and the cell wiring structure and between the stacked structure and the cell wiring structure; And A line pattern extending in the second direction, between the stacked structure and the cell wiring structure, and overlapping the cutting pattern in the first direction, The line pattern is at the same level as the channel contact.

2. The semiconductor memory device according to claim 1, further comprising: A contact pattern connecting the channel contact and the cell wiring structure, Wherein the line pattern is at a different level from the contact pattern.

3. The semiconductor memory device according to claim 1, wherein, The line pattern is spaced apart from the cell wiring structure in the first direction.

4. The semiconductor memory device according to claim 1, wherein, In a third direction intersecting the first direction and the second direction, the width of the line pattern is greater than the width of the cutting pattern.

5. The semiconductor memory device according to claim 1, wherein, The cell wiring structure includes a wire extending in a third direction intersecting the first direction and the second direction, and The channel contact connects the channel structure and the wire.

6. The semiconductor memory device according to claim 1, wherein, The source layer includes a polysilicon film doped with impurities.

7. The semiconductor memory device according to claim 1, wherein, The cutting pattern includes a silicon oxide film.

8. The semiconductor memory device according to claim 2, wherein The line pattern is at the same level as the contact pattern.

9. The semiconductor memory device according to claim 1, wherein, The channel structure includes a semiconductor film and a data storage film, the semiconductor film extends in the first direction to intersect the gate electrode, and the data storage film is between the semiconductor film and the gate electrode, and An end of the semiconductor film contacts the source layer.

10. The semiconductor memory device according to any one of claims 1 to 9, further comprising: A peripheral circuit structure including a peripheral circuit substrate and peripheral circuit elements on the peripheral circuit substrate, Wherein the stacked structure is between the source layer and the peripheral circuit structure.

11. A semiconductor memory device, comprising: A peripheral circuit structure including a peripheral circuit substrate and peripheral circuit elements on the peripheral circuit substrate; And A memory cell structure stacked on the peripheral circuit structure, The memory cell structure includes: A source layer including a first surface facing the peripheral circuit structure and a second surface opposite the first surface; A stacked structure including a plurality of gate electrodes sequentially stacked with spaces therebetween and on the source layer; A channel structure extending in a first direction, penetrating the plurality of gate electrodes, and connected to the source layer; A cutting pattern extending in a second direction intersecting the first direction and cutting the stacked structure; A wire extending in a third direction intersecting the first direction and the second direction and between the stacked structure and the peripheral circuit structure; A channel contact connecting the channel structure and the wire and between the stacked structure and the wire; and A line pattern extending in the second direction, between the stacked structure and the wire, and overlapping the cutting pattern in the first direction.

12. The semiconductor memory device according to claim 11, wherein, The upper surface of the channel contact and the upper surface of the line pattern are coplanar with each other; The lower surface of the channel contact and the lower surface of the line pattern are coplanar with each other.

13. The semiconductor memory device according to claim 11, wherein, The line pattern is spaced apart from the wire in a first direction.

14. The semiconductor memory device according to claim 11, wherein, In a third direction, the width of the line pattern is greater than the width of the cutting pattern.

15. The semiconductor memory device according to claim 11, wherein, The channel structure includes a semiconductor film and a data storage film. The semiconductor film extends in a first direction to cross the gate electrode, and the data storage film is between the semiconductor film and the gate electrode, and The end of the semiconductor film contacts the source layer.

16. The semiconductor memory device according to any one of claims 11 to 15, further comprising: A gate pattern, between the stacked structure and the wire and between the cutting pattern and the wire, Wherein, the channel structure extends in a first direction to penetrate the gate pattern.

17. The semiconductor memory device according to claim 16, wherein, The line pattern contacts the gate pattern.

18. The semiconductor memory device according to claim 16, wherein, The gate pattern includes a first part and a second part. The first part is penetrated by the channel structure, and the second part is between the cutting pattern and the line pattern, and The first part and the second part are spaced apart from each other by an isolation pattern extending in a second direction.

19. The semiconductor memory device according to claim 18, wherein, In a third direction, the width of the second part is greater than the width of the line pattern.

20. An electronic system, comprising: A main substrate; A semiconductor memory device, including a peripheral circuit structure and a memory cell structure stacked in sequence, and on the main substrate; And A controller, electrically connected to the semiconductor memory device, and on the main substrate, The memory cell structure includes: A source layer, including a first surface facing the peripheral circuit structure and a second surface opposite to the first surface; A stacked structure, including a plurality of gate electrodes stacked in sequence and spaced apart from each other, and on the source layer; A channel structure, extending in a first direction, penetrating the plurality of gate electrodes, and connected to the source layer; A cutting pattern, extending in a second direction crossing the first direction, and cutting the stacked structure; A wire, extending in a third direction crossing the first direction and the second direction, and between the stacked structure and the peripheral circuit structure; A channel contact, connecting the channel structure and the wire, and between the stacked structure and the wire; and A line pattern, extending in the second direction, between the stacked structure and the wire, and overlapping with the cutting pattern in the first direction.

Images