Transverse power device with surface low-resistance path

Abstract

The invention belongs to the technical field of power semiconductors, and particularly relates to a transverse power device with a surface low-resistance path. Compared with a traditional short-circuit anode structure, a high-concentration N top layer is introduced on the surface of a drift region, a first P buried layer is introduced in the drift region, and a second P buried layer is introduced in the drift region between an anode P + and an anode N +. At the beginning of conduction, the high-concentration N top layer provides an electron current low-resistance path, so that more electron current directly reaches the anode P + region, and the second P buried layer between the anode P + and the anode N + is favorable for increasing the anode distribution resistance, thereby eliminating the voltage turn-back effect under a small-size cell; in the turn-off process, the N top layer and the P buried layer in the drift region are mutually depleted to accelerate the depletion of the drift region, the anode N + region also accelerates the carrier extraction, and the turn-off loss is greatly reduced through the combined action of the N top layer and the P buried layer. Therefore, the invention has a better compromise relationship between the conduction voltage drop and the turn-off loss, and has no voltage turn-back effect.

Description

Technical Field

[0001] The present invention belongs to the technical field of power semiconductors, and particularly relates to a lateral power device with a surface low-resistance path. Background Art

[0002] Insulated Gate Bipolar Transistor (IGBT) is a gate-controlled bipolar conductive device. Its gate control characteristics make it have the advantages of high input impedance and easy drive. Its bipolar conduction ability makes it easy to achieve low on-state voltage drop and large current density, and it is very suitable for application in high-voltage and high-power power electronics technical fields such as smart grid, rail transit, and industrial control. Semiconductor devices based on SOI technology are easy to achieve all-dielectric isolation, with lower leakage current and smaller parasitic effects.

[0003] When the LIGBT device is conducting forward, the conductance modulation effect occurs in the drift region and a large number of excess carriers are stored. While reducing the on-state voltage drop (V on ) of the device, it will cause a long tail current during turn-off, increasing the turn-off loss (E off ).

[0004] To improve the contradictory relationship between the turn-off loss and the on-state voltage drop of the LIGBT device, Simpson et al. from Philips Laboratory first proposed the Shorted Anode LIGBT (SA LIGBT) in 1985, that is, a shorted anode N+ region is introduced beside the anode P+ region to accelerate the extraction of electrons stored in the drift region during the device turn-off process. However, the shorted anode structure causes the device to have the Snapback effect caused by the conversion from the unipolar conduction mode to the bipolar conduction mode during conduction, reducing the reliability of parallel use of the device. The Separated Shorted Anode LIGBT (SSALIGBT) proposed by Chum et al. from Seoul National University in 2000. When the distance L A between the anode P+ and the anode N+ is large enough, the path for electrons to flow to the anode N+ is extended, increasing the anode distributed resistance, making the P+ / N-buffer junction easier to turn on at a lower anode voltage, and the device directly enters the bipolar conduction mode, effectively suppressing the Snapback phenomenon. However, this structure requires a longer L AOnly by doing so can the Snapback phenomenon be suppressed, but the chip area utilization rate is relatively low. In 2015, Jing Zhu et al. from Southeast University proposed the segmented trench LIGBT (STA LIGBT) in the anode region. This structure separates the anode P+ region and the N+ region using deep trenches that penetrate the drift region, leaving a narrow gap in the middle of the deep trench for electron flow, significantly increasing the distributed resistance and thus suppressing the Snapback phenomenon. Compared with the SSA LIGBT, the STA LIGBT has a smaller cell size. However, due to the excessive anode distributed resistance, the extraction of electrons during the turn-off process is also restricted, and the STA LIGBT has too high a process precision requirement for the spacing of the segmented deep trenches. But both of these structures will cause an increase in the on-state voltage drop to varying degrees. Summary of the Invention

[0005] The object of the present invention is to propose a lateral power device with a surface low-resistance path in view of the above problems.

[0006] The technical solution of the present invention is as follows:

[0007] A lateral power device with a surface low-resistance path, as Figure 1 shown, includes a P substrate 1, an insulating dielectric layer 2, and an N-type drift region 3 stacked in sequence from bottom to top; along the lateral direction of the device, a cathode structure, an N top layer 12, and an anode structure are sequentially arranged on the upper layer of the N-type drift region 3;

[0008] The cathode structure includes a P-type well region 4, a cathode P+ region 5 and a cathode N+ region 6 arranged in parallel on the upper layer of the P-type well region 4, wherein the cathode N+ region 6 is located on the side close to the anode structure; a first conductive material 81 is commonly led out from the surfaces of the cathode P+ region 5 and the cathode N+ region 6 as the cathode electrode;

[0009] The gate structure is composed of a gate dielectric layer 7 and a gate electrode 82. Among them, the lower surface of the gate dielectric layer 7 is in contact with the upper surface of a part of the cathode N+ region 6, the upper surface of the P-type well region 4 between the cathode N+ region 6 and the N top layer 12, and the upper surface of a part of the N top layer 12, and the gate electrode 82 is located on the upper surface of the gate dielectric layer 7;

[0010] The anode structure includes an N-type buffer layer 9, an anode P+ region 10 on the upper layer of the N-type buffer layer 9, and an anode N+ region 11 at a distance L A from the N-type buffer layer 9, wherein the N-type buffer layer 9 is in contact with the N top layer 12; a second conductive material 83 is led out from the surface of the anode P+ region 10, and a third conductive material 84 is led out from the surface of the anode N+ 11. The second conductive material 83 and the third conductive material 84 serve as the anode electrodes;

[0011] Below the N top layer 12, there is a first P buried layer 13. The upper surface of the first P buried layer 13 is in contact with the N top layer 12. There are spacings between the two ends of the first P buried layer 13 and the P-type well region 4 and the N-type buffer layer 9 respectively; between the N-type buffer layer 9 and the anode N+ region 11, there is a second P buried layer 14. The junction depths of the upper and lower surfaces of the second P buried layer 14 are the same as those of the upper and lower surfaces of the first P buried layer 13.

[0012] The beneficial effects of the present invention are as follows. Compared with the traditional short-circuit anode LIGBT structure, the present invention adopts an N top layer and a first P buried layer above the drift region. During conduction, the N top layer fixes the electrons flowing out from the cathode NMOS in the upper layer of the N-type drift region and the electron current is very large, making it easy to reach the bipolar conduction condition. At the same time, a second P buried layer is added between the anode P+ and the anode N+ to prevent too many electrons from directly flowing into the anode N+, greatly shortening the anode spacing, reducing the cell size and eliminating the Snapback phenomenon; in the forward blocking state, due to the substrate-assisted depletion effect, the depletion effect of the substrate on the N top layer gradually weakens from the anode to the cathode. Therefore, a first P buried layer is added near the cathode part to maintain charge balance to obtain high breakdown voltage; during turn-off, due to the shorter distance between the anode P+ and the anode N+, an electron fast extraction channel is provided, which can greatly reduce the turn-off loss. At the same time, the first P buried layer and the second P buried layer jointly accelerate the depletion of the N-type region, accelerating the extraction of carriers and further reducing the turn-off loss. The trade-off relationship between the on-state voltage drop and the turn-off loss of the device is optimized. Description of the Drawings

[0013] Figure 1 It is a schematic structural diagram of the present invention.

[0014] Figures 2 - 9 It is a schematic structural diagram of a lateral power device with a surface low-resistance path provided by the present invention during the manufacturing process. Detailed Embodiments

[0015] The structure in the content of the invention is the best implementation mode of the present invention and will not be repeated here. The working principle of the present invention will be further described below:

[0016] During forward conduction, in the single-pole mode, the electrons flowing out from the cathode NMOS channel are directly collected by the highly doped low-resistance electron channel N top layer 12. At this time, the electron current is mainly concentrated in the N-top layer 12 and the electron current is very large, making it easier to reach the I e *R SA = 0.7V bipolar conduction condition, making the PN junction formed by the anode P+ region 10 / N-type buffer layer 9 conduct. At the same time, a second P buried layer 14 is added between the anode P+ 10 and the anode N+ 11 to prevent too many electrons from directly flowing into the anode N+ 11, greatly shortening the anode spacing L AReduces the unit cell size and eliminates the Snapback phenomenon.

[0017] In the blocking state, due to the substrate-assisted depletion effect, the depletion effect of the P-type substrate 1 on the N top layer 12 gradually weakens from the anode to the cathode. Therefore, a first P buried layer 13 is added near the P-type well region 4 below the N top layer 12 to maintain charge balance to obtain high breakdown voltage.

[0018] During the turn-off process, the anode N+ region 11 of the short-circuit anode structure provides a fast electron extraction channel. And due to the shorter distance between the anode P+ region 10 and the anode N+ region 11, the turn-off loss can be significantly reduced. At the same time, the first P buried layer 13 and the second P buried layer 14 jointly accelerate the depletion of the N-type region, accelerate the extraction of carriers, and accelerate the extraction of excess carriers, which can further reduce the turn-off loss.

[0019] Thus, compared with the traditional short-circuit anode LIGBT structure, the present invention can improve the current capacity of the device, accelerate the device turn-off, obtain a better trade-off relationship between on-state voltage drop and turn-off loss, and completely avoid the snapback effect brought by the short-circuit anode structure without using complex processes, adding external circuits, and occupying device area.

[0020] The present invention also provides a preparation process for a lateral power device with a surface low-resistance path. The basic preparation process is as follows: First, select a suitable SOI silicon wafer. The top silicon of the N-type drift region 3 is 6 μm, the insulating dielectric layer 2 is 3 μm, and the P-type substrate 1 is 3 μm, as Figure 2 shown; Boron and phosphorus ions are respectively implanted into the SOI silicon wafer and annealed and diffused to form a P well 4 and an N-type buffer layer 9, as Figure 3 shown; An oxide layer region is grown and polysilicon is deposited; The polysilicon region and the oxide layer region are etched to form a gate structure, as Figure 4 shown; Boron ions and phosphorus ions are implanted in sequence, and rapid thermal annealing is used to activate the impurities to form a first P buried layer 13, a second P buried layer 14, and an N top layer 12, as Figure 5 、 6 shown; Arsenic ions are implanted to form an anode N+ 11 and a cathode N+ 6, as Figure 7 shown; Boron difluoride ions are implanted to form an anode P+ 10 and a cathode P+ 5, as Figure 8 shown; Aluminum is deposited to form an ohmic contact and lead out electrodes, as Figure 9 shown.

Claims

1. A lateral power device with a low-surface resistance path, comprising a P substrate (1), an insulating dielectric layer (2), and an N-type drift region (3) stacked in sequence from bottom to top; characterized in that, The upper layer of the N-type drift region (3) sequentially has a cathode structure, an N top layer (12), and an anode structure along the lateral direction of the device; The cathode structure includes a P-type well region (4), a cathode P+ region (5) and a cathode N+ region (6) which are arranged in parallel on the upper layer of the P-type well region (4), wherein the cathode N+ region (6) is located on the side close to the anode structure; a first conductive material (81) is commonly led out from the surfaces of the cathode P+ region (5) and the cathode N+ region (6) as a cathode electrode; The gate structure is composed of a gate dielectric layer (7) and a gate electrode (82). Among them, the lower surface of the gate dielectric layer (7) is respectively in contact with the upper surface of a part of the cathode N+ region (6), the upper surface of the P-type well region (4) between the cathode N+ region (6) and the N top layer (12), and the upper surface of a part of the N top layer (12), and the gate electrode (82) is located on the upper surface of the gate dielectric layer (7); The anode structure includes an N-type buffer layer (9), an anode P+ region (10) located above the N-type buffer layer (9), and an anode N+ region (11) spaced apart from the N-type buffer layer (9) by a distance L A wherein the N-type buffer layer (9) is in contact with the N top layer (12); a second conductive material (83) is led out from the surface of the anode P+ region (10), and a third conductive material (84) is led out from the surface of the anode N+ (11), and the second conductive material (83) and the third conductive material (84) serve as anode electrodes; A first P buried layer (13) is provided below the N top layer (12). The upper surface of the first P buried layer (13) is in contact with the N top layer (12), and there are spacings between the two ends of the first P buried layer (13) and the P-type well region (4) and the N-type buffer layer (9) respectively; a second P buried layer (14) is provided between the N-type buffer layer (9) and the anode N+ region (11), and the junction depths of the upper and lower surfaces of the second P buried layer (14) are the same as those of the upper and lower surfaces of the first P buried layer (13).

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