IGBT device and preparation method thereof

Abstract

The invention relates to an IGBT (Insulated Gate Bipolar Translator) device and a preparation method thereof, and the preparation method comprises the steps: forming a plurality of gate grooves and a plurality of dummy grooves located between the gate grooves in a substrate, and enabling the distance between the adjacent dummy grooves to be smaller than the distance between the gate grooves and the adjacent dummy grooves; a gate structure is formed in the gate trench, a false gate structure is formed in the false trench, and the top surfaces of the gate structure and the false gate structure are both lower than the top surface of the substrate; forming a body region in the substrate; forming an emitter region in the body region between the gate structure and the adjacent dummy gate structure; performing a thermal oxidation process to oxidize the substrate material between the dummy gate structures and higher than the top surfaces of the dummy gate structures and the substrate material of partial thickness of the top surface and the side surface of the emitter region into silicon oxide layers; removing part of the silicon oxide layer until the top surface of the residual emitter region is exposed; removing a part of the emitter region through self-alignment etching, and forming an emitter contact hole in the emitter region; and forming an emitter metal layer in the emitter contact hole. The position precision of the emitter contact hole is improved, and a compromise curve is optimized.

Description

Technical Field

[0001] This application relates to the field of manufacturing semi-power devices, and particularly to an IGBT device and a manufacturing method thereof. Background Art

[0002] As a hybrid power device, an IGBT (Insulated Gate Bipolar Transistor) device has the characteristics of an MOS structure input and a bipolar structure output. Therefore, it has the advantages of high input impedance of MOSFET, low power of the drive circuit, simple drive, fast switching speed, and low switching loss, as well as the advantages of high current density of bipolar power transistors, strong current handling capacity, and low on-state saturation voltage. Since the early 1980s, it has been widely studied at home and abroad. Currently, domestic IGBT devices have made breakthroughs in the fields of home appliances, industrial control, and new energy. At the current stage, the IGBT device layouts of various companies have entered the automotive field.

[0003] After nearly forty years of development, IGBT devices have evolved from planar type to trench type. However, as the size of the cell (the smallest repeating unit) becomes smaller and smaller, during the process of manufacturing IGBT devices, when forming the emitter contact holes, if there is an alignment offset or insufficient alignment accuracy in the photomask, the positions of the emitter contact holes formed after corresponding photolithography and etching will also shift, affecting the position accuracy of the emitter contact holes, and the comprehensive performance of IGBT devices still needs to be improved. Summary of the Invention

[0004] Based on this, this application provides an IGBT device with a semiconductor structure and a manufacturing method thereof to improve the position accuracy of forming emitter contact holes and enhance the comprehensive performance of IGBT devices.

[0005] In a first aspect, an embodiment of this application provides a manufacturing method of an IGBT device, including:

[0006] Providing a substrate, the substrate includes a top surface and a back surface that face away from each other;

[0007] Forming a plurality of gate trenches and a plurality of dummy trenches located between two adjacent gate trenches in the substrate. The gate trenches and the dummy trenches penetrate the top surface of the substrate, and the first distance between two adjacent dummy trenches is less than the second distance between a gate trench and an adjacent dummy trench;

[0008] Forming a gate structure in the gate trenches and a dummy gate structure in the dummy trenches, and the top surfaces of the gate structure and the dummy gate structure are both lower than the top surface of the substrate;

[0009] Forming body regions in the substrate on both sides of the gate structure and in the substrate on both sides of the dummy gate structure;

[0010] An emitter region is formed in the body region between the gate structure and the adjacent dummy gate structure. The top surface of the emitter region is flush with the top surface of the substrate, and the bottom surface of the emitter region is lower than the top surface of the gate structure.

[0011] A thermal oxidation process is performed to oxidize the substrate material between the dummy gate structures and above the top surface of the dummy gate structures, as well as a part of the thickness of the top surface and side surfaces of the emitter region into a silicon oxide layer.

[0012] A dielectric layer is formed on the silicon oxide layer.

[0013] Part of the dielectric layer and the silicon oxide layer are etched away until the top surface of the remaining emitter region is exposed.

[0014] Using the etched silicon oxide layer and dielectric layer as a mask, part of the remaining emitter region is etched away self-alignedly to form an emitter contact hole in the remaining emitter region.

[0015] An emitter metal layer is formed in the emitter contact hole and on the top surfaces of the etched silicon oxide layer and dielectric layer.

[0016] In some embodiments of the present application, the range of the first spacing is 0.2 μm to 0.4 μm, and the range of the second spacing is 0.6 μm to 0.9 μm.

[0017] In some embodiments of the present application, the depth of the gate trench is the same as the depth of the dummy trench, and the width of the gate trench is the same as the width of the dummy trench; the depth range of the gate trench and the dummy trench is 3 μm to 6 μm, and the width range of the gate trench and the dummy trench is 0.3 μm to 0.7 μm.

[0018] In some embodiments of the present application, the number of dummy trenches between adjacent gate trenches is 2 - 7.

[0019] In some embodiments of the present application, the distance by which the top surfaces of both the gate structure and the dummy gate structure are lower than the top surface of the substrate is greater than 0.3 μm.

[0020] In some embodiments of the present application, the thickness of the silicon oxide layer is 3000 Å - 4000 Å.

[0021] In some embodiments of the present application, the thermal oxidation process includes a furnace tube oxidation process. The atmosphere of the furnace tube oxidation process is oxygen, and the temperature range is 1000 °C to 1200 °C.

[0022] In some embodiments of the present application, after the thermal oxidation process, the top surface of the substrate between two adjacent dummy gate structures is lower than the top surface of the remaining emitter region, and the height difference between the top surface of the remaining emitter region and the top surface of the substrate between two adjacent dummy gate structures is greater than 0.15 μm.

[0023] After performing the thermal oxidation process, the remaining emitter region has a trapezoidal or trapezoid-like cross-sectional shape in the direction perpendicular to the top surface of the substrate.

[0024] In some embodiments of the present application, the depth of the emitter contact hole is greater than the depth of the emitter region;

[0025] After forming the emitter contact hole, it further includes: performing hole implantation, and the type of impurity ions implanted in the hole is the same as the doping type of the body region.

[0026] In a second aspect, embodiments of the present application further provide an IGBT device, including:

[0027] A substrate, the substrate includes a top surface and a back surface that are opposite to each other;

[0028] A plurality of gate trenches located in the substrate and a plurality of dummy trenches located between two adjacent gate trenches, the gate trenches and the dummy trenches penetrate the top surface of the substrate, and the first distance between two adjacent dummy trenches is less than the second distance between the gate trench and the adjacent dummy trench;

[0029] A gate structure located in the gate trench, a dummy gate structure located in the dummy trench, and the top surfaces of the gate structure and the dummy gate structure are both lower than the top surface of the substrate;

[0030] Body regions located in the substrate on both sides of the gate structure and in the substrate on both sides of the dummy gate structure;

[0031] An emitter region located in the body region between the gate structure and the adjacent dummy gate structure, the top surface of the emitter region is flush with the top surface of the substrate, and the bottom surface of the emitter region is lower than the top surface of the gate structure;

[0032] A silicon oxide layer covering the side surface of the emitter region, and the top surfaces of the gate structure and the dummy gate structure, and the silicon oxide layer exposes the top surface of the emitter region;

[0033] A dielectric layer located on a part of the silicon oxide layer, and the dielectric layer exposes the top surface of the emitter region;

[0034] An emitter contact hole located in the emitter region;

[0035] An emitter metal layer located in the emitter contact hole, on the top surface of the dielectric layer, and on the top surfaces of a part of the silicon oxide layer.

[0036] Embodiments of the present application may / at least have the following advantages:

[0037] In the IGBT device and its manufacturing method according to the embodiments of the present application, a plurality of gate trenches and a plurality of dummy trenches located between two adjacent gate trenches are formed in a substrate. The gate trenches and the dummy trenches penetrate the top surface of the substrate, and a first distance between two adjacent dummy trenches is smaller than a second distance between a gate trench and an adjacent dummy trench. Then, a gate structure is formed in the gate trench, and a dummy gate structure is formed in the dummy trench, and the top surfaces of the gate structure and the dummy gate structure are both lower than the top surface of the substrate; a body region is formed in the substrate on both sides of the gate structure and in the substrate on both sides of the dummy gate structure; an emitter region is formed in the body region between the gate structure and an adjacent dummy gate structure, the top surface of the emitter region is flush with the top surface of the substrate, and the bottom surface of the emitter region is lower than the top surface of the gate structure; a thermal oxidation process is performed to oxidize the substrate material between the dummy gate structures and higher than the top surface of the dummy gate structures and a part of the thickness of the top surface and the side surfaces of the emitter region into a silicon oxide layer; a dielectric layer is formed on the silicon oxide layer; part of the dielectric layer and the silicon oxide layer are etched away until the top surface of the remaining emitter region is exposed; using the etched silicon oxide layer and dielectric layer as a mask, part of the remaining emitter region is etched away self-alignedly to form an emitter contact hole in the remaining emitter region; an emitter metal layer is formed in the emitter contact hole and on the top surfaces of the etched silicon oxide layer and dielectric layer.In this application, since the first spacing between two adjacent dummy trenches is smaller than the second spacing between the gate trench and the adjacent dummy trench, on the one hand, the layout of adjacent dummy trenches and the layout between the dummy trenches and the gate trench are optimized, that is, the layout between the dummy gate structures formed in the subsequent dummy trenches and the gate structure formed in the gate trench is optimized, which is beneficial to optimizing the trade-off curve of the IGBT device, thereby improving the comprehensive performance of the IGBT device; on the other hand, the width of the substrate material between two adjacent dummy trenches is smaller than the width of the substrate material between the gate trench and the adjacent dummy trench. When performing the thermal oxidation process to form the silicon oxide layer, when forming the silicon oxide layer, all or most of the substrate material between the dummy gate structures and above the top surface of the dummy gate structures will be oxidized. At the same time, only a partial thickness of the substrate material on the top surface and side surface of the emitter region is oxidized, so that only a partial thickness of the silicon oxide layer needs to be removed during etching to expose the remaining top surface of the emitter region. At the same time, the region between the dummy gate structures is still covered by the silicon oxide layer. After that, using the remaining silicon oxide layer as a mask, part of the remaining emitter region can be etched self-alignedly to form an emitter contact hole in the remaining emitter region. Therefore, in this application, the emitter contact hole can be formed self-alignedly (without using a lithography process or a photomask), thereby preventing the position offset of the emitter contact hole caused by the alignment offset or insufficient alignment accuracy of the photomask (especially when the size of the emitter contact hole is small), improving the position accuracy of the formed emitter contact hole, and avoiding the misconnection between the emitter metal layer formed by the emitter contact hole and the gate structure when the emitter contact hole position offset exposes the gate structure, thereby avoiding the impact on the comprehensive performance of the IGBT device. At the same time, during the self-aligned etching, no emitter contact hole will be formed in the silicon oxide layer in the region between the dummy gate structures, ensuring the integrity of the silicon oxide layer in the region between the dummy gate structures, which is beneficial to optimizing the trade-off curve of the IGBT device and further improving the comprehensive performance of the IGBT device; on the other hand, all or most of the substrate material between the dummy gate structures and above the top surface of the dummy gate structures will be oxidized into a silicon oxide layer, making the thickness of the silicon oxide layer on the dummy gate structure more reasonable, which is also beneficial to optimizing the trade-off curve of the IGBT device and further improving the comprehensive performance of the IGBT device.

[0038] Details of one or more embodiments of this application are set forth in the following drawings and description. Other features, objects, and advantages of this application will become apparent from the specification, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] To more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the accompanying drawings required for use in the embodiments. Obviously, the accompanying drawings described below are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can be obtained based on these drawings.

[0040] Figure 1 Schematic cross-sectional structure diagram after providing a substrate in a method for manufacturing an IGBT device provided by some embodiments of the present application;

[0041] Figure 2 Schematic cross-sectional structure diagram after forming a gate trench and a dummy trench in a method for manufacturing an IGBT device provided by some embodiments of the present application;

[0042] Figure 3 Schematic cross-sectional structure diagram after forming a gate structure and a dummy gate structure in a method for manufacturing an IGBT device provided by some embodiments of the present application;

[0043] Figure 4 Schematic cross-sectional structure diagram after forming a body region and an emitter region in a method for manufacturing an IGBT device provided by some embodiments of the present application;

[0044] Figure 5 Schematic cross-sectional structure diagram after performing a thermal oxidation process in a method for manufacturing an IGBT device provided by some embodiments of the present application;

[0045] Figure 6 Schematic cross-sectional structure diagram after forming a dielectric layer in a method for manufacturing an IGBT device provided by some embodiments of the present application;

[0046] Figure 7 Schematic cross-sectional structure diagram after etching a dielectric layer and a silicon oxide layer in a method for manufacturing an IGBT device provided by some embodiments of the present application;

[0047] Figure 8 Schematic cross-sectional structure diagram after forming an emitter contact hole in a method for manufacturing an IGBT device provided by some embodiments of the present application;

[0048] Figure 9 Schematic cross-sectional structure diagram after forming an emitter metal layer in a method for manufacturing an IGBT device provided by some embodiments of the present application;

[0049] Figure 10 Schematic cross-sectional structure diagram after forming a back gold in a method for manufacturing an IGBT device provided by some embodiments of the present application;

[0050] Figure 11Comparison chart of breakdown voltage curves of the IGBT device of this embodiment and the IGBT device in the comparative example provided by some embodiments of this application;

[0051] Figure 12 Comparison chart of output curves of the IGBT device of this embodiment and the IGBT device in the comparative example provided by some embodiments of this application;

[0052] Figure 13 Comparison chart of switching curves of the IGBT device of this embodiment and the IGBT device in the comparative example provided by some embodiments of this application;

[0053] Figure 14 Comparison chart of trade-off curves of the IGBT device of this embodiment and the IGBT device in the comparative example provided by some embodiments of this application.

[0054] Explanation of reference numerals:

[0055] Substrate - 101; Gate trench - 102; False trench - 103; Gate dielectric layer - 104; Gate electrode - 105; False gate electrode - 106; Body region - 107; Emitter region - 108; Silicon oxide layer - 109; Dielectric layer - 110; Emitter contact hole - 111; Emitter metal layer - 112; Back metal - 113;

[0056] First pitch - P1; Second pitch - P2. Detailed implementation manners

[0057] To facilitate the understanding of this application, the following will describe this application more comprehensively with reference to relevant attached drawings. Embodiments of this application are given in the attached drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of this application more thorough and comprehensive.

[0058] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0059] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to", or "coupled to" another element or layer, it can be directly on, adjacent to, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on", "directly adjacent to", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Thus, a first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion without departing from the teachings of the present application.

[0060] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. may be used herein to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatial relationship terms also include different orientations of the devices during use and operation. For example, if the device in the figures is flipped, an element or feature described as "under" or "beneath" or "below" other elements or features will be oriented "on" the other elements or features. Thus, the exemplary terms "under" and "below" may include both an upper and a lower orientation. Additionally, the device may also include other orientations (such as, rotated 90 degrees or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.

[0061] As used herein, the singular forms "a", "an", and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprises / comprising", "has / including", etc. specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Also, within this specification, the term "and / or" includes any and all combinations of the associated listed items.

[0062] The structure of the embodiments of the present application should not be limited to the specific shapes shown in the drawings of the specification, but includes shape deviations caused by, for example, manufacturing techniques.

[0063] It can be understood that in the accompanying drawings of the specification of the present application, adjacent film layers with the same processed film layer material are drawn as connected in some figures to make them closer to the actual structure.

[0064] The conventional method for manufacturing an IGBT device generally includes: providing a substrate, the substrate including a top surface and a back surface that face away from each other; forming a plurality of gate trenches in the substrate; forming a gate structure in the gate trenches; forming body regions in the substrate on both sides of the gate structure; forming emitter regions in the body regions; forming a dielectric layer on the top surface of the substrate; forming emitter contact holes in the dielectric layer, the emitter contact holes exposing part of the emitter regions; and forming an emitter metal layer in the emitter contact holes and on the top surface of the dielectric layer. As the size of the IGBT device continues to decrease, the size of the corresponding emitter contact holes continues to decrease, which requires a higher alignment accuracy for the photomask used to form the emitter contact holes. If the alignment accuracy of the photomask is insufficient, the position of the formed emitter contact holes will shift (for example, if the position of the emitter contact holes shifts to expose the gate structure, it will cause the emitter metal layer formed by the emitter contact holes to be misconnected to the gate structure), affecting the comprehensive performance of the IGBT device.

[0065] Moreover, the trade-off curve is one of the important ways to characterize the comprehensive performance of an IGBT device. The trade-off curve depicts the curve between the on-state voltage representing the static power consumption of the IGBT device and the off-state energy consumption representing the dynamic power consumption of the IGBT device. However, the comprehensive performance or the trade-off curve of the existing IGBT devices still needs to be optimized.

[0066] Therefore, the embodiments of the present application first provide a method for manufacturing an IGBT device. Figures 1 - 10 Schematic cross-sectional structures of various stages in a method for manufacturing an IGBT device provided in some embodiments of the present application.

[0067] Refer to Figure 1 , provide a substrate 101, the substrate 101 including a top surface and a back surface that face away from each other.

[0068] The material of the substrate 101 may include silicon (Si), germanium (Ge), silicon germanium (GeSi), silicon carbide (SiC); or may also include other materials, such as group III-V compounds such as gallium arsenide. In some embodiments, the substrate 101 may include a semiconductor substrate and a semiconductor epitaxial layer located on the top surface of the semiconductor substrate, and the materials of the semiconductor substrate and the semiconductor epitaxial layer are both semiconductor materials. For example, the materials of the semiconductor substrate and the semiconductor epitaxial layer may both be silicon (Si) or silicon carbide (SiC).

[0069] The substrate 101 may also be implanted with certain doping ions to change electrical parameters according to design requirements, such as forming a carrier storage layer of an IGBT device. The concentration and depth of the doping ions in the substrate 101 depend on the withstand voltage requirements of the IGBT device. In some embodiments, when an N-type IGBT device is formed, the substrate 101 may be doped with N-type impurity ions, and the N-type impurity ions include one or more of phosphorus ions, arsenic ions, or antimony ions. In one example, the N-type impurity ions implanted into the substrate 101 by the ion implantation process are phosphorus ions, and the implantation dose range of the ion implantation is 2e12 atom / cm 2 ~3e13atom / cm 2 , the implantation energy range is 80keV~2MeV, a push process is performed after ion implantation to activate the implanted ions, the temperature range of the push process is 1050℃~1250℃, and the time range of the push process is 30 min~300 min. In other embodiments, when forming a P-type IGBT device, the substrate 101 can be doped with P-type impurity ions, and the P-type impurity ions include one or more of boron ions, gallium ions or indium ions.

[0070] refer to Figure 2 A plurality of gate trenches 102 and a plurality of dummy trenches 103 located between two adjacent gate trenches 102 are formed in the substrate 101. The gate trenches 102 and the dummy trenches 103 penetrate the top surface of the substrate 101, and a first spacing P1 between two adjacent dummy trenches 103 is smaller than a second spacing P2 between a gate trench 102 and the adjacent dummy trenches 103.

[0071] A gate structure is subsequently formed in the gate trench 102, and a dummy gate structure is subsequently formed in the dummy trench 103. By forming the dummy trench 102 and the subsequent dummy gate structure, the on-state voltage drop and conductivity modulation capability of the IGBT device can be adjusted, and the switching rate of the IGBT device when it is turned on and off can be adjusted.

[0072] In some embodiments, the substrate 101 may include a cell region, and the cell region includes a plurality of repeating unit regions 21 . Each repeating unit region 21 is used to form a minimum repeating unit structure (pitch) of an IGBT device. Figure 2 Only one repeating unit region 21 of the cell region is shown as an example for explanation.

[0073] The number of the gate trenches 102 is at least 2, and specifically may be 2, 3 or more. Figure 2 In the description, the number of gate trenches 102 is 2 as an example. The number of dummy trenches 103 between two adjacent gate trenches 102 is at least 2. In some embodiments, the number of dummy trenches between two adjacent gate trenches is 2-7, specifically 2, 3, 4, 5, 6, 7.Figure 2 Taking the number of the grid trenches 102 as 3 as an example for illustration.

[0074] A plurality of dummy trenches 103 are arranged at equal intervals in sequence along the connection line between the centers of two adjacent grid trenches 102. The first distance P1 between two adjacent dummy trenches 103 is less than the second distance P2 between the grid trench 102 and the adjacent dummy trench 103. On the one hand, the layout of adjacent dummy trenches 103 and the layout between the dummy trenches 103 and the grid trenches 102 are optimized, that is, the layout between the dummy gate structures formed in the subsequent dummy trenches and the gate structure formed in the grid trench 102 is optimized, which is beneficial to improving and optimizing the comprehensive performance or trade-off curve of the IGBT device, thereby improving the comprehensive performance of the IGBT device; on the other hand, the width of the substrate material between two adjacent dummy trenches 103 is smaller than the width of the substrate material between the grid trench 102 and the adjacent dummy trench 103. When the thermal oxidation process is carried out subsequently, when the silicon oxide layer 109 is formed, most (more than 90%) or all of the substrate material between the dummy gate structures (the dummy gate structures are formed in the dummy trenches 103 and include the gate dielectric layer 104 and the dummy gate electrode 106, refer to Figure 5 ) and above the top surface of the dummy gate structure will be oxidized, and only a partial thickness of the substrate material on the top surface and the side surface of the emitter region 108 (refer to Figure 5 ) will be oxidized (refer to Figure 5 ). When etching subsequently, only a partial thickness of the silicon oxide layer 109 needs to be removed to expose the top surface of the remaining emitter region 108 (refer to Figure 7 ). At the same time, the region between the dummy gate structures is still covered by the silicon oxide layer 109. After that, taking the remaining silicon oxide layer 109 as a mask, part of the remaining emitter region 108 can be etched self-alignedly to form an emitter contact hole 111 in the remaining emitter region 108 (refer to Figure 8), so that in the present application, the emitter contact hole 111 can be formed in a self-aligned manner (without using a photolithography process or a photomask), thereby preventing the position shift of the emitter contact hole 111 caused by the alignment offset or insufficient alignment accuracy of the photomask (especially when the size of the emitter contact hole 111 is small), improving the position accuracy of the formed emitter contact hole 111, and avoiding the misconnection between the emitter metal layer formed by the emitter contact hole 111 and the gate structure when the emitter contact hole 111 is offset in position and exposes the gate structure, thereby avoiding the impact on the comprehensive performance of the IGBT device. At the same time, during self-aligned etching, no emitter contact hole is formed in the silicon oxide layer 109 in the region between the dummy gate structures, ensuring the integrity of the silicon oxide layer 109 in the region between the dummy gate structures, which is beneficial to optimizing the trade-off curve of the IGBT device and further improving the comprehensive performance of the IGBT device; on the other hand, the substrate material between the dummy gate structures (the dummy gate structures are formed in the dummy trenches 103 and include a gate dielectric layer 104 and dummy gate electrodes 106, refer to Figure 5 ), and most or all of the substrate material between the dummy gate structures and higher than the top surface of the dummy gate structures will be oxidized into the silicon oxide layer 109, making the thickness of the silicon oxide layer on the dummy gate structures more reasonable, which is also beneficial to optimizing the trade-off curve of the IGBT device and further improving the comprehensive performance of the IGBT device.

[0075] In one embodiment, the range of the first spacing is 0.2 micrometers to 0.4 micrometers, and the range of the second spacing is 0.6 micrometers to 0.9 micrometers. When the subsequent thermal oxidation process is carried out, the formed silicon oxide layer 109 covering the dummy gate structures can have a sufficient and reasonable thickness, and at the same time, the remaining emitter region 108 can maintain a sufficient height and width, which is more conducive to improving and optimizing the comprehensive performance or trade-off curve of the IGBT device. And in one embodiment, the depth of the gate trench 102 is the same as the depth of the dummy trench 103, and the width of the gate trench 102 is the same as the width of the dummy trench 103. In a specific example, the depth range of the gate trench 102 and the dummy trench 103 is 3 micrometers to 6 micrometers, and the width range of the gate trench 102 and the dummy trench 103 is 0.3 micrometers to 0.7 um, so as to realize a micro-trench IGBT device and improve the comprehensive performance of the IGBT device.

[0076] In some embodiments, an anisotropic dry etching process can be used to etch the substrate 101 to form the gate trench 102 and the dummy trench 103. The anisotropic dry etching process includes an anisotropic plasma etching process, such as the Bosch etching process.

[0077] Refer to Figure 3 , a gate structure is formed in the gate trench 102, a dummy gate structure is formed in the dummy trench 103, and the top surface of the gate structure and the top surface of the dummy gate structure are both lower than the top surface of the substrate.

[0078] Specifically, the gate structure includes a gate dielectric layer 104 on the inner wall surface of the gate trench 102 and a gate electrode 105 on the surface of the gate dielectric layer 104 filling the gate trench 102. The dummy gate structure includes a gate dielectric layer 104 on the inner wall surface of the dummy trench 103 and a dummy gate electrode 106 on the surface of the gate dielectric layer 104 filling the dummy trench 103.

[0079] The material of the gate dielectric layer 104 is silicon oxide, which is formed by thermal oxidation of the substrate 101. The formed gate dielectric layer 104 is not only located on the inner walls of the gate trench 102 and the dummy trench 103, but also on the top surface of the substrate 101. The materials of the gate electrode 105 and the dummy gate electrode 106 are polysilicon, which are formed by a deposition process and an etch-back process. Specifically, a polysilicon layer filling the gate trench 102 and the dummy trench 103 is formed on the surface of the gate dielectric layer 104 by the deposition process. The deposition process can be plasma enhanced chemical vapor deposition (PECVD) or low pressure chemical vapor deposition (LPCVD); part of the polysilicon layer is removed by etch-back to form the gate electrode 105 in the gate trench 102 and the dummy gate electrode 106 in the dummy trench 103. The top surfaces of the gate electrode 105 and the dummy gate electrode 106 are lower than the top surface of the substrate 101.

[0080] In some embodiments, the distances from the top surfaces of the gate structure (gate electrode 105) and the dummy gate structure (dummy gate electrode 106) to the top surface of the substrate 101 are both greater than 0.3 microns, so that the thickness of the silicon oxide layer 109 formed by oxidation (refer to Figure 9 ) can be maintained thick enough to reduce the forward and reverse leakage between the gate and the emitter.

[0081] In some embodiments, the silicon oxide layer 109 covering the dummy gate structure and the regions between the dummy gate structures is complete (no contact holes are formed in the silicon oxide layer 109), which is beneficial to optimizing the trade-off curve of the IGBT device and further improving the comprehensive performance of the IGBT device. In other embodiments, the dummy gate electrode 106 can be electrically connected to the emitter region subsequently, or the dummy gate electrode 106 can be electrically connected to the gate electrode 105 subsequently, or the dummy gate electrode 106 can also be floating.

[0082] Refer to Figure 4 , and body regions 107 are formed in the substrate 101 on both sides of the gate structure (including the gate dielectric layer 104 and the gate electrode 105) and in the substrate 101 on both sides of the dummy gate structure (including the gate dielectric layer 104 and the dummy gate electrode 106).

[0083] The body region 107 is formed in the substrate 101, and the doping type of the body region 107 is opposite to that of the substrate 101. In one example, the IGBT device is of N-type, the doping type of the substrate 101 is N-type, and the corresponding doping type of the body region 107 is P-type. In another example, the IGBT device is of P-type, the doping type of the substrate 101 is P-type, and the corresponding doping type of the body region 107 is N-type.

[0084] The depth of the body region 107 is less than the depth of the gate trench 102 and less than the depth of the dummy trench 103. The body region 107 is formed by an ion implantation process. In some embodiments, P-type impurity ions are implanted into the substrate 101 by an ion implantation process to form the body region 107. The P-type impurity ions include one or several of boron ions, gallium ions, or indium ions. In one example, the P-type impurity ions implanted by ion implantation are boron ions, the implantation energy range is 60 keV to 200 keV, and the implantation dose range is 4e13 atom / cm 2 ~1.2e14 atom / cm 2 , and after ion implantation, a body region drive-in process is performed to activate the implanted ions. The temperature range of the drive-in process is 1100 °C to 1250 °C, and the time range of the drive-in process is 30 min to 120 min. In other embodiments, N-type impurity ions are implanted into the substrate 101 by an ion implantation process to form the body region 107. The N-type impurity ions include one or several of phosphorus ions, arsenic ions, or antimony ions.

[0085] In some embodiments, the depth of the body region 107 in the substrate 101 on both sides of the dummy gate structure (including the gate dielectric layer 104 and the dummy gate electrode 106) is less than the depth of the body region in the substrate 101 on both sides of the gate structure (including the gate dielectric layer 104 and the gate electrode 105). The reason is that the width of the substrate 101 on both sides of the dummy gate structure is less than that of the substrate 101 on both sides of the gate structure, and the number of impurity ions in the substrate 101 on both sides of the dummy gate structure during ion implantation is less than that in the substrate 101 on both sides of the gate structure. After the drive-in process, the depth of the body region 107 in the substrate 101 on both sides of the dummy gate structure will be less than the depth of the body region in the substrate 101 on both sides of the gate structure.

[0086] Continuing to refer to Figure 4 , an emitter region 108 is formed in the body region 107 between the gate structure (including the gate dielectric layer 104 and the gate electrode 105) and the adjacent dummy gate structure (including the gate dielectric layer 104 and the dummy gate electrode 106). The top surface of the emitter region 108 is flush with the top surface of the substrate 101, and the bottom surface of the emitter region 108 is lower than the top surface of the gate structure (gate electrode 105).

[0087] The doping type of the emitter region 108 is opposite to that of the body region 107. In one example, the IGBT device is of N-type, the doping type of the body region 107 is P-type, and correspondingly, the doping type of the emitter region 108 is N-type. In another example, the IGBT device is of P-type, the doping type of the body region 107 is N-type, and correspondingly, the doping type of the emitter region 108 is P-type.

[0088] The emitter region 108 is formed by an ion implantation process. Before the ion implantation process, a patterned mask layer is formed on the top surface of the substrate 101, and the patterned mask layer exposes the region to be implanted. In some embodiments, an N-type impurity ion is implanted into the body region 107 between the gate structure and the adjacent dummy gate structure by an ion implantation process to form the emitter region 108. The N-type impurity ions include one or several of phosphorus ions, arsenic ions, or antimony ions. In one example, the N-type impurity ions implanted by ion implantation are phosphorus ions, the implantation energy range is 90 keV to 200 keV, and the implantation dose range is 5e15 atom / cm 2 ~2e16 atom / cm 2 , and during the subsequent thermal oxidation process, the implanted impurity ions are activated and pushed forward. In other embodiments, a P-type impurity ion is implanted into the body region 107 between the gate structure and the adjacent dummy gate structure by an ion implantation process to form the emitter region 108. The P-type impurity ions include one or several of boron ions, gallium ions, or indium ions.

[0089] Reference Figure 5 , perform a thermal oxidation process to oxidize the substrate material between the dummy gate structures (including the gate dielectric layer 104 and the dummy gate electrode 106) and above the top surface of the dummy gate structure (dummy gate electrode 106), as well as a part of the thickness of the top surface and side surfaces of the emitter region 108 into a silicon oxide layer 109.

[0090] Since the width of the substrate material between two adjacent dummy trenches is smaller than the width of the substrate material between the gate trench and the adjacent dummy trench, when most or all of the substrate material between the dummy gate structures (including the gate dielectric layer 104 and the dummy gate electrode 106) and above the top surface of the dummy gate structure (dummy gate electrode 106) is oxidized, only a part of the thickness of the substrate material on the top surface and side surfaces of the emitter region 108 is oxidized, that is, a part of the emitter region 108 remains unoxidized. Therefore, only a part of the thickness of the silicon oxide layer 109 needs to be removed subsequently to expose the top surface of the remaining emitter region 108 (reference Figure 7 ), and at the same time, the region between the dummy gate structures and the dummy gate structures is still covered by the silicon oxide layer 109. After that, using the remaining silicon oxide layer 109 as a mask, a part of the remaining emitter region 108 can be etched away self-alignedly to form an emitter contact hole 111 in the remaining emitter region 108 (reference Figure 8), that is, in the present application, the emitter contact hole 111 can be formed in a self-aligned manner (without using a photolithography process or a photomask), thereby preventing the position shift of the emitter contact hole 111 caused by the alignment deviation or insufficient alignment accuracy of the photomask (especially when the size of the emitter contact hole 111 is small), and improving the position accuracy of the formed emitter contact hole 111; in addition, the dummy gate structure (the dummy gate structure is formed in the dummy trench 103, including the gate dielectric layer 104 and the dummy gate electrode 106, refer to Figure 5 ), the substrate material between them and above the top surface of the dummy gate structure will be mostly or completely oxidized into the silicon oxide layer 109, so that the thickness of the silicon oxide layer 109 on and between the dummy gate structures is thicker, which is also beneficial to improving and optimizing the comprehensive performance or trade-off curve of the IGBT device.

[0091] It should be noted that when forming the silicon oxide layer 109, the top surfaces of the dummy gate electrode 106 and the gate electrode 105 will also be oxidized into a silicon oxide layer, and the silicon oxide layer formed on the top surfaces of the dummy gate electrode 106 and the gate electrode 105 is used as a part of the silicon oxide layer 109.

[0092] In some embodiments, after the thermal oxidation process, the top surface of the substrate between two adjacent dummy gate structures is lower than the top surface of the remaining emitter region, and the height difference between the top surface of the remaining emitter region and the top surface of the substrate between two adjacent dummy gate structures is greater than 0.15 micrometers, so that the subsequent process of removing part of the dielectric layer 110 and the silicon oxide layer 109 until the top surface of the remaining emitter region 108 is exposed is better controlled, and the substrate between the dummy gate structures will not be exposed.

[0093] In some embodiments, the thermal oxidation process includes a furnace tube oxidation process, the atmosphere of the furnace tube oxidation process is oxygen, and the temperature range is 1000 degrees Celsius to 1200 degrees Celsius. In one example, the thickness of the formed silicon oxide layer 109 is 3000 angstroms to 4000 angstroms.

[0094] In some embodiments, after the thermal oxidation process, the cross-sectional shape of the remaining emitter region 108 along the direction perpendicular to the top surface of the substrate is trapezoidal or trapezoid-like (the oxidation rate at the top corner of the emitter region 108 is a little faster), and then part of the remaining emitter region 108 is removed by self-aligned etching to form the emitter contact hole 111 (refer to Figure 8 ), it is easier to make part of the emitter region 108 remain on both sides of the emitter contact hole 111 to serve as the emitter region of the IGBT device.

[0095] Refer to Figure 6 , a dielectric layer 110 is formed on the silicon oxide layer 109.

[0096] The purpose of forming the dielectric layer 110 is to fill the uneven areas (such as depressions) of the silicon oxide layer 109, so as to facilitate the subsequent etching steps.

[0097] The dielectric layer 110 can be a single-layer or multi-layer stacked structure. In some embodiments, the material of the dielectric layer 110 includes one or several of undoped silicon glass (USG), boron-doped silicon glass (BSG), phosphorus-doped silicon glass (PSG), and boron-phosphorus-doped silicon glass (BPSG). The thickness of the dielectric layer 110 is 8kA - 15kA. After forming the dielectric layer 110 by a deposition process, a reflow process is carried out. The temperature range of the reflow process is 900°C - 1000°C, and the time range is 30 min - 240 min.

[0098] Reference Figure 7 , etch away part of the dielectric layer 110 and the silicon oxide layer 109 until the top surface of the remaining emitter region 108 is exposed.

[0099] The etching uses anisotropic dry etching, such as anisotropic plasma etching process.

[0100] Reference Figure 8 , using the etched silicon oxide layer 109 and dielectric layer 110 as masks, self-alignedly etch away part of the remaining emitter region 108 to form emitter contact holes 111 in the remaining emitter region 108.

[0101] An emitter metal layer is subsequently formed in the emitter contact holes 111. In some embodiments, the depth of the formed emitter contact holes 111 is greater than the depth of the emitter region 108.

[0102] When self-alignedly etching away part of the remaining emitter region 108 to form emitter contact holes 111 in the remaining emitter region 108, no emitter contact holes will be formed in the silicon oxide layer 109 and dielectric layer 110 between the dummy gate structures. In some embodiments, the self-aligned etching includes an anisotropic plasma etching process, and the emitter region 108 material (substrate material) has a high etching selectivity relative to the silicon oxide layer 109 and dielectric layer 110 during the etching process of the anisotropic plasma etching process. In some embodiments, the sidewalls of the emitter contact holes 111 are inclined outward, and the inclination angle of the sidewalls of the emitter contact holes 111 is 7 degrees - 30 degrees, and the inclination angle is the angle between the sidewalls of the emitter contact holes 111 and the direction perpendicular to the top surface of the substrate.

[0103] In some embodiments, after forming the emitter contact hole 111, the following steps are further included: performing hole implantation. The type of impurity ions implanted in the hole is the same as the doping type of the body region 107, so as to reduce the contact resistance between the subsequently formed emitter metal layer and the body region 107. In one example, the impurity ions implanted in the hole are boron ions, the energy range of the hole implantation is 20 keV to 100 keV, and the implantation dose range is 1e13 atom / cm 2 -3e15atom / cm 2 .

[0104] Referring to Figure 9 , an emitter metal layer 112 is formed in the emitter contact hole and on the top surfaces of the etched silicon oxide layer 109 and the dielectric layer 110.

[0105] The material of the emitter metal layer 112 includes one or more of Cu, Al, W, Ag, Au, Pt, Ni, Ti, Ta, TiN, TaN, TaC, and WN.

[0106] In some embodiments, referring to Figure 10 , the following steps are further included: thinning the back surface of the substrate 101, and the thinning thickness depends on the breakdown voltage requirement of the IGBT device. In some embodiments, impurity ions are implanted into the back surface of the thinned substrate 101 to form a doped layer, and the doped layer serves as the collector. In one example, the implanted impurity ions are P-type impurity ions, and the P-type impurity ions include boron ions. The implantation energy range is 60 KeV - 20 KeV, and the implantation dose is 1e12 atom / cm 2 -1e14atom / cm 2 , and annealing is performed after implantation to activate the impurity ions. In some embodiments, the following steps are further included: injecting hydrogen or phosphorus or both hydrogen and phosphorus into the back surface of the substrate 101 and annealing to form a buffer layer. In some embodiments, the following steps are further included: forming a back gold 113 on the back surface of the substrate 101. The material of the back gold 113 includes one or more of Cu, Al, W, Ag, Au, Pt, Ni, Ti, Ta, TiN, TaN, TaC, and WN, and the back gold serves as the collector metal layer of the IGBT device.

[0107] The embodiments of the present application further provide an IGBT device, referring to Figure 10 , including:

[0108] A substrate 101, where the substrate 101 includes a top surface and a back surface that face away from each other;

[0109] A plurality of gate trenches 102 located in the substrate 101 and a plurality of dummy trenches 103 located between two adjacent gate trenches 102. The gate trenches 102 and the dummy trenches 103 penetrate the top surface of the substrate, and a first pitch P1 between two adjacent dummy trenches 103 is smaller than a second pitch P2 between the gate trench 102 and the adjacent dummy trench 103;

[0110] A gate structure (including a gate dielectric layer 104 and a gate electrode 105) located in the gate trench 102, and a dummy gate structure (including a gate dielectric layer 104 and a dummy gate electrode 106) located in the dummy trench 103. The top surfaces of the gate structure (gate electrode 105) and the dummy gate structure (dummy gate electrode 106) are both lower than the top surface of the substrate 101;

[0111] Bulk regions 107 in the substrate 101 on both sides of the gate structure and in the substrate 101 on both sides of the dummy gate structure;

[0112] An emitter region 108 in the bulk region 107 between the gate structure and the adjacent dummy gate structure. The top surface of the emitter region 108 is flush with the top surface of the substrate 101, and the bottom surface of the emitter region 108 is lower than the top surface of the gate structure (gate electrode 105);

[0113] A silicon oxide layer 109 covering the side surfaces of the emitter region 108 and the top surfaces of the gate structure and the dummy gate structure. The silicon oxide layer 109 exposes the top surface of the emitter region 108;

[0114] A dielectric layer 110 located on a part of the silicon oxide layer 109. The dielectric layer 110 exposes the top surface of the emitter region 108;

[0115] An emitter contact hole 111 located in the emitter region 108;

[0116] An emitter metal layer 112 located in the emitter contact hole 111 and on the top surfaces of the dielectric layer 110 and a part of the silicon oxide layer 109.

[0117] It should be noted that the limitations or descriptions of the same or similar parts in this embodiment (IGBT device) and the previous embodiment (manufacturing method of IGBT device) are not repeated in this embodiment. For details, please refer to the corresponding parts of the previous embodiment.

[0118] To further illustrate the performance of the IGBT device described in the previous embodiments of the present application and the IGBT device obtained by the previous manufacturing method, the relevant parameters of the IGBT device in the embodiments of the present application and the IGBT device in the comparative example are simulated and compared below, which should not be construed as a limitation on the protection scope of the present application.

[0119] The main differences between the IGBT device in the comparative example and the IGBT device in the foregoing embodiment of the present application (hereinafter referred to as this embodiment) are as follows: in the comparative example, the distance between two adjacent dummy trenches is equal to the distance between the gate trench and the adjacent dummy trench. In the comparative example, the emitter contact holes between the gate structure and the adjacent dummy gate structure are formed by photolithography and etching processes. In the comparative example, emitter contact holes are also formed between adjacent dummy gate structures.

[0120] Reference Figure 11 , Figure 11 is a comparison chart of the breakdown voltage curves of the IGBT device in this embodiment and the IGBT device in the comparative example, where the abscissa represents the breakdown voltage between the collector and the emitter during turn-off, and the ordinate represents the breakdown current between the collector and the emitter during turn-off. It can be seen from Figure 11 that the changing trends of the breakdown voltage curves of the IGBT device in this embodiment and the IGBT device in the comparative example are basically the same.

[0121] Reference Figure 12 , Figure 12 is a comparison chart of the output curves of the IGBT device in this embodiment and the IGBT device in the comparative example, where the abscissa represents the output voltage between the collector and the emitter during conduction, and the ordinate represents the output current between the collector and the emitter during conduction. It can be seen from Figure 12 that the on-resistance of the IGBT device in this embodiment is much smaller than that of the IGBT device in the comparative example, where the on-resistance is the ratio of the output voltage to the output current.

[0122] Reference Figure 13 , Figure 13 is a comparison chart of the switching curves of the IGBT device in this embodiment and the IGBT device in the comparative example, where the abscissa represents the switching time, the left ordinate represents the switching current, and the right ordinate represents the switching voltage. It can be seen from Figure 13 that there are certain differences in the switching speeds of the IGBT device in this embodiment and the IGBT device in the comparative example, but this does not affect the comprehensive performance of the IGBT device in this embodiment.

[0123] Reference Figure 14 , Figure 14 is a comparison chart of the trade-off curves of the IGBT device in this embodiment and the IGBT device in the comparative example, where the abscissa represents the on-stage voltage of the static power consumption, and the ordinate represents the Eoff of the dynamic power consumption. It can be seen from Figure 14 that the trade-off curve of the IGBT device in this embodiment is better than that of the IGBT device in the comparative example. The closer the trade-off curve is to the origin, the better.

[0124] In the description of this specification, the descriptions referring to terms such as "some embodiments", "other embodiments", "ideal embodiments", etc. mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0125] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0126] The above embodiments only represent several implementation manners of the present application, and the descriptions thereof are relatively specific and detailed, but should not be construed as a limitation on the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the appended claims.

Claims

1. A method for manufacturing an IGBT device, characterized in that, Comprising: Providing a substrate, the substrate including a top surface and a back surface that face away from each other; Forming a plurality of gate trenches and a plurality of dummy trenches between two adjacent ones of the gate trenches in the substrate, the gate trenches and the dummy trenches penetrating through the top surface of the substrate, and a first pitch between two adjacent ones of the dummy trenches being smaller than a second pitch between a gate trench and an adjacent dummy trench; Forming a gate structure in the gate trenches and forming a dummy gate structure in the dummy trenches, and a top surface of the gate structure and a top surface of the dummy gate structure both being lower than the top surface of the substrate; Forming body regions in the substrate on both sides of the gate structure and in the substrate on both sides of the dummy gate structure; Forming an emitter region in the body region between the gate structure and an adjacent dummy gate structure, a top surface of the emitter region being flush with the top surface of the substrate, and a bottom surface of the emitter region being lower than the top surface of the gate structure; Performing a thermal oxidation process to oxidize a substrate material between the dummy gate structures and above the top surface of the dummy gate structures and a partial thickness of the substrate material on the top surface and side surfaces of the emitter region into a silicon oxide layer; Forming a dielectric layer on the silicon oxide layer; Etching away a part of the dielectric layer and the silicon oxide layer until the top surface of the remaining emitter region is exposed; Using the etched silicon oxide layer and dielectric layer as a mask to self-alignedly etch away a part of the remaining emitter region to form an emitter contact hole in the remaining emitter region; Forming an emitter metal layer in the emitter contact hole and on the top surfaces of the etched silicon oxide layer and dielectric layer.

2. The manufacturing method of the IGBT device according to claim 1, characterized in that, The range of the first pitch is 0.2 micrometers to 0.4 micrometers, and the range of the second pitch is 0.6 micrometers to 0.9 micrometers.

3. The manufacturing method of the IGBT device according to claim 2, characterized in that, The depth of the gate trenches is the same as the depth of the dummy trenches, and the width of the gate trenches is the same as the width of the dummy trenches; the depth range of the gate trenches and the dummy trenches is 3 micrometers to 6 micrometers, and the width range of the gate trenches and the dummy trenches is 0.3 micrometers to 0.7 μm.

4. The manufacturing method of the IGBT device according to claim 1 or 3, characterized in that, The number of the dummy trenches between two adjacent ones of the gate trenches is 2 - 7.

5. The manufacturing method of the IGBT device according to claim 1, characterized in that, The distance by which the top surfaces of the gate structure and the dummy gate structure are lower than the top surface of the substrate is greater than 0.3 micrometers.

6. The manufacturing method of the IGBT device according to claim 5, characterized in that, The thickness of the silicon oxide layer is 3000 angstroms - 4000 angstroms.

7. The manufacturing method of the IGBT device according to claim 1, characterized in that, The thermal oxidation process includes a furnace tube oxidation process, the atmosphere of the furnace tube oxidation process being oxygen, and the temperature range being 1000 degrees Celsius to 1200 degrees Celsius.

8. The manufacturing method of the IGBT device according to claim 1, characterized in that, After performing the thermal oxidation process, the top surface of the substrate between two adjacent ones of the dummy gate structures is lower than the top surface of the remaining emitter region, and the height difference between the top surface of the remaining emitter region and the top surface of the substrate between two adjacent ones of the dummy gate structures is greater than 0.15 micrometers; After performing the thermal oxidation process, the cross-sectional shape of the remaining emitter region along a direction perpendicular to the top surface of the substrate is trapezoidal or quasi-trapezoidal.

9. The manufacturing method of the IGBT device according to claim 1, characterized in that, The depth of the emitter contact hole is greater than the depth of the emitter region; After forming the emitter contact hole, further comprising: performing a hole injection, the type of impurity ions of the hole injection being the same as the doping type of the body region.

10. An IGBT device, characterized in that, Comprising: A substrate, the substrate including a top surface and a back surface that face away from each other; A plurality of gate trenches located in the substrate and a plurality of dummy trenches located between two adjacent ones of the gate trenches, the gate trenches and the dummy trenches penetrate the top surface of the substrate, and a first pitch between two adjacent ones of the dummy trenches is smaller than a second pitch between the gate trench and an adjacent dummy trench; A gate structure located in the gate trench, a dummy gate structure located in the dummy trench, and the top surfaces of the gate structure and the dummy gate structure are both lower than the top surface of the substrate; Bulk regions in the substrate on both sides of the gate structure and in the substrate on both sides of the dummy gate structure; An emitter region in the bulk region between the gate structure and an adjacent dummy gate structure, the top surface of the emitter region is flush with the top surface of the substrate, and the bottom surface of the emitter region is lower than the top surface of the gate structure; A silicon oxide layer covering the side surface of the emitter region, and the top surfaces of the gate structure and the dummy gate structure, the silicon oxide layer exposes the top surface of the emitter region; A dielectric layer located on a part of the silicon oxide layer, the dielectric layer exposes the top surface of the emitter region; An emitter contact hole located in the emitter region; An emitter metal layer located in the emitter contact hole and on the top surface of the dielectric layer and the top surfaces of a part of the silicon oxide layer.

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