Semiconductor structure, preparation method thereof and electronic device

Abstract

The invention relates to the technical field of semiconductors, in particular to a semiconductor structure, a preparation method thereof and an electronic device, and the preparation method comprises the steps: providing a substrate which is provided with a channel layer and a first protection layer located on the channel layer; forming a first dielectric layer on one side, deviating from the channel layer, of the first protection layer; forming a trench structure penetrating through the first dielectric layer and the first protective layer, wherein the trench structure exposes the channel layer; forming a second protection layer in the groove structure; forming a second protection layer in the groove structure; and forming a second dielectric layer based on the second protective layer. The interface trap problem of the dielectric layer can be avoided, and the quality of the dielectric layer is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure, a preparation method thereof, and an electronic device. Background Art

[0002] In semiconductor devices such as transistors, a channel is usually formed on the substrate as a key channel for carrier movement. Traditional semiconductor devices usually use polysilicon as the channel layer material. However, with the development of technology, the demand for device miniaturization has increased, and the structure of semiconductor devices has continued to change. Advanced research uses semiconductor compounds as channel materials to generate compressive channel stress along the channel direction, thereby improving the carrier mobility in the channel and optimizing device performance. However, some semiconductor compounds have problems such as element diffusion. When an interface layer is formed on the channel layer, the diffusion of the channel material can easily induce interface traps (Dit) problems, thereby reducing device performance. Summary of the invention

[0003] In view of the above problems in the prior art, the present application provides a semiconductor structure, a preparation method thereof and an electronic device. The specific technical solutions are as follows:

[0004] In one aspect, the present application provides a method for preparing a semiconductor structure, the method comprising:

[0005] Providing a substrate, wherein the substrate has a channel layer and a first protective layer located on the channel layer;

[0006] forming a first dielectric layer on a side of the first protective layer away from the channel layer;

[0007] forming a trench structure penetrating the first dielectric layer and the first protective layer, wherein the trench structure exposes the channel layer;

[0008] forming a second protective layer in the trench structure;

[0009] A second dielectric layer is formed based on the second protective layer.

[0010] In a possible implementation manner, forming the second dielectric layer based on the second protective layer includes:

[0011] The second protective layer is used as the second dielectric layer; or,

[0012] The second protective layer is oxidized to obtain the second dielectric layer.

[0013] In a possible implementation manner, before forming the groove structure penetrating the first dielectric layer and the first protective layer, the preparation method further includes:

[0014] An isolation layer and a dummy structure located within the isolation layer are formed on a side of the first dielectric layer facing away from the first protective layer, the dummy structure penetrating the isolation layer and contacting the first dielectric layer;

[0015] The forming of the trench structure penetrating the first dielectric layer and the first protective layer includes:

[0016] The dummy structure, and regions of the first dielectric layer and the first protective layer corresponding to the dummy structure are removed to form the trench structure.

[0017] In a possible implementation manner, the removing the dummy structure, and regions of the first dielectric layer and the first protective layer corresponding to the dummy structure to form the trench structure includes:

[0018] The dummy structure, the region of the first dielectric layer corresponding to the dummy structure, and the region of the first protective layer corresponding to the dummy structure are etched until the channel layer is exposed to form the trench structure.

[0019] In a possible implementation manner, the removing the dummy structure, and regions of the first dielectric layer and the first protective layer corresponding to the dummy structure to form the trench structure includes:

[0020] The dummy structure and the region of the first dielectric layer corresponding to the dummy structure are etched until the first protective layer is exposed;

[0021] The exposed region of the first protective layer is oxidized to form an oxidation structure;

[0022] The oxidation structure is removed until the channel layer is exposed to form the trench structure.

[0023] In a possible implementation manner, the providing the substrate includes:

[0024] A semiconductor substrate is provided;

[0025] The channel layer is deposited on the semiconductor substrate;

[0026] The first protective layer is deposited on a side of the channel layer facing away from the semiconductor substrate.

[0027] In a possible implementation manner, after the second dielectric layer is formed based on the second protective layer, the manufacturing method further includes:

[0028] A gate structure is formed on the second dielectric layer.

[0029] In a possible implementation manner, sidewalls of the second protective layer cover sidewalls of the first protective layer.

[0030] In a possible implementation, the material of the channel layer forms a diffusion region in the first protective layer.

[0031] In a possible implementation, the preparation method satisfies at least one of the following characteristics:

[0032] The material of the first protective layer includes one or more of silicon, silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxycarbonitride, and silicon carbon oxynitride;

[0033] The material of the second protective layer includes at least one of silicon, silicon nitride, and silicon oxynitride.

[0034] In a possible implementation, the preparation method satisfies at least one of the following characteristics:

[0035] The thickness of the first protective layer is greater than or equal to 0.4 nm;

[0036] The thickness of the second protective layer is greater than or equal to 0.4 nm.

[0037] In a possible implementation, the second protective layer has the same material as the first protective layer.

[0038] In a possible implementation, the sidewall of the second protective layer covers the sidewall of the first protective layer.

[0039] In a possible implementation, the second dielectric layer and the first dielectric layer form a continuous structure.

[0040] In a possible implementation, the first dielectric layer and the second dielectric layer have the same material.

[0041] On the other hand, the present application provides a semiconductor structure, which can be obtained by using the above preparation method. The semiconductor structure includes:

[0042] A substrate having a channel layer and a first protective layer located on the channel layer;

[0043] A first dielectric layer located on a side of the first protective layer away from the channel layer;

[0044] A trench structure penetrating the first dielectric layer and the first protective layer and exposing the channel layer;

[0045] A second dielectric layer located in the trench structure.

[0046] In a possible implementation, the second dielectric layer and the first dielectric layer form a continuous structure.

[0047] In a possible implementation, the semiconductor structure further includes:

[0048] The gate structure is located on a side of the second dielectric layer away from the channel layer.

[0049] In a possible implementation manner, the material of the channel layer includes a III-V group semiconductor compound.

[0050] On the other hand, the present application provides an electronic device, including a semiconductor structure prepared by the above preparation method, or including the above semiconductor structure.

[0051] On the other hand, the present application provides an electronic device, including a semiconductor structure prepared by the above preparation method, or including the above semiconductor structure.

[0052] Based on the above technical solutions, the present application has the following beneficial effects:

[0053] The present application provides a substrate having a channel layer and a first protective layer located on the channel layer, and forms a first dielectric layer on a side of the first protective layer away from the channel layer; then forms a trench structure penetrating the first dielectric layer and the first protective layer and exposing the channel layer, forms a second protective layer in the trench structure and forms a second dielectric layer based on the second protective layer; thus, through the first protective layer as oxidation protection, the defects of the channel layer and the oxidation risk in the subsequent process are reduced, and the area of the first protective layer with channel diffusion pollution at a corresponding position is removed before the second dielectric layer needs to be formed, so as to regrow the second protective layer with almost no channel diffusion and form the second dielectric layer, that is, the Dit problem caused by directly growing an interface layer on the channel layer is solved, and at the same time, the influence of trench layer diffusion on the quality of the interface layer is avoided, a high-quality dielectric layer is formed, the device process difficulty is reduced, and the device performance is improved. Description of the Drawings

[0054] In order to more clearly illustrate the technical solutions of the present application, the following will briefly introduce the drawings required for use in the embodiments or the description of the prior art. Obviously, the following drawings are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0055] Figure 1 : Schematic diagram of a method for forming an interface layer of a semiconductor structure provided by the prior art;

[0056] Figure 2 : Schematic flow chart of a preparation method of a semiconductor structure provided by an embodiment of the present application;

[0057] Figure 3 : Cross-sectional view of a structure during the preparation of another semiconductor structure provided by an embodiment of the present application;

[0058] Figure 4: Cross-sectional view of the structure during the preparation of another semiconductor structure provided by an embodiment of the present application;

[0059] Figure 5 : Cross-sectional view of the structure during the preparation of another semiconductor structure provided by an embodiment of the present application;

[0060] Figure 6 : Cross-sectional view of the structure during the preparation of another semiconductor structure provided by an embodiment of the present application;

[0061] Figure 7 : Cross-sectional view of the structure during the preparation of another semiconductor structure provided by an embodiment of the present application;

[0062] Figure 8 : Cross-sectional view of the structure during the preparation of another semiconductor structure provided by an embodiment of the present application;

[0063] Figure 9 : Cross-sectional view of a semiconductor structure provided by an embodiment of the present application;

[0064] Reference numerals: 10 - SiGe channel, 20 - interface layer, 21 - Ge diffusion region, 100 - substrate, 101 - semiconductor substrate, 102 - channel layer, 103 - first protective layer, 201 - first dielectric layer, 202 - isolation layer, 203 - pseudo-structure, 204 - trench structure, 205 - functional component trench, 206 - second protective layer, 207 - oxidation structure, 209 - second dielectric layer, 210 - diffusion region. Detailed implementation manners

[0065] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without making creative efforts belong to the scope of protection of the present application.

[0066] It should be noted that in the description of the present application, for the following defined terms, unless a different definition is given elsewhere in the claims or in this specification, these definitions shall apply. All numerical values, whether or not explicitly indicated, are hereby defined as being modified by the term "about". The term "about" generally refers to a numerical range that those of ordinary skill in the art regard as equivalent to the stated value to produce substantially the same properties, functions, results, etc. A numerical range indicated by a lower value and a higher value is defined to include all the numerical values included in the numerical range and all the sub-ranges included in the numerical range.

[0067] It should be noted that in the description of the present application, the terms "first", "second", etc. are used to distinguish similar objects and do not necessarily describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances so that the embodiments of the present application described herein can be implemented in an order different from those illustrated or described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion.

[0068] It should be noted that in the description of the present application, the meanings of the terms "on", "above", "over", "upon" should be interpreted in the broadest sense, meaning that the description containing these terms is interpreted as "a component can be disposed on another component in a directly contacting manner, or there can be intermediate components or layers between the components". In addition, for the convenience of description, the present application may also use spatial relative terms such as "under", "below", "beneath", "on", "above", "upon", "lower part", "upper part", etc. to describe the relationship between one element or component and another element or component shown in the drawings. In addition to the orientations described in the figures, the spatial relative terms are also intended to cover different orientations of the device during use or operation. The device can be oriented in other ways (rotated by 90° or in other orientations), and the spatial relative descriptive terms used in the present application can be correspondingly interpreted in the same way.

[0069] The term "layer" used in the present application refers to a part of a material including a region having a certain thickness. The layer can extend over the entire underlying or overlying structure, or can extend over a partial range of the underlying or overlying structure. In addition, the layer can be a region of a homogeneous or inhomogeneous continuous structure, and its thickness is less than the thickness of the continuous structure. For example, the layer can be located between the top surface and the bottom surface of the continuous structure or between any pair of horizontal planes therebetween. The layer can extend horizontally, vertically, and / or along a conical surface. One layer can include multiple layers. For example, a wiring layer can include one or more doped or undoped semiconductor layers or metal layers and can have the same or different materials.

[0070] It should be understood that the "plane" used in the present application refers to the XY plane of a chip, an active interposer, a wafer, or a package substrate, etc., corresponding to the XY plane of a semiconductor structure, and the "thickness direction" refers to the Z direction relative to the XY plane, and the Z direction can be perpendicular to the XY plane.

[0071] With the development of CMOS (Complementary Metal Oxide Semiconductor) technology, improving the performance of MOS transistors (such as PMOS (positive channel Metal Oxide Semiconductor)) has become a huge challenge. In related technologies, a compressive channel stress is generated by forming a channel layer with a lattice mismatch with the substrate to improve the carrier mobility. However, there are element diffusion problems in the direct growth of the interface layer (IL) on some channel layers. Refer to Figure 1 , for example, due to the instability of GeOx, the interface layer 20 directly grown on the SiGe channel 10 will form a Ge diffusion region 21 in the interface layer, which will in turn induce interface trap (Dit) problems and reduce the performance of the MOS transistor. The above interface layer can refer to a dielectric layer or a gate oxide layer (IOgate OX), etc.

[0072] To solve at least one of the above problems, the following combines Figures 1-9 to introduce a method for preparing a semiconductor structure provided by an embodiment of the present application. Figure 2 It is a schematic flowchart of the method for preparing a semiconductor structure. This specification provides method operation steps such as in the embodiment or flowchart, but based on routine or non-creative labor, it may include more or fewer operation steps. The step order listed in the embodiment is only one of the execution orders of many steps and does not represent the only execution order. When the actual preparation method is executed, it can be executed in the order shown in the embodiment or the drawing or executed in parallel. The method for preparing a semiconductor structure may include S11 - S15:

[0073] S11: Provide a substrate 100, the substrate 100 having a channel layer 102 and a first protective layer 103 located on the channel layer 102.

[0074] Refer to Figure 3 , the substrate 100 includes a semiconductor substrate 101 and a channel layer 102 located on one side of the semiconductor substrate 101. Exemplarily, the constituent material of the semiconductor substrate 101 can be at least one of the following: silicon, a material containing silicon (such as a III - V group compound semiconductor material such as gallium arsenide (GaAs)), silicon on insulator (SOI), or other types of semiconductor materials capable of forming source and drain regions.

[0075] Preferably, there is a lattice mismatch between the channel layer 102 and the semiconductor substrate 101, and the channel layer 102 generates compressive channel stress on the semiconductor substrate 101, thereby improving the carrier mobility of the channel. In some embodiments, the material of the channel layer 102 includes a III-V semiconductor compound. Exemplarily, the material of the channel layer 102 may include one or several of SiGe, GaAs, GaAsP, AlInAs, etc.

[0076] The first protective layer 103 is formed on the side surface of the channel layer 102 facing away from the semiconductor substrate 101 for preventing the channel layer 102 from being oxidized. Preferably, the first protective layer 103 covers the channel layer 102. The first protective layer 103 may be an insulating material or a non-insulating material, such as a semiconductor material, a polymer material or a metal material. Preferably, the material is any material that can form a film on the channel layer 102, prevent the channel layer 102 from being oxidized, withstand the device process temperature and can be removed subsequently. In some embodiments, the material of the first protective layer 103 includes one or several of silicon, silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbon oxynitride and silicon carbon nitride oxynitride to form oxidation protection and facilitate subsequent removal. Preferably, the material of the first protective layer 103 is silicon.

[0077] In some embodiments, the thickness of the first protective layer 103 is greater than or equal to 0.4 nm, preferably, the thickness of the first protective layer 103 is greater than or equal to 1 nm. The function of the first protective layer 103 is to prevent oxidation. By forming the protective layer with the above thickness, oxidation is avoided while facilitating device size reduction and the efficiency of subsequent removal processes.

[0078] In some embodiments, providing the substrate 100 in S11 includes S21 - S23:

[0079] S21: Provide a semiconductor substrate 101;

[0080] S22: Deposit a channel layer 102 on the semiconductor substrate 101;

[0081] S23: Deposit a first protective layer 103 on the side of the channel layer 102 facing away from the semiconductor substrate 101.

[0082] In some embodiments, the deposition process of the present application includes but is not limited to at least one of physical vapor deposition (PVD), chemical vapor deposition (CVD), evaporation and sputtering, molecular beam, epitaxial growth, molecular beam epitaxy and atomic layer deposition (ALD). Exemplarily, a channel layer 102 is formed on a semiconductor substrate 101 by deposition (PVD, CVD or ALD, etc.) or a first protective layer 103 is formed on the channel layer 102, or a channel layer 102 is formed by epitaxial growth or a first protective layer 103 is formed on the channel layer 102. In one example, the semiconductor substrate 101 is a Si substrate, and a layer of SiGe channel is grown on the Si substrate by epitaxial growth. The two form compressive channel stress due to lattice mismatch, and then a first silicon layer is formed on the SiGe channel by deposition as the first protective layer 103. Specifically, the thickness of the channel layer 102 can be set based on the actual application requirements of the device, and is not limited here. Preferably, the first protection layer 103 is formed immediately after the channel layer 102 is formed, that is, the formation process of the channel layer 102 and the first protection layer 103 is a continuous process to avoid oxidation to the greatest extent.

[0083] S12 : forming a first dielectric layer 201 on a side of the first protection layer 103 away from the channel layer 102 .

[0084] Specifically, refer to Figure 4 , the first dielectric layer 201 is formed on the first protective layer 103 by a deposition technology. Preferably, the first dielectric layer 201 covers the first protective layer 103. In some embodiments, the first dielectric layer 201 is an insulating layer, and its material is a High K material. Exemplarily, the material of the first dielectric layer may include at least one of the following: one or more of silicon oxide, silicon oxynitride, aluminum oxide, hafnium oxide, zirconium oxide, lanthanum oxide, silicon oxide, silicon nitride, tantalum oxide, tantalum oxide nitride, ethyl silicate, glass material, halogenated silicon oxide, etc.; preferably, the material of the first dielectric layer may be silicon oxide, silicon oxynitride, etc.

[0085] In some embodiments, the first dielectric layer 201 serves as a first gate oxide layer. For example, in semiconductor devices such as MOS tubes, the first dielectric layer 201 is formed between the source and drain regions of the substrate and a functional layer including an isolation layer 202 and a gate structure to electrically isolate the gate from the semiconductor.

[0086] S13 : forming a trench structure 204 penetrating the first dielectric layer 201 and the first protective layer 103 , wherein the trench structure 204 exposes the channel layer 102 .

[0087] In some embodiments, the trench structure 204 can be formed by an etching technique. The etching process of the present application can include dry etching, wet etching, etc. The first dielectric layer 201 and the first protective layer 103 can be removed by a single etching process, or the first dielectric layer 201 can be etched first to form a first opening penetrating the first dielectric layer 201, and then the area of the first protective layer 103 exposed by the first opening can be etched to form a second opening, thereby obtaining the trench structure 204. In some cases, after the first dielectric layer 201 is formed, the trench structure 204 can be directly formed by patterned etching to facilitate the subsequent deposition of the second protective layer 206.

[0088] In other cases, after the first protective layer 103 is formed, other structure formation processes such as the isolation layer 202 are also involved. A dummy structure 203 needs to be formed and filled at the position corresponding to the trench structure 204 to facilitate the processing, transfer, and preparation of other components in the semiconductor structure. Correspondingly, referring to Figure 4 , before S13, the preparation method further includes: forming an isolation layer 202 and a dummy structure 203 located in the isolation layer 202 on the side of the first dielectric layer 201 facing away from the first protective layer 103. The dummy structure 203 penetrates the isolation layer 202 and contacts the first dielectric layer 201; S13 can specifically include: removing the dummy structure 203, and the areas of the first dielectric layer 201 and the first protective layer 103 corresponding to the dummy structure 203 to form the trench structure 204.

[0089] The isolation layer 202 is used for electrical isolation between the semiconductor substrate 101 and its adjacent functional components. Its material can be a High K material. In some embodiments, the material of the isolation layer 202 can include at least one of the following: silicon oxide, silicon oxynitride, aluminum oxide, hafnium oxide, zirconium oxide, lanthanum oxide, silicon oxide, silicon nitride, tantalum oxide, tantalum oxynitride, tetraethyl orthosilicate, glass material, halogenated silicon oxide, etc.; preferably, the material of the isolation layer 202 can be silicon oxide, silicon oxynitride, etc.

[0090] Functional component trenches 205 may be formed in the isolation layer 202. The functional component trenches 205 communicate with the trench structure 204 and are in corresponding positions, for depositing and filling functional components of the semiconductor structure, such as gate structures, etc. in the subsequent process. A pseudo-structure 203 is deposited and filled in the functional component trenches 205 in advance to avoid trench deformation before the formation of the functional components, which is beneficial to component positioning and size fixation. In some embodiments, the material of the pseudo-structure 203 may be a semiconductor material, such as polysilicon, amorphous silicon, germanium, silicon germanium, silicon carbide, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, gallium antimonide, alloy semiconductors or other compound semiconductors; preferably, the pseudo-structure 203 is polysilicon. It can be understood that in the case where the functional component is a gate structure, the pseudo-structure 203 is used as a pseudo-gate structure to fill the functional component trenches 205.

[0091] Further, after the pseudo-structure 203 is formed, the pseudo-structure 203, the first dielectric layer 201 and the first protective layer 103 in the corresponding positions need to be removed to form the trench structure 204.

[0092] In some embodiments, removing the pseudo-structure 203, and the regions of the first dielectric layer 201 and the first protective layer 103 corresponding to the pseudo-structure 203 to form the trench structure 204 may include S31: etching the pseudo-structure 203, the regions of the first dielectric layer 201 corresponding to the pseudo-structure 203 and the regions of the first protective layer 103 corresponding to the pseudo-structure 203 until the channel layer 102 is exposed to form the trench structure 204. The etching method of the trench structure 204 can be selected based on the material requirements of the first dielectric layer 201, the first protective layer 103 and the pseudo-structure 203, which is not limited herein. For example, it can be etched at one time to directly form the trench structure 204, or it can also be that after etching the pseudo-structure 203 to expose the first dielectric layer 201, then etching the region of the first dielectric layer 201 exposed in the functional component trenches 205 to form a first opening, and then etching the region of the first protective layer 103 exposed by the first opening to form a second opening, thereby obtaining the trench structure 204. Forming the trench structure 204 by direct etching improves the preparation efficiency.

[0093] It can be understood that there may be situations where it is difficult to directly etch the protective layer material or the channel layer 102 is easily damaged when etching the protective layer. For example, when the first protective layer 103 is a first silicon layer and the channel layer 102 is a SiGe channel, etc., the conditions for directly etching the first silicon layer are harsh and the thickness control is difficult, and it is easy to cause mis-etching of the SiGe channel. Correspondingly, in some embodiments, referring to Figures 5-7 , removing the pseudo-structure 203, and the regions of the first dielectric layer 201 and the first protective layer 103 corresponding to the pseudo-structure 203 to form the trench structure 204 includes S32 - S34:

[0094] S32: Etch the pseudo-structure 203 and the area of the first dielectric layer 201 corresponding to the position of the pseudo-structure 203 until the first protective layer 103 is exposed;

[0095] S33: Oxidize the exposed area of the first protective layer 103 to form an oxidation structure 207;

[0096] S34: Remove the oxidation structure 207 until the channel layer 102 is exposed to form a trench structure 204.

[0097] After etching to the first protective layer 103, local oxidation of the exposed first protective layer 103 is performed to reduce the difficulty of material removal and avoid incorrect etching of the channel layer 102. The oxidation treatment process used can be thermal oxidation, dry oxidation, wet oxidation, etc. The removal treatment of the oxidation structure 207 can be an etching process, a cleaning process, etc. It can be understood that the oxidation structure 207 is formed by oxidizing the material of the first protective layer 103. For example, the oxidation structure 207 formed after local oxidation of the first silicon layer is silicon oxide.

[0098] It can be understood that the material of the channel layer 102 may have diffusivity. After directly forming an interface layer thereon, due to the instability of the interface substance, the elements in the channel layer 102 will diffuse into the interface layer to form a diffusion region 210. Exemplarily, the semiconductor substrate 101 is a Si substrate, and a SiGe channel layer 102 is formed thereon. Since GeOx is unstable, when directly forming an oxide-based dielectric layer on the SiGe channel layer 102, Ge elements will diffuse into the oxide dielectric layer through the interface, introducing defects or causing leakage, affecting the device performance and product yield. By forming the first protective layer 103, the diffusion region 210 is introduced into the protective layer to prevent oxidation and avoid infiltration into the interface layer (such as the first dielectric layer 201).

[0099] Correspondingly, in some cases, the material of the channel layer 102 forms a diffusion region 210 in the first protective layer 103; the diffusion region 210 refers to the region where the material of the channel layer 102 forms element diffusion into the first protective layer 103 due to instability. In particular, high-temperature processes may be involved in the subsequent processes after forming the first protective layer 103. For example, the filling of the pseudo-structure 203 requires high-temperature deposition, which accelerates the element diffusion rate of the channel layer 102, thereby increasing the range of the diffusion region 210. When the first protective layer 103 is the first silicon layer and the channel layer 102 is a SiGe channel, Ge will diffuse into the first silicon layer, which is not conducive to the growth quality of the interface layer. By removing the area of the first protective layer 103 corresponding to the functional component trench 205 in step S13, the layer structure that has been diffusively contaminated is removed to facilitate the subsequent formation of the second protective layer 206 and the second dielectric layer 209, improving the quality of the dielectric layer.

[0100] S14: Form a second protective layer 206 in the trench structure 204.

[0101] Reference Figure 8 Figure 8 , the second protective layer 206 can be formed on the channel layer 102 in the trench structure 204 by techniques such as deposition (e.g., physical vapor deposition), covering at least the bottom region of the trench structure; the material of the second protective layer 206 is an insulating material or a material that can be converted into an insulating material, and this material is a material that can form a film on the channel layer 102, prevent the oxidation of the channel layer 102, and can be used as or form a dielectric layer. In some embodiments, the material of the second protective layer 206 includes at least one of silicon, silicon nitride, and silicon oxynitride, so as to directly serve as the second dielectric layer 209 or be converted into the second dielectric layer 209 through oxidation. It can be understood that silicon oxynitride can be directly applied as the second dielectric layer 209, and silicon and silicon nitride can form the second dielectric layer 209 through oxidation treatment.

[0102] Preferably, the material of the second protective layer 206 is the same as that of the first protective layer 103. For example, silicon is used for both, and the second protective layer 206 is the second silicon layer, so as to reduce the interface problem between the sidewalls of the second protective layer 206 and the first protective layer 103, and further improve the electrical isolation effect of the second dielectric layer 209.

[0103] In some embodiments, the thickness of the second protective layer 206 is greater than or equal to 0.4 nm, so that the thickness of the second dielectric layer 209 is more than 0.4 nm, thereby avoiding excessive static power consumption of the device (such as a CMOS circuit chip, etc.) caused by tunneling current. Preferably, the thickness of the second protective layer 206 is greater than or equal to 1 nm.

[0104] S15: Form the second dielectric layer 209 based on the second protective layer 206.

[0105] It can be understood that, reference Figure 9 Figure 9 , after forming the trench structure 204, the deposition of the second protective layer 206 is directly carried out and the formation of the second dielectric layer 209 is directly carried out, so as to reduce the diffusion time of the trench layer into the second protective layer 206, so that there are few or almost no diffusion regions 210 of the diffused elements in the second protective layer 206, so as to ensure the formation quality of the second dielectric layer 209. The second dielectric layer 209 is used for electrically isolating the functional components in the functional component trench 205 from the semiconductor substrate 101.

[0106] In some embodiments, the material of the second dielectric layer 209 includes at least one of silicon, silicon nitride, and silicon oxynitride.

[0107] In some cases, the second protective layer 206 is an insulating material. Correspondingly, the second protective layer 206 is used as the second dielectric layer 209 to reduce the device manufacturing process.

[0108] In some other embodiments, S15 specifically includes: oxidizing the second protective layer 206 to obtain a second dielectric layer 209. It can be understood that the material of the second protective layer 206 may be a semiconductor material such as silicon, which is converted into an insulating material through oxidation treatment to serve as the second dielectric layer 209, reducing the difficulty of forming the second dielectric layer 209. The oxidation treatment process adopted may be a thermal oxidation method, a dry oxidation method, a wet oxidation method, etc. Exemplarily, the second protective layer 206 is a second silicon layer, and after oxidation, a silicon oxide dielectric layer is formed.

[0109] In some embodiments, after S15, the manufacturing method further includes S16: forming a gate structure on the second dielectric layer 209. The material of the gate structure is a material capable of manufacturing a gate for controlling electron emission and movement, such as aluminum, tungsten, molybdenum, silver, etc. The second dielectric layer 209 is used as a second gate oxide layer to electrically isolate the gate structure from the semiconductor substrate 101.

[0110] In some embodiments, the sidewall of the second protective layer 206 covers the sidewall of the first protective layer 103, so that the first protective layer 103 and the second protective layer 206 form a continuous structure. The side surface of the second protective layer 206 facing away from the channel layer 102 is higher than the first protective layer 103 in the thickness direction, so as to ensure that the sidewall of the first protective layer 103 is not exposed after the second protective layer 206 is formed, and is conducive to the continuity of the first dielectric layer 201 and the second dielectric layer 209, so as to protect the first protective layer 103 and avoid problems such as leakage caused by the contact between the first protective layer 103 and functional components.

[0111] In some embodiments, the second dielectric layer 209 and the first dielectric layer 201 form a continuous structure. Here, the continuous structure means that at least part of the sidewalls of the first dielectric layer 201 and the second dielectric layer 209 are in contact. It can be understood that the second protective layer 206 is formed on the channel layer 102 after removing part of the first dielectric layer 201 and the first protective layer 103. Correspondingly, the bottom surface of the second dielectric layer 209 is lower than the bottom surface of the first protective layer 103. By making at least part of the sidewalls of the first dielectric layer 201 and the second dielectric layer 209 in contact, it is possible to avoid the subsequent formed functional components such as the gate structure from contacting the first protective layer 103, thereby avoiding problems such as breakdown and leakage.

[0112] Preferably, the materials of the first dielectric layer 201 and the second dielectric layer 209 are the same, such as both being silicon oxide, so as to avoid interface problems at the contact part of the first dielectric layer 201 and the second dielectric layer 209.

[0113] Exemplarily, after removing the dummy structure 203 (such as a polysilicon dummy gate structure) and the trench region of the first dielectric layer 201 above the SiGe channel layer 102, the first silicon layer is oxidized and removed, and almost no Ge diffusion occurs in the formed second silicon layer, thereby making almost no Ge diffusion occur in the formed silicon oxide dielectric layer. Compared with directly oxidizing the first silicon layer into the second gate oxide layer, the technical solution of the present application can significantly reduce layer defects and improve the quality of the gate oxide layer, thereby avoiding the Dit problem.

[0114] It can be understood that after forming the second dielectric layer 209, if there is a need for thickening, a dielectric material can be continuously deposited on the second dielectric layer 209 to increase the thickness of the dielectric layer.

[0115] In summary, the present application provides an integration solution for forming an interface layer with good quality on the channel layer 102. Specifically, the first protective layer 103 is used as oxidation protection to reduce the defects of the channel layer 102 and the oxidation risk in the subsequent process, and the region of the first protective layer 103 where channel diffusion contamination exists at the corresponding position is removed before the second dielectric layer 209 needs to be formed, so as to regrow the second protective layer 206 (such as a second silicon layer without Ge) with almost no channel diffusion and form the second dielectric layer 209, that is, the Dit problem caused by directly growing the interface layer on the channel layer 102 is solved, and at the same time, the influence of trench layer diffusion on the quality of the interface layer is avoided, a high-quality dielectric layer is formed, the device process difficulty is reduced, and the device performance is improved. The above technical solution can be applied to all advanced technologies of the present invention having an easily diffusible channel layer 102 (such as SiGe channel).

[0116] The following combines Figure 9 to introduce the semiconductor structure of the present application. It can be understood that the semiconductor structure in the drawings is only the technical solution of an exemplary embodiment of the present application, and the semiconductor structure of the present application may include fewer or more structural features, and is not limited to the device structure described in the drawings. Refer to Figure 9 , which is a cross-sectional view of a semiconductor structure provided by an embodiment of the present application.

[0117] The semiconductor structure includes a substrate 100, and the substrate 100 has a channel layer 102 and a first protective layer 103 located on the channel layer 102. The channel layer 102 can be formed on the semiconductor substrate 101 of the substrate 100 through a deposition process, and the first protective layer 103 can be formed on the channel layer 102 through a deposition process.

[0118] The substrate 100 includes a semiconductor substrate 101 and a channel layer 102 located on one side of the semiconductor substrate 101. Exemplarily, the constituent material of the semiconductor substrate 101 may be at least one of the following: silicon, a silicon-containing material (such as a group III-V compound semiconductor material like gallium arsenide (GaAs)), silicon on insulator (SOI), or other types of semiconductor materials capable of forming source and drain regions.

[0119] Preferably, there is a lattice mismatch between the channel layer 102 and the semiconductor substrate 101, and the channel layer 102 generates compressive channel stress on the semiconductor substrate 101, thereby enhancing the carrier mobility of the channel. In some embodiments, the material of the channel layer 102 includes a group III-V semiconductor compound. Exemplarily, the material of the channel layer 102 may include one or several of SiGe, GaAs, GaAsP, AlInAs, etc.

[0120] The first protective layer 103 is formed on the side surface of the channel layer 102 facing away from the semiconductor substrate 101, and is used to prevent the channel layer 102 from being oxidized. Preferably, the first protective layer 103 covers the channel layer 102. The first protective layer 103 may be an insulating material or a non-insulating material, such as a semiconductor material, a polymer material, or a metal material. Preferably, the material is any material that can form a film on the channel layer 102, prevent the channel layer 102 from being oxidized, withstand the device process temperature, and can be removed subsequently. In some embodiments, the material of the first protective layer 103 includes one or several of silicon, silicon nitride, silicon oxynitride, silicon carbonitride, and silicon carbon oxynitride to form oxidation protection and facilitate subsequent removal. Preferably, the material of the first protective layer 103 is silicon.

[0121] In some embodiments, the thickness of the first protective layer 103 is greater than or equal to 0.4 nm, and preferably, the thickness of the first protective layer 103 is greater than or equal to 1 nm. The function of the first protective layer 103 is to prevent oxidation. By forming a protective layer with the above thickness, oxidation is avoided while facilitating device size reduction and the efficiency of subsequent removal processes.

[0122] Furthermore, the semiconductor structure further includes a first dielectric layer 201, and the first dielectric layer 201 is located on the side of the first protective layer 103 facing away from the channel layer 102.

[0123] Specifically, the first dielectric layer 201 is formed on the first protective layer 103 by a deposition technique. Preferably, the first dielectric layer 201 covers the first protective layer 103. In some embodiments, the first dielectric layer 201 is an insulating layer, and its material is a High K material. Exemplarily, the material of the first dielectric layer may include at least one of the following: one or more of silicon oxide, silicon oxynitride, aluminum oxide, hafnium oxide, zirconium oxide, lanthanum oxide, silicon oxide, silicon nitride, tantalum oxide, tantalum oxide nitride, ethyl silicate, glass material, halogenated silicon oxide, etc.; preferably, the material of the first dielectric layer may be silicon oxide, silicon oxynitride, etc.

[0124] In some embodiments, the first dielectric layer 201 serves as a first gate oxide layer. For example, in semiconductor devices such as MOS tubes, the first dielectric layer 201 is formed between the source and drain regions of the substrate and a functional layer including an isolation layer 202 and a gate structure to electrically isolate the gate from the semiconductor.

[0125] Furthermore, the semiconductor structure further includes a trench structure 204, and the trench structure 204 penetrates the first dielectric layer 201 and the first protective layer 103 and exposes the channel layer 102. In some embodiments, the trench structure 204 can be formed by etching technology.

[0126] In some embodiments, the semiconductor structure further includes an isolation layer 202, which is located on the side of the first dielectric layer 201 away from the first protective layer 103. The isolation layer 202 is used for electrical isolation between the semiconductor substrate 101 and its adjacent functional components, and its material may be a High K material. In some embodiments, the material of the isolation layer 202 may include at least one of the following: one or more of silicon oxide, silicon oxynitride, aluminum oxide, hafnium oxide, zirconium oxide, lanthanum oxide, silicon oxide, silicon nitride, tantalum oxide, tantalum oxide nitride, ethyl silicate, glass material, halogenated silicon oxide, etc.; preferably, the material of the isolation layer 202 may be silicon oxide, silicon oxynitride, etc.

[0127] Functional component trenches 205 may be formed in the isolation layer 202. The functional component trenches 205 communicate with the trench structure 204 and are in corresponding positions, for depositing and filling functional components of the semiconductor structure, such as gate structures, etc. in the subsequent process. A pseudo-structure 203 is deposited and filled in the functional component trenches 205 in advance to avoid trench deformation before the formation of the functional components, which is beneficial to component positioning and size fixation. In some embodiments, the material of the pseudo-structure 203 may be a semiconductor material, such as polysilicon, amorphous silicon, germanium, silicon germanium, silicon carbide, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide or gallium antimonide, alloy semiconductor or other compound semiconductors; preferably, the pseudo-structure 203 is polysilicon. It can be understood that when the functional component is a gate structure, the pseudo-structure 203 is used as a pseudo-gate structure to fill the functional component trenches 205.

[0128] Further, the semiconductor structure further includes a second dielectric layer 209. The second dielectric layer 209 is located in the trench structure 204 and is used to electrically isolate the functional components in the functional component trenches 205 from the semiconductor substrate 101. The second dielectric layer 209 may be formed based on the second protective layer 206 in the trench structure 204. The second protective layer 206 may be deposited in the trench structure 204 after removing the regions of the first dielectric layer 201 and the first protective layer 103 in the trench structure 204. Preferably, the second protective layer 206 may directly serve as the second dielectric layer 209, or the second dielectric layer 209 may be obtained by oxidizing the second protective layer 206.

[0129] Understandably, the material of the channel layer 102 may have diffusivity. After directly forming the interface layer thereon, due to the instability of the interface material, the elements in the channel layer 102 will diffuse into the interface layer to form a diffusion region 210. Exemplarily, the semiconductor substrate 101 is a Si substrate, and a SiGe channel layer 102 is formed thereon. Since GeOx is unstable, when a dielectric layer of oxide type is directly formed on the SiGe channel layer 102, the Ge element will diffuse into the oxide dielectric layer through the interface, introducing defects or causing leakage, which affects the device performance and the product yield. By forming the first protective layer 103, the diffusion region 210 is introduced into the protective layer to prevent oxidation and avoid infiltration into the interface layer (such as the first dielectric layer 201). Correspondingly, in some cases, the material of the channel layer 102 forms a diffusion region 210 in the first protective layer 103; the diffusion region 210 refers to the region where the material of the channel layer 102 forms element diffusion into the first protective layer 103 due to instability. In particular, the subsequent process after forming the first protective layer 103 may involve a high-temperature process. For example, the filling of the dummy structure 203 requires high-temperature deposition, which accelerates the element diffusion rate of the channel layer 102, thereby increasing the range of the diffusion region 210. When the first protective layer 103 is the first silicon layer and the channel layer 102 is a SiGe channel, Ge will diffuse into the first silicon layer, which is not conducive to the growth quality of the interface layer. By removing the region of the first protective layer 103 corresponding to the functional component trench 205, the layer structure that has been diffusively contaminated is removed, facilitating the subsequent formation of the second protective layer 206 and the second dielectric layer 209, and improving the quality of the dielectric layer.

[0130] In some embodiments, the thickness of the second dielectric layer 209 is 0.4 nm or more, preferably 1 nm or more, or 2 nm or more, to avoid excessive static power consumption of the device (such as a CMOS circuit chip, etc.) caused by tunneling current.

[0131] In some embodiments, the material of the second dielectric layer 209 includes at least one of silicon, silicon nitride, and silicon oxynitride.

[0132] In some embodiments, the second dielectric layer 209 and the first dielectric layer 201 form a continuous structure. Here, the continuous structure means that the sidewalls of the first dielectric layer 201 and the second dielectric layer 209 are at least partially in contact. Understandably, the second protective layer 206 is formed on the channel layer 102 after removing a part of the first dielectric layer 201 and the first protective layer 103. Correspondingly, the bottom surface of the second dielectric layer 209 is lower than the bottom surface of the first protective layer 103. By making the sidewalls of the first dielectric layer 201 and the second dielectric layer 209 at least partially in contact, it is possible to avoid the subsequent formation of functional components such as the gate structure from contacting the first protective layer 103, thereby avoiding problems such as breakdown and leakage.

[0133] Preferably, the materials of the first dielectric layer 201 and the second dielectric layer 209 are the same, such as silicon oxide, so as to avoid interface problems at the contact portion between the first dielectric layer 201 and the second dielectric layer 209.

[0134] In some embodiments, the semiconductor structure further includes a gate structure located on a side of the second dielectric layer 209 away from the channel layer 102. The material of the gate structure is a material capable of manufacturing a gate for controlling electron emission and movement, such as aluminum, tungsten, molybdenum, silver, etc. The second dielectric layer 209 is used as a second gate oxide layer to electrically isolate the gate structure from the semiconductor substrate 101.

[0135] It can be understood that the above embodiments of the semiconductor structure and the embodiments of the method for manufacturing the semiconductor structure are based on the same application concept, and the semiconductor structure can be obtained by using the above method for manufacturing the semiconductor structure.

[0136] Correspondingly, the present application further provides an electronic device, which is obtained by using the above semiconductor structure or the above method for manufacturing the semiconductor structure.

[0137] Correspondingly, the present application provides an electronic device including an electronic device, which is obtained by using the above semiconductor structure or the above method for manufacturing the semiconductor structure.

[0138] The electronic device according to the embodiments of the present application can be selected from any electronic product or device such as a mobile phone, a personal digital assistant (PDA), a tablet computer (pad), a notebook computer, a game console, a television, a video compact disc (VCD), a digital video disc (DVD), a navigator, a camera, a video camera, a recording pen, an MP3, an MP4, a PlayStation Portable (PSP), etc., or can also be any intermediate product including an electronic device obtained by using the above semiconductor structure.

[0139] It should be noted that the embodiments in this specification are all described in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts among the embodiments can be referred to each other.

[0140] The above description has fully disclosed the specific embodiments of the present application. It should be pointed out that any modification made by those skilled in the art to the specific embodiments of the present application does not deviate from the scope of the claims of the present application. Correspondingly, the scope of the claims of the present application is not limited to the foregoing specific embodiments.

Claims

1. A method for preparing a semiconductor structure, characterized in that, The preparation method includes: providing a substrate having a channel layer and a first protective layer on the channel layer; forming a first dielectric layer on a side of the first protective layer facing away from the channel layer; forming a trench structure penetrating through the first dielectric layer and the first protective layer, the trench structure exposing the channel layer; forming a second protective layer in the trench structure; forming a second dielectric layer based on the second protective layer.

2. The preparation method according to claim 1, wherein The forming the second dielectric layer based on the second protective layer includes: using the second protective layer as the second dielectric layer; or, performing an oxidation treatment on the second protective layer to obtain the second dielectric layer.

3. The preparation method according to claim 1, wherein Before forming the trench structure penetrating through the first dielectric layer and the first protective layer, the preparation method further includes: forming an isolation layer and a dummy structure in the isolation layer on a side of the first dielectric layer facing away from the first protective layer, the dummy structure penetrating through the isolation layer and contacting the first dielectric layer; The forming the trench structure penetrating through the first dielectric layer and the first protective layer includes: removing the dummy structure and regions of the first dielectric layer and the first protective layer corresponding to the dummy structure to form the trench structure.

4. The preparation method according to claim 3, wherein, The removing the dummy structure and regions of the first dielectric layer and the first protective layer corresponding to the dummy structure to form the trench structure includes: etching the dummy structure, the region of the first dielectric layer corresponding to the dummy structure, and the region of the first protective layer corresponding to the dummy structure until the channel layer is exposed to form the trench structure.

5. The preparation method according to claim 3, characterized in that, The removing the dummy structure and regions of the first dielectric layer and the first protective layer corresponding to the dummy structure to form the trench structure includes: etching the dummy structure and the region of the first dielectric layer corresponding to the dummy structure until the first protective layer is exposed; oxidizing an exposed region of the first protective layer to form an oxidation structure; removing the oxidation structure until the channel layer is exposed to form the trench structure.

6. The preparation method according to any one of claims 1-5, characterized in that, The providing the substrate includes: providing a semiconductor substrate; depositing the channel layer on the semiconductor substrate; depositing the first protective layer on a side of the channel layer facing away from the semiconductor substrate.

7. The preparation method according to any one of claims 1-5, characterized in that, After forming the second dielectric layer based on the second protective layer, the preparation method further includes: forming a gate structure on the second dielectric layer.

8. The preparation method according to any one of claims 1-5, characterized in that, The material of the channel layer forms a diffusion region in the first protective layer.

9. The preparation method according to any one of claims 1-5, characterized in that, Sidewalls of the second protective layer cover sidewalls of the first protective layer.

10. The preparation method according to any one of claims 1-5, characterized in that, The preparation method satisfies at least one of the following features: The material of the first protective layer includes one or more of silicon, silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbon oxynitride, and silicon carbon nitride; The material of the second protective layer includes at least one of silicon, silicon nitride, and silicon oxynitride.

11. The preparation method according to any one of claims 1-5, characterized in that, The preparation method satisfies at least one of the following features: The thickness of the first protective layer is greater than or equal to 0.4 nm; The thickness of the second protective layer is greater than or equal to 0.4 nm.

12. A semiconductor structure, characterized in that, The semiconductor structure includes: A substrate having a channel layer and a first protective layer located on the channel layer; A first dielectric layer, located on a side of the first protective layer away from the channel layer; A groove structure, penetrating the first dielectric layer and the first protective layer and exposing the channel layer; The second dielectric layer is located in the trench structure.

13. The semiconductor structure according to claim 12, wherein, The second dielectric layer and the first dielectric layer form a continuous structure.

14. The semiconductor structure according to claim 12, wherein The semiconductor structure further comprises: The gate structure is located on a side of the second dielectric layer away from the channel layer.

15. The semiconductor structure according to claim 12, wherein The material of the channel layer includes a III-V semiconductor compound.

16. An electronic device, characterized in that, The invention comprises a semiconductor structure prepared by the preparation method according to any one of claims 1 to 11, or comprises a semiconductor structure according to any one of claims 12 to 15.

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