Method of manufacturing semiconductor device including wide bandgap semiconductor body

Abstract

A method of manufacturing a semiconductor device including a wide bandgap semiconductor body includes forming a first mask pattern over a first surface of the wide bandgap semiconductor body. The method further includes forming a trench extending from the opening in the first mask pattern into the wide bandgap semiconductor body, where the trench includes a first sidewall and an opposing second sidewall. The method further includes forming a first spacer mask pattern including a first spacer portion covering at least the first sidewall and a second spacer portion covering at least the second sidewall. The method further includes forming a second mask pattern in the trench between a first spacer portion of the first spacer mask pattern and a second spacer portion of the first spacer mask pattern. The method further includes exposing a trench portion of the trench by removing at least a portion of the second spacer portion from the trench; and introducing a dopant into the wide bandgap semiconductor body through the trench portion.

Description

Technical Field

[0001] The present disclosure relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device including a wide bandgap semiconductor body. Background Art

[0002] The technological development of new generations of wide bandgap semiconductor devices (e.g., insulated gate field effect transistors (IGFETs), such as metal oxide semiconductor field effect transistors (MOSFETs) or insulated gate bipolar transistors (IGBTs)) aims to improve electrical device characteristics and reduce costs by shrinking device geometries. While costs can be reduced by shrinking device geometries, various trade - offs and challenges must be met when increasing the device functionality per unit area. For example, when trenches are arranged relative to doped regions or doped regions are arranged relative to each other, reducing the area - to - on - state resistance RonxA can be challenging considering process - related variations. Such process - related variations can be caused by process technologies including different lithography levels.

[0003] There is a need to improve the method of manufacturing wide bandgap semiconductor devices. Summary of the Invention

[0004] An example of the present disclosure relates to a method of manufacturing a semiconductor device. The method includes: forming a first mask pattern over a first surface of a wide bandgap semiconductor body. The method further includes: forming a trench that extends from an opening in the first mask pattern into the wide bandgap semiconductor body. The trench includes a first sidewall and an opposing second sidewall. The method further includes: forming a first spacer mask pattern including a first spacer portion covering at least the first sidewall and a second spacer portion covering at least the second sidewall. The method further includes: forming a second mask pattern in the trench between the first spacer portion of the first spacer mask pattern and the second spacer portion of the first spacer mask pattern. The method further includes: exposing a trench portion of the trench by removing at least a portion of the second spacer portion from the trench; and introducing dopants into the wide bandgap semiconductor body through the trench portion.

[0005] Examples of the present disclosure relate to another method of manufacturing a semiconductor device. The method includes: forming a first mask pattern over a first surface of a wide-bandgap semiconductor body. The method further includes: forming a trench that extends from an opening in the first mask pattern into the wide-bandgap semiconductor body. The trench includes a first sidewall and an opposing second sidewall. The method further includes: forming a first spacer mask pattern that includes a first spacer portion covering at least the first sidewall and a second spacer portion covering at least the second sidewall. The method further includes: forming a second mask pattern that covers the first spacer portion of the first spacer mask pattern and at least partially exposes the second spacer portion of the first spacer mask pattern. The method further includes: exposing a trench portion of the trench by removing at least a portion of the second spacer portion from the trench. The method further includes: introducing a dopant into the wide-bandgap semiconductor body through the trench portion.

[0006] Examples of the present disclosure relate to another method of manufacturing a semiconductor device. The method includes: forming a first mask pattern over a first surface of a wide-bandgap semiconductor body. The method further includes: forming a trench that extends from an opening in the first mask pattern into the wide-bandgap semiconductor body. The trench includes a first sidewall and an opposing second sidewall. The method further includes: forming a first spacer mask pattern that includes a first spacer portion covering at least the first sidewall and a second spacer portion covering at least the second sidewall. The method further includes: modifying the structure of the second spacer portion configured to increase the selective etchability of the second spacer portion relative to the first spacer portion. The method further includes: exposing a trench portion of the trench by removing at least a portion of the second spacer portion from the trench. The method further includes: introducing a dopant into the wide-bandgap semiconductor body through the trench portion.

[0007] Examples of the present disclosure relate to another method of manufacturing a semiconductor device. The method includes: forming a first mask pattern over a first surface of a wide-bandgap semiconductor body. The method further includes: forming a trench that extends from an opening in the first mask pattern into the wide-bandgap semiconductor body. The trench includes a first sidewall and an opposing second sidewall. The method further includes: forming a first spacer mask pattern that includes a first polysilicon spacer portion covering at least the first sidewall and a second polysilicon spacer portion covering at least the second sidewall. The method further includes: exposing a trench portion of the trench by removing the second polysilicon spacer portion. The method further includes: modifying the thickness of the first polysilicon spacer portion by oxidizing a portion of the first polysilicon spacer portion. The method further includes: removing the portion.

[0008] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description and upon viewing the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The accompanying drawings are included to provide a further understanding of the embodiments and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of manufacturing a wide bandgap semiconductor device and, together with the description, are used to explain the principles of the embodiments. Additional embodiments are described in the following detailed description and the claims.

[0010] Figures 1A to 1F is a cross-sectional view for schematically and exemplarily illustrating process features of manufacturing a wide bandgap semiconductor device.

[0011] Figure 2 is for illustrating Figure 1E associated process features.

[0012] Figure 3 is a cross-sectional view for illustrating process features associated with the formation of a spacer mask pattern for forming a semiconductor region self-aligned with the edge of a trench.

[0013] Figure 4 is for illustrating Figure 3 associated process features.

[0014] Figure 5 and 6 are cross-sectional views for illustrating process features associated with the formation of a semiconductor region self-aligned with the edge of a trench.

[0015] Figures 7A to 7E 7, 8A to 8E, 9A to 9C, 10A, and 10B are cross-sectional views for schematically and exemplarily illustrating process features of manufacturing a wide bandgap semiconductor device.

[0016] Figure 11 is a schematic cross-sectional view for illustrating an exemplary configuration of an n-channel FET manufactured through the process features described with reference to Figures 1A to 6 as described above. DETAILED DESCRIPTION

[0017] In the following detailed description, reference is made to the accompanying drawings, which form a part of the detailed description and illustrate specific examples of semiconductor substrates that can be processed. It should be understood that other examples can be used and structural or logical changes can be made without departing from the scope of the present disclosure. For example, features illustrated or described for one example can be used on or in combination with other examples to yield another example. It is intended that the present disclosure include such modifications and variations. The use of specific language to describe examples should not be construed as limiting the scope of the appended claims. The drawings are not drawn to scale and are for illustrative purposes only. Corresponding elements are designated by the same reference numerals in different drawings if not otherwise indicated.

[0018] The terms "having", "containing", "including", "comprising", etc. are open-ended and indicate the presence of the stated structure, element, or feature, but do not preclude the presence of additional elements or features. The articles "a", "an", and "the" are intended to include the plural as well as the singular, unless the context clearly indicates otherwise.

[0019] The term "electrically connected" can describe a permanent low-resistance connection between elements that are electrically connected, such as direct contact between the elements involved or a low-resistance connection through metal and / or heavily doped semiconductor materials. The term "electrically coupled" can include that one or more intermediate elements suitable for signal and / or power transfer can be connected between the electrically coupled elements, such as elements that can be controlled to temporarily provide a low-resistance connection in a first state and a high-resistance electrical decoupling in a second state.

[0020] If two elements A and B are combined using "or", if not otherwise defined explicitly or implicitly, this should be understood to disclose all possible combinations, i.e., only A, only B, and A and B. Alternative wordings for the same combination are "at least one of A and B" or "A and / or B". With appropriate modifications, this also applies to combinations of more than two elements.

[0021] Ranges given for physical dimensions include the boundary values. For example, a range of a parameter y from a to b is read as a ≤ y ≤ b. This also applies to ranges with one boundary value (such as "at most" and "at least").

[0022] The main components of a layer or structure from a chemical compound or alloy are the elements whose atoms form such chemical compound or alloy. For example, silicon (Si) and carbon (C) are the main components of a silicon carbide (SiC) layer.

[0023] The term "on" should not be construed as meaning only "directly on". Instead, if one element is disposed "on another element" (e.g., one layer "on another layer" or "on a substrate"), then another component (e.g., another layer) may be disposed between the two elements (e.g., if one layer is "on a substrate", then another layer may be disposed between the layer and the substrate).

[0024] The description and drawings merely illustrate the principles of the disclosure. Additionally, all examples recited herein are mainly intended to be clearly for illustrative purposes only to assist the reader in understanding the principles and concepts of the disclosure contributed by the inventor(s) for the advancement of the art. All statements of the principles, aspects and examples of the disclosure and specific examples thereof recited herein are intended to include their equivalents.

[0025] It should be understood that the disclosure of a plurality of acts, processes, operations, steps or functions in the specification or claims cannot be construed as falling within a particular order, unless, for example, due to technical reasons, it is explicitly or implicitly indicated otherwise, such as by a statement like "thereafter". Thus, the disclosure of a plurality of acts or functions will not limit these to a particular order, unless such acts or functions are non-interchangeable due to technical reasons. Additionally, in some examples, a single act, function, process, operation or step may respectively include a plurality of sub-acts, sub-functions, sub-processes, sub-operations or sub-steps, or may be decomposed into a plurality of sub-acts, sub-functions, sub-processes, sub-operations or sub-steps. Such sub-acts may be included and are part of the disclosure of this single act, unless explicitly excluded.

[0026] A configuration example of a method of manufacturing a semiconductor device may include: forming a first mask pattern over a first surface of a wide-bandgap semiconductor body. The method may further include: forming a trench that extends from an opening in the first mask pattern into the wide-bandgap semiconductor body, wherein the trench includes a first sidewall and an opposing second sidewall. The method may further include: forming a first spacer mask pattern that includes a first spacer portion covering at least the first sidewall and a second spacer portion covering at least the second sidewall. The method may further include: forming a second mask pattern in the trench between the first spacer portion of the first spacer mask pattern and the second spacer portion of the first spacer mask pattern. The method may further include: exposing a trench portion of the trench by removing at least a portion of the second spacer portion from the trench; and introducing dopants into the wide-bandgap semiconductor body through the trench portion.

[0027] For example, a semiconductor device can be part of an integrated circuit or can be a discrete semiconductor device or a semiconductor module. For example, a semiconductor device can be or can include an insulated-gate field-effect transistor (IGFET), such as a metal-oxide-semiconductor field-effect transistor (MOSFET) or an insulated-gate bipolar transistor (IGBT). A semiconductor device can be: a vertical semiconductor device having a load current flow between a first surface and a second surface opposite the first surface. The vertical power semiconductor device can be configured to conduct a current of more than 1 A or more than 10 A or more than 30 A or more than 50 A or more than 75 A or even more than 100 A, and can also be configured to block a voltage in the range of several hundreds or up to several thousands of volts between load electrodes (e.g., between the collector and emitter on an IGBT, or between the drain and source of a MOSFET), such as 400 V, 650 V, 1.2 kV, 1.7 kV, 3.3 kV, 4.5 kV, 5.5 kV, 6 kV, 6.5 kV, 10 kV. For example, the blocking voltage can correspond to the voltage rating specified in the data sheet of the power semiconductor device.

[0028] The semiconductor device can be based on a wide-bandgap semiconductor body from a crystalline wide-bandgap semiconductor material having a bandgap larger than that of silicon (i.e., larger than 1.12 eV). As an example, the wide-bandgap semiconductor material can have a hexagonal crystal lattice and can be silicon carbide (SiC) or gallium nitride (GaN). For example, the semiconductor material can be 2H-SiC (2H polymorph of SiC), 6H-SIC or 15R-SiC. According to an example, the semiconductor material is 4H polymorph of silicon carbide (4H-SiC). The semiconductor body can include or consist of a semiconductor substrate, on which there is no semiconductor layer (e.g., a layer grown epitaxially), having one or more than one of said semiconductor layers.

[0029] For example, the first surface can be the front surface or the top surface of the wide-bandgap semiconductor body, and the wide-bandgap semiconductor body can also have a second surface, which can be the back surface or the rear surface of the wide-bandgap semiconductor body. For example, the wide-bandgap semiconductor body can be attached to a lead frame via the second surface. Above the first surface of the wide-bandgap semiconductor body, for example, bonding pads can be arranged, and bonding wires can be bonded on the bonding pads.

[0030] For example, the trench may be stripe-shaped and may define the dimensions of a trench gate structure formed in the trench. Forming the trench gate structure may include: forming a trench gate dielectric, e.g., by thermal oxidation, and forming a trench gate electrode in the trench on the trench gate dielectric. The trench may also have another layout or geometry in a plan view, such as hexagonal, square, circular, oval. The trench gate electrode structure may include one or more conductive materials, such as: metals, metal alloys, e.g., Ni, Cu, Au, AlCu, Ag, Mo, Ta, W or their alloys; metal compounds, e.g., TiN, MoN; highly doped semiconductor materials, such as highly doped polysilicon or silicide, e.g., TiSi2. For example, the one or more conductive materials may form a layer stack. An exemplary layer stack may include a TiN barrier layer and a W fill. For example, via a gate interconnect structure, the trench gate electrode structure may be electrically connected to a gate pad. The gate pad and, for example, a first load electrode pad (e.g., the source pad of a MOSFET or the emitter pad of an IGBT) may be part of a wiring region over a wide bandgap semiconductor body. Forming the wiring region may include forming one or more than one (e.g., two, three, four or even more) wiring levels. Each wiring level may be formed by a single conductive layer or a stack of conductive layers (e.g., (one or more) metal layers). For example, the wiring levels may be patterned by a lithographic process. Between the stacked wiring levels, an interlayer dielectric structure may be disposed. One or more contact plugs and / or one or more contact lines may be formed in the openings of the interlayer dielectric structure to electrically connect parts of different wiring levels (e.g., metal lines or contact regions) to each other.

[0031] To achieve a desired current-carrying capacity, a wide-bandgap semiconductor device can be designed by a plurality of wide-bandgap semiconductor device elements connected in parallel. The wide-bandgap semiconductor device elements connected in parallel can be, for example, wide-bandgap semiconductor device elements formed in the shape of strips or strip segments. Of course, the wide-bandgap semiconductor device elements can also have any other shape, such as circular, elliptical, polygonal (such as hexagon or octahedron). The wide-bandgap semiconductor device elements can be arranged in the active transistor region of the wide-bandgap semiconductor body. The active transistor region can be a region in which the emitter region (or source region of a MOSFET) of the IGBT and the collector region (or drain region of a MOSFET) of the IGBT are arranged opposite to each other along the vertical direction. In the active transistor region, for example, through a contact plug on the first surface of the wide-bandgap semiconductor body, a load current can enter or leave the wide-bandgap semiconductor body of the semiconductor device. The wide-bandgap semiconductor device can also include an edge termination region, and the edge termination region can include a termination structure. In the blocking mode or in the reverse bias mode of the wide-bandgap semiconductor device, the blocking voltage between the active transistor region and the field-free region drops laterally along the termination structure. Compared with the active region, the termination structure can have a higher or slightly lower voltage blocking ability. For example, the termination structure can include a junction termination extension (JTE) with or without a lateral doping variation (VLD), one or more laterally separated guard rings, or any combination thereof.

[0032] The first mask pattern can be formed as a first hard mask pattern, such as an oxide hard mask pattern. For example, through a lithography process, the first mask pattern can be defined. For example, the size and arrangement of the opening(s) in the first mask pattern can define the layout of the trench(es) for forming the trench gate structure of the semiconductor device. For example, through an etching process, the trench(es) can be formed. Before forming the first mask pattern, the method can further include introducing a dopant into the wide-bandgap semiconductor body, for example, by ion implantation, to define a semiconductor layer in the wide-bandgap semiconductor body, such as a current spreading layer or a body layer.

[0033] For example, through one or more ion implantation processes, dopants can be introduced into the wide bandgap semiconductor body 106 through the bottom side and / or the second sidewall 1082 of the trench 108. Ion implantation parameters, such as ion implantation energy, ion implantation dose, implantation tilt angle, and dopant species (e.g., n- or p-type dopants), allow the formation of one or more p-type and / or n-type semiconductor regions that are self-aligned to the edge of the trench. The first mask pattern can not only allow the definition of the trench(es), but also serve as an ion implantation mask on the mesa confined by the opposite trenches when implanting dopants through the trench opening. And additionally, since the first spacer mask pattern is not only formed in the trench but also protrudes from the first surface of the wide bandgap semiconductor body, the first mask pattern can also serve as a mechanical support structure for the first spacer mask pattern. Thus, the process features described herein can allow for an improvement in the manufacturing method for critical dimensions. Thereby, a smaller transistor element layout or a transistor element layout with a higher manufacturing yield can be achieved.

[0034] For example, the method may further include: forming a third mask pattern over the first mask pattern. The third mask pattern can cover the top surface of the first spacer portion of the first spacer mask pattern. Through the opening in the third mask pattern, the top surface of the second spacer portion of the first spacer mask pattern can be exposed.

[0035] For example, exposing the trench portion may further include: selectively etching the second spacer portion of the first spacer mask pattern with respect to any one of the first mask pattern, the second mask pattern, or the third mask pattern.

[0036] For example, the material of the first spacer portion of the first spacer mask pattern can be polysilicon. The material of at least one of the first mask pattern or the second mask pattern can be an oxide of silicon. According to another example, each of the first spacer portion and the second spacer portion of the first spacer mask pattern can include a spacer of a first material and a covering layer on the spacer. The covering layer can be formed of a second material different from the first material. For example, the second material can be configured to be selectively etched with respect to the first material. For example, the first material can be polysilicon, and the second material can be an oxide of silicon. For example, the covering layer can be formed by thermal oxidation of the spacer. For example, the second mask pattern can be formed as a resist mask.

[0037] For example, introducing dopants into the wide bandgap semiconductor body through the trench portion can include: introducing dopants into the wide bandgap semiconductor body through ion implantation, through the bottom side, or through the second sidewall of the trench. The dopants can define a p-doped shielding region adjacent to the bottom side and / or the second sidewall of the trench. The p-doped shielding region is self-aligned with the edge of the trench.

[0038] For example, the method may further include: removing the first mask pattern. The method may further include: forming a second spacer mask pattern that includes a first spacer portion in a trench portion between the wide-bandgap semiconductor body and the second mask pattern. The second spacer mask pattern may further include: a second spacer portion that is laterally adjacent to the first spacer portion of the first spacer mask pattern.

[0039] For example, removing the first mask pattern may include: forming a fourth mask pattern over the first mask pattern. The fourth mask pattern may cover the top surface of the second mask pattern and the top surface of the first spacer portion of the first spacer mask pattern. Through an opening in the fourth mask pattern, a portion of the first mask pattern may be exposed.

[0040] For example, removing the first mask pattern may further include: selectively etching the first mask pattern with respect to either the first spacer portion of the first spacer mask pattern or the fourth mask pattern.

[0041] For example, the material of the fourth mask pattern may be a resist material.

[0042] For example, the method may further include: introducing a dopant into the wide-bandgap semiconductor body through an opening in the second spacer mask pattern by ion implantation. For example, this may allow defining another semiconductor region by ion implantation through the opening in the second spacer mask in a self-aligned manner with respect to the edge of the trench, such as a p-doped auxiliary or contact region for electrically connecting a shielding region to a source electrode.

[0043] For example, the method may further include: forming a sixth mask pattern that is laterally adjacent to the first and second spacer portions of the second mask pattern. The method may further include: forming a seventh mask pattern over the sixth mask pattern. The seventh mask pattern may cover the top surface of the second mask pattern and the top surface of the first spacer portion of the second spacer mask pattern. Through an opening in the seventh mask pattern, the top surface of the second spacer portion of the second spacer mask pattern may be exposed.

[0044] For example, the method may further include: exposing a surface portion of the wide-bandgap semiconductor body by selectively etching the second spacer portion of the second spacer mask pattern with respect to either the first spacer portion of the first spacer mask pattern or the sixth mask pattern or the seventh mask pattern. This may allow defining another semiconductor region by ion implantation through the exposed surface portion in a self-aligned manner with respect to the edge of the trench, such as an n + doped source region.

[0045] For example, the material of the sixth mask pattern may be polysilicon, and the material of the seventh mask pattern may be an oxide or nitride of silicon.

[0046] For example, the method may further include: introducing a dopant into the wide-bandgap semiconductor body through a surface portion of the wide-bandgap semiconductor body by ion implantation. For example, the dopant may define an n-doped source region.

[0047] For example, the method may further include: before forming the first mask pattern, introducing a dopant into the wide-bandgap semiconductor body through a first surface. For example, the dopant may be introduced into the wide-bandgap semiconductor body by ion implantation. For example, for a transistor elementary region, the ion implantation may be unmasked. For example, the dopant may define a body region of, for example, a FET. Additionally or alternatively, for example, the dopant may define a current spreading region of the FET. The dopant conductivity type of the dopant defining the body region and the current spreading region may be different. For example, for an n-channel SiC FET, an n-type dopant (e.g., nitrogen (N) or phosphorus (P)) may define the current spreading region, and a p-type dopant (e.g., boron (B) or aluminum (Al)) may define the body region.

[0048] For example, after forming the trench and before forming the first spacer mask pattern, the method may further include: forming a liner that lines the bottom side and sidewalls of the trench. The liner may further line the top side and sidewalls of the first mask pattern. For example, the material of the liner may be selected for an etching selectivity with respect to the second mask pattern.

[0049] For example, exposing the trench portion may further include: removing at least a portion of the second mask pattern, such as a part or all. For example, removing the second mask pattern may be implemented by an etching process selective to the liner and the spacer portion.

[0050] For example, the thickness of the first spacer portion may be increased to a target thickness. The increase in the thickness of the first spacer portion may be implemented by a suitable process (such as, for example, and depending on the material of the first spacer portion, an oxidation process). For example, an oxidation process may be used for the first spacer portion formed of polysilicon.

[0051] Another configuration example of a method of manufacturing a semiconductor device may include: forming a first mask pattern over a first surface of a wide bandgap semiconductor body. The method may further include: forming a trench that extends from an opening in the first mask pattern into the wide bandgap semiconductor body. The trench includes a first sidewall and an opposite second sidewall. The method may further include: forming a first spacer mask pattern that includes a first spacer portion covering at least the first sidewall and a second spacer portion covering at least the second sidewall. The method may further include: forming a second mask pattern that covers the first spacer portion of the first spacer mask pattern and at least partially exposes the second spacer portion of the first spacer mask pattern. The method may further include: exposing a trench portion of the trench by removing at least a portion of the second spacer portion from the trench. The method may further include: introducing dopants into the wide bandgap semiconductor body through the trench portion.

[0052] For example, each of the first spacer portion and the second spacer portion of the first spacer mask pattern may include a spacer of a first material and a covering layer on the spacer. The covering layer may be formed of a second material different from the first material. For example, the second material may be configured to be selectively etched relative to the first material. For example, the first material may be polysilicon, and the second material may be an oxide of silicon. For example, the covering layer may be formed by thermal oxidation of the spacer.

[0053] For example, the second mask pattern may be a resist mask pattern.

[0054] For example, through an etching process, using the second mask pattern as an etch mask, the covering layer of the second spacer portion can be removed. Thereafter, the resist of the second mask pattern can be removed. Thereafter, the spacer of the second spacer portion can be removed. Another configuration example of a method for manufacturing a semiconductor device may include: forming a first mask pattern over a first surface of a wide-bandgap semiconductor body. The method may further include: forming a trench that extends from an opening in the first mask pattern into the wide-bandgap semiconductor body. The trench includes a first sidewall and an opposing second sidewall. The method may further include: forming a first spacer mask pattern that includes a first spacer portion covering at least the first sidewall and a second spacer portion covering at least the second sidewall. The method may further include: changing the structure of the second spacer portion, the structure being configured to increase the selective etchability of the second spacer portion relative to the first spacer portion. The method may further include: exposing a trench portion of the trench by removing at least a portion of the second spacer portion from the trench. The method may further include: introducing a dopant into the wide-bandgap semiconductor body through the trench portion. The selective etchability of the second spacer portion relative to the first spacer portion can be increased by any measure of changing the lattice structure (e.g., changing the crystallinity by damaging the crystal structure) and / or the lattice composition (e.g., doping concentration).

[0055] For example, by introducing impurities into the second spacer portion through an inclined ion implantation process, the selective etchability of the second spacer portion relative to the first spacer portion can be increased. This can allow for increasing the selective etchability of the second spacer portion relative to the first spacer portion by changing the doping concentration in the second spacer portion and / or by damaging the crystal structure. By changing the doping concentration and / or the crystal structure, the selective etchability can be varied.

[0056] Another configuration example of a method for manufacturing a semiconductor device may include: forming a first mask pattern over a first surface of a wide-bandgap semiconductor body. The method may further include: forming a trench that extends from an opening in the first mask pattern into the wide-bandgap semiconductor body. The trench may include a first sidewall and an opposing second sidewall. The method may further include: forming a first spacer mask pattern that includes a first polysilicon spacer portion covering at least the first sidewall and a second polysilicon spacer portion covering at least the second sidewall. The method may further include: exposing a trench portion of the trench by removing the second polysilicon spacer portion. The method may further include: changing the thickness of the first polysilicon spacer portion by oxidizing a portion of the first polysilicon spacer portion. The method may further include: removing the portion.

[0057] For example, the method may further include: after exposing the trench portion and before changing the thickness of the first polysilicon spacer portion, introducing dopants into the wide bandgap semiconductor body through the trench portion.

[0058] For example, the method may further include: repeatedly changing the thickness of the first polysilicon spacer portion by oxidizing and removing a portion of the first polysilicon spacer portion.

[0059] For example, the method may further include: after changing and reducing the thickness of the first polysilicon spacer portion, introducing dopants into the wide bandgap semiconductor body through the trench portion.

[0060] Details of the structure or function or technical benefits of the features described above for wide bandgap semiconductor devices (such as FETs or IGBTs) apply equally to the exemplary methods described herein. Processing the semiconductor body may include one or more optional additional features corresponding to one or more aspects mentioned in connection with the concepts presented or one or more examples described above or below.

[0061] Some of the examples above and below are described in connection with a silicon carbide substrate. Alternatively, a wide bandgap semiconductor substrate (e.g., a wide bandgap wafer) may be processed, for example, including a wide bandgap semiconductor material different from silicon carbide. The wide bandgap semiconductor wafer may have a bandgap larger than that of silicon (1.12 eV). For example, the wide bandgap semiconductor wafer may be a silicon carbide (SiC) wafer or a gallium arsenide (GaAs) wafer or a gallium nitride (GaN) wafer.

[0062] More details and aspects are mentioned in connection with the examples described above or below. Processing the wide bandgap semiconductor body (such as a wafer) may include one or more optional additional features corresponding to one or more aspects mentioned in connection with the concepts presented or one or more examples described above or below.

[0063] Below, additional examples of field effect transistors FETs are explained in connection with the drawings. The functional and structural details described for the above examples will apply equally to the exemplary embodiments illustrated in the drawings and further described below. In the illustrated example, an n-channel FET is illustrated. However, the examples described herein may also be applied to p-channel devices, such as p-channel MOSFETs or p-channel device IGBTs.

[0064] Details of the structure or function or technical benefits of the above features apply equally to the examples below, and vice versa.

[0065] Figures 1A to 1F The schematic cross-sectional view schematically and exemplarily illustrates the process features of manufacturing the semiconductor device 100.

[0066] Referring to Figure 1A the schematic cross-sectional view of Figure 1A and additional openings (not shown in

[0067] Referring to Figure 1B the schematic cross-sectional view of

[0068] Referring to Figure 1CSchematic cross-sectional view, a first spacer mask pattern 110 is formed on the wide bandgap semiconductor body 106 and the first mask pattern 102. The first mask pattern 102 thus serves not only to define the trench 108, but also as a mechanical support structure for the upper part of the first spacer mask pattern 110 protruding from the first surface 104. Through a layer deposition process, followed by an etching process for removing the material of the deposited layer from the bottom side of the trench 108 and from the top side of the first mask pattern 102, the first spacer mask pattern 110 can be formed. As a result of the spacer etching process, a first spacer portion 1101 and a second spacer portion 1102 can remain, the first spacer portion 1101 covering at least the first sidewall 1081 and the second spacer portion 1102 covering at least the second sidewall 1082. The first spacer portion 1081 also covers the first sidewall 1026 and the second sidewall 1027 of the first mask pattern 102. Along the first lateral direction x1, the second sidewall 1027 is opposite to the first sidewall 1026. The materials of the first and second spacer portions 1101, 1102 of the first spacer mask pattern 110 can be suitably selected to allow selective etching of the second spacer portion 1102 with respect to either the first mask pattern 102 or the wide bandgap semiconductor body 106. For example, the first spacer portion 1101 and the second spacer portion 1102 of the first spacer mask pattern 110 can be formed of polysilicon (e.g., undoped polysilicon). For example, the first mask pattern 102 can be formed of an oxide of silicon.

[0069] Referring to Figure 1D Schematic cross-sectional view, a second mask pattern 112 is formed in the trench 108 between the first spacer portion 1101 and the second spacer portion 1102 of the first spacer mask pattern 110. Through a layer deposition process, followed by removing a part of the deposited layer disposed on the first mask pattern 110 and disposed on the first and second spacer portions 1101, 1102 of the first spacer mask pattern 110, the second mask pattern 112 can be formed. For example, through chemical mechanical polishing (CMP), or through a combination of, for example, dry etching and CMP, the said part of the deposited layer can be removed. For example, the deposited layer can be a tetraethyl orthosilicate (TEOS) layer. For example, through a spacer etching process, patterning of the TEOS layer can also be implemented.

[0070] Referring to Figure 1ESchematic cross-sectional view, by removing at least a portion of the second spacer portion 1102 from the trench 108, the trench portion 1083 of the trench 108 is exposed. Through the selective etching of the second spacer portion 1102 of the first spacer mask pattern 110 with respect to each of the first mask pattern 102, the wide-bandgap semiconductor body 106, and the second mask pattern 112, the trench portion 1083 can be exposed (see also the further description related to Figure 2 below).

[0071] Referring to Figure 1F Schematic cross-sectional view, through the exposed trench portion 1083, dopants are introduced into the wide-bandgap semiconductor body 106. For example, a p-doped shield region can be formed in a self-aligned manner with respect to the edge of the trench 102. When dopants are implanted through the exposed trench portion 1083, the first mask 102 serves as an ion implantation mask on the mesa limited by the opposing trenches 108.

[0072] Figure 2 The schematic cross-sectional view of Figure 1E is related to the process features illustrated in Figure 2 . Referring to

[0073] In a self-aligned manner with respect to the trench 108 or the mesa region defined by the opposing trenches, additional semiconductor regions can be arranged. Referring to Figure 3 Schematic cross-sectional view, after removing the first mask pattern 102, a second spacer mask pattern 116 is formed. The second spacer mask pattern 116 includes a first spacer portion 1161 in the trench portion 1083 between the wide-bandgap semiconductor body 106 and the second mask pattern 112. The second spacer mask pattern 116 further includes: a second spacer portion 1162, laterally adjacent to the first spacer portion 1101 of the first spacer mask pattern 110.

[0074] Referring to Figure 4The exemplary cross-sectional views depict exemplary process features for processing a wide bandgap semiconductor body from a stage of the process illustrated in Figure 1F to a stage of the process illustrated in Figure 3 .

[0075] Referring to Figure 4 , removing the first mask pattern 102 includes: forming a fourth mask pattern 118 over the first mask pattern 102, such as a resist mask pattern. The fourth mask pattern 118 covers the top surface of the second mask pattern 112 and the top surface of the first spacer portion 1101 of the first spacer mask pattern 110. The fourth mask pattern 118 also fills or covers the trench portion 1083, without completely filling the trench portion 1083, which has been previously used to form a trench 108 self-aligned semiconductor region through the bottom side and / or sidewalls of the exposed trench portion 1083 via an ion implantation process (see Figure 1F ). Through the opening 1181 in the fourth mask pattern 118, a portion of the first mask pattern 102 is exposed. The first mask pattern 102 is selectively etched with respect to either the first spacer portion 1101 of the first spacer mask pattern 110 or the fourth mask pattern 118. After removing the fourth mask pattern 118 and optionally recessing the second mask pattern 112 from its side surfaces, a spacer patterning process is performed to form a second spacer mask pattern 116 through a spacer layer deposition process (followed by a spacer etching process). The above-described process features are exemplary process features for processing the wide bandgap semiconductor body 106 between the stages of the processes illustrated in Figure 1F and Figure 3 .

[0076] Based on the second spacer mask pattern 116 illustrated in Figure 3 , dopants are introduced into the wide bandgap semiconductor body 106. For example, through ion implantation, through the opening 1163 in the second spacer mask pattern 116, dopants are introduced into the wide bandgap semiconductor body 106. Thereby, one or more n- or p-doped semiconductor regions can be formed in a self-aligned manner with respect to the edge of the trench 108. For example, through the thickness of the second spacer portion 1162, the lateral distance of the one or more n- or p-doped semiconductor regions from the trench 108 can be adjusted. Varying the ion implantation tilt angle can allow another degree of freedom for adjusting the lateral distance of the one or more n- or p-doped semiconductor regions from the trench 108. For example, a p + -doped assist region in an n-channel FET can be formed at an exact lateral distance from the channel region in the trench sidewall defined by the above-described self-alignment process. For example, a p+-doped assist region can allow electrically connecting a p-doped shield region and / or a p-doped body region to a source electrode.

[0077] Additional semiconductor regions may be arranged in a self-aligned manner with respect to the trench 108 or the mesa region defined by opposing trenches. Referring to Figure 5 a schematic cross-sectional view of Figure 3 , a sixth mask pattern 120 is formed, which is laterally adjacent to the first and second spacer portions 1161, 1162 of the second mask pattern 116. For example, the material of the sixth mask pattern 120 may be polysilicon. Forming the sixth mask pattern 120 may include a layer deposition process, such as a polysilicon layer deposition process. A first portion of the deposited layer fills

[0078] the opening 1163 illustrated in Figure 5 , and a second portion of the deposited layer covers the top sides of the second spacer mask pattern 116, the first spacer mask pattern 110, and the second mask pattern 112. The second portion may then be removed by CMP and / or etching. The remaining first portion of the deposited layer defines the sixth mask pattern 120.

[0079] Additionally, referring to Figure 6 a schematic cross-sectional view of

[0080] , a seventh mask pattern 122 is formed over the sixth mask pattern 120. For example, the material of the seventh mask pattern 122 may be an oxide or nitride of silicon. The seventh mask pattern 122 covers the top surface of the second mask pattern 112 and the top surface of the first spacer portion 1161 of the second spacer mask pattern 116. Through the opening 1221 in the seventh mask pattern 122, the top surface of the second spacer portion 1162 of the second spacer mask pattern 116 is exposed. + By selectively etching the second spacer portion 1162 of the second spacer mask pattern 116 with respect to any one of the first spacer portion 1101 of the first spacer mask pattern 110, the sixth mask pattern 120, or the seventh mask pattern 122, a surface portion of the wide-bandgap semiconductor body 106 is exposed. By removing the second spacer portion 1162, the opening 128 remains, which exposes the wide-bandgap semiconductor body 106.

[0081] Figures 7A to 7D a schematic cross-sectional view of

[0082] Figure 7AThe schematic cross-sectional view is based on Figure 1B the process features illustrated in Figure 1C and 1D and further illustrates the formation of the inner liner 136, which lines the bottom side and the side walls 1081, 1082 of the trench 108 and the top side and the side walls 1026, 1027 of the first mask pattern 102. Before defining the second mask pattern 112,

[0083] Referring to Figure 7B and similar to Figure 2 the process features illustrated in Figure 7B , the exposed trench portion 1083 includes: forming a third mask pattern 114 over the first mask pattern 102. The third mask pattern 114 covers the top surface of the first spacer portion 1101 of the first spacer mask pattern 110. Before removing the second spacer portion 1102 and the second mask pattern 112 from the trench 108, the top surface of the second spacer portion 1102 of the first spacer mask pattern 110 is exposed through the opening 1141 in the third mask pattern 114. For example, the third mask pattern 114 may include a resist mask pattern and an auxiliary mask pattern between the resist mask pattern and the first spacer mask pattern 110. For example, when etching the second spacer portion 1102 to expose the trench portion 1083, the auxiliary mask pattern and the second mask pattern 112 may protect the first spacer portion 1101. For example, the auxiliary mask pattern may include an oxide layer (e.g., a TEOS layer) or be formed of the oxide layer. After removing the second spacer portion 1102 as shown in Figure 7B and referring to Figure 7C , for example, through an etching process selective to the inner liner 136, the exposed trench portion 1083 is widened by removing the second mask pattern 112.

[0084] Referring to Figure 7D and 7E the schematic cross-sectional views, the first spacer portion 1101 may be widened, for example, through an oxidation process. In other words, through a suitable process (such as, for example, and depending on the material of the first spacer portion 1101, through oxidation), the thickness of the first spacer portion 1101 can be tuned. For example, when the first spacer portion 1101 is formed of polysilicon, by completely oxidizing the polysilicon (see Figure 7D ), or by partially oxidizing the polysilicon (see Figure 7E) can cause widening of the first spacer portion 1101. When the polysilicon is partially oxidized, the oxidized portion can be removed, and additional process features (e.g., ion implantation into the semiconductor substrate through the exposed portion of the bottom side of the trench) can be implemented. The partial oxidation can be repeated so that multiple precisely controlled spacer thicknesses can be achieved in the trench. For example, each of the multiple precisely controlled spacer thicknesses can be used to process the semiconductor substrate through the exposed portion of the trench. Similar to Figure 1E , through the exposed trench portion 1083, dopants are introduced into the wide bandgap semiconductor body 106. For example, a p-doped shield region can be formed in a self-aligned manner with respect to the edge of the trench 108. When dopants are implanted through the exposed trench portion 1083, the first mask 102 serves as an ion implantation mask on the mesa limited by the opposing trenches 108. For example, dopants introduced through the sidewalls of the trench 108 can define an interconnect region for electrically interconnecting the buried region below the bottom side of the trench to the contactors on the first surface. As an alternative or in addition, for example, before forming the trench 108, an interconnect region or a portion thereof can be defined through a masked ion implantation process.

[0085] Figure 8A The schematic cross-sectional view is based on Figure 1B the process features illustrated in

[0086] Figure 8B The cross-sectional view is based on Figure 1C the process features illustrated in

[0087] for defining the spacer 1105, followed by forming a cover layer 1106 on the spacer 1105, for example, through a partial oxidation process of the polycrystalline spacer. The spacer 1105 and the cover layer 1106 define the first spacer portion 1101 of the first spacer mask pattern 110 and the second spacer portion 1102 of the first spacer mask pattern 110. Figure 8C Referring to the cross-sectional view of

[0088] Referring to the cross-sectional view of Figure 8D through an etching process, using the second mask pattern 112 as an etching mask, the cover layer 1106 of the second spacer portion 1102 is removed.

[0089] Referring to Figure 8EIn the cross-sectional view, the second mask pattern 112 is removed, and thereafter, the spacer 1105 of the second spacer portion 1102 is removed. Additional process features, such as oxidation of the spacer 1105 of the first spacer portion 1101 and / or inclined ion implantation through the exposed portion of the trench 108, may follow.

[0090] The resist mask pattern includes two resist sub-patterns, as Figure 8D The partial exposure of the second spacer portion 1102 as shown in may also be achieved. Starting from Figure 8B the cross-sectional view illustrated in and referring to Figure 9A , a resist 1121 is formed over the wide-bandgap semiconductor body 106 and planarized.

[0091] Referring to Figure 9B the schematic cross-sectional view of, the resist 1121 is recessed, leaving a resist remainder 1122 in the trench 108. The resist remainder 1122 is hardened, for example, by thermally curing or carbonizing the resist remainder 1122.

[0092] Referring to Figure 9C the schematic cross-sectional view of, a resist pattern 1123 is formed, covering the first spacer portion 1101 of the first spacer mask pattern 110 and partially exposing the second spacer portion 1102 of the first spacer mask pattern 110. The resist pattern 1123 and the resist remainder 1122 define the second mask pattern 112. Additional process features, such as those illustrated and described with reference to Figure 8D and 8E , may follow.

[0093] Figure 10A The schematic cross-sectional view of is based on Figure 1C the process features illustrated in and further illustrates modifying the structure of the second spacer portion 1102 to increase the selective etchability of the second spacer portion 1102 relative to the first spacer portion 1101. By introducing impurities into the second spacer portion 1102 through an inclined ion implantation process, the selective etchability of the second spacer portion 1102 relative to the first spacer portion 1101 is increased. Thereby, the doping concentration of the second spacer portion 1102 is increased or decreased, and / or the damage in the crystal structure of the second spacer portion 1102 is increased.

[0094] Referring to Figure 10B the schematic cross-sectional view of, for example, through an etching process, by removing the second spacer portion 1102 from the trench 108, the trench portion 1083 of the trench 108 is exposed. Additional process features follow, such as those described with reference to Figure 7D .

[0095] Figure 11 The schematic cross-sectional view illustrates an example configuration of an n-channel FET 101. The fabrication of the n-channel FET 101 can be based on the process features described and illustrated herein. The n-channel FET 101 includes: a trench gate structure 130 that extends from a first surface 104 into a wide-bandgap semiconductor body 106. The trench gate structure includes a trench gate dielectric 1301 and a trench gate electrode 1302. After defining semiconductor regions in a self-aligned manner with respect to the trench as described in the above example, the trench gate structure 130 can be formed in the trench 108 illustrated in Figures 1B to 6 . The p-doped region 132 can be defined by a plurality of overlapping p-doped regions, such as a p-doped body region, a p-doped shield region, and a p-doped auxiliary region. For example, a first critical dimension cr1 of a first portion (e.g., the p-doped shield region) of the p-doped region 132 can be defined in a self-aligned manner with respect to the edge of the trench 108, as referenced in Figures 1A to 1F . A second critical dimension cr2 of a second portion (e.g., the p-doped auxiliary region) of the p-doped region 132 can be defined in a self-aligned manner with respect to the edge of the trench 108, as referenced in Figure 3 . A third critical dimension cr3 of the n + -doped source region 134 can be defined in a self-aligned manner with respect to the edge of the trench 108, as referenced in Figure 5 , 6 .

[0096] Aspects and features mentioned and described in conjunction with one or more of the examples and figures previously described can also be combined with one or more of the examples in other examples to replace similar features of other examples or to otherwise introduce the features into other examples.

[0097] Although specific embodiments have been illustrated and described herein, those of ordinary skill in the art will understand that various alternative and / or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Accordingly, it is intended that the present invention be limited only by the claims and their equivalents.

Claims

1. A method of manufacturing a semiconductor device (100), the method comprising: forming a first mask pattern (102) over a first surface (104) of a wide bandgap semiconductor body (106); forming a trench (108) that extends from an opening (1021) in the first mask pattern (102) into the wide bandgap semiconductor body (106), wherein the trench (108) includes a first sidewall (1081) and an opposing second sidewall (1082); forming a first spacer mask pattern (110), the first spacer mask pattern (110) including a first spacer portion (1101) covering at least the first sidewall (1081) and a second spacer portion (1102) covering at least the second sidewall (1082); forming a second mask pattern (112) in the trench (108) between the first spacer portion (1101) of the first spacer mask pattern (110) and the second spacer portion (1102) of the first spacer mask pattern (110); exposing a trench portion (1083) of the trench (108) by removing at least a portion of the second spacer portion (1102) from the trench (108); and introducing dopants into the wide bandgap semiconductor body (106) through the trench portion (1083).

2. The method according to the preceding claim, wherein exposing the trench portion (1083) includes: forming a third mask pattern (114) over the first mask pattern (102), wherein the third mask pattern (112) covers a top surface of the first spacer portion (1101) of the first spacer mask pattern (110), and wherein a top surface of the second spacer portion (1102) of the first spacer mask pattern (110) is exposed through an opening (1141) in the third mask pattern (114).

3. The method according to the preceding claim, wherein exposing the trench portion (1083) further includes: selectively etching the second spacer portion (1102) of the first spacer mask pattern (110) with respect to any one of the first mask pattern (102), the second mask pattern (112), or the third mask pattern (114).

4. The method according to any one of the preceding claims, wherein the material of the first spacer portion (1101) of the first spacer mask pattern (110) is polysilicon, and the material of at least one of the first mask pattern (102) or the second mask pattern (112) is an oxide of silicon.

5. The method according to any one of the preceding claims, wherein introducing dopants into the wide bandgap semiconductor body (106) through the trench portion (1083) comprises: Introducing dopants into the wide bandgap semiconductor body (106) through the bottom side or the second sidewall (1082) of the trench (108) by ion implantation.

6. The method according to any one of the preceding claims, further comprising: removing the first mask pattern (102); and A second spacer mask pattern (116) is formed, the second spacer mask pattern (116) including a first spacer portion (1161) and a second spacer portion (1162), the first spacer portion (1161) being located in the trench portion (1083) between the wide-bandgap semiconductor body (106) and the second mask pattern (112), and the second spacer portion (1162) being laterally adjacent to the first spacer portion (1101) of the first spacer mask pattern (110).

7. The method according to the previous claim, wherein removing the first mask pattern (102) comprises: Forming a fourth mask pattern (118) over the first mask pattern (102), wherein the fourth mask pattern (118) covers the top surface of the second mask pattern (112) and the top surface of the first spacer portion (1101) of the first spacer mask pattern (110), and through an opening (1181) in the fourth mask pattern (118), a portion of the first mask pattern (102) is exposed.

8. The method according to the previous claim, wherein removing the first mask pattern (102) further comprises: Selectively etching the first mask pattern (102) with respect to either the first spacer portion (1101) of the first spacer mask pattern (110) or the fourth mask pattern (118).

9. The method according to any one of the preceding three claims, further comprising: By ion implantation, dopants are introduced into the wide-bandgap semiconductor body (106) through an opening (1163) in the second spacer mask pattern (116).

10. The method according to any one of the previous four claims, further comprising: Forming a sixth mask pattern (120) that is laterally adjacent to the first spacer portion and the second spacer portion (1161, 1162) of the second mask pattern (116); and Forming a seventh mask pattern (122) over the sixth mask pattern (120), wherein the seventh mask pattern (122) covers the top surface of the second mask pattern (112) and the top surface of the first spacer portion (1161) of the second spacer mask pattern (116), and wherein through an opening (1221) in the seventh mask pattern (122), the top surface of the second spacer portion (1162) of the second spacer mask pattern (116) is exposed.

11. The method according to the previous claim, further comprising: Exposing a surface portion of the wide-bandgap semiconductor body (106) by selectively etching the second spacer portion (1162) of the second spacer mask pattern (116) with respect to either the first spacer portion (1101) of the first spacer mask pattern (110) or the sixth mask pattern (120) or the seventh mask pattern (122).

12. The method according to the preceding claim, further comprising: By ion implantation, dopants are introduced into the wide bandgap semiconductor body (106) through the surface portion of the wide bandgap semiconductor body (106).

13. The method according to any one of the preceding claims, further comprising: Before forming the first mask pattern (102), dopants are introduced into the wide bandgap semiconductor body (106) through the first surface (104).

14. The method according to any one of the preceding claims, further comprising: After forming the trench (108) and before forming the first spacer mask pattern (110): A liner (136) is formed, and the liner (136) lines the bottom side and sidewalls (1081, 1082) of the trench (108) and the top side and sidewalls (1026, 1027) of the first mask pattern (102).

15. The method according to any one of the preceding claims, wherein exposing the groove portion (1083) further comprises: At least a portion of the second mask pattern (112) is removed.

16. A method of manufacturing a semiconductor device (100), the method comprising: Forming a first mask pattern (102) over a first surface (104) of a wide bandgap semiconductor body (106); Forming a trench (108) that extends from an opening (1021) in the first mask pattern (102) into the wide bandgap semiconductor body (106), wherein the trench (108) includes a first sidewall (1081) and an opposite second sidewall (1082); Forming a first spacer mask pattern (110) that includes a first spacer portion (1101) covering at least the first sidewall (1081) and a second spacer portion (1102) covering at least the second sidewall (1082); Forming a second mask pattern (112) that covers the first spacer portion (1101) of the first spacer mask pattern (110) and at least partially exposes the second spacer portion (1102) of the first spacer mask pattern (110); By removing at least a portion of the second spacer portion (1102) from the trench (108), a trench portion (1083) of the trench (108) is exposed; and Through the trench portion (1083), dopants are introduced into the wide bandgap semiconductor body (106).

17. The method according to the previous claim, wherein each of the first spacer portion (1101) and the second spacer portion of the first spacer mask pattern (110) includes a spacer (1105) of a first material and a covering layer (1106) on the spacer (1105), and the covering layer (1106) is formed of a second material different from the first material.

18. The method according to the previous claim, wherein the first material is polysilicon and the second material is an oxide of silicon.

19. The method according to any one of the previous three claims, wherein the second mask pattern (112) is a resist mask pattern.

20. The method according to any one of the preceding three claims, wherein, by an etching process, using the second mask pattern (112) as an etching mask, the covering layer (1106) of the second spacer portion (1102) is removed, and thereafter, the resist of the second mask pattern (112) is removed, and thereafter, the spacer (1105) of the second spacer portion (1102) is removed.

21. A method of manufacturing a semiconductor device (100), the method comprising: forming a first mask pattern (102) over a first surface (104) of a wide bandgap semiconductor body (106); forming a trench (108) extending from an opening (1021) in the first mask pattern (102) into the wide bandgap semiconductor body (106), wherein the trench (108) includes a first sidewall (1081) and an opposite second sidewall (1082); forming a first spacer mask pattern (110) including a first spacer portion (1101) covering at least the first sidewall (1081) and a second spacer portion (1102) covering at least the second sidewall (1082); altering a structure of the second spacer portion (1102) configured to increase a selective etchability of the second spacer portion (1102) relative to the first spacer portion (1101); and exposing a trench portion (1083) of the trench (108) by removing at least a portion of the second spacer portion (1102) from the trench (108); and introducing a dopant into the wide bandgap semiconductor body (106) through the trench portion (1083).

22. The method according to the preceding claim, wherein the selective etchability of the second spacer portion (1102) relative to the first spacer portion (1101) is increased by introducing an impurity into the second spacer portion (1102) by an inclined ion implantation process.

23. A method of manufacturing a semiconductor device (100), the method comprising: forming a first mask pattern (102) over a first surface (104) of a wide bandgap semiconductor body (106); forming a trench (108) extending from an opening (1021) in the first mask pattern (102) into the wide bandgap semiconductor body (106), wherein the trench (108) includes a first sidewall (1081) and an opposite second sidewall (1082); forming a first polysilicon spacer mask pattern (110) including a first polysilicon spacer portion (1101) covering at least the first sidewall (1081) and a second polysilicon spacer portion (1102) covering at least the second sidewall (1082); By removing the second polysilicon spacer portion (1102) from the trench (108), a trench portion (1083) of the trench (108) is exposed; And By oxidizing and removing a portion of the first polysilicon spacer portion (1101), the thickness of the first polysilicon spacer portion (1101) is changed.

24. The method according to the preceding claim, further comprising: After exposing the trench portion (1083) and before changing the thickness of the first polysilicon spacer portion (1101), dopants are introduced into the wide bandgap semiconductor body (106) through the trench portion (1083).

25. The method according to any one of the preceding two claims, further comprising: Repeat changing the thickness of the first polysilicon spacer portion (1101) by oxidizing and removing a portion of the first polysilicon spacer portion (1101).

26. The method according to the previous claim, further comprising: After changing and reducing the thickness of the first polysilicon spacer portion (1101), dopants are introduced into the wide bandgap semiconductor body (106) through the trench portion (1083).

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