LDMOS device manufacturing method and LDMOS device

Abstract

The invention provides a manufacturing method of an LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and the LDMOS device. The method comprises the following steps: forming an epitaxial layer on a substrate; drift regions, body regions, source regions and drain regions are formed in the epitaxial layer, the drain regions are located in the drift regions, the source regions are located in the body regions, and the drift regions are located on the two sides of the body regions; an HTO layer is formed on the surface of the epitaxial layer, the HTO layer is located on the surfaces of the body region, the drift region and part of the drain region, an initial opening is formed in the HTO layer, and the source region is exposed out of the initial opening; finishing the HTO layer for multiple times by adopting a Trimming process to adjust the initial opening and form a step opening, the side wall of the step opening being a step-shaped structure, the step-shaped structure having at least two steps, and the thickness of the HTO layer close to the drain region being greater than the thickness of the HTO layer close to the source region; and after the HTO layer is trimmed for a plurality of times, a polycrystalline silicon field plate is formed on the surface of the step-shaped structure, so that the electric field distribution of the LDMOS device can be better improved, and the on-resistance is reduced while the breakdown voltage of the device is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular, to a manufacturing method of an LDMOS device and an LDMOS device. Background Art

[0002] In the field of semiconductor technology, LDMOS (Laterally Diffused Metal Oxide Semiconductor) has been widely used in power management, radio frequency amplifiers, LED drivers, AC-DC conversion and other fields due to its advantages such as high input impedance, small leakage current, fast switching speed and good temperature stability.

[0003] At present, there are two ways to modulate the electric field on the surface of the drift region of an LDMOS device. One is to use STI to modulate the electric field on the surface of the drift region, and the other is to set a locally oxidized silicon structure (Local Oxidation of Silicon) with a relatively thick SiO2 layer on the surface of the drift region, and at the same time, the polysilicon gate extends to the field oxide layer to form a field plate structure to reduce the electric field strength on the surface of the device, thereby increasing the breakdown voltage of the device.

[0004] However, both of the above two methods have problems of large on-resistance and unsatisfactory electric field distribution. Specifically, as the thickness of the field plate increases, the current path will be extended, which will lead to an increase in on-resistance; at the same time, due to the influence of carrier injection and capacitance effect, the performance of the device will be limited.

[0005] Therefore, how to optimize the electric field distribution at the drain end and the drift region of the device so that the device has a higher breakdown voltage and a low on-resistance has become a technical problem that needs to be solved urgently in the industry. Summary of the Invention

[0006] The present invention provides a manufacturing method of an LDMOS device and an LDMOS device, which solves the technical problem of how to optimize the electric field distribution at the drain end and the drift region of the device so that the device has a higher breakdown voltage and a low on-resistance.

[0007] According to the first aspect of the present invention, the technical solution of the present invention provides a manufacturing method of an LDMOS device, including:

[0008] Providing a substrate;

[0009] Forming an epitaxial layer on the substrate;

[0010] Forming a drift region, a body region, a source region and a drain region in the epitaxial layer, the drain region is located in the drift region, the source region is located in the body region, and the drift region is located on both sides of the body region;

[0011] An HTO layer is formed on the surface of the epitaxial layer. The HTO layer is located on the surfaces of the body region, the drift region, and a part of the drain region. An initial opening is formed in the HTO layer, and the initial opening exposes the source region.

[0012] The Trimming process is used to trim the HTO layer several times to adjust the initial opening and form a stepped opening. The sidewall of the stepped opening is a stepped structure. The stepped structure has at least two levels of steps, and the thickness of the HTO layer near the drain region is higher than the thickness of the HTO layer near the source region.

[0013] After trimming the HTO layer several times, a polysilicon field plate is formed on the surface of the stepped structure.

[0014] Optionally, the method for forming an initial opening in the HTO layer includes:

[0015] A patterned initial trimming mask layer is formed on the HTO layer, and the initial trimming mask layer exposes a part of the surface of the epitaxial layer.

[0016] Using the initial trimming mask layer as a mask, the HTO layer is etched until the source region is exposed.

[0017] Optionally, the method for trimming the HTO layer several times using the Trimming process includes:

[0018] During the nth trimming, the (n - 1)th trimming mask layer is trimmed to form the nth trimming mask layer, where n is a positive integer greater than or equal to 1, and the 0th trimming mask layer is the initial trimming mask layer.

[0019] Using the nth trimming mask layer as a mask, the HTO layer is continuously etched to form a corresponding step.

[0020] Optionally, the height range of the step is

[0021] Optionally, the method for forming a drift region, a body region, a source region, and a drain region in the epitaxial layer includes:

[0022] A patterned first mask layer is formed on the epitaxial layer.

[0023] Using the first mask layer as a mask, ion implantation is performed on the epitaxial layer to form the drift region in the epitaxial layer.

[0024] A patterned second mask layer is formed on the epitaxial layer.

[0025] Using the second mask layer as a mask, perform ion implantation on the epitaxial layer to form the drain region within the epitaxial layer;

[0026] Form a patterned third mask layer on the epitaxial layer;

[0027] Using the third mask layer as a mask, perform ion implantation on the epitaxial layer to form the body region within the epitaxial layer;

[0028] Form a patterned fourth mask layer on the epitaxial layer;

[0029] Using the fourth mask layer as a mask, perform ion implantation on the epitaxial layer to form the source region within the epitaxial layer.

[0030] Optionally, after forming the drift region, body region, source region, and drain region within the epitaxial layer and before forming the HTO layer on the surface of the epitaxial layer, the method further includes:

[0031] Form a patterned fifth mask layer on the epitaxial layer;

[0032] Using the fifth mask layer as a mask, etch the epitaxial layer to form a plurality of shallow trenches spaced apart on both sides of the drift region within the epitaxial layer;

[0033] Form a shallow trench isolation structure within the shallow trenches;

[0034] After forming the shallow trench isolation structure, form a patterned sixth mask layer on the epitaxial layer;

[0035] Using the sixth mask layer as a mask, perform ion implantation on the epitaxial layer to form a well region within the epitaxial layer, and the well region is located between adjacent shallow trench isolation structures.

[0036] Optionally, the first step of the stepped structure is the channel region of the LDMOS device, and the remaining steps are used to adjust the voltage of the drain region.

[0037] Optionally, an extraction region is further formed within the body region, and the source region is located on both sides of the extraction region, and the initial opening also exposes the extraction region.

[0038] Optionally, after performing several trimmings on the HTO layer using the Trimming process and before forming a polysilicon field plate on the surface of the stepped structure, the method further includes:

[0039] Perform planarization on the surface of the stepped structure using a wet etching process.

[0040] According to a second aspect of the present invention, the technical solution of the present invention further provides an LDMOS device, including:

[0041] A substrate;

[0042] An epitaxial layer, located on the substrate, a drift region, a body region, a source region, and a drain region are formed in the epitaxial layer, the drain region is located in the drift region, the source region is located in the body region, and the drift region is located on both sides of the body region;

[0043] An HTO layer, located on the surface of the epitaxial layer, wherein the HTO layer is located on the surfaces of the body region, the drift region, and a part of the drain region, the HTO layer has a stepped opening, the stepped opening exposes the source region, the side wall of the stepped opening is a stepped structure, the stepped structure has at least two levels of steps, and the thickness of the HTO layer near the drain region is higher than the thickness of the HTO layer near the source region;

[0044] A polysilicon field plate, located on the surface of the stepped structure.

[0045] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0046] In the manufacturing method of the LDMOS device of the technical solution of the present invention, the HTO layer is trimmed several times by the Trimming process to adjust the initial opening to form a stepped opening, the side wall of the stepped opening is a stepped structure, the stepped structure has at least two levels of steps, and the thickness of the HTO layer near the drain region is higher than the thickness of the HTO layer near the source region, and a polysilicon field plate is formed on the surface of the stepped structure. Among them, each step of the HTO layer forms MOS capacitors of different sizes, and these MOS capacitors have a strong modulation effect on the surface electric field of the LDMOS device. Therefore, when the polysilicon field plate acts on the HTO layer by means of electric field modulation, the polysilicon field plate can utilize the electric field peaks generated at each step of the stepped HTO layer to make the surface electric field distribution of the LDMOS device uniform, and further achieve a higher breakdown voltage and a lower on-resistance; at the same time, since the formed polysilicon field plate is stepped polysilicon, the present invention also utilizes the thickness gradual change effect of the stepped polysilicon to reduce the electric field intensity in the junction region between the thicker HTO layer and the thinner polysilicon field plate on the drift region, thereby also being beneficial to improving the breakdown voltage of the device.

[0047] In the LDMOS device of the technical solution of the present invention, the device includes a substrate; an epitaxial layer located on the substrate, a drift region, a body region, a source region, and a drain region are formed in the epitaxial layer, the drain region is located in the drift region, the source region is located in the body region, and the drift region is located on both sides of the body region; an HTO layer located on the surface of the epitaxial layer, wherein the HTO layer is located on the surfaces of the body region, the drift region, and a part of the drain region, a stepped opening is formed in the HTO layer, the stepped opening exposes the source region, the side wall of the stepped opening is a stepped structure, the stepped structure has at least two levels of steps, and the thickness of the HTO layer near the drain region is higher than the thickness of the HTO layer near the source region; a polysilicon field plate is located on the surface of the stepped structure. In the present invention, the polysilicon field plate makes the surface electric field distribution of the LDMOS device uniform by using the electric field peaks generated at each step of the HTO layer, and thus can achieve a higher breakdown voltage and a lower on-resistance. At the same time, since the formed polysilicon field plate is a stepped polysilicon, the polysilicon field plate also utilizes the thickness gradual change effect of the stepped polysilicon to reduce the electric field strength in the junction region between the thicker HTO layer and the thinner polysilicon field plate on the drift region, thereby further improving the breakdown voltage of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0049] Figure 1 is a schematic structural diagram of an LDMOS device embodiment provided by an embodiment of the prior art;

[0050] Figure 2 is a schematic structural diagram of an LDMOS device embodiment provided by another embodiment of the prior art;

[0051] Figure 3 is a schematic structural diagram corresponding to the LOCOS device in the process flow provided by another embodiment of the prior art;

[0052] Figure 4 is a schematic flow chart of a manufacturing method of an LDMOS device provided by an embodiment of the present invention;

[0053] Figures 5 to 14 are schematic structural diagrams of the device corresponding to each step of the manufacturing method of the LDMOS device provided by an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0054] As described in the background art, it is difficult for the prior art to optimize the electric field distribution at the drain end and the drift region of the device, so that the device has a higher breakdown voltage and a low on-resistance. The following will be described in detail with reference to the drawings.

[0055] Figure 1 It is a schematic structural diagram of an embodiment of an LDMOS device.

[0056] Please refer to Figure 1 . It can be seen that in the LDMOS device structure in this example, the STI (Shallow Trench Isolation) technology is used to modulate the electric field on the surface of the drift region, providing a surface current path for the LDMOS device, thereby effectively reducing the surface electric field.

[0057] However, since the boundary of the STI will change the current flow path in the drift region (as shown by the arrows in Figure 1 ), and as the thickness of the STI field plate increases, the current path will also increase accordingly, resulting in an increase in the on-resistance. In addition, higher-energy carriers are likely to enter the oxide layer embedded in the semiconductor body, thereby forming traps and interface states, which has an adverse effect on the hot carrier injection degradation effect of the device, thus affecting the long-term stability and performance of the device.

[0058] Figure 2 It is a schematic structural diagram of another embodiment of an LDMOS device.

[0059] Please refer to Figure 2 . It can be seen that Figure 2 In the high-voltage LDMOS structure shown, a relatively thick SiO2 local oxidation of silicon (LOCOS) structure is used on the surface of the drift region to improve the voltage withstand capacity of the device. At the same time, the polysilicon gate extends to the field oxide layer to form a field plate structure, which is used to reduce the electric field strength on the surface of the device, thereby increasing the breakdown voltage of the device.

[0060] However, the boundary of the LOCOS will also affect the current flow path in the drift region (as shown by the arrows in Figure 2 ), and as the thickness of the LOCOS field plate increases, the current path will also extend, resulting in the problem of an increase in the on-resistance.

[0061] In actual implementation, Figure 2 In the solution shown, the sidewall of the field oxide layer is etched, so that the sidewall of the field oxide layer is trimmed into a stepped sidewall. However, please refer to Figure 3, in the LOCOS process flow, when thermally growing the LOCOS field oxide layer, oxygen atoms will diffuse both longitudinally and laterally. Longitudinally, oxygen atoms react with the underlying silicon through the already grown oxide to form a silicon oxide layer; laterally, oxygen atoms diffuse into the silicon region (i.e., the drift region) beneath the Si3N4 barrier layer and react with this silicon to form an oxide. Since the Si3N4 barrier layer has a blocking effect on the diffusion of oxygen, the growth of the oxide beneath the Si3N4 barrier layer is restricted, which results in the formation of a bulge in the middle of the field oxide layer and extends into the region beneath the Si3N4 barrier layer on both sides, thus generating a structure resembling a bird's beak.

[0062] The bird's beak structure will generate a tip effect, that is, it will cause the distribution of the electric field on the device surface to be uneven, resulting in a reduction in the breakdown voltage performance of the device. Especially at the tip of the bird's beak, the electric field will concentrate in this area, and this concentration of the electric field usually leads to an increase in the local electric field strength, thereby increasing the risk of breakdown.

[0063] It can be seen that how to optimize the electric field distribution of the LDMOS device, improve the breakdown voltage of the device and reduce the on-resistance of the device has become a technical problem that the industry urgently needs to solve at present.

[0064] To solve the above technical problems, the technical solution of the present invention provides a manufacturing method for an LDMOS device. This method uses the Trimming process to perform several trimmings on the HTO layer to adjust the initial opening to form a stepped opening. The sidewall of the stepped opening is a stepped structure, and the stepped structure has at least two levels of steps. Moreover, the thickness of the HTO layer near the drain region is higher than the thickness of the HTO layer near the source region, and a polysilicon field plate is formed on the surface of the stepped structure. The polysilicon field plate in the present invention can utilize the electric field peaks generated at each step in the stepped HTO layer to make the surface electric field distribution of the LDMOS device uniform, and thus can achieve a higher breakdown voltage and a lower on-resistance.

[0065] Next, the technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative efforts shall fall within the protection scope of the present invention.

[0066] The terms "first", "second", "third", "fourth", etc. (if any) in the description, claims and the above-mentioned drawings of the present invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0067] The technical solution of the present invention will be described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments.

[0068] Figure 4 It is a schematic flow chart of a method for manufacturing an LDMOS device provided by an embodiment of the present invention.

[0069] Please refer to Figure 4 , the method for manufacturing an LDMOS device includes:

[0070] S1: Provide a substrate;

[0071] S2: Form an epitaxial layer on the substrate;

[0072] S3: Form a drift region, a body region, a source region and a drain region in the epitaxial layer, the drain region is located in the drift region, the source region is located in the body region, and the drift region is located on both sides of the body region;

[0073] S4: Form an HTO layer on the surface of the epitaxial layer, the HTO layer is located on the surfaces of the body region, the drift region and a part of the drain region, and an initial opening is formed in the HTO layer, and the initial opening exposes the source region;

[0074] S5: Use the Trimming process to trim the HTO layer several times to adjust the initial opening to form a stepped opening, the side wall of the stepped opening is a stepped structure, the stepped structure has at least two levels of steps, and the thickness of the HTO layer near the drain region is higher than the thickness of the HTO layer near the source region;

[0075] S6: After trimming the HTO layer several times, form a polysilicon field plate on the surface of the stepped structure.

[0076] It can be seen that the present invention uses the Trimming process to trim the HTO layer several times to adjust the initial opening to form a stepped opening. The side wall of the stepped opening is a stepped structure, and the stepped structure has at least two levels of steps. Moreover, the thickness of the HTO layer near the drain region is higher than that of the HTO layer near the source region, and a polysilicon field plate is formed on the surface of the stepped structure. Among them, each step of the HTO layer corresponds to forming MOS capacitors of different sizes, and these MOS capacitors have a strong modulation effect on the surface electric field of the LDMOS device. Therefore, when the polysilicon field plate acts on the HTO layer by means of electric field modulation, the polysilicon field plate can utilize the electric field peaks generated at each step in the stepped HTO layer to make the surface electric field distribution of the LDMOS device uniform, and thus can achieve a higher breakdown voltage and a lower on-resistance. At the same time, since the formed polysilicon field plate is stepped polysilicon, the present invention also utilizes the thickness gradual change effect of the stepped polysilicon to reduce the electric field strength in the junction region between the thicker HTO layer and the thinner polysilicon field plate on the drift region, thereby also being beneficial to improving the breakdown voltage of the device.

[0077] Figures 5 to 14 Schematic diagrams of device structures corresponding to each step of the manufacturing method of the LDMOS device provided by an embodiment of the present invention. The following will be based on Figure 4 and in combination with Figures 5 to 14 to detail each step in the preparation process of the LDMOS device provided by the embodiment of the present invention.

[0078] Please refer to Figure 5 to provide a substrate 101.

[0079] As an example, the substrate 101 can be an SOI substrate, a silicon substrate, etc. The present invention does not limit this, and those skilled in the art can select a suitable substrate 101 according to needs.

[0080] Please refer to Figure 6 to form an epitaxial layer 103 on the substrate 101.

[0081] As a preferred method, in the example of Figure 6 , a buried layer 102 is further formed on the substrate 101, and the buried layer 102 is used to reduce parasitic effects and achieve electrical isolation.

[0082] In a preferred embodiment, after forming the buried layer and the epitaxial layer, a bottom P-well 104 is further formed on the surface of the buried layer 102 corresponding to the drift region and the body region by using the Co-Implantation technology to prevent the Punch-Through effect and optimize the electric field distribution.

[0083] Please refer to Figure 7, a drift region 1031, a body region 1032, a source region 1033, and a drain region 1034 are formed in the epitaxial layer 103. The drain region 1034 is located within the drift region 1031, the source region 1033 is located within the body region 1032, and the drift region 1031 is located on both sides of the body region 1032.

[0084] In one implementation, the method of forming a drift region 1031, a body region 1032, a source region 1033, and a drain region 1034 in the epitaxial layer 103 includes: forming a patterned first mask layer on the epitaxial layer 103; using the first mask layer as a mask, performing ion implantation on the epitaxial layer 103 to form the drift region 1031 in the epitaxial layer 103; forming a patterned second mask layer on the epitaxial layer 103; using the second mask layer as a mask, performing ion implantation on the epitaxial layer 103 to form the drain region 1034 in the epitaxial layer 103; forming a patterned third mask layer on the epitaxial layer 103; using the third mask layer as a mask, performing ion implantation on the epitaxial layer 103 to form the body region 1032 in the epitaxial layer 103; forming a patterned fourth mask layer on the epitaxial layer 103; using the fourth mask layer as a mask, performing ion implantation on the epitaxial layer 103 to form the source region 1033 in the epitaxial layer 103.

[0085] Please continue to refer to Figure 7 , in actual implementation, a lead-out region 1035 is further formed in the body region 1032, and the source region 1033 is located on both sides of the lead-out region.

[0086] Considering that subsequent high-temperature process technologies may damage the doped layer, buried layer 102, and contact region pre-formed in the substrate 101, resulting in problems such as doping diffusion, interface degradation, and unstable device performance. In a preferred implementation, please refer to Figure 7 , after forming a drift region 1031, a body region 1032, a source region 1033, and a drain region 1034 in the epitaxial layer 103, a shallow trench isolation structure 1036 and a well region are further formed in the epitaxial layer 103.

[0087] Specifically, a patterned fifth mask layer is formed on the epitaxial layer 103; using the fifth mask layer as a mask, etching the epitaxial layer 103 to form a plurality of shallow trenches spaced apart on both sides of the drift region 1031 in the epitaxial layer 103; forming a shallow trench isolation structure in the shallow trenches; after forming the shallow trench isolation structure, forming a patterned sixth mask layer on the epitaxial layer 103; using the sixth mask layer as a mask, performing ion implantation on the epitaxial layer 103 to form a well region in the epitaxial layer 103, and the well region is located between adjacent shallow trench isolation structures.

[0088] In actual work, the well region will be divided into a P-type well region and an N-type well region, and a heavily doped region will also be formed on the top of the well region to reduce the contact resistance, suppress parasitic effects, and improve the carrier injection efficiency.

[0089] In Figure 7 the example of

[0090] it should be understood that the positions of the P-type well region and the N-type well region in the present invention are only examples. In actual production, those skilled in the art can select appropriate positions to set the well region according to needs.

[0091] Please refer to Figure 8 , and an HTO layer 301 is formed on the surface of the epitaxial layer 103.

[0092] As an example, the method of forming the HTO layer 301 can be: depositing an HTO material layer on the surface of the epitaxial layer 103 by using a chemical vapor deposition process; forming a seventh mask layer on the surface of the material layer, and the seventh mask layer exposes a part of the surface of the HTO material layer; using the seventh mask layer as a mask to etch the HTO material layer until the surface of the epitaxial layer is exposed, so as to form the HTO layer 301.

[0093] Among them, the HTO layer can be understood as High-Temperature Oxidation, a high-temperature thermal oxidation deposition layer.

[0094] Next, please refer to Figure 9 , and an initial opening is formed in the HTO layer 301.

[0095] Specifically, the method of forming an initial opening in the HTO layer includes: forming a patterned initial trimming mask layer 400 on the HTO layer 301, and the initial trimming mask layer 400 exposes a part of the surface of the epitaxial layer 103; using the initial trimming mask layer 400 as a mask to etch the HTO layer 301 until the source region 1033 is exposed.

[0096] In this embodiment Figure 9 , a lead-out region 1035 is further formed in the body region 1032, and then the initial opening will also expose the lead-out region 1035.

[0097] Next, the HTO layer 301 is trimmed several times using the Trimming process to adjust the initial opening and form a stepped opening. The sidewall of the stepped opening is a stepped structure, the stepped structure has at least two levels of steps, and the thickness of the HTO layer 301 near the drain region 1034 is higher than the thickness of the HTO layer 301 near the source region 1033.

[0098] Among them, the two boundaries of the stepped opening are respectively aligned with the boundary of the drain region 1034 close to the body region 1032 and the boundary of the source region 1033 close to the body region 1032.

[0099] In a specific embodiment, the height range of the steps is Of course, the present invention does not limit this, and those skilled in the art can select an appropriate step height according to needs.

[0100] In one embodiment, the method of trimming the HTO layer 301 several times using the Trimming process includes:

[0101] During the nth trimming, the (n - 1)th trimming mask layer is trimmed to form the nth trimming mask layer, where n is a positive integer greater than or equal to 1, and the 0th trimming mask layer is the initial trimming mask layer 400;

[0102] Using the nth trimming mask layer as a mask, continue to etch the HTO layer 301 to form corresponding steps.

[0103] It can be seen that the present invention only needs one photolithography mold to form a stepped structure, without the need for multiple overlay dimensions. While improving the manufacturing accuracy, it also simplifies the process flow and reduces the manufacturing cost.

[0104] Now, taking the number of steps in this embodiment as 3 layers as an example, combined with Figures 10 to 12 the method of trimming the HTO layer 301 in the embodiment of the present invention will be described.

[0105] Please refer to Figure 10 , during the first trimming, the initial trimming mask layer 400 is trimmed to form the first trimming mask layer 401; using the first trimming mask layer 401 as a mask, the HTO layer 301 is etched to form the first - level step.

[0106] Please refer to Figure 11 , during the second trimming, the first trimming mask layer 401 is trimmed to form the second trimming mask layer 402; using the second trimming mask layer 402 as a mask, the HTO layer 301 is etched to form the second - level step.

[0107] Please refer to Figure 12 During the third trimming, the second trimming mask layer 402 is trimmed to form a third trimming mask layer 403; using the third trimming mask layer 403 as a mask, the HTO layer 301 is etched to form a third-level step.

[0108] Among them, the first-level step in the stepped structure is the channel region of the LDMOS device, and the remaining steps are used to adjust the voltage of the drain region 1034.

[0109] Considering that burrs will appear on the surface of the HTO layer 301 during the trimming process, and these burrs will affect the uniformity of the electric field. Therefore, in a preferred embodiment, after performing several trimmings on the HTO layer 301 using the Trimming process, the method further includes:

[0110] Performing planarization on the surface of the stepped structure using a wet etching process.

[0111] Thus, the present invention reduces the surface roughness of the stepped structure, improves the uniformity of the electric field on the device surface, and increases the breakdown voltage of the device, thereby ensuring that the device has good reliability and performance.

[0112] As an example, in the embodiment of the present invention, the etching agent for the wet etching process includes nitric acid and hydrofluoric acid.

[0113] Please refer to Figure 13 , depositing a polysilicon material layer on the surface of the stepped opening; forming a patterned seventh mask layer 207 on the polysilicon material layer; using the seventh mask layer 207 as a mask, etching the polysilicon material layer to form the polysilicon field plate 303 on the epitaxial layer 103.

[0114] Please refer to Figure 14 , removing the seventh mask layer 207.

[0115] Since in actual operation, the number of steps will be much greater than 3 (as shown in the example of Figure 13 ), finally, the surface of the polysilicon field plate 303 facing away from the epitaxial layer 103 shows an approximately smooth transition, which can achieve a better electric field distribution.

[0116] In actual implementation, before depositing the polysilicon material layer on the surface of the stepped opening, an oxide layer 302 is also deposited on the surface of the HTO layer 301. In some embodiments, this oxide layer 302 can be understood as a gate oxide layer (gate ox).

[0117] Since the surface of the polysilicon field plate 303 close to the epitaxial layer 103 is stepped, the present invention also utilizes the thickness gradual change effect of the stepped polysilicon to reduce the electric field strength in the junction region between the thicker HTO layer 301 and the thinner oxide layer 302 on the drift region 1031. Thus, it is also beneficial to improve the breakdown voltage of the device.

[0118] And in this case, a capacitance will be formed between the polysilicon field plate 303 and the epitaxial layer 103 through a dielectric (HTO layer 301 and oxide layer 302). Among them, each step of the HTO layer 301 corresponds to forming MOS capacitors of different sizes. These MOS capacitors have a strong modulation effect on the surface electric field of the LDMOS device. And from the drain region 1034 to the source region 1033, the capacitance value of the MOS capacitor linearly decreases. Thus, the present invention can achieve effective linear modulation of the surface electric field of the LDMOS device.

[0119] Therefore, when the polysilicon field plate 303 acts on the HTO layer 301 in the way of electric field modulation, the polysilicon field plate 303 can utilize the electric field peaks generated at each step in the stepped HTO layer 301 to make the surface electric field distribution of the LDMOS device uniform, and further can achieve a higher breakdown voltage and a lower on-resistance.

[0120] Moreover, the boundary of the HTO layer in the present invention does not affect the current flow path in the drift region and does not increase the on-resistance of the LDMOS device.

[0121] In summary, in the manufacturing method of the LDMOS device according to the embodiment of the present invention, the Trimming process is adopted to trim the HTO layer several times to adjust the initial opening to form a stepped opening. The side wall of the stepped opening is a stepped structure. The stepped structure has at least two levels of steps. And the thickness of the HTO layer close to the drain region is higher than the thickness of the HTO layer close to the source region. And a polysilicon field plate is formed on the surface of the stepped structure. Among them, each step of the HTO layer corresponds to forming MOS capacitors of different sizes. These MOS capacitors have a strong modulation effect on the surface electric field of the LDMOS device. Therefore, when the polysilicon field plate acts on the HTO layer in the way of electric field modulation, the polysilicon field plate can utilize the electric field peaks generated at each step in the stepped HTO layer to make the surface electric field distribution of the LDMOS device uniform, and further can achieve a higher breakdown voltage and a lower on-resistance. At the same time, since the formed polysilicon field plate is stepped polysilicon, the present invention also utilizes the thickness gradual change effect of the stepped polysilicon to reduce the electric field strength in the junction region between the thicker HTO layer and the thinner polysilicon field plate on the drift region. Thus, it is also beneficial to improve the breakdown voltage of the device.

[0122] Correspondingly, the embodiment of the present invention also provides an LDMOS device. Please continue to refer to Figure 14, the LDMOS device includes: a substrate 101; an epitaxial layer 103 located on the substrate 101, in which a drift region 1031, a body region 1032, a source region 1033, and a drain region 1034 are formed. The drain region 1034 is located within the drift region 1031, the source region 1033 is located within the body region 1032, and the drift region 1031 is located on both sides of the body region 1032; an HTO layer 301 located on the surface of the epitaxial layer 103. Among them, the HTO layer 301 is located on the surfaces of the body region 1032, the drift region 1031, and a part of the drain region 1034. The HTO layer 301 has a stepped opening that exposes the source region 1033. The sidewall of the stepped opening is a stepped structure, and the stepped structure has at least two levels of steps. Moreover, the thickness of the HTO layer 301 near the drain region 1034 is higher than the thickness of the HTO layer 301 near the source region 1033; a polysilicon field plate 303 is located on the surface of the stepped structure.

[0123] Among them, the two boundaries of the stepped opening are respectively aligned with the boundary of the drain region 1034 close to the body region 1032 and the boundary of the source region 1033 close to the body region 1032.

[0124] In actual implementation, the height range of the steps is between. Of course, the present invention does not limit this, and those skilled in the art can select appropriate step heights according to needs.

[0125] In Figure 14 example, a lead-out region 1035 is further formed in the body region 1032, and then the stepped opening will also expose the lead-out region 1035.

[0126] In one embodiment, the LDMOS device is prepared based on the LDMOS device preparation method in any of the above technical solutions. Therefore, this LDMOS device has all the beneficial effects of the LDMOS device preparation method in the above technical solutions, and the present invention will not elaborate herein.

[0127] In summary, the polysilicon field plate in the LDMOS device of the technical solution of the present invention makes the surface electric field distribution of the LDMOS device uniform by using the electric field peaks generated at each step of the HTO layer, and thus can achieve a higher breakdown voltage and a lower on-resistance. At the same time, since the formed polysilicon field plate is a stepped polysilicon, the polysilicon field plate also utilizes the thickness gradual change effect of the stepped polysilicon to reduce the electric field strength in the junction region between the thicker HTO layer and the thinner polysilicon field plate on the drift region, thereby further improving the breakdown voltage of the device.

[0128] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A manufacturing method of an LDMOS device, characterized in that, Comprising: Providing a substrate; Forming an epitaxial layer on the substrate; Forming a drift region, a body region, a source region, and a drain region in the epitaxial layer, wherein the drain region is located within the drift region, the source region is located within the body region, and the drift region is located on both sides of the body region; Forming an HTO layer on the surface of the epitaxial layer, the HTO layer being located on the surfaces of the body region, the drift region, and a part of the drain region, and having an initial opening within the HTO layer that exposes the source region; Performing a plurality of trimmings on the HTO layer using a Trimming process to adjust the initial opening to form a stepped opening, the sidewall of the stepped opening being a stepped structure that has at least two levels of steps, and the thickness of the HTO layer near the drain region being higher than the thickness of the HTO layer near the source region; After performing a plurality of trimmings on the HTO layer, forming a polysilicon field plate on the surface of the stepped structure.

2. The manufacturing method of the LDMOS device according to claim 1, characterized in that, The method for forming an initial opening within the HTO layer includes: Forming a patterned initial trimming mask layer on the HTO layer, the initial trimming mask layer exposing a part of the surface of the epitaxial layer; Using the initial trimming mask layer as a mask to etch the HTO layer until the source region is exposed.

3. The manufacturing method of the LDMOS device according to claim 2, characterized in that, The method for performing a plurality of trimmings on the HTO layer using a Trimming process includes: During the nth trimming, trimming the (n - 1)th trimming mask layer to form the nth trimming mask layer, where n is a positive integer greater than or equal to 1, and the 0th trimming mask layer is the initial trimming mask layer; Using the nth trimming mask layer as a mask to continue etching the HTO layer to form a corresponding step.

4. The manufacturing method of the LDMOS device according to claim 1, characterized in that, The height range of the said step is 5. The manufacturing method of the LDMOS device according to claim 1, characterized in that, The method for forming a drift region, a body region, a source region, and a drain region within the epitaxial layer includes: Forming a patterned first mask layer on the epitaxial layer; Using the first mask layer as a mask to perform ion implantation on the epitaxial layer to form the drift region within the epitaxial layer; After forming the drift region, forming a patterned second mask layer on the epitaxial layer; Using the second mask layer as a mask to perform ion implantation on the epitaxial layer to form the drain region within the epitaxial layer; Forming a patterned third mask layer on the epitaxial layer; Using the third mask layer as a mask to perform ion implantation on the epitaxial layer to form the body region within the epitaxial layer; Forming a patterned fourth mask layer on the epitaxial layer; Using the fourth mask layer as a mask to perform ion implantation on the epitaxial layer to form the source region within the epitaxial layer.

6. The manufacturing method of the LDMOS device according to claim 5, characterized in that, After forming a drift region, a body region, a source region, and a drain region within the epitaxial layer, and before forming an HTO layer on the surface of the epitaxial layer, the method further includes: Forming a patterned fifth mask layer on the epitaxial layer; Using the fifth mask layer as a mask to etch the epitaxial layer to form a plurality of shallow trenches spaced apart on both sides of the drift region within the epitaxial layer; Forming a shallow trench isolation structure within the shallow trenches; After forming the shallow trench isolation structure, forming a patterned sixth mask layer on the epitaxial layer; Using the sixth mask layer as a mask, ion implant the epitaxial layer to form a well region within the epitaxial layer, the well region being located between adjacent shallow trench isolation structures.

7. The manufacturing method of the LDMOS device according to claim 1, characterized in that, The first step in the stepped structure is the channel region of the LDMOS device, and the remaining steps are used to adjust the voltage of the drain region.

8. The manufacturing method of the LDMOS device according to claim 1, characterized in that, An extraction region is also formed within the body region, and the source regions are located on both sides of the extraction region, and the initial opening also exposes the extraction region.

9. The manufacturing method of the LDMOS device according to claim 1, characterized in that, After performing a number of trimmings on the HTO layer using a Trimming process and before forming a polysilicon field plate on the surface of the stepped structure, the method further includes: Performing planarization on the surface of the stepped structure using a wet etching process.

10. An LDMOS device, characterized in that, Comprising: A substrate; An epitaxial layer, located on the substrate, a drift region, a body region, a source region, and a drain region being formed within the epitaxial layer, the drain region being located within the drift region, the source regions being located within the body region, and the drift region being located on both sides of the body region; An HTO layer, located on the surface of the epitaxial layer, wherein the HTO layer is located on the surfaces of the body region, the drift region, and a part of the drain region, the HTO layer having a stepped opening, the stepped opening exposing the source regions, the sidewalls of the stepped opening being a stepped structure, the stepped structure having at least two steps, and the thickness of the HTO layer near the drain region being higher than the thickness of the HTO layer near the source regions; A polysilicon field plate, located on the surface of the stepped structure.

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