Semiconductor power device and preparation method thereof

Abstract

This application relates to the field of semiconductor technology and discloses a semiconductor power device and a method for fabricating the same, comprising: providing an N+ substrate, forming a first epitaxial layer on the N+ substrate, forming a first P-type diffusion region on the first epitaxial layer; forming at least one second epitaxial layer on the first epitaxial layer, forming a second P-type diffusion region on the second epitaxial layer; forming at least one third epitaxial layer on the second epitaxial layer, forming a third P-type diffusion region on the third epitaxial layer; forming a fourth epitaxial layer on the third epitaxial layer, and connecting the first P-type diffusion region, the second P-type diffusion region, and the third P-type diffusion region into one; and forming a double-layer shielded gate structure in the gate trench of the fourth epitaxial layer. This application reduces the on-resistance per unit area and conduction loss of a semiconductor power device while maintaining the same withstand voltage.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor power device and a method for preparing the same. Background Art

[0002] In semiconductor manufacturing, performance optimization of power semiconductor devices has become a core focus of technological research and development. Shielded-gate trench metal-oxide semiconductor field-effect transistors (SGT-MOSFETs), with their low conduction losses, high switching speeds, and excellent withstand voltage characteristics, play a crucial role in medium- and high-voltage power conversion scenarios. As switching devices, they are used in motor drive systems, inverter systems, and power management systems for new energy electric vehicles, new photovoltaic power generation, and energy-saving home appliances, serving as core power control components. However, as device efficiency requirements continue to increase in application scenarios, reducing conduction losses while maintaining withstand voltage (BV) has become crucial for SGT-MOSFET performance upgrades. Summary of the Invention

[0003] In view of this, the present application provides a semiconductor power device and a method for preparing the same, so as to reduce the on-resistance per unit area of ​​the semiconductor power device and reduce the conduction loss under the premise of the same withstand voltage.

[0004] In a first aspect, the present invention discloses a method for manufacturing a semiconductor power device, comprising:

[0005] Providing an N+ substrate;

[0006] forming a first epitaxial layer of the same doping type as the N+ substrate, performing ion implantation on the first epitaxial layer, and then forming a first P-type diffusion region on the first epitaxial layer;

[0007] forming at least one second epitaxial layer on the first epitaxial layer, performing ion implantation on the second epitaxial layer, and then forming a second P-type diffusion region on the second epitaxial layer;

[0008] forming at least one third epitaxial layer on the second epitaxial layer, and forming a third P-type diffusion region on the third epitaxial layer after ion implantation on the third epitaxial layer;

[0009] forming a fourth epitaxial layer on the third epitaxial layer, and connecting the first P-type diffusion region, the second P-type diffusion region, and the third P-type diffusion region into one by high-temperature diffusion to form a functional diffusion region;

[0010] forming a plurality of gate trenches on the fourth epitaxial layer, and forming a double-layer shielding gate structure on the gate trenches;

[0011] Performing self-aligned ion implantation between adjacent gate trenches on the fourth epitaxial layer to form a P-type body region and an N+ source region located above the P-type body region;

[0012] A contact hole region connected to the P-type body region and a source metal layer covering the contact hole region are formed on the fourth epitaxial layer, and a drain region is formed on the N+ substrate back gold.

[0013] In a possible example, when forming the first P-type diffusion region, the second P-type diffusion region, and the third P-type diffusion region, respectively, the ion implantation concentrations in the first epitaxial layer, the second epitaxial layer, and the third epitaxial layer are the same.

[0014] In a possible example: the formation area of ​​the first P-type diffusion region on the first epitaxial layer is S1, the formation area of ​​the second P-type diffusion region on the second epitaxial layer is S2, and the formation area of ​​the third P-type diffusion region on the third epitaxial layer is S3, then the vertical projections of S1, S2, and S3 in the direction from the fourth epitaxial layer to the N+ substrate are concentrically arranged and overlap with each other.

[0015] In a possible example, when forming the first P-type diffusion region, the second P-type diffusion region, and the third P-type diffusion region, respectively, ion implantation doses for the first epitaxial layer, the second epitaxial layer, and the third epitaxial layer are distributed in a stepped manner.

[0016] In a possible example, in the direction from the fourth epitaxial layer to the N+ substrate, the curve profile of the side lines connecting the first P-type diffusion region, the second P-type diffusion region, and the third P-type diffusion region on the same side is normally distributed.

[0017] In a possible example, forming a double-layer shielding gate structure on the gate trench includes:

[0018] forming a first trench oxide layer on the bottom and sidewalls of the gate trench;

[0019] Depositing a first polysilicon layer in the gate trench, wherein the first polysilicon layer covers the first trench oxide layer, etching back the first polysilicon layer from the top to the bottom of the gate trench to a first etching back depth, and then continuing to etch back the first trench oxide layer to the first etching back depth, wherein the first trench oxide layer after etching back forms a second trench oxide layer;

[0020] Depositing a second polysilicon layer in the gate trench, wherein the second polysilicon layer covers the first polysilicon layer and the second trench oxide layer, and etching back the second polysilicon layer and the second trench oxide layer to a second etching back depth;

[0021] A gate structure is formed in the gate trench.

[0022] In a possible example, forming a gate structure in the gate trench includes:

[0023] forming a gate oxide layer in the gate trench, wherein the gate oxide layer covers the second polysilicon layer and the sidewall of the gate trench;

[0024] depositing a gate polysilicon layer in the gate trench;

[0025] After etching back the gate polysilicon layer to below the top surface of the fourth epitaxial layer, the gate oxide layer flush with the top surface of the fourth epitaxial layer is formed on the gate polysilicon layer.

[0026] In a possible example, the functional diffusion region is formed in part of the first epitaxial layer, the second epitaxial layer, the third epitaxial layer, and the fourth epitaxial layer.

[0027] In a possible example, forming a contact hole region connected to the P-type body region on the fourth epitaxial layer includes:

[0028] forming a field oxide layer on the fourth epitaxial layer;

[0029] Etching a contact hole on the field oxide layer through a contact hole mask, wherein the contact hole extends from the top surface of the fourth epitaxial layer into the P-type body region;

[0030] P++ ions are implanted into the contact hole to form the contact hole region.

[0031] In a second aspect, an embodiment of the present application discloses a semiconductor power device, which is prepared by the semiconductor power device preparation method described in any of the above embodiments, comprising:

[0032] N+ substrate, functional diffusion region, double-layer shielded gate structure, P-type body region, N+ source region, contact hole region, source metal layer and drain region;

[0033] A first epitaxial layer, a second epitaxial layer, a third epitaxial layer, and a fourth epitaxial layer are sequentially stacked on the N+ substrate; the functional diffusion region is connected to a portion of the first epitaxial layer, the second epitaxial layer, the third epitaxial layer, and the fourth epitaxial layer; and a plurality of gate trenches are provided on the fourth epitaxial layer, and the double-layer shielded gate structure is configured in the gate trenches;

[0034] The P-type body region is connected between adjacent gate trenches in the fourth epitaxial layer;

[0035] The N+ source region is connected to the P-type body region in the fourth epitaxial layer;

[0036] The contact hole region is provided on the fourth epitaxial layer between adjacent gate trenches and connected to the P-type body region;

[0037] The source metal layer is provided on the top surface of the fourth epitaxial layer and covers the contact hole region;

[0038] The drain region is arranged on the bottom surface of the N+ substrate.

[0039] In summary, compared with the prior art, the present application discloses a semiconductor power device and a preparation method thereof, comprising: forming a first epitaxial layer of the same doping type on an N+ substrate, performing ion implantation on the first epitaxial layer, and then forming a first P-type diffusion region on the first epitaxial layer; forming at least one second epitaxial layer on the first epitaxial layer, performing ion implantation on the second epitaxial layer, and then forming a second P-type diffusion region on the second epitaxial layer; forming at least one third epitaxial layer on the second epitaxial layer, performing ion implantation on the third epitaxial layer, and then forming a third P-type diffusion region on the third epitaxial layer; forming a fourth epitaxial layer on the third epitaxial layer, and implanting the fourth epitaxial layer into the epitaxial layer by high-temperature diffusion; forming the fourth epitaxial layer on the third epitaxial layer, and then implanting the fourth epitaxial layer into the epitaxial layer by high-temperature diffusion; forming the fourth epitaxial layer on the ... second epitaxial layer on the epitaxial layer, and then implanting the second epitaxial layer into the epitaxial layer. A P-type diffusion region, a second P-type diffusion region and a third P-type diffusion region are connected as a whole to form a functional diffusion region; a plurality of gate trenches are formed on the fourth epitaxial layer, and a double-layer shielded gate structure is formed on the gate trenches; self-aligned ion implantation is performed between adjacent gate trenches on the fourth epitaxial layer to form a P-type body region and an N+ source region located above the P-type body region; a contact hole region connected to the P-type body region and a source metal layer covering the contact hole region are formed on the fourth epitaxial layer, and a drain region is formed by back gold on the N+ substrate. That is, through the above arrangement, the power device uses an N-type epitaxial layer with a higher concentration, thereby reducing the on-resistance per unit area of ​​the power device and reducing the conduction loss. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following is a brief introduction to the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0041] Figure 1 This is a flow chart of a method for preparing a semiconductor power device according to an embodiment of the present application;

[0042] Figure 2 This is a schematic structural diagram of the first semiconductor power device according to an embodiment of the present application;

[0043] Figure 3 This is a schematic structural diagram of the second semiconductor power device according to an embodiment of the present application;

[0044] Figure 4 This is a schematic structural diagram of the third semiconductor power device according to an embodiment of the present application;

[0045] Figure 5 This is a schematic structural diagram of the fourth semiconductor power device according to an embodiment of the present application;

[0046] Figure 6 This is a schematic structural diagram of the fifth semiconductor power device according to an embodiment of the present application;

[0047] Figure 7 This is a schematic structural diagram of the sixth semiconductor power device according to an embodiment of the present application;

[0048] Figure 8 This is a schematic structural diagram of the seventh semiconductor power device according to an embodiment of the present application;

[0049] Figure 9 This is a schematic structural diagram of the eighth semiconductor power device according to an embodiment of the present application;

[0050] Figure 10 This is a sub-flowchart of the method for preparing a semiconductor power device according to an embodiment of the present application. DETAILED DESCRIPTION

[0051] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. When the following description refers to the drawings, identical numbers in different figures represent identical or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.

[0052] It should be noted that, in this document, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprising a ..." does not exclude the presence of other identical elements in the process, method, article or device comprising the element. In addition, components, features, and elements with the same name in different embodiments of the present application may have the same meaning or different meanings, and their specific meanings need to be determined based on their explanation in the specific embodiment or further combined with the context of the specific embodiment.

[0053] It should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application.

[0054] In the subsequent description, the use of suffixes such as "module", "component" or "unit" to represent elements is only for the purpose of facilitating the description of the present application and has no specific meaning. Therefore, "module", "component" or "unit" can be used interchangeably.

[0055] In the description of this application, it should be noted that the terms "upper," "lower," "left," "right," "inner," and "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate the description of this application and simplify the description. They do not indicate or imply that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0056] The technical solutions shown in this application will be described in detail below through specific embodiments. It should be noted that the description order of the following embodiments does not limit the priority order of the embodiments.

[0057] Please refer to Figure 1 , and combined Figures 2 to 9 The method for preparing a semiconductor power device according to an embodiment of the present application includes:

[0058] S101, providing an N+ substrate 1.

[0059] In a possible implementation of this application, reference Figure 2 The material for forming the N+ substrate 1 can be single crystal silicon, polycrystalline silicon, amorphous silicon or doped silicon. The material of the N+ substrate 1 can also be a SiGe substrate, a III-V group element compound substrate, a silicon carbide substrate or a stacked structure thereof, or a silicon-on-insulator structure. It can also be a diamond substrate or other semiconductor material substrates known to those skilled in the art. For example, P atoms can be implanted into single crystal silicon to form an N-type conductive semiconductor substrate to improve the material selectivity and adaptability to the actual production environment.

[0060] In an example, the N+ substrate 1 can be divided into several cell regions to include a large number of repeated basic units of the semiconductor power device, and the gate trench on the N+ substrate 1 can be regarded as a cell trench.

[0061] S102 , forming a first epitaxial layer 21 of the same doping type on the N+ substrate 1 , performing ion implantation on the first epitaxial layer 21 , and then forming a first P-type diffusion region 31 on the first epitaxial layer 21 .

[0062] In a possible implementation of this application, reference Figures 2 to 4A first epitaxial layer 21 is formed on the N+ substrate 1 through an epitaxial growth process. The first epitaxial layer 21 has the same N-type doping as the N+ substrate 1. After the first epitaxial layer 21 is formed, a P-type ion implantation process is performed to form a first P-type diffusion region 31.

[0063] S103 , forming at least one second epitaxial layer 22 on the first epitaxial layer 21 , performing ion implantation on the second epitaxial layer 22 , and then forming a second P-type diffusion region 32 on the second epitaxial layer 22 .

[0064] In a possible implementation of this application, reference Figure 3 and Figure 4 At least one second epitaxial layer 22 is formed on the first epitaxial layer 21 through an epitaxial growth process. The second epitaxial layer 22 has the same N-type doping as the first epitaxial layer 21. After the second epitaxial layer 22 is formed, a P-type ion implantation process is performed to form a second P-type diffusion region 32.

[0065] It is understandable that, according to device design requirements or specific application environment requirements, the second epitaxial layer 22 can be provided as a single layer or multiple layers.

[0066] S104 , forming at least one third epitaxial layer 23 on the second epitaxial layer 22 , performing ion implantation on the third epitaxial layer 23 , and forming a third P-type diffusion region 33 on the third epitaxial layer 23 .

[0067] In a possible implementation of this application, reference Figure 3 and Figure 4 At least one third epitaxial layer 23 is formed on the second epitaxial layer 22 through an epitaxial growth process. The third epitaxial layer 23 has the same N-type doping as the second epitaxial layer 22. After the third epitaxial layer 23 is formed, a P-type ion implantation process is performed to form a third P-type diffusion region 33.

[0068] It is understandable that, according to device design requirements or specific application environment requirements, the third epitaxial layer 23 can be configured as a single layer or multiple layers.

[0069] S105 , forming a fourth epitaxial layer 24 on the third epitaxial layer 23 , and connecting the first P-type diffusion region 31 , the second P-type diffusion region 32 and the third P-type diffusion region 33 into one by high-temperature diffusion to form a functional diffusion region 3 .

[0070] In a possible implementation of this application, reference Figure 3 and Figure 4, a fourth epitaxial layer 24 is formed on the third epitaxial layer 23 through an epitaxial growth process. The fourth epitaxial layer 24 has the same N-type doping as the third epitaxial layer 23, that is, the first epitaxial layer 21, the second epitaxial layer 22, the third epitaxial layer 23 and the fourth epitaxial layer 24 have the same doping type and are all stacked in sequence on the N+ substrate 1 through an epitaxial growth process, thereby ensuring crystal continuity and material interface quality.

[0071] Furthermore, after the fourth epitaxial layer 24 is formed, a high-temperature diffusion process is used to diffuse and connect the first P-type diffusion region 31, the second P-type diffusion region 32 and the third P-type diffusion region 33 previously formed in the first epitaxial layer 21, the second epitaxial layer 22 and the third epitaxial layer 23, respectively, to form an integrated functional diffusion region 3. The functional diffusion region 3 is then formed in part of the first epitaxial layer 21, the second epitaxial layer 22, the third epitaxial layer 23 and the fourth epitaxial layer 24, that is, the functional diffusion region 3 penetrates the second epitaxial layer 22 and the third epitaxial layer 23 in the vertical direction from the fourth epitaxial layer 24 to the N+ substrate 1 in the power device structure, and extends to the upper part of the first epitaxial layer 21 and the lower part of the fourth epitaxial layer 24.

[0072] In an example, the functional diffusion regions 3 may be distributed in a spherical shape in the first epitaxial layer 21 , the second epitaxial layer 22 , the third epitaxial layer 23 and the fourth epitaxial layer 24 .

[0073] Therefore, through the functional diffusion region 3 in the first epitaxial layer 21, the second epitaxial layer 22, the third epitaxial layer 23 and the fourth epitaxial layer 24, the electric field distribution of each epitaxial layer can be effectively adjusted to give the power device a higher voltage resistance and optimized breakdown characteristics, that is, the functional diffusion region 3 enables each epitaxial layer to have a higher concentration of ion doping, which is equivalent to improving the voltage resistance, reducing the on-resistance per unit area of ​​the power device, and thereby reducing its conduction loss.

[0074] In one example, the high temperature diffusion process includes a thermal annealing furnace or a rapid thermal treatment process, which is performed in an inert atmosphere (such as nitrogen or argon) or an oxidizing atmosphere, the high temperature conditions include 1000°C to 1150°C, and the high temperature diffusion time includes 30 minutes to 90 minutes to form a continuous functional diffusion region 3 in each epitaxial layer.

[0075] In one example, when forming the first P-type diffusion region 31 , the second P-type diffusion region 32 , and the third P-type diffusion region 33 , the ion implantation concentrations in the first epitaxial layer 21 , the second epitaxial layer 22 , and the third epitaxial layer 23 are the same.

[0076] That is, in order to form a continuous functional diffusion region 3 with consistent electrical properties, the same ion implantation process parameters are used in the process of forming the first P-type diffusion region 31, the second P-type diffusion region 32 and the third P-type diffusion region 33 respectively to ensure that each diffusion region in each epitaxial layer has the same doping concentration and electrical properties.

[0077] Specifically, when ion implantation is performed on the first epitaxial layer 21, the second epitaxial layer 22 and the third epitaxial layer 23 respectively, the same P-type doping ions are selected, for example, boron ions B + , and set consistent implantation energy and implantation dose. For example, the implantation energy can be set to 60 keV, the implantation dose can be set to 3×10¹³ ions / cm², and the implantation method can adopt a vertical implantation process to ensure that the doping distribution has good consistency between layers.

[0078] Therefore, in the high-temperature diffusion step, the diffusion areas with consistent concentration are more easily integrated in the vertical direction, avoiding the formation of high-resistance junctions or potential steps, thereby improving the structural integrity and conductive continuity of the functional diffusion area 3. The consistent charge concentration of the three-layer diffusion area can enable the overall functional diffusion area 3 to establish a stable and uniform electric field regulation area in the longitudinal direction of the epitaxial layer, which helps to improve the breakdown voltage of the power device and alleviate the electric field concentration below the trench.

[0079] Among them, the formation area of ​​the first P-type diffusion region 31 on the first epitaxial layer 21 is S1, the formation area of ​​the second P-type diffusion region 32 on the second epitaxial layer 22 is S2, and the formation area of ​​the third P-type diffusion region 33 on the third epitaxial layer 23 is S3, then the vertical projections of S1, S2, and S3 in the direction from the fourth epitaxial layer 24 to the N+ substrate 1 are concentrically arranged and overlap with each other.

[0080] As a result, the first P-type diffusion region 31, the second P-type diffusion region 32 and the third P-type diffusion region 33 form a structure that is stacked up and down and corresponds to each other in the vertical direction, and are arranged in the vertical direction within the depth range from the fourth epitaxial layer 24 to the N+ substrate 1, which helps to achieve effective vertical fusion of the three-layer diffusion region in the high-temperature diffusion process, avoid the formation of lateral deviations or diffusion dead corners, and ensure the integrity and symmetry of the functional diffusion region 3. The symmetrical distribution along the depth direction of the power device can establish a uniform electric field gradient below the gate trench 11, reduce the electric field concentration effect, and improve the breakdown voltage resistance performance of the power device.

[0081] In a possible implementation of the present application, when forming the first P-type diffusion region 31 , the second P-type diffusion region 32 and the third P-type diffusion region 33 respectively, the ion implantation doses for the first epitaxial layer 21 , the second epitaxial layer 22 and the third epitaxial layer 23 are distributed in a stepped manner.

[0082] Specifically, when the first P-type diffusion region 31 is formed in the first epitaxial layer 21, the applied ion implantation dose is set to D1; when the second P-type diffusion region 32 is formed in the second epitaxial layer 22, the ion implantation dose is set to D2; when the third P-type diffusion region 33 is formed in the third epitaxial layer 23, the ion implantation dose is set to D3. Then, D1>D2>D3, forming a doping concentration gradient that decreases layer by layer from bottom to top, so as to constitute a vertical P-type doping step distribution structure.

[0083] Optionally, D1 can be set to 5×10¹³ ions / cm², D2 to 3×10¹³ ions / cm², and D3 to 1×10¹³ ions / cm² to ensure that the first P-type diffusion region 31 , the second P-type diffusion region 32 , and the third P-type diffusion region 33 have similar diffusion depths but distinct concentration levels.

[0084] As a result, the relatively highly doped first P-type diffusion region 31 is located near the high voltage end of the N+ substrate 1, so as to effectively suppress the electric field peak at its bottom, while the relatively low-doped second P-type diffusion region 32 and the third P-type diffusion region 33 above constitute a transition region, thereby gradient-adjusting the electric field strength and improving the overall voltage resistance of the power device. The P-type doping step distribution structure can avoid the formation of obvious potential mutations at the diffusion region interface, thereby improving the consistency and stability of the breakdown voltage of the power device. Moreover, due to the gradual decrease in concentration, the doping distribution is smoother during the high-temperature diffusion process, and the functional diffusion region 3 can form an extended structure with good continuity and controllable doping gradient in the vertical direction.

[0085] In one example, in the direction from the fourth epitaxial layer 24 to the N+ substrate 1, the curve profile of the side connection line on the same side of the first P-type diffusion region 31, the second P-type diffusion region 32 and the third P-type diffusion region 33 is normally distributed, so as to facilitate the fusion of the first epitaxial layer 21, the second epitaxial layer 22 and the third epitaxial layer 23 in the high-temperature diffusion process, thereby forming a continuous functional diffusion region 3.

[0086] S106 , forming a plurality of gate trenches 11 on the fourth epitaxial layer 24 , and forming a double-layer shielding gate structure 4 on the gate trenches 11 .

[0087] In a possible implementation of this application, continue to combine Figure 10 , forming a double-layer shielding gate structure 4 on the gate trench 11, including:

[0088] S1061 , forming a first trench oxide layer 41 on the bottom and sidewalls of the gate trench 11 .

[0089] In one example, reference Figures 4 to 6 The first trench oxide layer 41 can be formed on the bottom and sidewalls of the gate trench 11 by a thermal oxidation process.

[0090] S1062, deposit a first polysilicon layer 42 in the gate trench 11, the first polysilicon layer 42 covers the first trench oxide layer 41, and after etching the first polysilicon layer 42 back from the top to the bottom of the gate trench 11 to a first etching depth, continue etching the first trench oxide layer 41 back to the first etching depth, wherein the first trench oxide layer 41 after etching back is formed into a second trench oxide layer 43.

[0091] In one example, the first etching depth is marked as H1. After the first polysilicon layer 42 is etched back to the depth of H1, the first trench oxide layer 41 is further etched back to the depth of H1, so that after the polysilicon layer is deposited in the trench, it has a suitable depth to form an effective shielding structure in the gate trench 11, optimize the electric field distribution at the bottom and sidewall of the gate trench 11, help reduce the on-resistance and improve the overall performance of the device, that is, the first trench oxide layer 41 and the first polysilicon layer 42 after etching back construct the first layer of shielding gate structure in the gate trench 11.

[0092] S1063 , depositing a second polysilicon layer 44 in the gate trench 11 , the second polysilicon layer 44 covers the first polysilicon layer 42 and the second trench oxide layer 43 , and etching back the second polysilicon layer 44 and the second trench oxide layer 43 to a second etching back depth.

[0093] In one example, reference Figures 6 to 8 , marking the second back-etching depth as H2, then the second polysilicon layer 44 and the second trench oxide layer 43 are etched back to the depth of H2, so that the second polysilicon layer 44 has a suitable depth on the first shielding gate structure to form a second shielding gate structure in the gate trench 11, thereby constructing a double-layer shielding gate structure 4 of the semiconductor power device, so as to reduce the on-resistance of the semiconductor power device and improve the overall performance of the device.

[0094] The second back engraving depth H2 is less than the first back engraving depth H1.

[0095] In the power device of the embodiment of the present application, a double-layer shielding gate structure 4 is formed in the gate trench 11, that is, two layers of independent polysilicon shielding gates are arranged at the bottom of the gate trench 11. This stacked structure design can more effectively "divide the voltage" and form two gradient electric field shielding areas below the bottom of the gate trench 11. That is, through the electric field regulation effect of the double-layer shielding gate structure 4, the electric field spikes under high voltage operation of the power device can be effectively suppressed, and the maximum electric field strength of the PN junction of the power device can be reduced, thereby improving the high voltage withstand characteristics of the power device. The double-layer shielding gate structure 4 can also effectively reduce the direct electric field coupling path between the gate structure 5 and the drain region 10 of the subsequent embodiment, thereby reducing the parasitic gate-drain capacitance and improving the switching performance and dv / dt anti-interference capability of the power device.

[0096] It should be noted that the double-layer shielding gate structure 4 not only optimizes the electric field below the gate trench 11, but also further covers the potential difference between the upper part of the gate trench 11 and the area outside the gate trench 11, so as to weaken the induction intensity of the body region of the power device to the drain electric field. Based on this effect, the fourth epitaxial layer 24 can use an N-type epitaxial material with a higher doping concentration, which is beneficial to reduce the on-resistance of the epitaxial layer, thereby further reducing the total conduction loss of the power device.

[0097] Therefore, based on the dual synergy of the functional diffusion region 3 and the double-layer shielding gate structure 4, they act on the vertical drift region and the trench control region of the power device respectively, ensuring the voltage resistance of the power device and optimizing the electric field distribution of each epitaxial layer, so that the multi-layer N-type epitaxial structure can comprehensively improve the doping concentration, so as to reduce the on-resistance per unit area of ​​the power device and reduce its conduction loss while maintaining the voltage resistance of the power device.

[0098] S1064 , forming a gate structure 5 in the gate trench 11 .

[0099] In a possible implementation of this application, combined with Figure 7 and Figure 8 , forming a gate structure 5 in the gate trench 11, including:

[0100] I. Form a gate oxide layer 51 in the gate trench 11 . The gate oxide layer 51 covers the second polysilicon layer 44 and the sidewalls of the gate trench 11 .

[0101] In one example, the etched-back second trench oxide layer 43 continues to remain on the sidewall of the gate trench 11 and can be regarded as a gate oxide layer 51 . A thermal oxidation process can also be used to form a gate oxide layer 51 covering the second polysilicon layer 44 in the gate trench 11 .

[0102] II. Depositing a gate polysilicon layer 52 in the gate trench 11.

[0103] In one example, the gate polysilicon layer 52 covers the gate oxide layer 51 , that is, the gate oxide layer 51 separates the gate polysilicon layer 52 from the second polysilicon layer 44 in the gate trench 11 .

[0104] III. After etching back the gate polysilicon layer 52 to below the top surface of the fourth epitaxial layer 24 , a gate oxide layer 51 flush with the top surface of the fourth epitaxial layer 24 is formed on the gate polysilicon layer 52 , thereby forming a gate structure 5 in the gate trench 11 .

[0105] S107 , performing self-aligned ion implantation between adjacent gate trenches 11 on the fourth epitaxial layer 24 to form a P-type body region 6 and an N+ source region 7 located above the P-type body region 6 .

[0106] In one example, reference Figure 9, self-aligned P- ion implantation is performed between adjacent gate trenches 11 on the fourth epitaxial layer 24 to form a P-type body region 6, and N+ ion implantation is performed to form an N+ source region 7, and annealing is performed to push the well, wherein the push-well junction depth of the P-type body region 6 is greater than the push-well junction depth of the N+ source region 7.

[0107] S108 , forming a contact hole region 8 connected to the P-type body region 6 and a source metal layer 9 covering the contact hole region 8 on the fourth epitaxial layer 24 , and forming a drain region 10 on the back of the N+ substrate 1 with gold.

[0108] In one possible implementation of the present application, a contact hole region 8 connected to the P-type body region 6 is formed on the fourth epitaxial layer 24, including: forming a field oxide layer 12 on the fourth epitaxial layer 24; etching a contact hole 81 on the field oxide layer 12 through a contact hole 81 mask, and the contact hole 81 extends from the top surface of the fourth epitaxial layer 24 into the P-type body region 6; and performing P++ ion implantation into the contact hole 81 to form a contact hole region 8.

[0109] The source metal layer 9 may include an alloy layer and a surface metal layer, and the alloy layer is deposited in the contact hole 81 .

[0110] In addition, P++ ions of the same type as those injected into the P-type body region 6 are injected into the contact hole 81 and annealed to push the well to form the contact hole region 8. Then, based on the fact that the contact hole 81 extends from the top surface of the fourth epitaxial layer 24 into the P-type body region 6, the P++ ions diffuse out of the contact hole region 8 in the P-type body region 6, and by utilizing the design that the P++ ion concentration is greater than the ion concentration of the P-type body region 6, the contact hole region 8 forms a graded junction in the P-type body region 6, thereby reducing the Schottky barrier.

[0111] The present application also discloses a semiconductor power device, which is prepared by the semiconductor power device preparation method of any of the above embodiments. Figure 9 The semiconductor power device includes: an N+ substrate 1, a functional diffusion region 3, a double-layer shielded gate structure 4, a P-type body region 6, an N+ source region 7, a contact hole region 8, a source metal layer 9 and a drain region 10.

[0112] In a possible implementation of the present application, a first epitaxial layer 21, a second epitaxial layer 22, a third epitaxial layer 23 and a fourth epitaxial layer 24 are stacked in sequence on the N+ substrate 1; the functional diffusion region 3 is connected to part of the first epitaxial layer 21, the second epitaxial layer 22, the third epitaxial layer 23 and the fourth epitaxial layer 24, and a plurality of gate trenches 11 are provided on the fourth epitaxial layer 24, and a double-layer shielded gate structure 4 is configured in the gate trenches 11; the P-type body region 6 is connected between adjacent gate trenches 11 in the fourth epitaxial layer 24; the N+ source region 7 is connected above the P-type body region 6 in the fourth epitaxial layer 24; the contact hole region 8 is provided between adjacent gate trenches 11 on the fourth epitaxial layer 24 and is connected to the P-type body region 6; the source metal layer 9 is provided on the top surface of the fourth epitaxial layer 24 and covers the contact hole region 8; the drain region 10 is provided on the bottom surface of the N+ substrate 1.

[0113] For other working principles and processes of the semiconductor power device of this embodiment, please refer to the description of the semiconductor power device preparation method of the aforementioned embodiment, which will not be repeated here.

[0114] The semiconductor power device and its preparation method provided by this application are described in detail above. Specific examples are used herein to illustrate the principles and implementation methods of this application. It should be noted that in this application, the descriptions of each embodiment have their own emphasis. For parts that are not described or recorded in detail in a particular embodiment, please refer to the relevant descriptions of other embodiments.

[0115] The above are only preferred embodiments of the present application and do not limit the patent scope of the present application. The various technical features of the technical solution of the present application can be arbitrarily combined. In order to make the description concise, all possible combinations of the various technical features in the above embodiments are not described. Any equivalent structure or equivalent process transformation made using the contents of the description and drawings of this application, or directly or indirectly applied in other related technical fields, as long as there is no contradiction in the combination of these technical features, are also included in the patent protection scope of the present application.

Claims

1. A method for preparing a semiconductor power device, characterized in that: include: Providing an N+ substrate; forming a first epitaxial layer of the same doping type as the N+ substrate, performing ion implantation on the first epitaxial layer, and then forming a first P-type diffusion region on the first epitaxial layer; forming at least one second epitaxial layer on the first epitaxial layer, performing ion implantation on the second epitaxial layer, and forming a second P-type diffusion region on the second epitaxial layer; forming at least one third epitaxial layer on the second epitaxial layer, and forming a third P-type diffusion region on the third epitaxial layer after ion implantation; forming a fourth epitaxial layer on the third epitaxial layer, and connecting the first P-type diffusion region, the second P-type diffusion region, and the third P-type diffusion region into one by high-temperature diffusion to form a functional diffusion region, wherein the functional diffusion region is formed in portions of the first epitaxial layer, the second epitaxial layer, the third epitaxial layer, and the fourth epitaxial layer, and in a direction from the fourth epitaxial layer to the N+ substrate, a curve profile connecting the sides of the first P-type diffusion region, the second P-type diffusion region, and the third P-type diffusion region on the same side is normally distributed, and the high-temperature diffusion is extended at a temperature of 1000° C. to 1150° C. for 30 to 90 minutes; forming a plurality of gate trenches on the fourth epitaxial layer, and forming a double-layer shielding gate structure on the gate trenches; Performing self-aligned ion implantation between adjacent gate trenches on the fourth epitaxial layer to form a P-type body region and an N+ source region located above the P-type body region; A contact hole region connected to the P-type body region and a source metal layer covering the contact hole region are formed on the fourth epitaxial layer, and a drain region is formed on the N+ substrate back gold.

2. The method for preparing a semiconductor power device according to claim 1, wherein: The double-layer shielding gate structure is formed on the gate trench, comprising: forming a first trench oxide layer on the bottom and sidewalls of the gate trench; Depositing a first polysilicon layer in the gate trench, wherein the first polysilicon layer covers the first trench oxide layer, etching back the first polysilicon layer from the top to the bottom of the gate trench to a first etching back depth, and then continuing to etch back the first trench oxide layer to the first etching back depth, wherein the first trench oxide layer after etching back forms a second trench oxide layer; Depositing a second polysilicon layer in the gate trench, wherein the second polysilicon layer covers the first polysilicon layer and the second trench oxide layer, and etching back the second polysilicon layer and the second trench oxide layer to a second etching back depth; A gate structure is formed in the gate trench.

3. The method for preparing a semiconductor power device according to claim 2, wherein: The forming of a gate structure in the gate trench comprises: forming a gate oxide layer in the gate trench, wherein the gate oxide layer covers the second polysilicon layer and the sidewall of the gate trench; depositing a gate polysilicon layer in the gate trench; After etching back the gate polysilicon layer to below the top surface of the fourth epitaxial layer, the gate oxide layer flush with the top surface of the fourth epitaxial layer is formed on the gate polysilicon layer.

4. The method for preparing a semiconductor power device according to claim 1, wherein: The step of forming a contact hole region connected to the P-type body region on the fourth epitaxial layer comprises: forming a field oxide layer on the fourth epitaxial layer; Etching a contact hole on the field oxide layer through a contact hole mask, wherein the contact hole extends from the top surface of the fourth epitaxial layer into the P-type body region; P++ ions are implanted into the contact hole to form the contact hole region.

5. A semiconductor power device, prepared by the semiconductor power device preparation method according to any one of claims 1 to 4, characterized in that: include: N+ substrate, functional diffusion region, double-layer shielded gate structure, P-type body region, N+ source region, contact hole region, source metal layer and drain region; A first epitaxial layer, a second epitaxial layer, a third epitaxial layer, and a fourth epitaxial layer are sequentially stacked on the N+ substrate; the functional diffusion region is connected to a portion of the first epitaxial layer, the second epitaxial layer, the third epitaxial layer, and the fourth epitaxial layer; and a plurality of gate trenches are provided on the fourth epitaxial layer, and the double-layer shielded gate structure is configured in the gate trenches; The P-type body region is connected between adjacent gate trenches in the fourth epitaxial layer; The N+ source region is connected to the P-type body region in the fourth epitaxial layer; The contact hole region is provided on the fourth epitaxial layer between adjacent gate trenches and connected to the P-type body region; The source metal layer is provided on the top surface of the fourth epitaxial layer and covers the contact hole region; The drain region is arranged on the bottom surface of the N+ substrate.

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