Gallium nitride power device and preparation method thereof

Abstract

The invention relates to the technical field of semiconductors, and discloses a gallium nitride power device and a preparation method thereof, and the method comprises the steps: growing and forming a gallium nitride epitaxial structure layer on a P + substrate; growing and forming a P-type gallium nitride layer on the gallium nitride epitaxial structure layer; forming a P-type gallium nitride gate region on the P-type gallium nitride layer; passivating the P-type gallium nitride gate region in a set gas environment to form a functional high-resistance region which is distributed on the side wall of the P-type gallium nitride gate region and on the top surface of the P-type gallium nitride gate region partially connected with the side wall; depositing and forming a first ohmic contact metal layer and a second ohmic contact metal layer on the gallium nitride epitaxial structure layer; and a passivation dielectric layer is deposited on the gallium nitride epitaxial structure layer, and after the passivation dielectric layer on the P-type gallium nitride gate region is etched, a gate metal layer is deposited on the P-type gallium nitride gate region. The power consumption of the device is optimized, and the reliability of the device is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and particularly to a gallium nitride power device and a manufacturing method thereof. Background Art

[0002] In semiconductor manufacturing processes, gallium nitride (GaN) high electron mobility transistors (HEMTs) have received extensive attention and practical applications in power electronics and high-frequency switching applications in recent years due to the advantages of the material itself, such as high breakdown voltage, low on-resistance, high operating frequency, and small device size. In particular, enhancement-mode GaN HEMT devices have become the mainstream choice due to their good thermal stability and long-term reliability. However, the gate leakage problem in enhancement-mode GaN HEMT devices in related technologies is relatively prominent, and the gate leakage current is usually in the range of hundreds of microamperes to milliamperes, seriously affecting the driving power consumption and long-term reliability of the devices. Summary of the Invention

[0003] In view of this, this application provides a gallium nitride power device and a manufacturing method thereof to solve the above-mentioned technical problems.

[0004] In a first aspect, an embodiment of this application discloses a manufacturing method of a gallium nitride power device, including: Providing a highly doped P+ substrate, and growing a gallium nitride epitaxial structure layer on the P+ substrate; Growing a P-type gallium nitride layer on the gallium nitride epitaxial structure layer; After setting a gate region on the P-type gallium nitride layer, etching the non-gate region of the P-type gallium nitride layer to form a P-type gallium nitride gate region; Performing passivation treatment on the P-type gallium nitride gate region in a set gas environment to form a functional high-resistance region, where the functional high-resistance region is distributed on the sidewalls of the P-type gallium nitride gate region and on part of the top surface of the P-type gallium nitride gate region connected to the sidewalls; Depositing a first ohmic contact metal layer and a second ohmic contact metal layer spaced apart from the P-type gallium nitride gate region on the gallium nitride epitaxial structure layer; Depositing a passivation dielectric layer on the gallium nitride epitaxial structure layer, etching the passivation dielectric layer on the P-type gallium nitride gate region, and then depositing a gate metal layer on the P-type gallium nitride gate region.

[0005] In a possible example, growing the gallium nitride epitaxial structure layer on the P+ substrate includes: An aluminum nitride nucleation layer, an aluminum gallium nitride buffer layer, a gallium nitride channel layer, and an aluminum gallium nitride barrier layer are sequentially grown on the P+ substrate; wherein, the P-type gallium nitride gate region, the first ohmic contact metal layer, the second ohmic contact metal layer, and the passivation dielectric layer are located on the aluminum gallium nitride barrier layer.

[0006] In a possible example, the first ohmic contact metal layer includes a source metal layer, and the second ohmic contact metal layer includes a drain metal layer.

[0007] In a possible example, the passivation dielectric layer covers between the first ohmic contact metal layer and the P-type gallium nitride gate region, and between the second ohmic contact metal layer and the P-type gallium nitride gate region on the aluminum gallium nitride barrier layer.

[0008] In a possible example, the passivation treatment of the P-type gallium nitride gate region in a set gas environment to form a functional high-resistance region includes: Forming a functional mask in the central region of the top surface of the P-type gallium nitride gate region; Performing passivation treatment on the P-type gallium nitride gate region with hydrogen; Forming the functional high-resistance region in the region of the P-type gallium nitride gate region not covered by the functional mask.

[0009] In a possible example, the passivation treatment of the P-type gallium nitride gate region in a set gas environment to form a functional high-resistance region includes: Performing passivation treatment on the P-type gallium nitride gate region with hydrogen to form an initial high-resistance region on the outer surface of the P-type gallium nitride gate region; Etching the initial high-resistance region at the central region of the top surface of the P-type gallium nitride gate region to form the functional high-resistance region.

[0010] In a possible example, the functional high-resistance region includes a first high-resistance region and a second high-resistance region. The second high-resistance region is symmetrically distributed on the sidewalls of the P-type gallium nitride gate region, and the first high-resistance region is symmetrically distributed on the top surface of a part of the P-type gallium nitride gate region connected to the sidewalls.

[0011] In a possible example, it is set that the thickness of the P-type gallium nitride gate region is H1, the width of the P-type gallium nitride gate region is W1, the thickness of the first high-resistance region is H2, and the width of the first high-resistance region is W2, then: H2 < 1 / 10H1, W2 < 1 / 5W1.

[0012] In a possible example, after depositing and forming the passivation dielectric layer on the gallium nitride epitaxial structure layer, ion implantation is performed on the non-active region on the gallium nitride epitaxial structure layer to form an isolation region.

[0013] In a second aspect, embodiments of the present application disclose a gallium nitride power device, including: a P+ substrate, a gallium nitride epitaxial structure layer, a P-type gallium nitride gate region, a first ohmic contact metal layer, a second ohmic contact metal layer, a passivation dielectric layer, and a gate metal layer; The gallium nitride epitaxial structure layer is connected to the P+ substrate, and the P-type gallium nitride gate region, the first ohmic contact metal layer, and the second ohmic contact metal layer are connected to the gallium nitride epitaxial structure layer and are arranged at intervals; The passivation dielectric layer covers between the first ohmic contact metal layer and the P-type gallium nitride gate region, and between the second ohmic contact metal layer and the P-type gallium nitride gate region on the gallium nitride epitaxial structure layer; Wherein, on the sidewalls of the P-type gallium nitride gate region, and on part of the top surface connected to the sidewalls, there are functional high-resistance regions, and the gate metal layer is connected to the P-type gallium nitride gate region and covers part of the functional high-resistance regions.

[0014] In summary, compared with the prior art, the present application discloses a gallium nitride power device and its manufacturing method, including growing a gallium nitride epitaxial structure layer on a P+ substrate, growing a P-type gallium nitride layer on the gallium nitride epitaxial structure layer, forming a P-type gallium nitride gate region on the P-type gallium nitride layer, performing passivation treatment on the P-type gallium nitride gate region in a set gas environment to form functional high-resistance regions, the functional high-resistance regions are distributed on the sidewalls of the P-type gallium nitride gate region, and on part of the top surface of the P-type gallium nitride gate region connected to the sidewalls, and depositing and forming a first ohmic contact metal layer, a second ohmic contact metal layer, and a passivation dielectric layer on the gallium nitride epitaxial structure layer, after etching the passivation dielectric layer on the P-type gallium nitride gate region, depositing and forming a gate metal layer on the P-type gallium nitride gate region. Thus, based on the functional high-resistance regions, the P-type gallium nitride gate region can effectively block its leakage paths along the sidewalls and the gallium nitride epitaxial structure layer to the source / drain electrodes, effectively suppress gate leakage, reduce the leakage loss during device driving, avoid device performance degradation caused by long-term high gate leakage, and improve the long-term reliability of the device under high-voltage and high-frequency applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present application. For those skilled in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0016] Figure 1 is a flowchart of the manufacturing method of the gallium nitride power device in the embodiments of the present application; Figure 2 is a schematic structural diagram of the first gallium nitride power device according to an embodiment of the present application; Figure 3 is a schematic structural diagram of the second gallium nitride power device according to an embodiment of the present application; Figure 4 is a schematic structural diagram of the third gallium nitride power device according to an embodiment of the present application; Figure 5 is Figure 4 an enlarged view of portion A of Figure 6 is a schematic structural diagram of the fourth gallium nitride power device according to an embodiment of the present application; Figure 7 is a schematic structural diagram of the fifth gallium nitride power device according to an embodiment of the present application; Figure 8 is a schematic structural diagram of the sixth gallium nitride power device according to an embodiment of the present application; Figure 9 is a schematic structural diagram of the seventh gallium nitride power device according to an embodiment of the present application; Figure 10 is a schematic structural diagram of the eighth gallium nitride power device according to an embodiment of the present application; Figure 11 is a schematic structural diagram of the ninth gallium nitride power device according to an embodiment of the present application. Detailed implementation manners

[0017] Here, exemplary embodiments will be described in detail, and examples thereof are shown in the drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation manners described in the following exemplary embodiments do not represent all implementation manners consistent with the present application. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0018] It should be noted that in this document, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusively, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including one..." does not exclude the presence of another identical element in the process, method, article or device including the element. In addition, components, features, elements with the same name in different embodiments of the present application may have the same meaning or different meanings, and their specific meanings need to be determined according to their explanations in the specific embodiments or further in combination with the context in the specific embodiments.

[0019] It should be understood that the specific embodiments described herein are merely for explaining the present application and are not intended to limit the present application.

[0020] In the following description, suffixes such as "module", "component" or "unit" used to represent elements are only for the convenience of explaining the present application, and they have no specific meaning in themselves. Therefore, "module", "component" or "unit" can be used interchangeably.

[0021] In the description of the present application, it should be noted that the orientation or positional relationship indicated by the terms "upper", "lower", "left", "right", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present application. In addition, the terms "first", "second", "third" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance.

[0022] The technical solution shown in the present application will be described in detail below through specific embodiments. It should be noted that the description order of the following embodiments does not limit the priority order of the embodiments.

[0023] Please refer to Figure 1 and in combination with Figures 2 to 11 A method for fabricating a gallium nitride power device according to an embodiment of the present application includes: S101, providing a highly doped P+ substrate 1, and growing a gallium nitride epitaxial structure layer 2 on the P+ substrate 1.

[0024] In a possible implementation manner of the present application, referring to Figure 2 the material for forming the P+ substrate 1 may be single crystal silicon, polycrystalline silicon, amorphous silicon, doped silicon or the like. The material of the P+ substrate 1 may also be a SiGe substrate, a group III-V element compound substrate, a silicon carbide substrate or a stacked structure thereof, or a silicon-on-insulator structure, or a diamond substrate or other semiconductor material substrates well known to those skilled in the art. For example, boron ions can be implanted into single crystal silicon to form a P-type conductive semiconductor substrate to improve the material selectivity and adaptability to the actual production environment.

[0025] In a possible implementation manner of the present application, growing a gallium nitride epitaxial structure layer 2 on the P+ substrate 1 includes: Growing an aluminum nitride nucleation layer 21, a gallium aluminum nitride buffer layer 22, a gallium nitride channel layer 23 and a gallium aluminum nitride barrier layer 24 on the P+ substrate 1 in sequence.

[0026] It should be noted that the aluminum nitride nucleation layer 21 is located on the upper surface of the highly doped P+ substrate 1, which can provide a starting surface suitable for the epitaxial growth of gallium nitride; the aluminum gallium nitride buffer layer 22 is located above the aluminum nitride nucleation layer 21, which can be used to relieve the interlayer lattice mismatch and stress difference, and improve the crystal quality of gallium nitride; the gallium nitride channel layer 23, as a key part of the gallium nitride power device, can be used for electron transport and power amplification, and by setting the thickness and doping concentration, the required electron flow characteristics can be achieved; the aluminum gallium nitride barrier layer 24 is located above the gallium nitride channel layer 23, which is used to form a barrier structure for electron transport, and this barrier structure controls current injection and conduction when the device is operating.

[0027] S102, grow and form a P-type gallium nitride layer 30 on the gallium nitride epitaxial structure layer 2.

[0028] In one example, the P-type gallium nitride layer 30 can achieve P-type conductive characteristics through Mg (magnesium) doping, and is used to form the P-type gallium nitride gate region of the enhancement-mode gallium nitride power device in subsequent processes.

[0029] In one example, the P-type gallium nitride layer 30 is formed on the aluminum gallium nitride barrier layer 24.

[0030] S103, after setting the gate region on the P-type gallium nitride layer 30, etch the non-gate region of the P-type gallium nitride layer 30 to form the P-type gallium nitride gate region 3.

[0031] In a possible implementation manner of this application, photolithography or a mask can be used to define the gate region, that is Figure 3 the 3a region shown, and then etch the non-gate region of the P-type gallium nitride layer 30. Among them, plasma dry etching or ICP etching process can be used to ensure that the edge morphology of the P-type gallium nitride gate region 3 is flat.

[0032] In one example, the P-type gallium nitride gate region 3 is formed on the aluminum gallium nitride barrier layer 24.

[0033] S104, perform passivation treatment on the P-type gallium nitride gate region 3 under a set gas environment to form a functional high-resistance region 4. The functional high-resistance region 4 is distributed on the sidewalls of the P-type gallium nitride gate region 3 and on part of the top surface of the P-type gallium nitride gate region 3 connected to the sidewalls.

[0034] Thus, a functional high-resistance region 4 is formed on the P-type gallium nitride gate region 3, and the functional high-resistance region 4 is used to block the leakage paths of the P-type gallium nitride gate region 3 along the sidewalls and the gallium nitride epitaxial structure layer 2 to the source / drain electrodes, so as to effectively suppress the gate leakage of the gallium nitride power device, reduce the leakage power loss during device driving, avoid the device performance degradation caused by long-term high gate leakage, and improve the long-term reliability of the gallium nitride power device under high-voltage and high-frequency applications.

[0035] In a possible implementation manner of the present application, referring to Figure 4 , Figure 8 and Figure 9 , the P-type gallium nitride gate region 3 is passivated in a set gas environment to form a functional high-resistance region 4, including: The P-type gallium nitride gate region 3 is passivated with hydrogen to form an initial high-resistance region 4a on the outer surface of the P-type gallium nitride gate region 3; the initial high-resistance region 4a at the central region 4b on the top surface of the P-type gallium nitride gate region 3 is etched to form a functional high-resistance region 4.

[0036] Thus, in a hydrogen environment, hydrogen reacts with the magnesium doping in the outer surface region of the P-type gallium nitride gate region 3 to passivate the P-type characteristics of the outer surface of the P-type gallium nitride gate region 3, forming an initial high-resistance region 4a. Then, the initial high-resistance region 4a at the central region 4b on the top surface of the P-type gallium nitride gate region 3 is etched, and a functional high-resistance region 4 is formed on the sidewall of the P-type gallium nitride gate region 3 and part of the top surface connected to the sidewall, thereby realizing high resistance for the sidewall and the top surface edge of the P-type gallium nitride gate region 3 and cutting off its leakage path.

[0037] In a possible implementation manner of the present application, referring to Figure 10 and Figure 11 , the P-type gallium nitride gate region 3 is passivated in a set gas environment to form a functional high-resistance region 4, including: A functional mask 3b is formed in the central region on the top surface of the P-type gallium nitride gate region 3; the P-type gallium nitride gate region 3 is passivated with hydrogen; a functional high-resistance region 4 is formed in the region of the P-type gallium nitride gate region 3 not covered by the functional mask.

[0038] Thus, in a hydrogen environment, hydrogen can react with the magnesium doping in the region of the P-type gallium nitride gate region 3 not covered by the functional mask to passivate the P-type characteristics of the P-type gallium nitride gate region 3, making its local region turn into high resistance, that is, a functional high-resistance region 4 is formed on the sidewall of the P-type gallium nitride gate region 3 and part of the top surface connected to the sidewall, thereby realizing high resistance for the sidewall and the top surface edge of the P-type gallium nitride gate region 3 and cutting off its leakage path.

[0039] In a possible implementation manner of the present application, continuing to combine Figure 4 , Figure 5 and Figure 11 , the functional high-resistance region 4 includes a first high-resistance region 41 and a second high-resistance region 42. The second high-resistance region 42 is symmetrically distributed on the sidewall of the P-type gallium nitride gate region 3, and the first high-resistance region 41 is symmetrically distributed on part of the top surface of the P-type gallium nitride gate region 3 connected to the sidewall.

[0040] In one example, the first high-resistance region 41 is opposite to and protrudes from the top surface of the P-type gallium nitride gate region 3, or the first high-resistance region 41 is formed in the top surface of the P-type gallium nitride gate region 3.

[0041] Thus, based on the first high-resistance region 41 and the second high-resistance region 42, the high resistance of the sidewalls and the top surface edges of the P-type gallium nitride gate region 3 is further ensured, the leakage paths of the P-type gallium nitride gate region 3 along the sidewalls and the gallium nitride epitaxial structure layer 2 to the source / drain are blocked, so as to effectively suppress the gate leakage of the gallium nitride power device, reduce the leakage loss during device driving, avoid the device performance degradation caused by long-term high gate leakage, and improve the long-term reliability of the gallium nitride power device under high-voltage and high-frequency applications.

[0042] Furthermore, the P-type gallium nitride gate region 3 is passivated in a set gas environment, including: The P-type gallium nitride gate region 3 is passivated with hydrogen to form an initial high-resistance region 4a on the outer surface of the P-type gallium nitride gate region 3; the initial high-resistance region 4a at the central region 4b of the top surface of the P-type gallium nitride gate region 3 is etched to form the first high-resistance region 41 and the second high-resistance region 42, and the second high-resistance region 42 is symmetrically distributed on the sidewalls of the P-type gallium nitride gate region 3, and the first high-resistance region 41 is symmetrically distributed on the part of the top surface of the P-type gallium nitride gate region 3 connected to the sidewalls.

[0043] On the other hand, the P-type gallium nitride gate region 3 is passivated in a set gas environment, including: forming a functional mask 3b in the central region of the top surface of the P-type gallium nitride gate region 3; passivating the P-type gallium nitride gate region 3 with hydrogen; forming the first high-resistance region 41 and the second high-resistance region 42 in the region of the P-type gallium nitride gate region 3 not covered by the functional mask, and the second high-resistance region 42 is symmetrically distributed on the sidewalls of the P-type gallium nitride gate region 3, and the first high-resistance region 41 is symmetrically distributed on the part of the top surface of the P-type gallium nitride gate region 3 connected to the sidewalls.

[0044] In one example, referring to Figure 5 , it is set that the thickness of the P-type gallium nitride gate region 3 is H1, the width of the P-type gallium nitride gate region 3 is W1, the thickness of the first high-resistance region 41 is H2, and the width of the first high-resistance region 41 is W2, then: H2 < 1 / 10H1, W2 < 1 / 5W1.

[0045] And, it is set that the width of the second high-resistance region 42 is W3, then: W3 = H2.

[0046] That is, through the limitation of this parameter relationship, the relative thickness and relative width of the first high-resistance region 41 are ensured, and the passivation dimensions of the first high-resistance region 41 and the second high-resistance region 42 are ensured, so that it will not overly affect the subsequent conductivity of the P-type gallium nitride gate region 3, and the drawback of excessive diffusion is also prevented, thereby ensuring the regional integrity of the P-type gallium nitride gate region 3.

[0047] S105. Deposit and form a first ohmic contact metal layer 51 and a second ohmic contact metal layer 52 on the gallium nitride epitaxial structure layer 2, which are spaced apart from the P-type gallium nitride gate region 3.

[0048] In a possible implementation manner of this application, referring to Figure 6 , the first ohmic contact metal layer 51 includes a source metal layer, and the second ohmic contact metal layer 52 includes a drain metal layer.

[0049] Moreover, the distance from the second ohmic contact metal layer 52 to the P-type gallium nitride gate region 3 is greater than the distance from the first ohmic contact metal layer 51 to the P-type gallium nitride gate region 3.

[0050] Then, based on the unequal distance design between the P-type gallium nitride gate region 3 and the source metal layer and the drain metal layer, it is prevented that the distance between the P-type gallium nitride gate region 3 and the second ohmic contact metal layer 52 is too close, and a high electric field region is prevented from being formed between the gate and the drain, that is, the electric field strength between the two is reduced, thereby improving the breakdown voltage performance of the device. And it is designed with a larger distance from the drain metal layer, which can extend the electric field diffusion path between the high-voltage end and the P-type gallium nitride gate region 3, avoid excessive local electric field concentration, improve the overall breakdown voltage of the device, and also reduce the direct electric field coupling effect of the high drain voltage on the P-type gallium nitride gate region 3, reduce the subsequent gate leakage current and parasitic leakage current, and contribute to maintaining the low power consumption and high switching efficiency of the device. Relatively speaking, the source metal layer is closer to the P-type gallium nitride gate region 3, which is beneficial for the gallium nitride power device to quickly deplete the carriers in the channel in the off state, ensuring better gate control effect during turn-off and reducing the leakage current during turn-off.

[0051] Of course, in other application scenarios of the embodiments of this application, the distances between the P-type gallium nitride gate region 3 and the source metal layer and the drain metal layer can also be set to be equal.

[0052] S106. Deposit and form a passivation dielectric layer 6 on the gallium nitride epitaxial structure layer 2. After etching the passivation dielectric layer 6 on the P-type gallium nitride gate region 3, deposit and form a gate metal layer 7 on the P-type gallium nitride gate region 3.

[0053] Wherein, after etching the passivation dielectric layer 6 on the P-type gallium nitride gate region 3, the functional high-resistance region 4 on the P-type gallium nitride gate region 3 is exposed to form a gate window, so as to facilitate the Schottky contact between the P-type gallium nitride gate region 3 and the gate metal layer 7.

[0054] In a possible implementation manner of the present application, with reference to Figure 6 and Figure 7 , the passivation dielectric layer 6 covers between the first ohmic contact metal layer 51 and the P-type gallium nitride gate region 3, and between the second ohmic contact metal layer 52 and the P-type gallium nitride gate region 3 on the aluminum gallium nitride barrier layer 24.

[0055] Thus, the surface path between the gate region and the source / drain region of the gallium nitride power device is isolated by the passivation dielectric layer 6 to prevent surface conduction and the influence of external impurities.

[0056] It can be understood that the P-type gallium nitride gate region 3, the first ohmic contact metal layer 51, the second ohmic contact metal layer 52, and the passivation dielectric layer 6 are located on the aluminum gallium nitride barrier layer 24.

[0057] In one example, after depositing and forming the passivation dielectric layer 6 on the gallium nitride epitaxial structure layer 2, ion implantation is performed on the non-active region on the gallium nitride epitaxial structure layer 2 to form an isolation region.

[0058] Specifically, ion implantation is performed on the non-active regions outside the first ohmic contact metal layer 51, the second ohmic contact metal layer 52, and the P-type gallium nitride gate region 3, so as to form a high-resistance isolation region in the gallium nitride epitaxial structure layer 2, to enhance the electrical isolation between gallium nitride power devices and around the devices, suppress leakage current and parasitic effects, and improve device reliability.

[0059] It should be noted that the gallium nitride power device in the embodiment of the present application is an enhancement-mode GaN HEMT. The device is turned off at zero gate voltage (VGS = 0), and the gate structure of the device is formed by epitaxially growing a P-type gallium nitride gate region 3 on the aluminum gallium nitride barrier layer 24 and depositing a gate metal layer 7 on the P-type gallium nitride gate region 3, so as to utilize the built-in electric field of the p-n junction to deplete the two-dimensional electron gas (2DEG) in the channel and realize the normally-off characteristic. However, a high-density interface state will be formed at the heterojunction interface between the aluminum gallium nitride barrier layer 24 and the P-type gallium nitride gate region 3. These interface states can serve as carrier traps or recombination centers. When a negative bias voltage is applied to the gate, the ionization of the interface states will introduce an additional leakage current path. Then, after designing and forming the functional high-resistance region 4, the gate leakage can be effectively suppressed, thereby optimizing the device power consumption and improving the device reliability.

[0060] The embodiment of the present application also discloses a gallium nitride power device, with reference to Figure 7 , the gallium nitride power device is prepared by the preparation method of the gallium nitride power device in any of the above embodiments, and includes: P+ substrate 1, gallium nitride epitaxial structure layer 2, P-type gallium nitride gate region 3, first ohmic contact metal layer 51, second ohmic contact metal layer 52, passivation dielectric layer 6, and gate metal layer 7.

[0061] In a possible implementation manner of the present application, a gallium nitride epitaxial structure layer 2 is connected to a P+ substrate 1, a P-type gallium nitride gate region 3, a first ohmic contact metal layer 51, and a second ohmic contact metal layer 52 are connected to the gallium nitride epitaxial structure layer 2 and are arranged at intervals; a passivation dielectric layer 6 covers the gallium nitride epitaxial structure layer 2 and is located between the first ohmic contact metal layer 51 and the P-type gallium nitride gate region 3, and between the second ohmic contact metal layer 52 and the P-type gallium nitride gate region 3; wherein, on the side walls of the P-type gallium nitride gate region 3 and on part of the top surfaces connected to the side walls, a functional high-resistance region 4 is provided, and a gate metal layer 7 is connected to the P-type gallium nitride gate region 3 and covers part of the functional high-resistance region 4.

[0062] In one example, the functional high-resistance region 4 includes a first high-resistance region 41 and a second high-resistance region 42. The second high-resistance region 42 is symmetrically distributed on the side walls of the P-type gallium nitride gate region 3, and the first high-resistance region 41 is symmetrically distributed on part of the top surfaces of the P-type gallium nitride gate region 3 connected to the side walls.

[0063] Thus, a functional high-resistance region 4 is formed on the P-type gallium nitride gate region 3, and the functional high-resistance region 4 is used to block the leakage paths of the P-type gallium nitride gate region 3 along the side walls and the gallium nitride epitaxial structure layer 2 to the source / drain electrodes, so as to effectively suppress the gate leakage of the gallium nitride power device, reduce the leakage loss during device driving, avoid the device performance degradation caused by long-term high gate leakage, and improve the long-term reliability of the gallium nitride power device under high-voltage and high-frequency applications.

[0064] For other working principles and processes of the gallium nitride power device in this embodiment, refer to the description of the preparation method of the gallium nitride power device in the foregoing embodiment of this application, which will not be elaborated here.

[0065] The above has introduced in detail the gallium nitride power device and its preparation method provided by the present application. Specific examples are used in this article to elaborate on the principles and implementation manners of the present application. It should be noted that in the present application, the descriptions of each embodiment have their own emphases. For parts not detailed or recorded in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0066] The above is only the preferred embodiment of the present application, and does not limit the patent scope of the present application. The technical features of the technical solutions of the present application can be combined arbitrarily. For the sake of concise description, not all possible combinations of the technical features in the above embodiments are described. Any equivalent structural or equivalent process transformation made by using the content of the specification and drawings of the present application, or directly or indirectly applied in other related technical fields, as long as the combination of these technical features does not conflict, is similarly included in the patent protection scope of the present application.

Claims

1. A method for preparing a gallium nitride power device, characterized in that, Including: Providing a highly doped P+ substrate, and growing a gallium nitride epitaxial structure layer on the P+ substrate; Growing a P-type gallium nitride layer on the gallium nitride epitaxial structure layer; After setting a gate region on the P-type gallium nitride layer, etching the non-gate region of the P-type gallium nitride layer to form a P-type gallium nitride gate region; Performing passivation treatment on the P-type gallium nitride gate region in a set gas environment to form a functional high-resistance region, where the functional high-resistance region is distributed on the sidewalls of the P-type gallium nitride gate region and on part of the top surface of the P-type gallium nitride gate region connected to the sidewalls; Depositing a first ohmic contact metal layer and a second ohmic contact metal layer spaced apart from the P-type gallium nitride gate region on the gallium nitride epitaxial structure layer; Depositing a passivation dielectric layer on the gallium nitride epitaxial structure layer, etching the passivation dielectric layer on the P-type gallium nitride gate region, and then depositing a gate metal layer on the P-type gallium nitride gate region.

2. The method for manufacturing a gallium nitride power device according to claim 1, characterized in that The growing the gallium nitride epitaxial structure layer on the P+ substrate includes: Growing an aluminum nitride nucleation layer, a gallium aluminum nitride buffer layer, a gallium nitride channel layer, and a gallium aluminum nitride barrier layer in sequence on the P+ substrate; wherein, the P-type gallium nitride gate region, the first ohmic contact metal layer, the second ohmic contact metal layer, and the passivation dielectric layer are located on the gallium aluminum nitride barrier layer.

3. The method for manufacturing a gallium nitride power device according to claim 2, wherein The first ohmic contact metal layer includes a source metal layer, and the second ohmic contact metal layer includes a drain metal layer.

4. The method for manufacturing a gallium nitride power device according to claim 2, wherein, The passivation dielectric layer covers between the first ohmic contact metal layer and the P-type gallium nitride gate region, and between the second ohmic contact metal layer and the P-type gallium nitride gate region on the gallium aluminum nitride barrier layer.

5. The method for manufacturing a gallium nitride power device according to claim 1, wherein The performing passivation treatment on the P-type gallium nitride gate region in a set gas environment to form a functional high-resistance region includes: Forming a functional mask in the central region of the top surface of the P-type gallium nitride gate region; Performing passivation treatment on the P-type gallium nitride gate region with hydrogen; Forming the functional high-resistance region in the region of the P-type gallium nitride gate region not covered by the functional mask.

6. The method for manufacturing a gallium nitride power device according to claim 1, wherein, The performing passivation treatment on the P-type gallium nitride gate region in a set gas environment to form a functional high-resistance region includes: Performing passivation treatment on the P-type gallium nitride gate region with hydrogen to form an initial high-resistance region on the outer surface of the P-type gallium nitride gate region; Etching the initial high-resistance region at the central region of the top surface of the P-type gallium nitride gate region to form the functional high-resistance region.

7. The method for manufacturing a gallium nitride power device according to claim 5 or 6, characterized in that, The functional high-resistance region includes a first high-resistance region and a second high-resistance region, the second high-resistance region is symmetrically distributed on the sidewalls of the P-type gallium nitride gate region, and the first high-resistance region is symmetrically distributed on part of the top surface of the P-type gallium nitride gate region connected to the sidewalls.

8. The method for manufacturing a gallium nitride power device according to claim 7, wherein, Setting the thickness of the P-type gallium nitride gate region as H1, the width of the P-type gallium nitride gate region as W1, the thickness of the first high-resistance region as H2, and the width of the first high-resistance region as W2, then: H2 < 1 / 10H1, W2 < 1 / 5W1.

9. The method for manufacturing a gallium nitride power device according to claim 1, wherein After depositing and forming the passivation dielectric layer on the gallium nitride epitaxial structure layer, ion implantation is performed on the non-active region of the gallium nitride epitaxial structure layer to form an isolation region.

10. A gallium nitride power device, characterized in that, It includes: a P+ substrate, a gallium nitride epitaxial structure layer, a P-type gallium nitride gate region, a first ohmic contact metal layer, a second ohmic contact metal layer, a passivation dielectric layer, and a gate metal layer; The gallium nitride epitaxial structure layer is connected to the P+ substrate, and the P-type gallium nitride gate region, the first ohmic contact metal layer, and the second ohmic contact metal layer are connected to the gallium nitride epitaxial structure layer and are arranged at intervals; The passivation dielectric layer covers between the first ohmic contact metal layer and the P-type gallium nitride gate region, and between the second ohmic contact metal layer and the P-type gallium nitride gate region on the gallium nitride epitaxial structure layer; Wherein, a functional high-resistance region is provided on the side wall of the P-type gallium nitride gate region and on a part of the top surface connected to the side wall, and the gate metal layer is connected to the P-type gallium nitride gate region and covers a part of the functional high-resistance region.

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