Semiconductor structure and forming method

Abstract

The invention provides a semiconductor structure and a forming method. The semiconductor structure includes a substrate, a channel layer, a barrier layer, a compound semiconductor layer, a gate electrode, a source electrode, and a drain electrode. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The compound semiconductor layer is disposed on the barrier layer and includes a first portion and a second portion separated from each other. The gate electrode is disposed on the first portion of the compound semiconductor layer. The source electrode and the drain electrode are respectively arranged on the barrier layer and are respectively arranged on opposite sides of the gate electrode. Wherein the drain electrode covers the second portion of the compound semiconductor layer.

Description

Technical Field

[0001] The present invention relates to a semiconductor structure and a forming method thereof, and more particularly to a semiconductor structure including a compound semiconductor layer covered by a drain electrode and a forming method thereof. Background Art

[0002] Due to the wide band-gap and strong polarization effect of gallium nitride materials, gallium nitride materials are widely used. For example, currently, gallium nitride-based semiconductors have been widely used in power devices, such as high electron mobility transistors (HEMTs) including heterojunction structures.

[0003] However, in high electron mobility transistors, there may be problems such as over-concentration of electric field distribution, insufficient on-current, deterioration of dynamic resistance characteristics, the need to apply a turn-on voltage to turn on, and complex processes and structures. Therefore, although existing semiconductor structures and their forming methods have gradually met their intended uses, they still do not fully meet the requirements in all aspects. Therefore, there are still some problems to be overcome regarding semiconductor structures and their forming methods. Summary of the Invention

[0004] The drain electrode of the present invention forms an ohmic contact (non-rectifying contact) with the second portion of the compound semiconductor layer. Since the ohmic contact (non-rectifying contact) can be analogous to a resistor, the semiconductor structure can be turned on without applying a turn-on voltage. Specifically, in the case where no voltage is applied (or the turn-on voltage is substantially 0), the two-dimensional electron gas in the semiconductor structure can be un-fully depleted, enabling the semiconductor structure to be turned on. In addition, the ohmic contact (non-rectifying contact) can provide more holes to neutralize the trapped charges captured by defects in each layer, thereby making the electric field distribution in the semiconductor structure uniform, increasing the on-current and / or improving the dynamic resistance characteristics. Among them, improving the dynamic resistance characteristics may include maintaining the dynamic on-resistance to avoid the problem of the on-resistance increasing with the increase in voltage. Furthermore, by adjusting the shape, size, and arrangement of the second portion of the compound semiconductor layer, the regrowth process can be omitted, thereby reducing the process and structure complexity.

[0005] In some embodiments, a semiconductor structure is provided. The semiconductor structure includes a substrate, a channel layer, a blocking layer, a compound semiconductor layer, a gate electrode, a source electrode, and a drain electrode. The channel layer is disposed on the substrate. The blocking layer is disposed on the channel layer. The compound semiconductor layer is disposed on the blocking layer and includes a first part and a second part separated from each other. The gate electrode is disposed on the first part of the compound semiconductor layer. The source electrode and the drain electrode are respectively disposed on the blocking layer and on opposite sides of the gate electrode. Wherein, the drain electrode covers the second part of the compound semiconductor layer.

[0006] In some embodiments, a method of forming a semiconductor structure is provided. The method of forming a semiconductor structure includes providing a substrate. Forming a channel layer on the substrate. Forming a blocking layer on the channel layer. Forming a compound semiconductor layer on the blocking layer, wherein the compound semiconductor layer includes a first part and a second part separated from each other. Forming a gate electrode on the first part of the compound semiconductor layer. Forming a source electrode and a drain electrode on the blocking layer, and the source electrode and the drain electrode are respectively disposed on opposite sides of the gate electrode. Wherein, the drain electrode covers the second part of the compound semiconductor layer.

[0007] In the present invention, by making the drain electrode cover the second part of the compound semiconductor layer, an ohmic contact (non-rectifying contact) is formed between the drain electrode and the second part of the compound semiconductor layer. Thus, the drain electrode providing an ohmic contact (non-rectifying contact) can supply holes, resulting in a uniform electric field distribution, an increased conduction current, and / or an improved dynamic resistance characteristic. Additionally, the drain electrode with an ohmic contact (non-rectifying contact) can conduct at a conduction voltage of approximately 0, and can also reduce the process and structure complexity. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The present invention can be more fully understood from the following detailed description when read in conjunction with the drawings. It should be noted that, in accordance with standard industry practice, the components are not drawn to scale. In fact, for clarity purposes, the dimensions of the components can be arbitrarily enlarged or reduced.

[0009] Figures 1 to 3 are cross-sectional schematic views of different stages of a method of forming a semiconductor structure according to an embodiment of the present invention.

[0010] Figure 4 is a top view schematic of a semiconductor structure according to an embodiment of the present invention.

[0011] Figure 5 is a cross-sectional schematic of a semiconductor structure according to an embodiment of the present invention.

[0012] Figure 6 is a top view schematic of a semiconductor structure according to an embodiment of the present invention.

[0013] Figure 7 is a cross-sectional schematic view of a semiconductor structure according to an embodiment of the present invention.

[0014] Figure 8 is a top-down schematic view of a semiconductor structure according to an embodiment of the present invention.

[0015] Figure 9 is a cross-sectional schematic view of a semiconductor structure according to an embodiment of the present invention.

[0016] Figure 10 is a top-down schematic view of a semiconductor structure according to an embodiment of the present invention.

[0017] Symbol Explanation

[0018] 1, 2, 3, 4: Semiconductor Structure

[0019] 100: Substrate

[0020] 200: Buffer Layer

[0021] 300: Channel Layer

[0022] 310: Two-Dimensional Electron Gas

[0023] 400: Barrier Layer

[0024] 500: Compound Semiconductor Layer

[0025] 510: First Part

[0026] 520: Second Part

[0027] 600: Gate Electrode

[0028] 620: Source Electrode

[0029] 640: Drain Electrode

[0030] 640E1, 640E2: Edges

[0031] 700: First Dielectric Layer

[0032] 800: Second Dielectric Layer

[0033] 820, 840: Connectors

[0034] 822: Source Field Plate

[0035] 842: Drain Field Plate

[0036] D1: First Direction

[0037] D2: Second Direction

[0038] D3: Third Direction

[0039] I-I’, II-II’, III-III’, IV-IV’: Sections

[0040] S1: Distance

[0041] W520, W640: Widths Detailed implementation manners

[0042] The semiconductor structures of the embodiments of the present invention are described in detail below. It should be understood that the following description provides many different embodiments for implementing different aspects of some embodiments of the present invention. The specific devices and arrangements described below are only for simply and clearly describing some embodiments of the present invention. Of course, these are only for illustration and not for limiting the present invention. In addition, similar and / or corresponding device symbols may be used in different embodiments to indicate similar and / or corresponding devices to clearly describe the present invention. However, the use of these similar and / or corresponding device symbols is only for simply and clearly describing some embodiments of the present invention, and does not represent any relevance between the different embodiments and / or structures discussed.

[0043] It should be understood that in each embodiment, relative terms may be used, for example, "lower" or "bottom" or "higher" or "top", to describe the relative relationship of one device in the figure to another device. It can be understood that if the device in the figure is flipped upside down, the device described on the "lower" side will become the device on the "higher" side. The embodiments of the present invention can be understood in conjunction with the figures, and the figures of the present invention are also regarded as part of the invention description.

[0044] Furthermore, when it is mentioned that a first material layer is on or over a second material layer, it may include the case where the first material layer is in direct contact with the second material layer, or the first material layer and the second material layer may not be in direct contact, that is, there may be one or more other material layers between the first material layer and the second material layer. However, when the first material layer is directly on the second material layer, it means that the first material layer is in direct contact with the second material layer.

[0045] In addition, it should be understood that the ordinal numbers such as "first", "second", etc. used in the specification and the claims are used to modify the devices, and they do not themselves intend to imply that the device (or the plurality of devices) has any previous ordinal numbers, nor do they represent the order of one device and another device, or the order in the manufacturing method. The use of these ordinal numbers is only to clearly distinguish a device with a certain name from another device with the same name. The claims and the specification may not use the same terms. For example, the first device in the specification may be the second device in the claims.

[0046] In some embodiments of the present invention, terms related to joining and connection, such as "connect", "interconnect", "bond", etc., unless otherwise specifically defined, may refer to two structures being in direct contact, or may also refer to two structures not being in direct contact, with other structures disposed between these two structures. And these terms related to connection and joining may also include cases where both structures are movable, or both structures are fixed. In addition, the term "electrically connected" or "electrically coupled" includes any direct and indirect electrical connection means.

[0047] In the text, terms such as "approximate", "about", "substantially" generally mean within 10%, or 5%, or 3%, or 2%, or 1%, or 0.5% of a given value or range. The given quantity is an approximate quantity, that is, the meaning of "approximate", "about", "substantially" may still be implied even without specific mention of "approximate", "about", "substantially". The term "ranging from a first value to a second value" or "the first value ~ the second value" means that the said range includes the first value, the second value, and other values therebetween. Moreover, there may be a certain error between any two values or directions being compared. If the first value is equal to the second value, it implies that there may be an error of about 10%, or within 5%, or within 3%, or within 2%, or within 1%, or within 0.5% between the first value and the second value.

[0048] Throughout the specification and claims of the present invention, certain terms are used to refer to specific devices. Those skilled in the art should understand that electronic device manufacturers may refer to the same device by different names. This article is not intended to distinguish devices with the same function but different names. In the following specification and claims, words such as "comprise", "include", "have", etc. are open-ended words, and thus should be interpreted as meaning "including but not limited to...". Therefore, when the description of the present invention uses the terms "comprise", "include" and / or "have", it specifies the existence of corresponding components, regions, steps, operations and / or devices, but does not exclude the existence of one or more corresponding components, regions, steps, operations and / or devices.

[0049] It should be understood that, without departing from the spirit of the present invention, the components in multiple different embodiments can be replaced, recombined, and combined to complete other embodiments in the following examples. As long as the components between the embodiments do not violate the spirit of the invention or conflict with each other, they can be arbitrarily combined and used.

[0050] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. It is understood that such terms, if defined in a commonly used dictionary, should be interpreted as having a meaning consistent with the context of the relevant art and the background or context of the present invention, and should not be interpreted in an idealized or overly formal manner, unless specifically defined in the embodiments of the present invention.

[0051] In the present invention, each direction is not limited to the three axes of the Cartesian coordinate system, namely the X-axis, the Y-axis, and the Z-axis, and can be interpreted in a broader sense. For example, the X-axis, the Y-axis, and the Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other, but are not limited thereto. For the sake of illustration, hereinafter, the X-axis direction is the first direction D1 (width direction), the Y-axis direction is the second direction D2 (length direction), and the Z-axis direction is the third direction D3 (thickness direction). In some embodiments, the top view schematic diagram described herein is a schematic diagram of observing the XY plane (the plane formed by the first direction D1 and the second direction D2), and the cross-sectional schematic diagram described herein is a schematic diagram of observing the XZ plane (the plane formed by the first direction D1 and the third direction D3).

[0052] Hereinafter, the current-voltage characteristic curve of an "Ohmic contact (non-rectifying contact)" shows a linear relationship and is bidirectionally conductive without rectifying characteristics.

[0053] Refer to Figure 1 , which is a cross-sectional schematic diagram of different stages of a method for forming a semiconductor structure 1 according to an embodiment of the present invention. As Figure 1 shown, in some embodiments, a substrate 100 may be provided. In some embodiments, the substrate 100 may include a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, or the like. A semiconductor-on-insulator substrate includes a semiconductor layer formed on an insulator. For example, the insulating layer may include silicon oxide, silicon nitride, poly-silicon, or a combination thereof, and the semiconductor substrate may include silicon, aluminum nitride (AlN), or the like.

[0054] In some embodiments, the substrate 100 may be an undoped or doped substrate, such as a substrate doped with a p-type or n-type dopant. In some embodiments, the substrate 100 may include a multi-layered substrate or a gradient substrate. In some embodiments, the substrate 100 may include a semiconductor substrate or a ceramic substrate, such as a gallium nitride (GaN) substrate, a silicon carbide (SiC) substrate, an aluminum nitride substrate, or a sapphire substrate. In some embodiments, the substrate 100 may be a silicon substrate.

[0055] As Figure 1 shown, in some embodiments, a buffer layer 200 may be formed on the substrate 100 to improve the compatibility between the substrate 100 and other devices disposed on the substrate 100, such as reducing the difference in thermal expansion coefficient and / or reducing the difference in lattice constant. In some embodiments, the buffer layer 200 may include a III-V compound semiconductor material, such as a group III nitride. For example, the buffer layer 200 may include gallium nitride (GaN), aluminum nitride (AlN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), the like, or a combination thereof, but the present invention is not limited thereto. In some embodiments, the buffer layer 200 may be formed by a deposition process. For example, the deposition process may be chemical vapor deposition (CVD), atomic layer deposition (ALD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), the like, or a combination thereof, but the present invention is not limited thereto.

[0056] In some embodiments, a nucleation layer may be further disposed between the substrate 100 and the buffer layer 200 to reduce the lattice difference between the substrate 100 and other layers disposed on the substrate 100, thereby improving the epitaxial quality and reliability. In some embodiments, the nucleation layer may include aluminum nitride (AlN), aluminum gallium nitride (AlGaN), the like, or a combination thereof, but the present invention is not limited thereto. In some embodiments, the nucleation layer may be formed by a deposition process. In other embodiments, the buffer layer 200 may be omitted.

[0057] As Figure 1As shown, in some embodiments, a channel layer 300 may be formed on a substrate 100. Specifically, the channel layer 300 may be formed on a buffer layer 200. In some embodiments, the channel layer 300 may include a III-V compound semiconductor material, such as, but not limited to, group III nitrides. For example, the channel layer 300 may include gallium nitride (GaN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), indium aluminum gallium nitride (InAlGaN), analogs thereof, or combinations thereof, but not limited to this. In some embodiments, the channel layer 300 may be gallium nitride. In some embodiments, the channel layer 300 may be formed by a deposition process.

[0058] As Figure 1 shown, in some embodiments, a blocking layer 400 may be formed on the channel layer 300. In some embodiments, the blocking layer 400 may include a III-V compound semiconductor material, such as group III nitrides, but not limited to this. For example, the blocking layer may include aluminum nitride (AlN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium aluminum gallium nitride (InAlGaN), analogs thereof, or combinations thereof, but not limited to this. In some embodiments, the blocking layer 400 may be aluminum gallium nitride. In some embodiments, the blocking layer 400 may be formed by a deposition process. Since there is a heterointerface between the channel layer 300 and the blocking layer 400, and there is a difference in lattice constant between the channel layer 300 and the blocking layer 400, a two-dimensional electron gas (2DEG) 310 may be formed near the top surface of the channel layer 300 and serve as a current path.

[0059] Referring Figure 2 , which is a cross-sectional schematic diagram of different stages of a method for forming a semiconductor structure 1 according to an embodiment of the present invention. As Figure 2 shown, in some embodiments, a compound semiconductor layer 500 may be formed on the blocking layer 400. In some embodiments, the compound semiconductor layer 500 may be formed by a deposition process. In some embodiments, the compound semiconductor layer 500 may be a semiconductor material doped with p-type dopants. For example, the compound semiconductor layer 500 may include p-type doped gallium nitride (p-GaN). Therefore, the formation of the two-dimensional electron gas 310 located below the compound semiconductor layer 500 can be suppressed, so that the two-dimensional electron gas 310 located below the compound semiconductor layer 500 is depleted. In some embodiments, the compound semiconductor layer 500 may include a first part 510 and a second part 520 separated from each other.

[0060] Referring Figure 3, which is a cross-sectional schematic diagram of different stages of a method of forming a semiconductor structure 1 according to an embodiment of the present invention. In some embodiments, a gate electrode 600 may be formed on a first portion 510 of a compound semiconductor layer 500 such that the semiconductor structure 1 is a normally off structure. In some embodiments, the gate electrode 600 may include a conductive material. In some embodiments, the conductive material may include a metal, a metal nitride, a semiconductor material, an analogue thereof, or a combination thereof, but the present invention is not limited thereto. In some embodiments, the metal may include gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), copper (Cu), an analogue thereof, or a combination thereof. In some embodiments, the metal nitride may include titanium nitride (TiN), tantalum nitride (TaN), an analogue thereof, or a combination thereof. In some embodiments, the semiconductor material may include polycrystalline silicon or polycrystalline germanium, an analogue thereof, or a combination thereof. In some embodiments, the conductive material may be formed by chemical vapor deposition, sputtering, resistive heating evaporation, electron beam evaporation, an analogue process, or a combination thereof, but the present invention is not limited thereto. In some embodiments, the gate electrode 600 and the first portion 510 of the compound semiconductor layer 500 may be a Schottky contact (rectifying contact).

[0061] As Figure 3 shown, in some embodiments, a source electrode 620 and a drain electrode 640 may be formed on the barrier layer 400. In some embodiments, the source electrode 620 and the drain electrode 640 may be disposed on opposite sides of the gate electrode 600, respectively. In some embodiments, the source electrode 620 may be in contact with the barrier layer 400, and the drain electrode 640 may be in contact with the barrier layer 400 and a second portion 520 of the compound semiconductor layer 500. In some embodiments, the materials and formation methods of the source electrode 620 and the drain electrode 640 may be the same as or different from those of the gate electrode 600. In some embodiments, the source electrode 620 may be an ohmic contact (non-rectifying contact) to the barrier layer 400. In some embodiments, the drain electrode 640 may be an ohmic contact (non-rectifying contact) to the barrier layer 400, and the drain electrode 640 may be an ohmic contact (non-rectifying contact) to the second portion 520 of the compound semiconductor layer 500.

[0062] As Figure 3As shown, in some embodiments, the drain electrode 640 covers the second portion 520 of the compound semiconductor layer 500. In some embodiments, the drain electrode 640 is closer to the gate electrode 600 than the second portion 520 of the compound semiconductor layer 500. In some embodiments, a portion of the drain electrode 640 may be interposed between the gate electrode 600 and the second portion 520 of the compound semiconductor layer 500. In some embodiments, the drain electrode 640 and the barrier layer 400 may jointly surround the second portion 520 of the compound semiconductor layer 500 without exposing the second portion 520 of the compound semiconductor layer 500. In some embodiments, the drain electrode 640 may cover the top surface and the side surface of the second portion 520 of the compound semiconductor layer 500, and the barrier layer 400 may cover the bottom surface of the second portion 520 of the compound semiconductor layer 500.

[0063] As Figure 3 shown, in some embodiments, in the first direction D1, the second portion 520 of the compound semiconductor layer 500 may have a width W520, and the drain electrode 640 may have a width W640. In some embodiments, the width W640 may be greater than the width W520. In some embodiments, the ratio of the width W520 to the width W640 (width W520 / width W640) may be less than 1 and greater than or equal to 0.1. For example, the ratio of the width W520 to the width W640 may be 0.1, 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, 0.9, 0.95 or any value between the foregoing values or any value range composed of any values, but the present invention is not limited thereto. Accordingly, the current path can be retained.

[0064] As Figure 3 shown, in some embodiments, a first dielectric layer 700 may be formed on the barrier layer 400. In some embodiments, the first dielectric layer 700 may be interposed between the source electrode 620 and the gate electrode 600 and between the gate electrode 600 and the drain electrode 640. In some embodiments, the first dielectric layer 700 may be spaced apart from the second portion 520 of the compound semiconductor layer 500 by a distance. In some embodiments, the first dielectric layer 700 may be formed by a deposition process. In some embodiments, the first dielectric layer 700 may serve as a passivation layer or a planarization layer. In some embodiments, the first dielectric layer 700 may include an oxide such as silicon oxide, a nitride such as silicon nitride, a oxynitride such as silicon oxynitride, analogs thereof, or combinations thereof, but the present invention is not limited thereto.

[0065] As Figure 3As shown, in some embodiments, a second dielectric layer 800 may be formed on the gate electrode 600, source electrode 620, drain electrode 640, and the first dielectric layer 700. In some embodiments, the material and formation method of the second dielectric layer 800 may be the same as or different from those of the first dielectric layer 700. In some embodiments, the second dielectric layer 800 may serve as an interlayer dielectric layer. In some embodiments, connectors 820 and 840 may be formed in the second dielectric layer 800. In some embodiments, the connectors 820 and 840 may penetrate through the second dielectric layer 800. In some embodiments, the connectors 820 and 840 may include a conductive material. In some embodiments, the connector 820 may be electrically connected to the source electrode 620, and the connector 840 may be electrically connected to the drain electrode 640. In some embodiments, the connectors 820 and 840 may be formed by forming an opening (not shown) that penetrates the second dielectric layer 800 and then redepositing a conductive material in the opening.

[0066] As Figure 3 shown, in some embodiments, a source field plate 822 and a drain field plate 842 may be formed on the second dielectric layer 800 to obtain the semiconductor structure 1. In some embodiments, the source field plate 822 may be electrically connected to the source electrode 620 through the connector 820. In some embodiments, the drain field plate 842 may be electrically connected to the drain electrode 640 through the connector 840. In some embodiments, the source field plate 822 and the drain field plate 842 may be used to adjust the electric field distribution. In some embodiments, the source field plate 822 and the drain field plate 842 may include a conductive material. In some embodiments, the projection of the source electrode 620 on the substrate 100 may be located within the projection of the source field plate 822 on the substrate 100. In some embodiments, the projection of the gate electrode 600 on the substrate 100 may be located within the projection of the source field plate 822 on the substrate 100. Accordingly, the source field plate 822 may make the electric field near the source electrode 620 and the gate electrode 600 evenly distributed. In some embodiments, the projection of the drain electrode 640 on the substrate 100 may be located within the projection of the drain field plate 842 on the substrate 100. Accordingly, the drain field plate 842 may make the electric field near the drain electrode 640 evenly distributed.

[0067] Referring Figure 4 to, which is a top view schematic diagram of the semiconductor structure 1 according to an embodiment of the present invention. For ease of illustration, Figure 4 some devices are omitted. Among them, Figure 4 the structure shown in the cross-section I-I’ is shown in Figure 3 the figure.

[0068] In some embodiments, the projection of the second portion 520 of the compound semiconductor layer 500 onto the substrate 100 may be located within the projection of the drain electrode 640 onto the substrate 100. In some embodiments, the projected area of the second portion 520 of the compound semiconductor layer 500 onto the substrate 100 may be smaller than the projected area of the drain electrode 640 onto the substrate 100. In some embodiments, the ratio of the projected area of the second portion 520 of the compound semiconductor layer 500 onto the substrate 100 to the projected area of the drain electrode 640 onto the substrate 100 may be 0.1 to 0.95. For example, the ratio of the projected area of the second portion 520 onto the substrate 100 to the projected area of the drain electrode 640 onto the substrate 100 (projected area of the second portion 520 onto the substrate 100 / projected area of the drain electrode 640 onto the substrate 100) may be 0.1, 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, 0.9, 0.95, or any value between the foregoing values or any numerical range composed of any values, but the present invention is not limited thereto. Accordingly, the ratio of the depletion region to the undepleted region can be adjusted such that the two-dimensional electron gas in the semiconductor structure is not completely depleted, thereby retaining the current path.

[0069] In some embodiments, the drain electrode 640 may have a pair of edges 640E1 that are opposite to each other in the extending direction of the gate electrode 600 (i.e., the second direction D2), and the drain electrode 640 may have a pair of edges 640E2 that are opposite to each other in the direction perpendicular to the extending direction of the gate electrode 600 (i.e., the first direction D1). Among them, the edge 640E1 and the edge 640E2 are adjacent to each other. In some embodiments, in the extending direction of the gate electrode 600 (i.e., the second direction D2), the second portion 520 of the compound semiconductor layer 500 is spaced apart from the edge 640E1 of the drain electrode 640 by a distance S1.

[0070] In some embodiments, the second portion 520 of the compound semiconductor layer 500 may include a plurality of sub-portions, and the plurality of sub-portions may be spaced apart. In some embodiments, the plurality of sub-portions may be arranged in an array. In some embodiments, each of the plurality of sub-portions may have a rectangular, triangular, polygonal, semi-circular, semi-elliptical, bullet-shaped, water-drop-shaped, other suitable shape, or a combination thereof, but the present invention is not limited thereto. In some embodiments, the total width of the plurality of sub-portions of the second portion 520 of the compound semiconductor layer 500 may be the width W520.

[0071] In some embodiments, the second portion 520 of the compound semiconductor layer 500 may include multiple columns of sub-portions, and each column of sub-portions in the multiple columns may extend along the second direction D2 and may be spaced along the first direction D1. In some embodiments, each column in the multiple columns may be staggeredly arranged. In some embodiments, the number of sub-portions of adjacent columns in the multiple columns may be the same or different. In some embodiments, taking the edge 640E2 of the drain electrode 640 far from the gate electrode 600 as a reference, the number of sub-portions in odd-numbered columns may be greater than the number of sub-portions in even-numbered columns.

[0072] In some embodiments, the second portion 520 of the compound semiconductor layer 500 may include multiple rows of sub-portions, and each row of sub-portions in the multiple rows may extend along the first direction D1 and may be spaced along the second direction D2. In some embodiments, each row in the multiple rows may be staggeredly arranged. In some embodiments, the number of sub-portions of adjacent rows in the multiple rows may be the same or different. In some embodiments, the total width of the sub-portions of each row in the multiple rows may be the width W520. In some embodiments, the total width of the sub-portions of each row in the multiple rows may be the same or different.

[0073] Accordingly, when no voltage is applied (for example, the turn-on voltage is approximately 0), a part of the two-dimensional electron gas 310 remains continuous, thus retaining the current path. For example, when the turn-on voltage is approximately 0, the two-dimensional electron gas 310 under the blocking layer 400 not covered by the second portion 520 of the compound semiconductor layer 500 is continuous, so that there is still a current path between the source electrode 620 and the drain electrode 640. In some embodiments, the second portion 520 of the compound semiconductor layer 500 may not be provided on a virtual connection line between the gate electrode 600 and the drain electrode 640 to retain the current path. For example, the current path may flow through the gaps between the sub-portions of the second portion 520 of the compound semiconductor layer 500.

[0074] Hereinafter, the same or similar device symbols and descriptions may be omitted.

[0075] Refer to Figure 5 and Figure 6 , which are a cross-sectional schematic diagram and a top-view schematic diagram of a semiconductor structure 2 according to an embodiment of the present invention. For ease of illustration, Figure 6 some devices are omitted. Among them, Figure 6 the structure shown in the cross-section II-II’ is shown in Figure 5In some embodiments, the second portion 520 of the compound semiconductor layer 500 may include a plurality of sub-portions, and each of the plurality of sub-portions may extend along the first direction D1 and may be spaced apart along the second direction D2. In some embodiments, in the first direction D1, the width W640 of the drain electrode 640 may be greater than the width W520 of the second portion 520 of the compound semiconductor layer 500. In some embodiments, the ratio of the width W520 to the width W640 (width W520 / width W640) may be less than 1 and greater than or equal to 0.5. For example, the ratio of the width W520 to the width W640 may be 0.5, 0.6, 0.7, 0.8, 0.9, 0.95 or any value between the foregoing values or any numerical range composed of any values, but the present invention is not limited thereto. Accordingly, the current path can be retained. For example, the current path may flow through the gaps between the sub-portions of the second portion 520 of the compound semiconductor layer 500.

[0076] Referring to Figure 7 and Figure 8 , which are a cross-sectional schematic view and a top view of a semiconductor structure 3 according to an embodiment of the present invention. For ease of illustration, Figure 8 some devices are omitted. Among them, Figure 8 the structure shown in the cross-section III-III' is shown in Figure 7 In some embodiments, the drain electrode 640 may cover a part of the top surface of the second portion 520 of the compound semiconductor layer 500 and expose the remaining part of the top surface of the second portion 520 of the compound semiconductor layer 500. In some embodiments, the first dielectric layer 700 may contact the second portion 520 of the compound semiconductor layer 500. In some embodiments, compared with the drain electrode 640, the second portion 520 of the compound semiconductor layer 500 may be closer to the gate electrode 600. Even though the second portion 520 of the compound semiconductor layer 500 may be closer to the gate electrode 600, since the second portions 520 of the compound semiconductor layer 500 are spaced apart from each other in the second direction D2, the current path can still be retained.

[0077] In some embodiments, the ratio of the width W520 to the width W640 may be less than or equal to 1.2 and greater than or equal to 0.1. For example, the ratio of the width W520 to the width W640 may be 0.1, 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, 0.9, 1, 1.1, 1.2 or any value between the foregoing values or any numerical range composed of any values, but the present invention is not limited thereto. For example, the current path may flow through the gaps between the sub-portions of the second portion 520 of the compound semiconductor layer 500. Furthermore, the process margin for forming the second portion 520 of the compound semiconductor layer 500 can be improved.

[0078] In some embodiments, the projection of the second portion 520 of the compound semiconductor layer 500 onto the substrate 100 may be located outside the projection of the drain electrode 640 onto the substrate 100, and the projection of the second portion 520 of the compound semiconductor layer 500 onto the substrate 100 may be located inside the projection of the drain field plate 842 onto the substrate 100. Accordingly, the drain field plate 842 can evenly distribute the electric field adjacent to the drain electrode 640.

[0079] Referring to Figure 9 and Figure 10 , which are a cross-sectional schematic view and a top view schematic view of a semiconductor structure 4 according to an embodiment of the present invention. For ease of illustration, Figure 10 some devices are omitted. Among them, Figure 10 the structure shown in the cross-section IV-IV' is shown in Figure 9 . In some embodiments, in a top view, the second portion 520 of the compound semiconductor layer 500 may be in a grid shape, a tic-tac-toe shape, a cross shape, or other suitable shapes, but the present invention is not limited thereto.

[0080] In some embodiments, the second portion 520 of the compound semiconductor layer 500 may include a plurality of first extension portions and a plurality of second extension portions that are alternately arranged with each other. In some embodiments, each of the plurality of first extension portions may extend along a first extension direction, and each of the plurality of second extension portions may extend along a second extension direction that forms an angle of 15 degrees to 90 degrees with the first extension direction, but the present invention is not limited thereto. For example, the plurality of first extension portions may be horizontal extension portions, and each of the plurality of first extension portions may extend along a first direction D1, and the plurality of second extension portions may be vertical extension portions, and each of the plurality of second extension portions may extend along a second direction D2. Accordingly, the current path can be retained. For example, the current path may flow along the outer edge of the second portion 520 of the compound semiconductor layer 500 in a grid shape.

[0081] In some embodiments, the semiconductor structures 1 to 4 of the present invention can be used in any combination and can be used as high electron mobility transistors. In other embodiments, a further process may be performed on any one of the semiconductor structures 1 to 4 to form a high electron mobility transistor.

[0082] Accordingly, in the present invention, by covering the second portion of the compound semiconductor layer with the drain electrode, an ohmic contact (non-rectifying contact) is formed between the drain electrode and the second portion of the compound semiconductor layer. Thus, the drain electrode with an ohmic contact (non-rectifying contact) can provide holes, so that the electric field distribution is uniform, the on-current is increased, and / or the dynamic resistance characteristics are improved. In addition, the drain electrode with an ohmic contact (non-rectifying contact) can conduct when the on-voltage is approximately 0, and can also reduce the process and structure complexity.

[0083] The scope of protection of the present invention is not limited to the processes, machines, manufactures, compositions of matter, devices, methods, and steps in the specific embodiments described in the specification. Any person skilled in the art can understand from the disclosure of the present invention the processes, machines, manufactures, compositions of matter, devices, methods, and steps developed currently or in the future. As long as they can perform substantially the same functions or achieve substantially the same results in the embodiments described herein, they can be used according to the present invention. Therefore, the scope of protection of the present invention includes the aforementioned processes, machines, manufactures, compositions of matter, devices, methods, and steps. Any embodiment or claim of the present invention does not have to achieve all the purposes, advantages, and / or features described in the present invention.

[0084] The above outlines several embodiments so that those skilled in the art of the present invention can better understand the viewpoints of the embodiments of the present invention. Those skilled in the art of the present invention should understand that they can design or modify other processes and structures based on the embodiments of the present invention to achieve the same purposes and / or advantages as the embodiments herein. Those skilled in the art of the present invention should also understand that such equivalent processes and structures do not depart from the spirit and scope of the present invention, and they can make various changes, substitutions, and replacements without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor structure, characterized in that, Comprising: A substrate; A channel layer disposed on the substrate; A blocking layer disposed on the channel layer; A compound semiconductor layer disposed on the blocking layer, including a first part and a second part separated from each other; A gate electrode disposed on the first part of the compound semiconductor layer; And A source electrode and a drain electrode, respectively disposed on the blocking layer and on opposite sides of the gate electrode, wherein the drain electrode covers the second part of the compound semiconductor layer.

2. The semiconductor structure according to claim 1, wherein The projected area of the second part of the compound semiconductor layer on the substrate is smaller than the projected area of the drain electrode on the substrate.

3. The semiconductor structure according to claim 1, wherein In an extending direction of the gate electrode, the second part of the compound semiconductor layer is spaced apart from an edge of the drain electrode by a distance.

4. The semiconductor structure according to claim 1, wherein Compared with the drain electrode, the second part of the compound semiconductor layer is closer to the gate electrode.

5. The semiconductor structure according to claim 1, wherein The drain electrode and the blocking layer surround the second part of the compound semiconductor layer.

6. The semiconductor structure according to claim 1, wherein, In an extending direction of the gate electrode, the second part of the compound semiconductor layer includes a plurality of sub-parts, and the plurality of sub-parts are spaced apart.

7. The semiconductor structure according to claim 1, characterized in that, The second part of the compound semiconductor layer includes multiple columns of sub-parts, and each column of the multiple columns of sub-parts is staggered.

8. The semiconductor structure according to claim 1, wherein In a top view, the second part of the compound semiconductor layer has a grid-like shape.

9. The semiconductor structure according to claim 1, wherein The gate electrode and the first part of the compound semiconductor layer are in Schottky contact, and the drain electrode and the second part of the compound semiconductor layer are in ohmic contact.

10. A method for forming a semiconductor structure, characterized in that, Comprising: Providing a substrate; Forming a channel layer on the substrate; Forming a blocking layer on the channel layer; Forming a compound semiconductor layer on the blocking layer, wherein the compound semiconductor layer includes a first part and a second part separated from each other; Forming a gate electrode on the first part of the compound semiconductor layer; and Forming a source electrode and a drain electrode on the blocking layer, and the source electrode and the drain electrode are respectively disposed on opposite sides of the gate electrode, wherein the drain electrode covers the second part of the compound semiconductor layer.

Images