LDMOS device of stepped field plate and manufacturing method thereof

Abstract

The embodiment of the invention provides an LDMOS (Laterally Diffused Metal Oxide Semiconductor) device of a stepped field plate and a manufacturing method of the LDMOS device. The method comprises the following steps: providing a substrate; forming a drift region at one end of the substrate, and forming a body region at the other end; forming a drain region in the drift region, forming a source region in the body region, and forming a gate region on the drift region and the body region; depositing a silicide barrier layer on a part covering the upper surface of the gate region and extending to the upper surface of the drain region along the direction towards the drain region; covering a dielectric layer on the substrate on which the silicide barrier layer is formed; the contact hole layer is formed through etching of the mask plate of the contact hole layer, and meanwhile a first layer field plate of the stepped contact field plate is formed through etching of the mask plate of the contact hole layer; and forming the remaining (n-1) layers of field plates of the stepped contact field plate, different field plate layers staying in different layers in the silicide barrier layer. The problems that an existing multi-layer stepped field plate structure is complex in manufacturing process, high in manufacturing cost and the like are solved.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the technical field of semiconductor power devices, and more particularly, to a LDMOS device with a stepped field plate and a manufacturing method thereof. Background Art

[0002] Contact Field Plate (CFP) technology is a highly competitive field plate technology, which is widely used in the electric field optimization of lateral diffused metal oxide semiconductor (LDMOS) devices. Specifically, by adding a contact field plate and connecting the contact field plate to the source terminal, gate terminal, or drain terminal, the voltage difference between the drain terminal and the contact field plate will make the electric field under the contact field plate evenly distributed. Without changing the specific on-resistance of the device, the peak value of the device surface electric field can be reduced, thereby improving the breakdown voltage (BV) performance of the device. At the same time, the contact field plate can improve the hot carrier injection effect (HCI) of the device and simplify the manufacturing process.

[0003] Common field plates of LDMOS devices include drain field plates, source field plates, and gate electrode field plates. Among them, the setting of the field plate on the side of the drift region close to the source is particularly crucial. Currently, there are various structures and methods for setting field plates. For example Figure 1 As shown, it is a structure of a radio frequency HEMT device with a drain stepped field plate structure in the prior art, which includes a substrate 1, an AlGaN back barrier layer 2, a GaN channel layer 5, and an AlGaN barrier layer 7 stacked on the substrate 1 in sequence. The source 9, the P-type GaN region 8, and the drain 11 are spaced apart and distributed on the surface of the AlGaN barrier layer 7. The P-type GaN region 8 is on the side close to the source 9 and is located between the source 9 and the drain 11. A first passivation layer 10 is provided as a spacer between the P-type GaN region 8 and the drain 11. A gate 13 is provided on the P-type GaN region 8. In the first passivation layer 10, the horizontal drain field plate 12-1 extends along a part of the upper surface of the drain 11 towards the P-type GaN region 8 and extends beyond the drain 11 region. The horizontal drain field plate 12-2 extends along a part of the upper surface of the horizontal drain field plate 12-1 towards the gate 13 and extends beyond the horizontal drain field plate 12-1 region. The horizontal drain field plate 12-1, the horizontal drain field plate 12-2, and the drain 11 form a stepped structure. The vertical drain field plates 3-3, 3-2, and 3-1 are generally in a stepped shape that shrinks downward. The inventors found Figure 1A multi-layer stepped field plate is set in the [device], which can effectively reduce the peak value of the body electric field in the reverse blocking state, and improve the doping concentration of the drift region as much as possible on the premise that the breakdown voltage meets the requirements, thereby reducing the on-resistance of the device. However, when it is applied to the LDMOS device, it is found that in the prior art, when preparing the multi-layer field plate structure, each layer of the field plate needs to be made by relying on a mask and cannot be shared with other masks. That is, for each additional layer of stepped field plate, an additional etching layer is required. The manufacturing process is complex, and it is necessary to optimize the consideration of multi-layer dielectric isolation and field plate forming, and the requirements for subsequent wiring are also higher, and the manufacturing cost is also high. Summary of the Invention

[0004] The embodiments described herein provide a stepped field plate LDMOS device and a manufacturing method thereof to solve the problems of complex manufacturing process and high manufacturing cost of the existing multi-layer stepped field plate structure.

[0005] According to a first aspect of the present disclosure, a manufacturing method of a stepped field plate LDMOS device is provided. The method includes: providing a substrate; forming a drift region at one end of the substrate and a body region at the other end, the upper surface of the body region is flush with the upper surface of the drift region, and the lower surface of the body region is lower than the lower surface of the drift region; forming a drain region in the drift region, forming a source region in the body region, and forming a gate region on the drift region and the body region, the gate region is horizontally located between the source region and the drain region; depositing a silicide blocking layer on a part of the upper surface of the gate region and extending along the direction towards the drain region to the upper surface of the drain region, the silicide blocking layer is composed of alternately arranged silicide layers of different types of materials; covering a dielectric layer on the substrate formed with the silicide blocking layer; etching to form a contact hole layer through a mask of the contact hole layer, and simultaneously etching to form the first field plate of the stepped contact field plate through the mask of the contact hole layer; forming the remaining n-1 field plates of the stepped contact field plate, where different field plate layers stay in different layers of the silicide blocking layer, and n is a positive integer greater than or equal to 2.

[0006] Optionally, forming the remaining n-1 field plates of the stepped contact field plate includes: etching to form each via layer through a mask of each via layer, and simultaneously etching to form the remaining n-1 field plates in sequence through the mask of each via layer.

[0007] Optionally, the remaining n - 1 field plates forming the stepped contact field plate include: forming the second field plate by etching through a field plate groove mask, where n equals 2; or, the remaining n - 1 field plates forming the stepped contact field plate include: selecting one field plate from the remaining n - 1 field plates and etching it through a field plate groove mask, and etching the other n - 2 field plates respectively while etching different via layers through masks of different via layers, where n is greater than 2.

[0008] Optionally, the first field plate of the stepped contact field plate formed by etching through the mask of the contact hole layer includes: when etching the contact hole layer, etching the first field plate groove staying on the first layer of the silicide blocking layer through the mask of the contact hole layer; while filling the contact holes of the contact hole layer with metal, also filling metal in the first field plate groove to form the first field plate, and then covering the first metal layer or metal compound layer; forming the field plate by etching through the mask of the via layer includes: when etching the via layer, etching the field plate groove staying on the silicide layer in the silicide blocking layer through the mask of the via layer; while filling the vias of the via layer with metal, also filling metal in the corresponding field plate groove to form the corresponding field plate, and covering a new metal layer or metal compound layer after filling each via layer with metal.

[0009] Optionally, if the k-th field plate is the field plate formed by etching through the field plate groove mask, forming the field plate by etching through the field plate groove mask includes: etching the k-th field plate groove after etching the (k - 1)-th field plate groove and before covering the (k - 1)-th metal layer or metal compound layer. The k-th field plate groove and the (k - 1)-th field plate groove are filled with metal while filling the (k - 1)-th contact hole or via with metal to form the k-th field plate and the (k - 1)-th field plate, where k is a positive integer greater than or equal to 2.

[0010] Optionally, the field plates in the stepped contact field plate are coupled to the source contact portion or gate contact portion or drain contact portion of the LDMOS device of the stepped field plate through corresponding metal layers or metal compound layers. The source contact portion is the source connection end led out from the source region, the gate contact portion is the gate connection end led out from the gate region, and the drain contact portion is the drain connection end led out from the drain region.

[0011] According to a second aspect of the present disclosure, a stepped field plate LDMOS device is provided, characterized in that the LDMOS device includes a substrate, a drift region, a body region, a source region, a drain region, a gate region, a silicide blocking layer, and a stepped contact field plate. Among them, the substrate is the bottom layer of the LDMOS device; one end above the substrate is the drift region, and the other end is the body region. The upper surface of the body region is flush with the upper surface of the drift region, and the lower surface of the body region is lower than the lower surface of the drift region; the source region is located in the body region, the drain region is located in the drift region, the gate region is located above the body region and the drift region, and in the horizontal direction, the gate region is located between the source region and the drain region; the silicide blocking layer is composed of silicide layers of different types arranged alternately, covers a part of the upper surface of the gate region, and extends along the direction towards the drain region to the upper surface of the drain region; the stepped contact field plate is formed by n field plates arranged in a stepped manner on the silicide layers in the silicide blocking layer. Different field plate layers stay in different layers of the silicide blocking layer. The surface of the first field plate is flush with the upper surface of the etched contact hole; the upper surfaces of the second to nth field plates are respectively flush with the upper surface of the etched contact hole or the through hole, and n is a positive integer greater than or equal to 2.

[0012] Optionally, the number of layers of the stepped field plate is set according to the breakdown voltage value of the LDMOS device. The first boundary line of the first field plate close to the source region side is coplanar with the side surface of the gate layer in the gate region close to the drain region.

[0013] Optionally, the number of layers of the silicide blocking layer is greater than or equal to the number of layers of the field plates in the stepped contact field plate. The first layer of the silicide blocking layer is a silicon oxide layer, and the thickness of each silicide layer in the silicide blocking layer is set respectively according to the breakdown voltage value of the LDMOS device.

[0014] Optionally, the n field plates are arranged at intervals in the horizontal direction. The value range of the interval between the field plates in the stepped contact field plate is greater than or equal to 0.05 micrometers and less than or equal to 10 micrometers.

[0015] In the stepped field plate LDMOS device and its manufacturing method according to the embodiments of the present disclosure, a stepped contact field plate is formed on the silicide layer in the silicide blocking layer, and different field plate layers stay in different layers of the silicide blocking layer, which can effectively reduce the peak value of the body electric field in the reverse blocking state, and on the premise of ensuring that the breakdown voltage meets the requirements, the doping concentration of the drift region is increased as much as possible, thereby reducing the on-resistance of the device; moreover, the field plates in the stepped contact field plate in the embodiments of the present disclosure are mainly formed by etching through the mask plate of the contact hole layer or the mask plate of the via hole layer when etching to form the contact hole layer or etching to form the via hole layer. The etching to form the contact hole layer and the etching to form the via hole layer are etching layers that are already used in the LDMOS manufacturing process. Therefore, compared with the method of adding a new etching layer for each layer of the field plate in the prior art, it can better be compatible with the existing process, the manufacturing method is easier to implement, and the manufacturing cost is also reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below. It should be understood that the following described drawings only relate to some embodiments of the present disclosure and do not limit the present disclosure, where:

[0017] Figure 1 shows a schematic structural diagram of a device of an existing multi-layer stepped field plate process;

[0018] Figure 2 shows a schematic structural diagram of a stepped field plate LDMOS device according to an embodiment of the present disclosure;

[0019] Figure 3 shows a top view schematic diagram of the stepped field plate in a stepped field plate LDMOS device according to an embodiment of the present disclosure;

[0020] Figure 4 shows a flowchart of a manufacturing method of a stepped field plate LDMOS device according to an embodiment of the present disclosure;

[0021] Figures 5-6 shows a schematic diagram of the process of depositing a silicide blocking layer according to an embodiment of the present disclosure;

[0022] Figures 7-19 shows schematic diagrams of three processes of forming a stepped field plate according to an embodiment of the present disclosure;

[0023] The elements in the drawings are schematic and not drawn to scale. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0024] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings. Apparently, the described embodiments are only a part rather than all of the embodiments of the present disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of the present disclosure without creative efforts shall also fall within the scope of protection of the present disclosure.

[0025] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the subject matter of the present disclosure pertains. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the specification and the relevant art, and will not be interpreted in an idealized or overly formal manner unless expressly so defined herein. As used herein, the statement of joining or coupling two or more parts together shall mean that these parts are directly joined together or joined through one or more intermediate components.

[0026] In all embodiments of the present disclosure, terms such as "first" and "second" are only used to distinguish one component (or a part of a component) from another component (or another part of a component).

[0027] To solve problems such as the complex manufacturing process of the existing multi-layer field plate LDMOS structure, a stepped field plate LDMOS device and its manufacturing method are proposed. In the stepped field plate LDMOS device of the embodiments of the present disclosure, different field plate layers form a stepped shape and stay in different layers of the silicide blocking layer respectively, which can effectively reduce the peak value of the body electric field in the reverse blocking state, and as much as possible increase the doping concentration of the drift region on the premise that the breakdown voltage meets the requirements, thereby reducing the on-resistance of the device; and without adding new etching layers or only adding one etching layer, combining the etching contact hole layer and the etching through hole layers of each layer that are already used in the manufacturing process can form a multi-layer stepped field plate, which can be well compatible with the existing process and the manufacturing method is easy to implement. The stepped field plate LDMOS device and its manufacturing method of the present disclosure will be described in detail below.

[0028] Figure 2 FIG. shows a schematic cross-sectional structure of a stepped field plate LDMOS device 200 according to an embodiment of the present disclosure. First, it should be noted that in actual applications, when manufacturing an LDMOS device, it is usually a structure where two LDMOSs share one source electrode. Therefore Figure 2 what is shown in the figure is also a structure where two LDMOSs share one source electrode, Figure 2 and both sides of the dashed line a in the figure are symmetric. Specifically, as Figure 2As shown, the LDMOS device includes a substrate 201, a drift region 202, a body region 203, a source region 204, a drain region 205, a gate region 206, a silicide blocking layer 207, and a stepped contact field plate 208.

[0029] Among them, the substrate 201 is the bottom layer of the LDMOS device; the substrate 201 can be a silicon substrate, a silicon germanium substrate, a III-V group element compound substrate, or other semiconductor material substrates well-known to those skilled in the art. The conductivity type of the substrate 201 can be N-type or P-type. Preferably, in the embodiments of the present disclosure, it is P-type.

[0030] One end above the substrate 201 is the drift region 202, and the other end is the body region 203. The conductivity type of the drift region 202 can also be N-type or P-type. Preferably, the drift region 202 in the embodiments of the present disclosure is an N-type drift region (NDRF), and the body region 203 is a P-type body region (PBODY). In addition, in the embodiments of the present disclosure, the upper surface of the body region 203 is substantially the same as the upper surface of the drift region 202, and the lower surface of the body region 203 is lower than the lower surface of the drift region 202. Both the body region 203 and the drift region 202 can be formed by ion implantation.

[0031] The source region 204 is located in the body region 203, the drain region 205 is located in the drift region 202, and both the source region 204 and the drain region 205 can be formed by ion implantation. The gate region 206 is located above the body region 203 and the drift region 202, and in the horizontal direction, the gate region 206 is located between the source region 204 and the drain region 205, and the gate region 206 is close to the source region 204 and far from the drain region 205. As Figure 2 shown, the gate region 206 includes a gate dielectric layer 2061, a gate layer 2062, and sidewalls 2063. The gate dielectric layer 2061 can be silicon dioxide or other suitable dielectric materials, the gate layer 2062 can be polysilicon or other suitable conductive materials, and the sidewalls 2063 can include one or more of a silicon dioxide layer and a silicon nitride layer.

[0032] The silicide blocking layer 207 is composed of silicide layers of different types of materials arranged alternately, covering a part of the upper surface of the gate region 206 (not completely covering the upper surface of the gate region 206), and extending along the direction towards the drain region 205 to the upper surface of the drain region 205 (covering a part of the upper surface of the drain region 205, not completely covering). The silicide layers of different types of materials include a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, etc. In practical applications, the silicide blocking layer 207 can be selected to have at least two types of material silicide layers arranged alternately. In addition, regardless of the number of layers of the silicide blocking layer 207, its first layer is a silicon oxide layer. In the embodiments of the present disclosure, the number of layers of the silicide blocking layer 207 is greater than or equal to the number of field plates in the stepped contact field plate 208. Figure 2Shown in the figure is a schematic diagram of the three-layer field plate corresponding to the silicide barrier layer 207 with a three-layer structure. Suppose the silicide barrier layer 207 is composed of an alternating arrangement of a silicon oxide layer and a silicon nitride layer, then Figure 2 in it, the first layer 2071 is a silicon oxide layer, the second layer 2072 is a silicon nitride layer, and the third layer 2073 is a silicon oxide layer. Suppose the silicide barrier layer 207 is composed of an alternating arrangement of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer, then Figure 2 in it, the first layer 2071 is a silicon oxide layer, the second layer 2072 can be a silicon nitride layer, and the third layer 2073 can be a silicon oxynitride layer. In addition, the thickness of each layer of silicide in the silicide barrier layer 207 is set according to the breakdown voltage value of the LDMOS device. The breakdown voltage value of the device determines the number of layers of the field plate and the thickness required for the field plate. Therefore, it is necessary to set the number of layers of the field plate and the thickness of each layer of silicide in the silicide barrier layer 207 according to the breakdown voltage value of the LDMOS device. Taking the example where the silicide barrier layer 207 is composed of an alternating arrangement of a silicon oxide layer and a silicon nitride layer, if the breakdown voltage is 50 - 100V, corresponding to two layers of field plates, then the silicide barrier layer 207 can be set as follows: the thickness of the silicon oxide in the first layer is 400 - 1000 angstroms, and the thickness of the silicon nitride in the second layer is 600 - 1500 angstroms; if the breakdown voltage is 80 - 200V, corresponding to three layers of field plates, then the silicide barrier layer 207 is set as follows: the thickness of the silicon oxide in the first layer is 400 - 1000 angstroms, the thickness of the silicon nitride in the second layer is 600 - 1500 angstroms, and the thickness of the silicon oxide in the third layer is 800 - 2000 angstroms.

[0033] The stepped contact field plate 208 is formed by n layers of field plates arranged in a stepped manner on the silicide layer in the silicide barrier layer 207, where n is a positive integer greater than or equal to 2, and the number of layers of the stepped field plate is set according to the breakdown voltage value of the LDMOS device. For example, if the breakdown voltage is 50 - 100V, it corresponds to two layers of field plates; if the breakdown voltage is 80 - 200V, it corresponds to three layers of field plates. Figure 2 Shown in the figure is a schematic diagram of the three-layer field plate (from the first layer to the third layer are 2081, 2082, and 2083 in sequence). Different field plate layers stay in different layers of the silicide barrier layer. The first layer of the field plate is formed when etching the contact hole layer (CT layer), and the surface of the first layer of the field plate is consistent with the upper surface of the etched contact hole; the upper surfaces of the second to nth layers of the field plates are respectively consistent with the upper surfaces of the etched contact holes or through holes. The first boundary line ( Figure 2 the straight line inward from point A in the figure) on the side of the first layer of the field plate close to the source region is coplanar with the side of the source layer 206 in the source region 206 close to the drain region 205. The fact that the first layer of the field plate 2081 is formed by etching the contact hole layer means that when etching the contact holes (the contact holes corresponding to the source, drain, and gate, Figure 2The source contact portion 209, gate contact portion 210, and drain contact portion 211 are formed by simultaneous etching at the same time when they are corresponding contact holes before being filled with metal, that is, the field plate grooves corresponding to the first layer of field plates are etched. That is, the mask used for etching the field plate grooves corresponding to the first layer of field plates and the mask used for etching the contact holes are the same. Before etching, a dielectric layer is usually covered, which can be an oxide layer or a nitride layer. The upper plane of the oxide layer or nitride layer is horizontal. Therefore, the upper surface of the etched contact hole is the same as the upper surface of the field plate groove of the first layer of field plate 2081 (which is also the upper surface of the first layer of field plate 2081). The difference is that the etching stop positions are different. The etching stop position of the field plate groove of 2081 is on the first layer 2071 of the silicide blocking layer. While injecting metal into the contact holes, metal is also injected into the field plate grooves corresponding to the first layer of field plate 2081. After injecting metal, the field plate grooves form the first layer of field plate 2081.

[0034] The second to nth layers of field plates are respectively formed when different via layers are etched in sequence. The upper surfaces of the second to nth layers of field plates are respectively the same as the upper surfaces of the sequentially etched vias. "The second to nth layers of field plates are respectively formed when different via layers are etched in sequence" means that when each layer of via is etched, the field plate grooves corresponding to one layer of field plate are etched simultaneously. That is, the mask used for etching the field plate grooves corresponding to each layer of field plate and the mask used for etching each layer of via are the same. Similarly, before etching each layer of via, a dielectric layer is usually covered, which can be an oxide layer or a nitride layer. The upper plane of the oxide layer or nitride layer is horizontal. Therefore, the upper surfaces of the field plate grooves corresponding to the second to nth layers of field plates (which are also the upper surfaces of the second to nth layers of field plates) are respectively the same as the upper surfaces of the sequentially etched vias. The difference is that the etching stop positions are different. The etching stop positions of the field plate grooves of the second to nth layers are respectively on the 2nd to nth layers of the silicide blocking layer. Similarly, while injecting metal into different layers of vias, metal is also injected into the corresponding field plate grooves. After injecting metal, the field plate grooves form the second to nth layers of field plates.

[0035] There are other cases in the formation of the second to nth layer field plates: that is, one of the second to nth layer field plates is etched through a field plate groove mask plate, and the other layer field plates are respectively etched while etching different via layers through the mask plates of different via layers. The upper surface of the field plate etched through the field plate groove mask plate is the same as the upper surface of the upper layer field plate, and the upper surfaces of the other layer field plates are the same as the upper surfaces of different vias. Among them, the field plate groove mask plate is a mask plate used for the etching layer specifically for etching the field plate groove added relative to the necessary etching layers (etching layers required when no field plate is set, such as contact hole layer, via layer, metal layer, etc.) during device manufacturing, and it is a separate mask plate. "The upper surface of the field plate etched through the field plate groove mask plate is the same as the upper surface of the upper layer field plate" means that after etching the corresponding field plate groove of the upper layer field plate, metal is not injected first, and no metal layer or metal compound layer is covered. Instead, the corresponding field plate groove is etched immediately through the field plate groove mask plate, and there is no need to cover dielectric layers such as oxide layer or nitride layer again before etching. Therefore, the upper surface of the field plate etched through the field plate groove mask plate is the same as the upper surface of the upper layer field plate, and then metal is injected into both of them uniformly, and a metal layer or metal compound layer is covered.

[0036] It should be noted that Figure 2 shows a schematic diagram of the second to nth layer field plates formed by etching different via layers in sequence; if one of the second to nth layer field plates is etched through a field plate groove mask plate, and the other layer field plates are respectively etched while etching different via layers through the mask plates of different via layers, then corresponding Figure 2 in the case where 2082 is etched through the field plate groove mask plate, the upper surface of 2082 is the same as that of 2081. If 2083 is etched through the field plate groove mask plate, the upper surface of 2083 is the same as that of 2082.

[0037] Furthermore, in the embodiments of the present disclosure, the filled metal and the covered metal can be tungsten, copper, etc., and the covered metal compound can be titanium nitride TiN, tungsten silicide SiW, etc.

[0038] Furthermore, as Figure 3 shown, a top view schematic diagram of the stepped contact field plate 208 corresponding to Figure 2 is also provided. It can be seen that the three-layer field plates are arranged at intervals in the horizontal direction, as can also be seen from the Figure 2 schematic diagram. In this embodiment, the value range of the interval between each layer of the stepped contact field plate 208 is greater than or equal to 0.05 micrometers and less than or equal to 10 micrometers. In addition, each layer of the field plate also has a value range in the horizontal direction, which is greater than or equal to 0.05 micrometers and less than or equal to 10 micrometers. Furthermore, as can be seen from Figure 3 each layer of the field plate is a strip structure and is equal to the channel width in the channel width direction.

[0039] From the above description, it can be seen that in the LDMOS device with a stepped field plate according to the embodiments of the present disclosure, a stepped stepped contact field plate is formed on the silicide layer in the silicide blocking layer, and different field plate layers stay in different layers of the silicide blocking layer, which can effectively reduce the peak value of the body electric field in the reverse blocking state, and on the premise of ensuring that the breakdown voltage meets the requirements, the doping concentration of the drift region is increased as much as possible, thereby reducing the on-resistance of the device; and the field plates in the stepped contact field plate in the embodiments of the present disclosure are mainly formed by etching through the mask plate of the contact hole layer or the mask plate of the via hole layer when etching to form the contact hole layer or etching to form the via hole layer. The etching to form the contact hole layer and the etching to form the via hole layer are etching layers that are already used in the LDMOS manufacturing process. Therefore, compared with the prior art method in which a new etching layer is required for each layer of the field plate, it can be better compatible with the existing process, the manufacturing method is easier to implement, and the manufacturing cost is also reduced.

[0040] Further, as Figure 4 shown, the embodiments of the present disclosure also provide a manufacturing method for an LDMOS device with a stepped field plate, which is used to manufacture the LDMOS device with a stepped field plate in the foregoing embodiments ( Figures 2-3 ). The specific manufacturing method includes steps S301 - S305: S301. Provide a substrate; S302. Form a drift region at one end of the substrate and a body region at the other end; S303. Form a drain region in the drift region, a source region in the body region, and a gate region on the drift region and the body region; S304. Deposit a silicide blocking layer on a part of the upper surface covering the gate region and extending along the direction towards the drain region to the upper surface of the drain region, and the silicide blocking layer is composed of silicide layers of different types arranged alternately; S305. Cover a dielectric layer on the substrate formed with the silicide blocking layer; S306. Etch to form a contact hole layer through the mask plate of the contact hole layer, and at the same time, etch to form the first layer of the stepped contact field plate through the mask plate of the contact hole layer; S307. Form the remaining n - 1 layers of the stepped contact field plate, wherein different field plate layers stay in different layers of the silicide blocking layer.

[0041] In S301, the substrate ( Figure 2 201 therein) serves as the bottom layer of the LDMOS device structure. The substrate can be a silicon substrate, a silicon-germanium substrate, a III-V group element compound substrate, or other semiconductor material substrates well-known to those skilled in the art. The conductivity type of the substrate can be N-type or P-type. Preferably, in the embodiments of the present disclosure, it is P-type. After obtaining the substrate material, its surface needs to be pre-cleaned. Removing the natural oxide layer can improve the surface performance and characteristics of the material, improve the success rate of subsequent process operations, and ultimately affect the quality and performance of the product.

[0042] In S302, "forming a drift region at one end on the substrate (202 in Figure 2 ), and forming a body region at the other end (203 in Figure 2 )" specifically means: formed by ion implantation. The drift region can be P-type or N-type. If it is N-type, the implanted elements can include phosphorus and arsenic. If it is P-type, the implanted elements can include boron and boron difluoride. Preferably, the drift region in the embodiments of the present disclosure is an N-type drift region (NDRF). Preferably, the body region in the embodiments of the present disclosure is a P-type body region (PBODY), and the implanted elements include: boron, boron difluoride, phosphorus, and arsenic. The upper surface of the body region is flush with the upper surface of the drift region, and the lower surface of the body region is lower than the lower surface of the drift region.

[0043] In S303, the gate region (206 in Figure 2 ) is located horizontally between the source region (204 in Figure 2 ) and the drain region (205 in Figure 2 ). The gate region includes a gate dielectric layer (gate oxide layer) (2061 in Figure 2 ), a gate layer (2062 in Figure 2 ), and sidewalls (2063 in Figure 2 ). The gate dielectric layer can be silicon dioxide or other suitable dielectric materials. The gate layer can be polysilicon or other suitable conductive materials. The sidewalls can include one or more of a silicon dioxide layer and a silicon nitride layer. Both the source region and the drain region are formed by ion implantation.

[0044] In S304, the silicide layers of different types of materials include a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, etc. The silicide barrier layer can be selected to be alternately arranged with at least two types of silicide layers. In addition, regardless of the number of layers of the silicide barrier layer, its first layer is a silicon oxide layer. The number of layers of the silicide barrier layer is greater than or equal to the number of field plates in the stepped contact field plate. The thickness of each silicide layer in the silicide barrier layer is determined by the breakdown voltage value of the LDMOS. For specific examples, reference can be made to the relevant descriptions in the foregoing embodiments, and details are not described herein again.

[0045] Furthermore, Figures 5 to 6 shows the process of obtaining Figure 2 the deposited silicide barrier layer 207. As shown in Figure 5 , three layers of silicides (2071, 2072, 2073) will grow in sequence on the surface of the entire device, and then according to Figure 2 the final structure of 207, the unnecessary silicide parts are etched away to obtain Figure 6 the structural diagram shown. It should be noted that Figures 5-6 all the structural diagrams are taken as an example on the right side of a in Figure 2 , because Figure 2The left and right sides of a are symmetrical, so only one side needs to be described. In the subsequent steps, the right side of a is taken as an example for description as well.

[0046] S305 - S307 is the process of forming a stepped contact field plate, where S305 - S306 correspond to the formation of the first - layer field plate and there is only one way. Step S307 corresponds to the formation of the remaining n - 1 layer field plates, where n is a positive integer greater than or equal to 2. Specifically, there are three ways to implement S307. After combining these three ways with the formation of the first - layer field plate respectively, three ways of forming a stepped contact field plate are obtained.

[0047] The first way is specifically: covering a dielectric layer on the substrate with the silicide barrier layer formed; etching to form a contact hole layer through the mask of the contact hole layer, and at the same time, etching to form the first - layer field plate of the stepped contact field plate through the mask of the contact hole layer; etching to form each via - hole layer through the mask of each via - hole layer, and at the same time, etching to form the remaining n - 1 layer field plates in sequence through the mask of each via - hole layer. The second way is specifically: covering a dielectric layer on the substrate with the silicide barrier layer formed; etching to form a contact hole layer through the mask of the contact hole layer, and at the same time, etching to form the first - layer field plate of the stepped contact field plate through the mask of the contact hole layer; etching to form the second - layer field plate through the mask of the field - plate groove, where n equals 2. The third way is specifically: covering a dielectric layer on the substrate with the silicide barrier layer formed; etching to form a contact hole layer through the mask of the contact hole layer, and at the same time, etching to form the first - layer field plate of the stepped contact field plate through the mask of the contact hole layer;; selecting one field plate from the remaining n - 1 layer field plates and etching it through the mask of the field - plate groove, and etching the other n - 2 layer field plates respectively through the masks of different via - hole layers while etching different via - hole layers, where n is greater than 2.

[0048] Among the three ways, all include "etching to form the first - layer field plate through the mask of the contact hole layer", specifically: when etching the contact hole layer, etching the first - layer field - plate groove staying on the first layer of the silicide barrier layer through the mask of the contact hole layer; while filling the contact holes of the contact hole layer with metal, also filling metal in the first - layer field - plate groove to form the first - layer field plate, and then covering the first - layer metal layer or metal compound layer.

[0049] Both the first way and the third way include "etching to form the field plate through the mask of the via - hole layer", specifically: when etching the via - hole layer, etching the field - plate groove staying on the silicide layer in the silicide barrier layer through the mask of the via - hole layer; while filling the vias of the via - hole layer with metal, also filling metal in the corresponding field - plate groove to form the corresponding field plate, and covering a new - layer metal layer or metal compound layer after filling metal for each via - hole layer.

[0050] Both the second method and the third method include "forming the field plate by etching through the field plate groove mask plate", specifically: If the k-th layer field plate is the field plate formed by etching through the field plate groove mask plate, the k-th layer field plate groove is etched after etching the (k - 1)-th layer field plate groove and before covering the (k - 1)-th layer metal layer or metal compound layer. The k-th layer field plate groove and the (k - 1)-th layer field plate groove are filled with metal simultaneously through the (k - 1)-th layer contact hole or via to form the k-th layer field plate and the (k - 1)-th layer field plate, where k is a positive integer greater than or equal to 2.

[0051] Further, each layer of the stepped contact field plate needs to be coupled to any one of the source electrode, gate electrode, or drain electrode. The specific connection implementation is as follows: Each layer of the stepped contact field plate is coupled to the source contact portion 209 (as shown in Figure 2 ), or the gate contact portion 210 (as shown in Figure 2 ), or the drain contact portion 211 (as shown in Figure 2 ) of the LDMOS device of the stepped field plate through the corresponding metal layer or metal compound layer. The source contact portion is the source connection end led out from the source region, the gate contact portion is the gate connection end led out from the gate region, and the drain contact portion is the drain connection end led out from the drain region. Specifically, if the metal layer or metal compound layer covering the field plate is the first metal layer or metal compound layer, the coupling between the field plate and the source electrode, gate electrode, or drain electrode is achieved by directly connecting through the contact portion with the source electrode, gate electrode, or drain electrode of the first metal layer or metal compound layer; if the metal layer or metal compound layer covering the field plate is not the first metal layer or metal compound layer, the coupling between the field plate and the source contact portion, gate contact portion, or drain contact portion is indirectly achieved by connecting the metal layer or metal compound layer covering the field plate and the corresponding metal layer or metal compound layer of the previous layer of the field plate (i.e., the previous layer of the metal layer or metal compound layer) through the via after injecting metal.

[0052] To illustrate the above three methods more clearly, the following will be described with specific examples.

[0053] The first method, assuming n = 3:

[0054] Among them, the first layer field plate is formed by etching through the mask plate of the contact hole layer as shown in Figures 7-11 . It includes: First, after obtaining the structure through step S304, a dielectric layer is covered on the substrate with the silicide blocking layer, that is, a dielectric layer 212 (oxide layer or nitride layer) grows on the silicide blocking layer 207 to obtain the structure as shown in Figure 6 ; Second, the dielectric layer 212 is etched through the mask plate of the contact hole layer to obtain the contact hole 213 and the first layer field plate groove 214, and the structure as shown in Figure 7 is obtained; Third, the contact hole 213 and the first layer field plate groove 214 are filled with metal simultaneously to form the first layer field plate, and the structure as shown in Figure 8The structure shown, where the contact holes 213 include contact holes corresponding to the source, gate, and drain respectively, and the first field plate groove 214 is a groove or hole corresponding to the first field plate 2081. It should be noted that in the embodiments of the present disclosure, a mask corresponding to the contact hole layer is used to etch the groove or hole of the first field plate 2081. Therefore, the mask corresponding to the contact hole layer needs to be correspondingly improved according to the position of the groove or hole of the first field plate 2081, so that the position of the etched first field plate groove 214 satisfies the first boundary line ( Figure 2 in which is a straight line inward from point A) in the gate region 206 to be coplanar with the side surface of the gate layer 2062 close to the drain region 205, and the etching stop position is on the first layer 2071 of the silicide blocking layer 207. Third, for Figure 8 the contact holes 213 and the first field plate groove 214 in, metal (which can be tungsten, copper, etc.) is injected to obtain the structure as shown in Figure 9 After injecting metal into the contact holes corresponding to the source, gate, and drain, the source contact portion 209, gate contact portion 210, and drain contact portion 211 are obtained. After injecting metal into the first field plate groove 214, the first field plate 2081 is obtained; Fourth, a metal layer 215 (which can be metal (tungsten, copper, etc.) or a metal compound layer 215 (TiN, SiW, etc.)) is grown (covered) on the dielectric layer 212 to obtain the structure as shown in Figure 10 ; Fifth, the metal layer 215 or the metal compound layer 215 is etched to obtain the structure as shown in Figure 11 . It should be noted that in this embodiment, when etching the 215 layer, in addition to retaining the metal or metal compound on each electrode contact portion, the first field plate 2081 also needs to be connected to the contact portion of one of the electrodes. Figure 11 The figure shows a schematic diagram of connecting to the gate contact portion 210. The following two methods are also described by taking the connection to the gate contact portion 210 as an example. In actual applications, it can also be connected to the contact portion 209 of the source or the contact portion 211 of the drain according to actual needs.

[0055] Among them, the remaining two layers of field plates are sequentially etched and formed through the mask of each layer of via hole layer as shown in Figures 12-15 . The process includes: First, a dielectric layer 216 (oxide layer or nitride layer) is grown on the etched metal layer 215 or metal compound layer 215 to obtain the structure as shown in Figure 12 ; Second, the dielectric layer 216 of this layer is etched through the mask of the first layer of via hole layer to obtain the first layer of via holes 217 and the second field plate groove 218, and metal is injected into the first layer of via holes 217 and the second field plate groove 218 to obtain the structure as shown in Figure 13For the structure shown, after the second field plate groove 218 is implanted with metal, the second field plate 2082 is formed; it should be noted that in the embodiments of the present disclosure, the mask corresponding to the first via layer is used to etch the grooves or holes of the second field plate 2082. Therefore, the mask corresponding to the first via layer needs to be correspondingly improved according to the positions of the grooves or holes of the second field plate 2082, so that the position of the second field plate groove 218 satisfies that the interval from the first field plate is greater than or equal to 0.05 micrometers and less than or equal to 10 micrometers, and the etching stop position is on the second layer 2072 of the silicide blocking layer; third, a metal layer 219 or a metal compound layer 219 is grown (covered) on the dielectric layer 216, and 219 is etched to obtain as Figure 14 For the structure, it should be noted that when etching the metal layer 219 or the metal compound layer 219 in this embodiment, in addition to the vias 217 and the metal or metal compound on the second field plate being retained, the second field plate 2082 and the first field plate 2081 need to be connected through the metal layer 219 or the metal compound layer 219, so that the contact parts (209 or 210 or 211) where the second field plate 2082 is indirectly connected to the first field plate 2081 are connected. Fourth, referring to the process of forming the second field plate 2082, the above three steps are repeated (covering the dielectric layer 220, etching the second via 221 and the third field plate groove 222 and implanting metal to obtain the third field plate 2083, covering the metal layer 223 or the metal compound layer 223 and etching) to obtain Figure 15 For the structure shown, it should be noted that the etching stop position of the third field plate 2083 is on the third layer 2073 of the silicide blocking layer, and the third field plate 2083 and the second field plate 2082 are connected through the metal layer 223 or the metal compound layer 223, so that the contact parts (209 or 210 or 211) where the third field plate 2083 is indirectly connected to the first field plate 2081 are connected.

[0056] Finally, after Figure 15 For the structure shown, that is, after all the required field plates are fabricated, a dielectric layer 224 still needs to be covered and etched to expose the metal or metal compound part remaining after etching the last metal layer 223 or metal compound layer 223 for convenient connection to the outside, to obtain the final LDMOS structure as shown in Figure 16 shown.

[0057] The second method:

[0058] The second method only includes two layers of field plates. The first field plate is also formed by etching through the mask of the contact hole layer. Except that the number of layers of the silicide blocking layer can be greater than or equal to 2, the process before obtaining the first field plate groove is the same as the first method, that is Figure 8 And before that is the same as the first method. At Figure 8After that, in the second method, instead of immediately injecting metal to cover the metal layer 215 or the metal compound layer 215, the second-layer field plate trench 218 is first etched in the dielectric layer 212 through the field plate trench mask plate. Then, metal is uniformly injected into the contact hole 213, the first-layer field plate trench 214, and the second-layer field plate trench 218, and then the metal layer 215 or the metal compound layer 215 is covered. After that, the layer 215 is etched. In the second method, etching the metal layer 215 or the metal compound layer 215 needs to satisfy the connection of the first-layer field plate 2081, the second-layer field plate 2082, and a certain pole contact part (the gate contact part 210 shown) through the layer 215. After the etching of the metal layer 215 or the metal compound layer 215 is completed, the dielectric layer 216 is covered, and then the first-layer through hole 217 is etched, metal is injected, the metal layer 219 or the metal compound layer 219 is covered, the layer 219 is etched, the dielectric layer 220 is covered, the second-layer through hole 221 is etched, metal is injected, the metal layer 223 or the metal compound layer 223 is covered, the 223 is etched, the dielectric layer 224 is covered, and the dielectric layer 224 is etched, and finally, the LDMOS structure diagram as shown in Figure 17 is obtained.

[0059] In the third method, assuming n = 3:

[0060] Compared with the first method, in the third method, the first-layer field plate 2081 is also formed by etching through the mask plate of the contact hole layer. One of the latter two-layer field plates is formed by etching through the field plate trench mask plate, and the remaining one is formed by etching through the mask plate corresponding to the through hole layer.

[0061] Suppose the second-layer field plate 2082 is formed by etching through the mask plate corresponding to the through hole layer, and the third-layer field plate is formed by etching through the field plate trench mask plate. Then, the steps up to and including obtaining the second-layer field plate trench are the same as those in the first method. After obtaining the second-layer field plate trench 218, instead of immediately injecting metal to cover the metal layer 219 or the metal compound layer 219, the third-layer field plate trench 222 is first etched in the dielectric layer 216 through the field plate trench mask plate. Then, metal is uniformly injected into the first-layer through hole 217, the second-layer field plate trench 218, and the third-layer field plate trench 222, and then the metal layer 219 or the metal compound layer 219 is covered. After that, the layer 219 is etched. The etching needs to satisfy the connection of the second-layer field plate 2082, the third-layer field plate 2083, and the first-layer field plate 2081 through the metal layer 219 or the metal compound layer 219. After the etching of the metal layer 219 or the metal compound layer 219 is completed, the dielectric layer 220 is covered, and then the second-layer through hole 221 is etched, metal is injected, the metal layer 223 or the metal compound layer 223 is covered, the 223 layer is etched, the dielectric layer 224 is covered, and the dielectric layer 224 is etched, and finally, the LDMOS structure diagram as shown in Figure 18 is obtained.

[0062] Suppose the second-layer field plate 2082 is formed by etching through a field plate groove mask plate, and the third-layer field plate 2083 is formed by etching through a mask plate corresponding to the via layer. Except that the number of layers of the silicide blocking layer 207 is greater than or equal to 3, the steps before covering the dielectric layer 216 are the same as those in the second method. After covering the dielectric layer 216, the first-layer vias 217 and the third-layer field plate grooves 222 are etched, and metal is implanted into the first-layer vias 217 and the third-layer field plate grooves 222 to obtain the third-layer field plate 2083. Then, a metal layer 219 or a metal compound layer 219 is covered, and the 219 layer is etched. The etching of the 219 layer also needs to satisfy the connection of the third-layer field plate 2083 to the second-layer field plate 2082. Then, a dielectric layer 220 is covered, the second-layer vias 221 are etched, and metal is implanted. A metal layer 223 or a metal compound layer 223 is covered, the 223 layer is etched, a dielectric layer 224 is covered, and the dielectric layer 224 is etched. Finally, the LDMOS structure diagram as shown in Figure 19 is obtained.

[0063] For the above three methods, the first method does not require a new etching layer and is the simplest to implement. Although the second method and the third method require one new etching layer and are not as simple as the first method, compared with the prior art, the method that each layer of field plate requires a new etching layer is also much simpler. From the above description, it can be seen that in the LDMOS device with a stepped field plate according to the embodiments of the present disclosure, different field plate layers form a stepped shape and stay in different layers of the silicide blocking layer respectively, which can effectively reduce the peak value of the body electric field in the reverse blocking state, and can increase the doping concentration of the drift region as much as possible on the premise of ensuring that the breakdown voltage meets the requirements, thereby reducing the on-resistance of the device; and without adding a new etching layer or only adding one etching layer, combined with the contact holes and the etching layers of each layer of vias that are already used in the manufacturing process, a multi-layer stepped field plate can be formed, which can be well compatible with the existing process and is easier to manufacture.

[0064] In the above embodiments of the present disclosure, the descriptions of the respective embodiments have their own emphases. For parts not detailed in a certain embodiment, reference may be made to the relevant descriptions of other embodiments.

[0065] Unless otherwise explicitly specified in the context, the singular forms of the words used in this specification and the appended claims include the plural, and vice versa. Thus, when referring to the singular, the corresponding plural is usually included. Similarly, the terms "comprising" and "including" will be interpreted as inclusive rather than exclusive. Likewise, the terms "including" and "or" should be interpreted as inclusive, unless such an interpretation is explicitly prohibited in this specification. Where the term "example" is used in this specification, especially when it is located after a group of terms, the "example" is merely exemplary and illustrative and should not be considered exclusive or extensive.

[0066] Further aspects and scope of adaptability will become apparent from the description provided herein. It should be understood that various aspects of the present disclosure may be implemented alone or in combination with one or more other aspects. It should also be understood that the description and specific embodiments herein are for illustrative purposes only and are not intended to limit the scope of the present disclosure.

[0067] The above has described several embodiments of the present disclosure in detail. However, it is obvious that those skilled in the art can make various modifications and variations to the embodiments of the present disclosure without departing from the spirit and scope of the present disclosure. The protection scope of the present disclosure is defined by the appended claims.

Claims

1. A manufacturing method of an LDMOS device with a stepped field plate, characterized in that The method includes: providing a substrate; forming a drift region at one end on the substrate and a body region at the other end, the upper surface of the body region being flush with the upper surface of the drift region, and the lower surface of the body region being lower than the lower surface of the drift region; forming a drain region in the drift region, a source region in the body region, and a gate region on the drift region and the body region, the gate region being horizontally located between the source region and the drain region; depositing a silicide blocking layer on a part of the upper surface covering the gate region and extending along the direction towards the drain region to the upper surface of the drain region, the silicide blocking layer being composed of silicide layers of different types arranged alternately; covering a dielectric layer on the substrate formed with the silicide blocking layer; forming a contact hole layer by etching through a mask of the contact hole layer, and simultaneously forming a first layer of the stepped contact field plate by etching through the mask of the contact hole layer; forming the remaining n - 1 layers of the stepped contact field plate, where different field plate layers stay in different layers of the silicide blocking layer, and n is a positive integer greater than or equal to 2.

2. The manufacturing method of the LDMOS device with a stepped field plate according to claim 1, characterized in that, Forming the remaining n - 1 layers of the stepped contact field plate includes: forming each layer of the via hole layer by etching through a mask of each layer of the via hole layer, and simultaneously etching to form the remaining n - 1 layers of the field plate in sequence through the mask of each layer of the via hole layer.

3. The manufacturing method of the LDMOS device with a stepped field plate according to claim 1, characterized in that, Forming the remaining n - 1 layers of the stepped contact field plate includes: forming a second layer of the field plate by etching through a mask of the field plate groove, where n is equal to 2; or, Forming the remaining n - 1 layers of the stepped contact field plate includes: selecting one field plate from the remaining n - 1 layers of the field plate and forming it by etching through a mask of the field plate groove, and forming the other n - 2 layers of the field plate by etching through masks of different via hole layers while etching different via hole layers, where n is greater than 2.

4. The manufacturing method of the LDMOS device with a stepped field plate according to claim 2 or 3, characterized in that, The forming of the first layer of the stepped contact field plate by etching through the mask of the contact hole layer includes: when etching the contact hole layer, etching a first layer of the field plate groove staying on the first layer of the silicide blocking layer through the mask of the contact hole layer; when filling metal into the contact holes of the contact hole layer, also filling metal into the first layer of the field plate groove to form the first layer of the field plate, and then covering a first layer of metal layer or metal compound layer; Forming a field plate by etching through a mask of the via hole layer includes: when etching the via hole layer, etching a field plate groove staying on the silicide layer in the silicide blocking layer through the mask of the via hole layer; when filling metal into the vias of the via hole layer, also filling metal into the corresponding field plate groove to form the corresponding field plate, and covering a new layer of metal layer or metal compound layer after filling metal into each layer of the via hole layer.

5. The manufacturing method of the LDMOS device with a stepped field plate according to claim 4, characterized in that, If the k-th layer of the field plate is formed by etching through a mask of the field plate groove, then forming a field plate by etching through a mask of the field plate groove includes: The k-th field plate groove is etched after etching the (k - 1)-th field plate groove and before covering the (k - 1)-th metal layer or metal compound layer. The k-th field plate groove and the (k - 1)-th field plate groove are filled with metal simultaneously through the (k - 1)-th contact hole or via hole to form the k-th field plate and the (k - 1)-th field plate, where k is a positive integer greater than or equal to 2.

6. The manufacturing method of the LDMOS device with a stepped field plate according to claim 5, characterized in that, The field plates in the stepped contact field plate are coupled to the source contact part or gate contact part or drain contact part of the LDMOS device of the stepped field plate through the corresponding metal layer or metal compound layer. The source contact part is the source connection end led out from the source region, the gate contact part is the gate connection end led out from the gate region, and the drain contact part is the drain connection end led out from the drain region.

7. A LDMOS device with a stepped field plate, characterized in that, The LDMOS device includes a substrate, a drift region, a body region, a source region, a drain region, a gate region, a silicide blocking layer, and a stepped contact field plate. Among them, the substrate is the bottom layer of the LDMOS device. One end above the substrate is the drift region, and the other end is the body region. The upper surface of the body region is the same as the upper surface of the drift region, and the lower surface of the body region is lower than the lower surface of the drift region. The source region is located in the body region, the drain region is located in the drift region, the gate region is located above the body region and the drift region, and in the horizontal direction, the gate region is located between the source region and the drain region. The silicide blocking layer is composed of silicide layers of different types arranged alternately, covers a part of the upper surface of the gate region, and extends along the direction towards the drain region to the upper surface of the drain region. The stepped contact field plate is formed by n field plates arranged in a stepped manner on the silicide layer in the silicide blocking layer. Different field plate layers stay in different layers of the silicide blocking layer. The surface of the first field plate is the same as the upper surface of the etched contact hole. The upper surfaces of the second to n-th field plates are respectively the same as the upper surfaces of the etched contact holes or vias, where n is a positive integer greater than or equal to 2.

8. The LDMOS device with a stepped field plate according to claim 7, characterized in that, The number of layers of the stepped field plate is set according to the breakdown voltage value of the LDMOS device. The first boundary line of the first field plate on the side close to the source region is coplanar with the side of the gate layer in the gate region close to the drain region.

9. The LDMOS device with a stepped field plate according to claim 7, wherein The number of layers of the silicide blocking layer is greater than or equal to the number of layers of the field plates in the stepped contact field plate. The first layer of the silicide blocking layer is a silicon oxide layer, and the thickness of each silicide layer in the silicide blocking layer is set respectively according to the breakdown voltage value of the LDMOS device.

10. The LDMOS device with a stepped field plate according to claim 7, wherein, The n field plates are arranged at intervals in the horizontal direction. The value range of the interval between the field plates in the stepped contact field plate is greater than or equal to 0.05 micrometers and less than or equal to 10 micrometers.

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