Semiconductor structure and forming method thereof

Abstract

The invention provides a semiconductor structure and a forming method thereof, and the forming method comprises the steps: providing a substrate; forming a plurality of epitaxial layers on the substrate; forming a gate structure which penetrates through part or all of the epitaxial layer and is in contact with part or all of the epitaxial layer; wherein each epitaxial layer has respective doping type and doping concentration. By adopting the technical scheme, the influence of a short-channel effect can be reduced while the size of the conducting channel is reduced, and the balance between the size of the conducting channel and the short-channel effect is achieved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular, to a semiconductor structure and a method for forming the same. Background Art

[0002] With the improvement of integrated circuit manufacturing processes, semiconductor processes have been continuously miniaturized, the technology nodes have been continuously reduced, and the sizes of devices have been continuously reduced. As the sizes of devices are continuously reduced, the sizes of gate structures become smaller and smaller, resulting in shorter and shorter conductive channels under the gate structures.

[0003] Currently, to adapt to the rapid changes in technology nodes, advanced lithography machines are usually used, for example, EUV (Extreme Ultra-violet) lithography machines, to perform patterning processes.

[0004] However, due to the limitations of lithography machines, the sizes of conductive channels cannot meet the process requirements, and blindly reducing the channel size will cause short-channel effects, affecting the device quality.

[0005] Under this background, how to provide technical solutions to reduce the size of conductive channels while reducing the influence of short-channel effects has become a technical problem that needs to be urgently solved by those skilled in the art. Summary of the Invention

[0006] In view of this, the present invention provides a semiconductor structure and a method for forming the same, which can reduce the size of a conductive channel while reducing the influence of short-channel effects, and achieve a balance between the size of the conductive channel and short-channel effects.

[0007] The present invention provides a method for forming a semiconductor structure, including: providing a substrate; forming a multi-layer epitaxial layer on the substrate; forming a gate structure that penetrates through part or all of the epitaxial layers and contacts part or all of the epitaxial layers; wherein each epitaxial layer has its own doping type and doping concentration.

[0008] Optionally, each epitaxial layer is formed by an epitaxial process, and doping treatment is performed during the epitaxial growth process;

[0009] Among them, in any two adjacent epitaxial layers, the upper epitaxial layer is based on the top surface of the lower epitaxial layer for growth, and the bottommost epitaxial layer is based on the top surface of the substrate for growth.

[0010] Optionally, the formation temperature of each epitaxial layer is between 600 degrees Celsius and 800 degrees Celsius.

[0011] Optionally, the formation parameters of each epitaxial layer further include: the pressure is from 70 Torr to 90 Torr, the flow rate of Purge MainH2 is from 3200 sccm to 3800 sccm, the flow rate of Purge SlitH2 is from 80 sccm to 120 sccm, the flow rate of the silicon source gas is from 120 sccm to 180 sccm, and the epitaxial rate is at least one of from 200 angstroms per minute to 300 angstroms per minute.

[0012] Optionally, the number of the epitaxial layers is greater than or equal to 3, and satisfies at least one or more of the following:

[0013] A first epitaxial layer, which is used to form a first source / drain doping layer;

[0014] A second epitaxial layer, which is used to form a channel layer;

[0015] A third epitaxial layer, which is used to form a second source / drain doping layer.

[0016] Optionally, the first source / drain doping layer is one of the source electrode or the drain electrode, and the second source / drain doping layer is the other of the source electrode or the drain electrode.

[0017] Optionally, the first source / drain doping layer and / or the second source / drain doping layer satisfy at least one or more of the following:

[0018] The doping type of the first source / drain doping layer is different from the doping type of the channel layer;

[0019] The doping concentration of the first source / drain doping layer is greater than the doping concentration of the channel layer;

[0020] The doping type of the second source / drain doping layer is different from the doping type of the channel layer;

[0021] The doping concentration of the second source / drain doping layer is greater than the doping concentration of the channel layer.

[0022] Optionally, the epitaxial layer in contact with the gate structure includes the channel layer.

[0023] Optionally, the first source / drain doping layer and / or the second source / drain doping layer satisfy at least one or more of the following:

[0024] The doping concentration of the first source / drain doping layer is 10 times to 100 times the doping concentration of the channel layer;

[0025] The doping concentration of the first source / drain doping layer is 10 times to 100 times the doping concentration of the channel layer.

[0026] Optionally, the method for forming the semiconductor structure satisfies at least one or more of the following:

[0027] The thickness of the first source / drain doping layer is 500 angstroms to 1000 angstroms;

[0028] The doping concentration of the first source / drain doping layer is 1E 14 atom / cm 3 to 1E 15 atom / cm 3 ;

[0029] The thickness of the second source / drain doping layer is 500 angstroms to 1000 angstroms;

[0030] The doping concentration of the second source / drain doping layer is 1E 14 atom / cm 3 to 1E 15 atom / cm 3 ;

[0031] The thickness of the channel layer is 10 nanometers to 50 nanometers;

[0032] The doping concentration of the channel layer is 1E 12 atom / cm 3 to 1E 13 atom / cm 3 。

[0033] Optionally, the step of forming the gate structure includes: forming a first trench that penetrates part or all of the epitaxial layer, and the sidewalls of the penetrated epitaxial layer are exposed by the first trench; forming a gate material layer on the topmost epitaxial layer, and the gate material layer fills the first trench; removing the gate material layer that is higher than the topmost epitaxial layer, and using the gate material layer remaining in the first trench as the gate structure.

[0034] Optionally, the step of forming the gate structure further includes: forming a gate oxide layer on the topmost epitaxial layer, and the sidewalls and bottom of the first trench are covered by the gate oxide layer;

[0035] The gate structure also covers the gate oxide layer.

[0036] Optionally, the method for forming the semiconductor structure satisfies at least one or more of the following:

[0037] For each epitaxial layer in part or all of the epitaxial layers, form at least one first conductive structure, and each first conductive structure is electrically connected to the corresponding epitaxial layer;

[0038] Form a second conductive structure, and the second conductive structure is electrically connected to the gate structure.

[0039] Optionally, the step of forming at least one first conductive structure includes: forming a second trench that at least exposes a partial sidewall of the epitaxial layer electrically connected to the first conductive structure; forming an insulating layer on the sidewalls of the second trench; forming a first conductive plug at least in the remaining space of the second trench, the first conductive plug being electrically connected to the epitaxial layer, and the first conductive plug and the insulating layer serving as the first conductive structure.

[0040] Optionally, when the epitaxial layer electrically connected to the first conductive structure is the topmost epitaxial layer, the second trench only exposes a partial sidewall of the epitaxial layer;

[0041] When the epitaxial layer electrically connected to the first conductive structure is not the topmost epitaxial layer, the second trench exposes a partial sidewall of the epitaxial layer and the sidewalls of other epitaxial layers located on the epitaxial layer.

[0042] Correspondingly, the present invention further provides a semiconductor structure, including: a substrate; a plurality of epitaxial layers located on the substrate, and each epitaxial layer has its own doping type and doping concentration; a gate structure that penetrates through part or all of the epitaxial layers and contacts the sidewalls of part or all of the epitaxial layers.

[0043] Optionally, the number of the epitaxial layers is greater than or equal to 3, and satisfies at least one or more of the following:

[0044] A first epitaxial layer that serves as a first source / drain doping layer;

[0045] A second epitaxial layer that serves as a channel layer;

[0046] A third epitaxial layer that serves as a second source / drain doping layer.

[0047] Optionally, the first source / drain doping layer is one of the source or the drain, and the second source / drain doping layer is the other of the source or the drain.

[0048] Optionally, the semiconductor structure satisfies at least one or more of the following:

[0049] The doping type of the first source / drain doping layer is different from the doping type of the channel layer;

[0050] The doping concentration of the first source / drain doping layer is greater than the doping concentration of the channel layer;

[0051] The doping type of the second source / drain doping layer is different from the doping type of the channel layer;

[0052] The doping type of the second source / drain doping layer is greater than the doping concentration of the channel layer.

[0053] Optionally, the semiconductor structure satisfies at least one or more of the following:

[0054] The doping concentration of the first source / drain doping layer is 10 to 100 times that of the channel layer;

[0055] The doping concentration of the first source / drain doping layer is 10 to 100 times that of the channel layer.

[0056] Optionally, the semiconductor structure satisfies at least one or more of the following:

[0057] The thickness of the first source / drain doping layer is 500 angstroms to 1000 angstroms;

[0058] The doping concentration of the first source / drain doping layer is 1E 14 atom / cm 3 to 1E 15 atom / cm 3 ;

[0059] The thickness of the second source / drain doping layer is 500 angstroms to 1000 angstroms;

[0060] The doping concentration of the second source / drain doping layer is 1E 14 atom / cm 3 to 1E 15 atom / cm 3 ;

[0061] The thickness of the channel layer is 10 nanometers to 50 nanometers;

[0062] The doping concentration of the channel layer is 1E 12 atom / cm 3 to 1E 13 atom / cm 3 .

[0063] Optionally, the semiconductor structure further includes:

[0064] At least one first conductive structure, which is electrically connected to the corresponding epitaxial layer;

[0065] Form a second conductive structure, which is electrically connected to the gate structure.

[0066] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0067] In the method for forming a semiconductor structure provided by the present invention, a multi-layer epitaxial layer is formed on a substrate. By arranging along the normal direction of the substrate, the size of the epitaxial layer can be reduced, without being limited by a lithography machine, and the formed epitaxial layer has better doping density and uniformity through epitaxial growth. In this way, when at least one of the epitaxial layers is used as a channel layer, the influence of the short-channel effect can be reduced, so as to reduce the influence of the short-channel effect while reducing the size of the conductive channel, and a balance is achieved between the size of the conductive channel and the short-channel effect.

[0068] In the semiconductor structure provided by the present invention, a multi-layer epitaxial layer is located on a substrate. By arranging along the normal direction of the substrate, the size of the epitaxial layer can be reduced, without being limited by a lithography machine, and the epitaxial layer has better doping density and uniformity. In this way, when at least one of the epitaxial layers is used as a channel layer, the influence of the short-channel effect can be reduced, so as to reduce the influence of the short-channel effect while reducing the size of the conductive channel, and a balance is achieved between the size of the conductive channel and the short-channel effect. Brief Description of the Drawings

[0069] Figure 1 A schematic structural diagram of a semiconductor structure is shown;

[0070] Figures 2 to 17 Schematic structural diagrams corresponding to each step in an embodiment of the method for forming the semiconductor structure of the present invention are shown. Detailed Description of the Embodiments

[0071] As can be seen from the background art, as the device size continues to shrink, the size of the gate structure becomes smaller and smaller, making the conductive channel under the gate structure shorter and shorter. However, blindly reducing the channel size will cause the short-channel effect.

[0072] Refer to Figure 1 A schematic structural diagram of a semiconductor structure shown, as Figure 1 shown, the semiconductor structure includes: a substrate 10; a gate structure 20, located on the substrate 10; source / drain doping layers 30, located in the substrate 10 on both sides of the gate structure 20, and the gate structure 20 exposes the source / drain doping layers 30.

[0073] In Figure 1 the structure shown, the size of the gate structure 20 determines the length L of the conductive channel, and the size of the gate structure 20 is jointly defined by lithography and etching.

[0074] On the one hand, due to the limitations of lithography machines and etching processes, it is impossible to further reduce the size of the gate structure 20. On the other hand, as the size of the gate structure 20 decreases, the distance between the source-drain doping layers 30 on both sides of the gate structure 20 continues to decrease, and the contact area between the gate structure 20 and the source-drain doping layers 30 becomes smaller and smaller. As a result, the ability of the gate structure 20 to control the channel deteriorates, and it becomes more and more difficult for the gate voltage to pinch off the channel, leading to the phenomenon of subthreshold leakage, that is, the so-called short-channel effect is more likely to occur.

[0075] To solve the above technical problems, the present invention provides a method for forming a semiconductor structure, including: providing a substrate; forming a multi-layer epitaxial layer on the substrate; forming a gate structure that penetrates part or all of the epitaxial layer and contacts part or all of the epitaxial layer; wherein each epitaxial layer has its own doping type and doping concentration.

[0076] By using the semiconductor structure provided by the present invention and arranging it along the normal direction of the substrate, the size of the epitaxial layer can be reduced without being limited by the lithography machine, and the formed epitaxial layer has better doping density and uniformity through epitaxial growth. In this way, when at least one of the epitaxial layers is used as the channel layer, the influence of the short-channel effect can be reduced, so as to reduce the influence of the short-channel effect while reducing the size of the conductive channel, and a balance can be achieved between the size of the conductive channel and the short-channel effect.

[0077] To make the above objects, features, and advantages of the present invention more obvious and understandable, the present invention will be described by way of examples with reference to the accompanying drawings.

[0078] Figures 2 to 17 FIG. is a schematic structural diagram corresponding to each step in an embodiment of the method for forming a semiconductor structure of the present invention, where Figure 17 is a top-view structural diagram of a semiconductor structure in an embodiment of the present invention, Figure 10 and Figure 11 is Figure 17 a cross-sectional view along the A-A1 direction, Figure 12 and Figure 13 is Figure 17 a cross-sectional view along the C-C1 direction, Figure 14 and Figure 15 is Figure 17 a cross-sectional view along the B-B1 direction, Figure 16 is Figure 17 a cross-sectional view along the D-D1 direction.

[0079] Referring to Figure 2 , a substrate 100 is provided.

[0080] The substrate 100 can provide a process operation basis for the formation process of the semiconductor structure.

[0081] In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium arsenide, etc. The substrate can also be other types of substrates such as a silicon-on-insulator substrate or a germanium-on-insulator substrate. The material of the substrate can be a material suitable for process requirements or easy to integrate.

[0082] The semiconductor substrate can also be a silicon-on-insulator structure, such as silicon-on-insulator (SOI), and can also be a germanium-on-insulator structure, such as germanium-on-insulator; the semiconductor substrate can also include an alloy semiconductor structure, such as GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or a combination thereof; the semiconductor substrate can also be a lightly doped substrate or a substrate with an epitaxial layer grown thereon.

[0083] It should be noted that the substrate 100 can also be removed during subsequent formation processes.

[0084] See Figures 3 to 5 , and a multi-layer epitaxial layer is formed on the substrate 100.

[0085] The epitaxial layer provides a process basis for the formation of film layers such as a channel layer and a source / drain doping layer. Or rather, the epitaxial layer can be a film layer structure with different or the same functions in a semiconductor structure.

[0086] In this embodiment, each epitaxial layer is formed by an epitaxial process, and doping treatment is performed during the epitaxial growth process.

[0087] In other words, when forming any epitaxial layer, doping operations are performed while the epitaxial process is being carried out. On the one hand, the process parameters of the epitaxial process are controllable, and epitaxial layers with different thicknesses can be formed, thereby reducing the thickness of some or all of the epitaxial layers; on the other hand, by synchronously performing the epitaxial process and doping operations, the epitaxial layer formed by epitaxial growth has better doping density and uniformity, improving the uniformity of the doping concentration at different positions of the same epitaxial layer, which is beneficial to reducing the short-channel effect.

[0088] In this embodiment, the epitaxial process can include an atomic layer deposition process or a molecular beam epitaxy process.

[0089] In this embodiment, when forming each epitaxial layer by an epitaxial process, among any two adjacent epitaxial layers, the upper epitaxial layer uses the top surface of the lower epitaxial layer as the growth basis, and the bottommost epitaxial layer uses the top surface of the substrate 100 as the growth basis.

[0090] In other words, the top surface of the substrate 100 serves as the initial growth basis for the entire semiconductor structure. The first epitaxial layer uses the top surface of the substrate 100 as the growth basis, and for subsequent formed epitaxial layers, the top surface of the previous epitaxial layer serves as the growth basis.

[0091] Moreover, in this solution, the surface of the substrate 100 is relatively flat, making the surface of the first epitaxial layer flat. On this basis, the surface of any epitaxial layer is relatively flat, reducing the resistance at the interface between the epitaxial layer and the substrate 100, as well as the resistance at the interface between adjacent epitaxial layers, and improving the electrical performance of the semiconductor structure.

[0092] In this embodiment, for any epitaxial layer, the forming step may include: successively forming a plurality of sub-epitaxial layers, and doping treatment is performed in the step of forming any one sub-epitaxial layer. Among them, in the steps of each sub-epitaxial layer, the doping type and doping concentration are the same, so as to further improve the doping uniformity of the epitaxial layer.

[0093] In this embodiment, each epitaxial layer has its own doping type, so that the doping type between adjacent epitaxial layers can be controlled. Among the three epitaxial layers, the doping type of the middle epitaxial layer is different from that of the upper and lower epitaxial layers. In this way, an epitaxial structure with a conductive channel can be formed through the three epitaxial layers with the above doping characteristics, so as to enhance the control ability of the gate structure.

[0094] In this embodiment, the doping concentration of the epitaxial layer directly affects parameters such as the conductivity and carrier mobility of the semiconductor structure. Therefore, based on actual requirements, the doping concentration of each epitaxial layer can be set so that each epitaxial layer has its own doping concentration, that is, different epitaxial layers have the same or different doping concentrations.

[0095] In practical applications, the inventor further found that under the action of temperature, there is a diffusion phenomenon between adjacent epitaxial layers, and the higher the temperature, the more serious the diffusion phenomenon. Driven by the diffusion effect, the doping ions between adjacent epitaxial layers will undergo a transfer phenomenon, which will change the characteristics of some or all of the epitaxial layers, significantly reducing the performance of the semiconductor structure, or the semiconductor structure cannot play its intended role.

[0096] As an example, if the doping concentrations of adjacent epitaxial layers are different, due to the diffusion phenomenon, the doping concentration of the epitaxial layer with a high doping concentration may become lower, while the doping concentration of the epitaxial layer with a low doping concentration may increase.

[0097] As another example, if the doping types of adjacent epitaxial layers are different, due to the diffusion phenomenon, the doping types of these two epitaxial layers may become the same, and the semiconductor structure fails.

[0098] In this embodiment, each epitaxial layer is formed in a low-temperature environment.

[0099] In some embodiments, the forming temperature of each epitaxial layer is between 600 degrees Celsius and 800 degrees Celsius. For example, 650 degrees Celsius, 700 degrees Celsius, and 750 degrees Celsius, etc.

[0100] That is, the formation temperature of any epitaxial layer is not higher than 800 degrees Celsius, so that when forming the second and subsequent epitaxial layers, diffusion phenomena are reduced or avoided, enabling each epitaxial layer to maintain its own characteristics and improving the performance of the semiconductor structure.

[0101] It should be noted that, in order to further reduce the influence of temperature, the epitaxial layer, gate structure, and film layers related to the gate structure in this solution are all formed using a process with a temperature not higher than 800 degrees Celsius.

[0102] In addition, the formation parameters of each epitaxial layer may further include: a pressure of 70 Torr to 90 Torr, a flow rate of Purge MinH2 of 3200 sccm to 3800 sccm, a flow rate of Purge SlitH2 of 80 sccm to 120 sccm, a flow rate of silicon source gas of 120 sccm to 180 sccm, and an epitaxial rate of at least one of 200 angstroms per minute to 300 angstroms per minute.

[0103] In other words, by changing the formation temperature of the first epitaxial layer, the aforementioned at least one parameter is adaptively adjusted, enabling the silicon source gas used in the epitaxial process to be adapted to the current temperature, and by reducing the epitaxial rate per unit time, the thickness uniformity of the same epitaxial layer can be improved, and the formation quality of the epitaxial layer can be enhanced. That is, while reducing the generation temperature, the epitaxial rate also decreases accordingly.

[0104] In this embodiment, the number of epitaxial layers is greater than or equal to 3. By making the number of epitaxial layers greater than or equal to 3, at least a source electrode, a drain electrode, and a channel layer located between the source electrode and the drain electrode can be formed to function as a current flow path.

[0105] In this embodiment, when the number of epitaxial layers is greater than or equal to 3, the formation method of the semiconductor structure in this solution can satisfy:

[0106] A first epitaxial layer, which is used to form a first source / drain doping layer.

[0107] The first source / drain doping layer can be used as the source electrode or drain electrode of a field-effect transistor. When the field-effect transistor is operating, the first source / drain doping layer can be used to provide a carrier source.

[0108] In this embodiment, when forming an NMOS transistor, the first epitaxial layer may include an epitaxial layer doped with N-type ions, and the material of the first epitaxial layer may be Si or SiC, or other materials adapted to the substrate material; when forming a PMOS transistor, the first epitaxial layer may include an epitaxial layer doped with P-type ions, and the material of the first epitaxial layer is Si or SiGe, or other materials adapted to the substrate material.

[0109] In a specific embodiment, the material of the first epitaxial layer may be Si.

[0110] A second epitaxial layer for forming a channel layer.

[0111] The channel layer is used to provide a flow region for the carrier source.

[0112] In this embodiment, when forming an NMOS transistor, the second epitaxial layer may include an epitaxial layer doped with P-type ions, and the material of the second epitaxial layer may be Si or SiGe, or other materials adapted to the substrate material; when forming a PMOS transistor, the second epitaxial layer may include an epitaxial layer doped with N-type ions, and the material of the second epitaxial layer is Si or SiC, or other materials adapted to the substrate material.

[0113] In a specific embodiment, the material of the second epitaxial layer may be Si.

[0114] A third epitaxial layer for forming a second source / drain doping layer.

[0115] The second source / drain doping layer can be used as the source or drain of the field effect transistor, and when the field effect transistor is working, the second source / drain doping layer can be used to provide the carrier source.

[0116] In this embodiment, when forming an NMOS transistor, the third epitaxial layer may include an epitaxial layer doped with N-type ions, and the material of the third epitaxial layer may be Si or SiC, or other materials adapted to the substrate material; when forming a PMOS transistor, the third epitaxial layer may include an epitaxial layer doped with P-type ions, and the material of the third epitaxial layer is Si or SiGe, or other materials adapted to the substrate material.

[0117] In a specific embodiment, the material of the third epitaxial layer may be Si.

[0118] It should be noted that, first, when the number of epitaxial layers is more (for example, greater than 3), there are adjacent epitaxial layers that play the same role, such as two consecutive epitaxial layers serving as the source / drain doping layer; second, the functions of the first epitaxial layer, the second epitaxial layer, and the third epitaxial layer listed in the above examples are only for illustrative purposes, and are used to indicate that among three consecutive epitaxial layers, they can serve as the source, drain, and the channel layer located between the source and the drain in the semiconductor structure, and should not be construed as a limitation of the present invention.

[0119] In this embodiment, the first source / drain doping layer is one of the source or the drain, and the second source / drain doping layer is the other of the source or the drain.

[0120] In other words, one of the first source-drain doping layer and the second source-drain doping layer serves as the source electrode, and the other serves as the drain electrode.

[0121] For example, the first source-drain doping layer serves as the drain electrode, and the second source-drain doping layer serves as the source electrode. Also for example, the first source-drain doping layer serves as the drain electrode, and the second source-drain doping layer serves as the source electrode.

[0122] In this embodiment, the doping type of the first source-drain doping layer is different from that of the channel layer.

[0123] In a specific embodiment, the doping type of the first source-drain doping layer is N-type, and the doping type of the channel layer is P-type.

[0124] In a specific embodiment, the doping type of the first source-drain doping layer is P-type, and the doping type of the channel layer is N-type.

[0125] In this embodiment, the doping type of the second source-drain doping layer is different from that of the channel layer.

[0126] In a specific embodiment, the doping type of the second source-drain doping layer is N-type, and the doping type of the channel layer is P-type.

[0127] In a specific embodiment, the doping type of the second source-drain doping layer is P-type, and the doping type of the channel layer is N-type.

[0128] It should be noted that, first, this solution does not limit the doping types of the first source-drain doping layer, the second source-drain doping layer, and the channel layer. As long as the doping types of the first source-drain doping layer and the channel layer are different, and the doping types of the second source-drain doping layer and the channel layer are different; second, in this solution, when the doping type is N-type, the doping ions may include: P, As, or Sb; when the doping type is P-type, the doping ions may include: B, Ga, or In.

[0129] In this embodiment, the doping types of the first source-drain doping layer and the second source-drain doping layer are the same and are both different from that of the channel layer. In this way, when a voltage is applied to the gate structure, the carrier (electron or hole) concentration in the channel layer region will increase significantly, so that the region adjacent to the gate structure in the channel layer is inverted. For example Figure 12 the region indicated by the dashed box in forms a conductive channel, for example Figure 12 the flow path indicated by the arrow in. When a voltage is applied between the first source-drain doping layer and the second source-drain doping layer, the carriers start to move along the conductive channel under the action of the electric field, forming a current.

[0130] In this embodiment, the doping concentration of the first source-drain doping layer is greater than that of the channel layer. Under the same electric field strength, the first source-drain doping layer with a higher doping concentration can provide more carriers and has a stronger current conduction ability.

[0131] In some embodiments, the doping concentration of the first source-drain doping layer is 10 to 100 times that of the channel layer.

[0132] By making the doping concentration of the first source-drain doping layer 10 to 100 times that of the channel layer, the selection range of the doping concentration of the first source-drain doping layer is broadened, and a first source-drain doping layer adapted to the doping concentration of the channel layer can be formed based on the doping concentration of the channel layer.

[0133] In a specific embodiment, the doping concentration of the first source-drain doping layer can be 1E 14 atom / cm 3 to 1E 15 atom / cm 3 . The doping concentration of the channel layer can be 1E 12 atom / cm 3 to 1E 13 atom / cm 3 .

[0134] In this embodiment, the doping concentration of the second source-drain doping layer is greater than that of the channel layer. Under the same electric field strength, the second source-drain doping layer with a higher doping concentration can provide more carriers and has a stronger current conduction ability.

[0135] In some embodiments, the doping concentration of the second source-drain doping layer is 10 to 100 times that of the channel layer.

[0136] By making the doping concentration of the second source-drain doping layer 10 to 100 times that of the channel layer, the selection range of the doping concentration of the second source-drain doping layer is broadened, and a second source-drain doping layer adapted to the doping concentration of the channel layer can be formed based on the doping concentration of the channel layer.

[0137] In a specific embodiment, the doping concentration of the second source-drain doping layer can be 1E 14 atom / cm 3 to 1E 15 atom / cm 3 . The doping concentration of the channel layer can be 1E 12 atom / cm 3 to 1E 13 atom / cm 3 .

[0138] In this embodiment, the thickness of the channel layer will directly affect the performance of the semiconductor structure, such as conductivity, current driving ability, and switching speed. For example, when the thickness of the channel layer is relatively thin, the migration time of carriers in the channel layer can be reduced, improving conductivity.

[0139] Moreover, in this solution, the channel layer is in direct contact with the first source-drain doping layer and the second source-drain doping layer. The short-channel effect is not obvious, and the thickness range value of the channel layer has a relatively large span. Therefore, it can be set based on process requirements to cope with different process nodes.

[0140] In a specific embodiment, the thickness of the channel layer is 10 nanometers to 50 nanometers. For example, 14nm, 28nm, 40nm, etc. In this way, a process machine of a large technology node can be used to produce a channel layer equivalent to that of a smaller technology node, reducing the requirements for the process machine.

[0141] It should be noted that the thickness of the channel layer described in the above example is only for illustrative purposes. In the actual manufacturing process, the thickness of the channel layer can be appropriately reduced or increased.

[0142] In other words, in this solution, an epitaxial process is adopted, and the thickness of the channel layer is controllable. According to the requirements of the semiconductor structure to be manufactured, by setting the parameters of the epitaxial process, the thickness of the channel layer can meet the process requirements.

[0143] In this embodiment, the first source-drain doping layer or the second source-drain doping layer serves to provide carriers, and its influence on the performance of the semiconductor structure is less than that of the channel layer on the performance of the semiconductor structure. The thickness of the first source-drain doping layer or the second source-drain doping layer can be greater than the thickness of the channel layer.

[0144] In addition, a relatively thick first source-drain doping layer or second source-drain doping layer can usually reduce the contact resistance between it and the channel layer, thereby improving the carrier injection efficiency and the conductivity of the device.

[0145] In a specific embodiment, the thickness of the first source-drain doping layer can be 500 angstroms to 1000 angstroms.

[0146] In a specific embodiment, the thickness of the second source-drain doping layer can be 500 angstroms to 1000 angstroms.

[0147] For better understanding and illustration of the formation process of the epitaxial layer in this solution, an Figures 3 to 5 exemplary illustration is given.

[0148] It should be noted that Figures 3 to 5 shows three of the multiple epitaxial layers.

[0149] See Figure 3, taking the top surface of the substrate 100 as the growth basis, an epitaxial layer 102 is formed by using an epitaxial and doping process.

[0150] The first epitaxial layer 102 can be used as the first source / drain doping layer.

[0151] Among them, for more details about the first epitaxial layer 102, reference can be made to the foregoing examples.

[0152] See Figure 4 , taking the top surface of the first epitaxial layer 102 as the growth basis, a second epitaxial layer 104 is formed by using an epitaxial and doping process.

[0153] The second epitaxial layer 104 can be used as the channel layer.

[0154] Among them, for more details about the second epitaxial layer 104, reference can be made to the foregoing examples.

[0155] See Figure 5 , taking the top surface of the second epitaxial layer 104 as the growth basis, a third epitaxial layer 106 is formed by using an epitaxial and doping process.

[0156] The third epitaxial layer 106 can be used as the second source / drain doping layer.

[0157] Among them, for more details about the third epitaxial layer 106, reference can be made to the foregoing examples.

[0158] By forming the first epitaxial layer 102, the second epitaxial layer 104, and the third epitaxial layer 106 through an epitaxial process, the first epitaxial layer 102, the second epitaxial layer 104, and the third epitaxial layer 106 have different thicknesses, so that the thickness of some or all of the epitaxial layers can be reduced; on the other hand, the epitaxial process and the doping operation are carried out synchronously, and the epitaxial layer formed by epitaxial growth has better doping density and uniformity, improving the uniformity of the doping concentration at different positions of the same epitaxial layer, which is beneficial to reducing the short-channel effect.

[0159] See Figures 6 to 8 , a gate structure 110 is formed, and the gate structure 110 penetrates through some or all of the epitaxial layers and is in contact with some or all of the epitaxial layers.

[0160] When the device is operating, the gate structure 110 is used to control the opening and closing of the conductive channel.

[0161] In this embodiment, the gate structure 110 is a polysilicon gate structure or an amorphous silicon gate structure. In some other embodiments, the gate structure 110 can also be a metal gate structure.

[0162] In this embodiment, the gate structure 110 penetrates through the first epitaxial layer 102, the second epitaxial layer 104, and the third epitaxial layer 106, and is in contact with the first epitaxial layer 102, the second epitaxial layer 104, and the third epitaxial layer 106.

[0163] In this way, when the second epitaxial layer 104 is used as the channel layer, the gate structure 110 is in contact with the channel layer. When a driving voltage is applied to the gate structure 110, the channel layer can be turned on, so that a conductive channel is formed between the first epitaxial layer 102 and the third epitaxial layer 106.

[0164] In this solution, it is only necessary that the gate structure 110 is in contact with the epitaxial layer used as the channel layer. Or rather, the epitaxial layer in contact with the gate structure 110 includes the channel layer.

[0165] In this case, the gate structure 110 can only penetrate through the third epitaxial layer 106 and the second epitaxial layer 104, and be in contact with the third epitaxial layer 106 and the second epitaxial layer 104. Or, the gate structure 110 can only penetrate through the third epitaxial layer 106 and the second epitaxial layer 104, and be in contact with the second epitaxial layer 104.

[0166] In this embodiment, the steps of forming the gate structure 110 include:

[0167] See Figure 6 , a first trench G1 that penetrates through part or all of the epitaxial layers is formed, and the side walls of the penetrated epitaxial layers are exposed by the first trench.

[0168] The first trench G1 provides a position space for forming the gate structure 110.

[0169] In this embodiment, the first trench G1 can penetrate through the first epitaxial layer 102, the second epitaxial layer 104, and the third epitaxial layer 106, and expose the side walls of the first epitaxial layer 102, the second epitaxial layer 104, and the third epitaxial layer 106.

[0170] In other embodiments, the first trench G1 can only penetrate through the third epitaxial layer 106 and the second epitaxial layer 104, and expose the side walls of the third epitaxial layer 106 and the second epitaxial layer 104, and optionally, expose the top surface of the first epitaxial layer 102.

[0171] In other words, the first trench G1 needs to expose the side walls of the epitaxial layer used as the channel layer.

[0172] In this embodiment, a patterning process is used to remove part of the first epitaxial layer 102, the second epitaxial layer 104, and the third epitaxial layer 106 to form the first trench G1.

[0173] See Figure 7 and Figure 8, a gate material layer (not shown in the figure) is formed on the outermost epitaxial layer, and the gate material layer fills the first trench; the gate material layer higher than the outermost epitaxial layer is removed, and the gate material layer remaining in the first trench G1 is used as the gate structure 110.

[0174] The gate material layer provides a process basis for forming the gate structure 110.

[0175] In this embodiment, the material of the gate material layer includes polysilicon.

[0176] In this embodiment, the gate material layer is formed by chemical vapor deposition process. The film layer formed by chemical vapor deposition is thin and uniform, and the structure is dense, which is beneficial to improving the formation quality of the gate material layer.

[0177] In a specific embodiment, the chemical vapor deposition process can be low-pressure chemical vapor deposition (LPCVD).

[0178] In this embodiment, the gate material layer higher than the outermost epitaxial layer is removed by a grinding process (for example, chemical mechanical polishing CMP).

[0179] It should be noted that during the process of forming the gate structure 110, the process temperature should not exceed 800 degrees Celsius.

[0180] In this embodiment, then refer to Figures 6 to 8 , the steps of forming the gate structure 110 may further include: forming a gate oxide layer 108 on the outermost epitaxial layer, and the gate oxide layer 108 covers the side wall and the bottom of the first trench G1.

[0181] The gate oxide layer 108 can play a role in protecting the epitaxial layer (for example, the third epitaxial layer 106) below the gate oxide layer 108 when removing the gate material layer higher than the outermost epitaxial layer.

[0182] In this embodiment, methods such as low-temperature chemical vapor deposition process, atomic layer deposition, and low-temperature wet oxidation can be used to form the gate oxide layer 108.

[0183] Compared with the traditional high-temperature thermal oxidation, these methods can grow a high-quality oxygen gate oxide layer 108 at a lower temperature, and have better thickness control and uniformity.

[0184] In this embodiment, when the forming method further includes forming the gate oxide layer 108, the gate structure 110 can also cover the side wall and the bottom of the gate oxide layer 108, and the gate oxide layer 108 and the gate material layer can jointly serve as the gate structure 110.

[0185] In this embodiment, refer toFigure 8 When forming the gate oxide layer 108, during the process of forming the gate structure 110, the gate oxide layer 108 and the gate material layer on the topmost epitaxial layer can jointly serve as the gate structure 110.

[0186] Next, refer to Figures 6 to 8 In some embodiments, the gate structure 110 penetrates through all the epitaxial layers and partially penetrates the substrate 100.

[0187] In this embodiment, after forming the gate structure 110, a conductive structure can be formed to realize the electrical connection between the gate structure 110, part or all of the epitaxial layers and other interconnect structures or external circuits.

[0188] For each of the partial or all epitaxial layers, at least one first conductive structure is formed, and each first conductive structure is electrically connected to the corresponding epitaxial layer; a second conductive structure is formed, and the second conductive structure is electrically connected to the gate structure.

[0189] In this embodiment, along the normal direction of the surface of the substrate 100, the multiple epitaxial layers are stacked. When forming the first conductive structure, there is a case where the first conductive structure is electrically connected to at least two epitaxial layers. In this case, during the process of forming the first conductive structure, the first conductive structure needs to be electrically insulated from the non-electrically connected epitaxial layers to avoid short-circuit problems caused by the first conductive structure being electrically connected to at least two epitaxial layers.

[0190] To facilitate understanding of the formation process of the first conductive structure and the second conductive structure in this solution, refer to Figures 9 to 17 and a brief description is given through an example.

[0191] Refer to Figures 9 to 11 、 Figure 17 The steps of forming the first conductive structure 120 electrically connected to the third epitaxial layer 106 include:

[0192] Forming a second trench G21, and the second trench G21 exposes at least a part of the sidewall of the epitaxial layer (for example, the third epitaxial layer 106) electrically connected to the first conductive structure 120.

[0193] The second trench G21 provides a process space for forming the first conductive structure 120.

[0194] In this embodiment, the steps of forming the second trench G21 include: forming an interlayer dielectric layer 112 on the topmost epitaxial layer (in this embodiment, the third epitaxial layer 106 is the topmost epitaxial layer); removing a part of the interlayer dielectric layer 112 to expose the surface of the third epitaxial layer 106; then removing a part of the thickness of the third epitaxial layer 106 to form the second trench G21.

[0195] Among them, the second trench G21 is at least composed of the sidewalls and the bottom of the third epitaxial layer 106, and optionally, also includes the sidewalls of the interlayer dielectric layer 112.

[0196] In this embodiment, the interlayer dielectric layer 112 is used to achieve electrical isolation between the first conductive structure and the second conductive structure, and is also used to achieve electrical isolation between adjacent devices.

[0197] In this embodiment, the material of the interlayer dielectric layer 112 is an insulating material. For example, the material of the interlayer dielectric layer 112 is silicon oxide. In other embodiments, the material of the interlayer dielectric layer can also be other dielectric materials such as silicon nitride or silicon oxynitride.

[0198] An insulating layer 122 is formed on the sidewalls of the second trench G21.

[0199] In this embodiment, the step of forming the insulating layer 122 includes: forming an insulating material layer in the second trench G21; removing the insulating material layer located at the bottom of the second trench G21, and using the remaining insulating material layer as the insulating layer 122. For example, a re-etching process is used to remove the insulating material layer located at the bottom of the second trench G21.

[0200] It should be noted that when removing the insulating material layer at the bottom of the second trench G21, the insulating material layer on the interlayer dielectric layer 112 is also removed.

[0201] In this embodiment, the material of the insulating layer 122 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, boron nitride, and carbon boron nitride.

[0202] At least a first conductive plug 124 is formed in the remaining space of the second trench G21. The first conductive plug 124 is electrically connected to the epitaxial layer (the third epitaxial layer 106), and the first conductive plug 124 and the insulating layer 122 serve as the first conductive structure 120.

[0203] In other words, the sidewalls of the third epitaxial layer 106 are covered by the insulating layer 122, and the first conductive plug 124 is in contact with the top surface of the third epitaxial layer 106.

[0204] In this embodiment, the material of the first conductive plug 124 includes materials with good electrical conductivity such as cobalt, copper, aluminum, or tungsten.

[0205] In this embodiment, the depth of the first conductive plug 124 in the third epitaxial layer 106 is 1 / 2 to 2 / 3 of the thickness of the second epitaxial layer 104. On the one hand, by making the depth of the first conductive plug 124 in the third epitaxial layer 106 not exceed 2 / 3 of the thickness of the third epitaxial layer 106, the isolation degree between the first conductive plug 124 and the underlying device is improved, and the formation difficulty is reduced. On the other hand, by making the depth of the first conductive plug 124 in the first epitaxial layer 102 not less than 1 / 2 of the thickness of the first epitaxial layer 102, the distance between the bottom of the first conductive plug 124 and the top of the first epitaxial layer 102 is appropriate, and the first conductive plug 124 is only electrically connected to the third epitaxial layer 106.

[0206] It should be noted that when the epitaxial layer is the topmost epitaxial layer, the first conductive structure 120 can be directly formed in the second trench G21.

[0207] See Figure 9 、 Figure 12 、 Figure 13 and Figure 17 , the steps of forming the first conductive structure 130 electrically connected to the first epitaxial layer 102 include:

[0208] Form a second trench G22, and the second trench G22 exposes at least part of the sidewalls of the epitaxial layer electrically connected to the first conductive structure 130.

[0209] For example, the second trench G22 exposes all the sidewalls of the third epitaxial layer 106 and the second epitaxial layer 104, and part of the sidewalls of the first epitaxial layer 102.

[0210] The second trench G22 provides a process space for forming the first conductive structure 130.

[0211] In this embodiment, the steps of forming the second trench G22 can refer to the description of the first trench G21.

[0212] Among them, the second trench G22 is at least composed of the sidewalls of the third epitaxial layer 106 and the second epitaxial layer 104, and part of the sidewalls and the bottom of the first epitaxial layer 102, and optionally, also includes the sidewalls of the interlayer dielectric layer 112.

[0213] Form an insulating layer 132 on the sidewalls of the second trench G22.

[0214] Among them, for the detailed description of forming the insulating layer 132, reference can be made to the relevant content of the insulating layer 122 in the foregoing embodiment.

[0215] At least a first conductive plug 134 is formed in the remaining space of the second trench G22. The first conductive plug 134 is electrically connected to the epitaxial layer (the first epitaxial layer 102), and the first conductive plug 134 and the insulating layer 132 serve as the first conductive structure 130.

[0216] In other words, the sidewalls of the third epitaxial layer 106, the second epitaxial layer 104, and the first epitaxial layer 102 are covered by the insulating layer 132, and the first conductive plug 134 is in contact with the top surface of the first epitaxial layer 102.

[0217] In this embodiment, the material of the first conductive plug 134 includes a material with good electrical conductivity such as cobalt, copper, aluminum, or tungsten.

[0218] Similarly, the depth of the first conductive plug 134 in the first epitaxial layer 102 is 1 / 2 to 2 / 3 of the thickness of the first epitaxial layer 102.

[0219] See Figure 9 、 Figures 14 to 17 , the steps of forming the first conductive structure 140 electrically connected to the second epitaxial layer 104 include:

[0220] Form a second trench G23, and the second trench G23 exposes at least a part of the sidewall of the epitaxial layer electrically connected to the first conductive structure 140.

[0221] The first conductive structure 140 exposes all the sidewalls of the third epitaxial layer 106 and a part of the sidewalls of the second epitaxial layer 104.

[0222] The second trench G23 provides a process space for forming the first conductive structure 140.

[0223] In this embodiment, the steps of forming the second trench G23 can refer to the foregoing example.

[0224] Among them, the second trench G23 is at least composed of the sidewalls of the third epitaxial layer 106 and the second epitaxial layer 104, and the bottom of the second epitaxial layer 104, and optionally, also includes the sidewalls of the interlayer dielectric layer 112.

[0225] Form an insulating layer 142 on the sidewall of the second trench G23. For a detailed description of forming the insulating layer 142, reference can be made to the relevant content of the insulating layer 122 in the foregoing embodiment.

[0226] At least a first conductive plug 144 is formed in the remaining space of the second trench G23. The first conductive plug 144 is electrically connected to the epitaxial layer (the second epitaxial layer 104), and the first conductive plug 144 and the insulating layer 142 serve as the first conductive structure 140.

[0227] In other words, the sidewalls of the third epitaxial layer 106 and the second epitaxial layer 104 are covered by the insulating layer 142, and the first conductive plug 144 is in contact with the top surface of the second epitaxial layer 104.

[0228] In this embodiment, the material of the first conductive plug 134 includes materials with good conductivity such as cobalt, copper, aluminum, or tungsten.

[0229] In this embodiment, the reason for leading out the second epitaxial layer 104 through the first conductive structure 140 is as follows: on the one hand, the second epitaxial layer 104 is used as a channel layer, and the second epitaxial layer 104 is not in contact with the substrate 100, so the substrate 100 cannot serve as a discharge channel for the second epitaxial layer 104; on the other hand, referring to Figure 16 , the first conductive structures 120, 130, and 140 overlap with each other along the D-D1 direction, and the distance between the first conductive structures 120, 130, and 140 is relatively close, resulting in the problem of charge accumulation in the second epitaxial layer 104. For the above two reasons, by providing the first conductive structure 140 electrically connected to the second epitaxial layer 104, the charges in the second epitaxial layer 104 can be extracted.

[0230] In addition, the first conductive structure 140 can be used as a ground terminal to provide a reference benchmark value for the entire semiconductor structure.

[0231] In this embodiment, when forming at least one first conductive structure, when the epitaxial layer electrically connected to the first conductive structure is the topmost epitaxial layer, the second trench only exposes a part of the sidewall of the epitaxial layer.

[0232] For example, in one embodiment, the third epitaxial layer 106 is the topmost epitaxial layer, then the second trench G21 only exposes a part of the sidewall of the third epitaxial layer 106.

[0233] When the epitaxial layer electrically connected to the first conductive structure is not the topmost epitaxial layer, the second trench exposes a part of the sidewall of the epitaxial layer and the sidewalls of other epitaxial layers located above the epitaxial layer.

[0234] For example, in one embodiment, the first epitaxial layer 102 is not the topmost epitaxial layer, then the second trench G22 not only exposes a part of the sidewall of the first epitaxial layer 102, but also exposes the sidewalls of the second epitaxial layer 104 and the third epitaxial layer 106.

[0235] In short, when forming the first conductive structure, at least a part of the sidewall of the epitaxial layer electrically connected to the first conductive structure needs to be exposed, and when the epitaxial layer is not the topmost epitaxial layer, the sidewalls of other epitaxial layers located above the epitaxial layer also need to be exposed.

[0236] It should be noted that Figures 9 to 15The process of the first conductive structure illustrated is only an example and should not be construed as a limitation of the present invention.

[0237] Referring to Figure 9 、 Figure 14 and Figure 15 ,the steps of forming the second conductive structure 150 include: forming a third trench G3 that exposes the top surface of the gate structure 110.

[0238] The third trench G3 provides a process space for forming the second conductive structure 150.

[0239] In this embodiment, the steps of forming the third trench G3 include: forming an interlayer dielectric layer 112 on the topmost epitaxial layer (in this embodiment, the third epitaxial layer 106 is the topmost epitaxial layer); removing a portion of the interlayer dielectric layer 112 to expose the top surface of the gate structure 110.

[0240] Forming a second conductive plug electrically connected to the gate structure 110 in the third trench G3, and the second conductive plug serves as the second conductive structure 150.

[0241] It should be noted that Figure 9 、 Figure 14 and Figure 15 the process of the second conductive structure illustrated is only an example and should not be construed as a limitation of the present invention.

[0242] For example, in the steps of forming the first conductive structure and the second conductive structure, the same interlayer dielectric layer can be used, and through the same interlayer dielectric layer, the second trench and the third trench are formed step by step.

[0243] Also for example, the second conductive plug and the first conductive plug are formed in the same step.

[0244] Specifically, an insulating layer is formed in the second trench, and after forming the third trench, a conductive material layer is formed on the interlayer dielectric layer 112. The conductive material layer also fills the remaining space of the second trench and the third trench; using the interlayer dielectric layer 112 as a stop layer, the conductive material layer higher than the interlayer dielectric layer 112 is removed, and the remaining portion of the conductive material layer is used as the second conductive plug or the first conductive plug.

[0245] It should be noted that the above describes multiple embodiment solutions provided by the embodiments of the present disclosure. The various alternative ways described in each embodiment solution can be combined and cross-referenced with each other without conflict, thereby extending a variety of possible embodiment solutions, and all of these can be considered as the embodiment solutions disclosed and made public by the present disclosure.

[0246] The present invention also provides a semiconductor structure. Referring to Figures 15 to 17, the semiconductor structure includes: a substrate 100; a multi-layer epitaxial layer (as a non-limiting example, Figure 16 illustrates three of the epitaxial layers, for example, a first epitaxial layer 102, a second epitaxial layer 104, and a third epitaxial layer 106), located on the substrate 100, and each epitaxial layer has its own doping type and doping concentration; a gate structure 110, penetrating through part or all of the epitaxial layers and in contact with the sidewalls of part or all of the epitaxial layers (as a non-limiting example, the gate structure 110 penetrates through the first epitaxial layer 102, the second epitaxial layer 104, and the third epitaxial layer 106).

[0247] The substrate 100 can provide a process operation basis for the formation process of the semiconductor structure.

[0248] In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate can also be other materials such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate can also be other types of substrates such as a silicon-on-insulator substrate or a germanium-on-insulator substrate. The material of the substrate can be a material suitable for process requirements or easy to integrate.

[0249] It should be noted that the semiconductor structure in this solution may not include the substrate 100, Figure 15 The illustrated semiconductor structure can be regarded as an intermediate structure, not the final semiconductor structure.

[0250] The multi-layer epitaxial layer provides a process basis for the formation of film layers such as a channel layer and a source / drain doping layer. Or rather, the multi-layer epitaxial layer can be used as film layer structures with different or the same functions in the semiconductor structure.

[0251] In this embodiment, among any two adjacent epitaxial layers, the upper epitaxial layer is grown on the top surface of the lower epitaxial layer, and the bottommost epitaxial layer is grown on the top surface of the substrate 100.

[0252] In other words, the top surface of the substrate 100 serves as the initial growth basis for the entire semiconductor structure. The first epitaxial layer is grown on the top surface of the substrate 100, and subsequent epitaxial layers are grown on the top surface of the previous epitaxial layer.

[0253] And in this solution, the surface of the substrate 100 is relatively flat, making the surface of the first epitaxial layer flat. On this basis, the surface of any epitaxial layer is relatively flat, reducing the resistance at the interface between the epitaxial layer and the substrate 100, as well as the resistance at the interface between adjacent epitaxial layers, and improving the electrical performance of the semiconductor structure.

[0254] In this embodiment, each epitaxial layer has its own doping type, so that the doping types between adjacent epitaxial layers can be controlled. Among the three epitaxial layers, the doping type of the middle epitaxial layer is different from that of the upper and lower epitaxial layers. In this way, an epitaxial structure with a conductive channel can be formed through the three epitaxial layers with the above doping characteristics to enhance the control ability of the gate structure.

[0255] In this embodiment, the doping concentration of the epitaxial layer directly affects parameters such as the conductivity and carrier mobility of the semiconductor structure. Therefore, the doping concentration of each epitaxial layer can be set based on actual needs, so that each epitaxial layer has its own doping concentration, that is, different epitaxial layers have the same or different doping concentrations.

[0256] In this embodiment, the number of epitaxial layers is greater than or equal to 3. By making the number of epitaxial layers greater than or equal to 3, at least a source electrode, a drain electrode, and a channel layer located between the source electrode and the drain electrode can be formed to play the role of current flow.

[0257] In this embodiment, when the number of epitaxial layers is greater than or equal to 3, the semiconductor structure in this solution can meet at least one or more of the following:

[0258] The first epitaxial layer 102, and the first epitaxial layer 102 serves as the first source / drain doping layer.

[0259] The first source / drain doping layer can be used as the source electrode or the drain electrode of the field effect transistor. When the field effect transistor works, the first source / drain doping layer can be used to provide a carrier source.

[0260] The second epitaxial layer 104, and the second epitaxial layer 104 serves as the channel layer.

[0261] The channel layer is used to provide a flow region for the carrier source.

[0262] The third epitaxial layer 106, and the third epitaxial layer 106 serves as the second source / drain doping layer.

[0263] The second source / drain doping layer can be used as the source electrode or the drain electrode of the field effect transistor. When the field effect transistor works, the second source / drain doping layer can be used to provide a carrier source.

[0264] In this embodiment, the first source / drain doping layer is one of the source electrode or the drain electrode, and the second source / drain doping layer is the other of the source electrode or the drain electrode.

[0265] In other words, one of the source / drain doping layers of the first source / drain doping layer and the second source / drain doping layer serves as the source electrode, and the other serves as the drain electrode.

[0266] For example, the first source-drain doping layer serves as the drain, and the second source-drain doping layer serves as the source. Also for example, the first source-drain doping layer serves as the drain, and the second source-drain doping layer serves as the source.

[0267] In this embodiment, the doping type of the first source-drain doping layer is different from that of the channel layer.

[0268] In a specific embodiment, the doping type of the first source-drain doping layer is N-type, and the doping type of the channel layer is P-type.

[0269] In a specific embodiment, the doping type of the first source-drain doping layer is P-type, and the doping type of the channel layer is N-type.

[0270] In this embodiment, the doping type of the second source-drain doping layer is different from that of the channel layer.

[0271] In a specific embodiment, the doping type of the second source-drain doping layer is N-type, and the doping type of the channel layer is P-type.

[0272] In a specific embodiment, the doping type of the second source-drain doping layer is P-type, and the doping type of the channel layer is N-type.

[0273] It should be noted that, first, this solution does not limit the doping types of the first source-drain doping layer, the second source-drain doping layer, and the channel layer. As long as the doping types of the first source-drain doping layer and the channel layer are different, and the doping types of the second source-drain doping layer and the channel layer are different; second, in this solution, when the doping type is N-type, the doping ions may include: P, As, or Sb; when the doping type is P-type, the doping ions may include: B, Ga, or In.

[0274] In this embodiment, the doping types of the first source-drain doping layer and the second source-drain doping layer are the same and are both different from the channel layer. In this way, when a voltage is applied to the gate structure, the carrier (electron or hole) concentration in the channel layer region will increase significantly, so that the region adjacent to the gate structure in the channel layer is inverted to form a conductive channel. When a voltage is applied between the first source-drain doping layer and the second source-drain doping layer, the carriers start to move along the conductive channel under the action of the electric field to form a current.

[0275] In this embodiment, the doping concentration of the first source-drain doping layer is greater than that of the channel layer. Under the same electric field strength, the first source-drain doping layer with a higher doping concentration can provide more carriers, and the current conduction ability is stronger.

[0276] In some embodiments, the doping concentration of the first source-drain doping layer is 10 to 100 times that of the channel layer.

[0277] By making the doping concentration of the first source-drain doping layer 10 to 100 times that of the channel layer, the selection range of the doping concentration of the first source-drain doping layer is broadened, and a first source-drain doping layer adapted to the doping concentration of the channel layer can be formed based on the doping concentration of the channel layer.

[0278] In a specific embodiment, the doping concentration of the first source-drain doping layer can be 1E 14 atom / cm 3 to 1E 15 atom / cm 3 . The doping concentration of the channel layer can be 1E 12 atom / cm 3 to 1E 13 atom / cm 3 .

[0279] In this embodiment, the doping concentration of the second source-drain doping layer is greater than that of the channel layer. Under the same electric field strength, the second source-drain doping layer with a higher doping concentration can provide more carriers and has a stronger current conduction ability.

[0280] In some embodiments, the doping concentration of the second source-drain doping layer is 10 to 100 times that of the channel layer.

[0281] By making the doping concentration of the second source-drain doping layer 10 to 100 times that of the channel layer, the selection range of the doping concentration of the second source-drain doping layer is broadened, and a second source-drain doping layer adapted to the doping concentration of the channel layer can be formed based on the doping concentration of the channel layer.

[0282] In a specific embodiment, the doping concentration of the second source-drain doping layer can be 1E 14 atom / cm 3 to 1E 15 atom / cm 3 . The doping concentration of the channel layer can be 1E 12 atom / cm 3 to 1E 13 atom / cm 3 .

[0283] In this embodiment, the thickness of the channel layer will directly affect the performance of the semiconductor structure such as conductivity, current driving ability, and switching speed. For example, when the thickness of the channel layer is relatively thin, the migration time of carriers in the channel layer can be reduced, improving conductivity.

[0284] Moreover, in this solution, the channel layer is directly in contact with the first source / drain doping layer and the second source / drain doping layer, and the short-channel effect is not obvious. The thickness range of the channel layer has a large span, so it can be set based on process requirements to cope with different process nodes.

[0285] In a specific embodiment, the thickness of the channel layer is 10 nanometers to 50 nanometers. For example, 14nm, 28nm, 40nm, etc. In this way, a manufacturing machine for a large technology node can be used to produce a channel layer equivalent to that of a smaller technology node, reducing the requirements for the manufacturing machine.

[0286] It should be noted that the thickness of the channel layer described in the above example is only for illustrative purposes. In the actual manufacturing process, the thickness of the channel layer can be appropriately reduced or increased.

[0287] In other words, in this solution, an epitaxial process is adopted, and the thickness of the channel layer is controllable. According to the requirements of the semiconductor structure to be manufactured, by setting the parameters of the epitaxial process, the thickness of the channel layer can meet the process requirements.

[0288] In this embodiment, the first source / drain doping layer or the second source / drain doping layer serves to provide carriers, and its influence on the performance of the semiconductor structure is less than that of the channel layer on the performance of the semiconductor structure. The thickness of the first source / drain doping layer or the second source / drain doping layer can be greater than the thickness of the channel layer.

[0289] In addition, a relatively thick first source / drain doping layer or second source / drain doping layer can usually reduce the contact resistance between it and the channel layer, thereby improving the carrier injection efficiency and the conductivity of the device.

[0290] In a specific embodiment, the thickness of the first source / drain doping layer can be 500 angstroms to 1000 angstroms.

[0291] In a specific embodiment, the thickness of the second source / drain doping layer can be 500 angstroms to 1000 angstroms.

[0292] During device operation, the gate structure 110 is used to control the opening and closing of the conductive channel.

[0293] In this embodiment, the gate structure 110 penetrates through the first epitaxial layer 102, the second epitaxial layer 104, and the third epitaxial layer 106, and is in contact with the first epitaxial layer 102, the second epitaxial layer 104, and the third epitaxial layer 106.

[0294] In this way, when the second epitaxial layer 104 is used as the channel layer, the gate structure 110 is in contact with the channel layer. When a driving voltage is applied to the gate structure 110, the channel layer can be turned on, enabling a conductive channel to be formed between the first epitaxial layer 102 and the second epitaxial layer 106.

[0295] In this solution, it is only necessary that the gate structure 110 is in contact with the epitaxial layer serving as the channel layer. Or rather, the epitaxial layer in contact with the gate structure 110 includes the channel layer.

[0296] In this case, the gate structure 110 can penetrate only through the third epitaxial layer 106 and the second epitaxial layer 104 and be in contact with the third epitaxial layer 106 and the second epitaxial layer 104, or the gate structure 110 can penetrate only through the third epitaxial layer 106 and the second epitaxial layer 104 and be in contact with the second epitaxial layer 104.

[0297] In this embodiment, the gate structure 110 penetrates through all the epitaxial layers and also penetrates through a part of the substrate 100.

[0298] In this embodiment, after the gate structure 110 is formed, a conductive structure can also be formed to realize the gate. In this embodiment, the gate structure 110 can also include a gate oxide layer 108, and the gate oxide layer 108 covers the sidewalls of the epitaxial layer penetrated by the gate structure 110, as well as the sidewalls and the bottom of the gate structure 110.

[0299] In this embodiment, the semiconductor structure can also include: at least one first conductive structure, and each first conductive structure is electrically connected to the corresponding epitaxial layer.

[0300] In a specific embodiment, the semiconductor structure can include a first conductive structure 120, and the first conductive structure 120 is electrically connected to the third epitaxial layer 106.

[0301] The first conductive structure 120 can realize the electrical connection between the third epitaxial layer 106 and other interconnect structures or an external circuit.

[0302] In this embodiment, the first conductive structure 120 includes: an insulating layer 122 covering a part of the sidewalls of the third epitaxial layer 106 and a first conductive plug 124 covering the sidewalls of the insulating layer 122 and in contact with the top surface of the third epitaxial layer 106.

[0303] Among them, the insulating layer 122 is used to realize the insulation between the first conductive structure 120 and other epitaxial layers.

[0304] In this embodiment, the material of the insulating layer 122 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, boron nitride, and boron carbonitride.

[0305] The first conductive plug 124 is used to lead out the third epitaxial layer 106.

[0306] In this embodiment, the material of the first conductive plug 124 includes a material with good conductivity such as cobalt, copper, aluminum, or tungsten.

[0307] In this embodiment, the depth of the first conductive plug 124 in the third epitaxial layer 106 is 1 / 2 to 2 / 3 of the thickness of the second epitaxial layer 104. On the one hand, by making the depth of the first conductive plug 124 in the third epitaxial layer 106 not exceed 2 / 3 of the thickness of the third epitaxial layer 106, the isolation degree between the first conductive plug 124 and the underlying device is improved, and the formation difficulty is reduced. On the other hand, by making the depth of the first conductive plug 124 in the first epitaxial layer 102 not less than 1 / 2 of the thickness of the first epitaxial layer 102, the distance between the bottom of the first conductive plug 124 and the top of the first epitaxial layer 102 is appropriate, and the first conductive plug 124 is only electrically connected to the third epitaxial layer 106.

[0308] In a specific embodiment, the semiconductor structure may include a first conductive structure 130, and the first conductive structure 130 is electrically connected to the first epitaxial layer 102.

[0309] The first conductive structure 130 can realize the electrical connection between the first epitaxial layer 102 and other interconnect structures or external circuits.

[0310] In this embodiment, the first conductive structure 130 includes: an insulating layer 132 covering the sidewalls of the third epitaxial layer 106 and the second epitaxial layer 104, and a partial sidewall of the first epitaxial layer 102; a first conductive plug 134 covering the sidewall of the insulating layer 132 and in contact with the top surface of the first epitaxial layer 102.

[0311] Among them, the insulating layer 132 is used to realize the insulation between the first conductive structure 130 and other epitaxial layers.

[0312] In this embodiment, the material of the insulating layer 132 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbon oxynitride, boron nitride, and boron carbonitride.

[0313] The first conductive plug 134 is used to lead out the first epitaxial layer 102.

[0314] In this embodiment, the material of the first conductive plug 134 includes a material with good electrical conductivity such as cobalt, copper, aluminum, or tungsten.

[0315] Similarly, in this embodiment, the depth of the first conductive plug 134 in the first epitaxial layer 102 is 1 / 2 to 2 / 3 of the thickness of the first epitaxial layer 102.

[0316] In a specific embodiment, the semiconductor structure may include a first conductive structure 140, and the first conductive structure 140 is electrically connected to the second epitaxial layer 104.

[0317] By providing the first conductive structure 140, the second epitaxial layer 104 can be led out. In this embodiment, the first conductive structure 140 includes: a sidewall covering the third epitaxial layer 106, and an insulating layer 142 covering a partial sidewall of the second epitaxial layer 104; a first conductive plug 144 covering the sidewall of the insulating layer 142 and contacting the top surface of the second epitaxial layer 104.

[0318] Among them, the insulating layer 142 is used to insulate the first conductive structure 140 from other epitaxial layers.

[0319] In this embodiment, the material of the insulating layer 142 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, boron nitride, and boron carbonitride.

[0320] The first conductive plug 144 is used to lead out the first epitaxial layer 102.

[0321] In this embodiment, the reason for leading out the second epitaxial layer 104 through the first conductive structure 140 is that, on the one hand, the second epitaxial layer 104 is used as a channel layer, and the second epitaxial layer 104 does not contact the substrate 100, so the substrate 100 cannot be used as a discharge channel for the second epitaxial layer 104; on the other hand, referring to Figure 16 , the first conductive structures 120, 130, and 140 overlap with each other along the D-D1 direction, and the distance between the first conductive structures 120, 130, and 140 is relatively close, resulting in a problem of charge accumulation in the second epitaxial layer 104. For the above two reasons, by providing the first conductive structure 140 electrically connected to the second epitaxial layer 104, the charges in the second epitaxial layer 104 can be extracted.

[0322] In addition, the first conductive structure 140 can be used as a ground terminal to provide a reference benchmark value for the entire semiconductor structure.

[0323] In this embodiment, the material of the first conductive plug 144 includes materials with good electrical conductivity such as cobalt, copper, aluminum, or tungsten.

[0324] Similarly, in this embodiment, the depth of the first conductive plug 144 in the second epitaxial layer 104 is 1 / 2 to 2 / 3 of the thickness of the second epitaxial layer 104.

[0325] Then referring to Figure 17 , along the D-D1 direction, the first conductive structures 120, 130, and 140 overlap with each other along the D-D1 direction, correspondingly shortening the current flow path.

[0326] In this embodiment, the semiconductor structure may further include: a second conductive structure 150 electrically connected to the gate structure 110.

[0327] The second conductive structure 150 is used to achieve the electrical connection between the gate structure 110 and other interconnect structures or external circuits.

[0328] In this embodiment, the semiconductor structure may further include: an interlayer dielectric layer 112, which is located on the topmost epitaxial layer and covers the sidewalls of the first conductive structure and the second conductive structure.

[0329] In this embodiment, the interlayer dielectric layer 112 is used to achieve electrical isolation between the first conductive structure and the second conductive structure, and is also used to achieve electrical isolation between adjacent devices.

[0330] In this embodiment, the material of the interlayer dielectric layer 112 is an insulating material. For example, the material of the interlayer dielectric layer 112 is silicon oxide. In other embodiments, the material of the interlayer dielectric layer may also be other dielectric materials such as silicon nitride or silicon oxynitride.

[0331] It should be noted that the semiconductor structure described in this embodiment may be formed by the forming method described in the foregoing embodiment, or may be formed by other forming methods. For the specific description of the semiconductor structure described in this embodiment, reference may be made to the corresponding description in the foregoing embodiment, and details are not repeated herein.

[0332] Although the present specification discloses the above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be determined by the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, Including: Providing a substrate; Forming a multi-layer epitaxial layer on the substrate; Forming a gate structure that penetrates through part or all of the epitaxial layers and contacts part or all of the epitaxial layers; Wherein, each epitaxial layer has its own doping type and doping concentration.

2. The method for forming a semiconductor structure according to claim 1, wherein, Each epitaxial layer is formed by an epitaxial process, and doping treatment is performed during the epitaxial growth process; Wherein, among any two adjacent epitaxial layers, the upper epitaxial layer is based on the top surface of the lower epitaxial layer for growth, and the bottommost epitaxial layer is based on the top surface of the substrate for growth.

3. The method for forming a semiconductor structure according to claim 1, wherein The formation temperature of each epitaxial layer is between 600 degrees Celsius and 800 degrees Celsius.

4. The method for forming a semiconductor structure according to claim 3, wherein The formation parameters of each epitaxial layer further include: the pressure is from 70 Torr to 90 Torr, the flow rate of Purge MainH2 is from 3200 sccm to 3800 sccm, the flow rate of PurgeSlitH2 is from 80 sccm to 120 sccm, the flow rate of the silicon source gas is from 120 sccm to 180 sccm, and the epitaxial rate is at least one of from 200 angstroms per minute to 300 angstroms per minute.

5. The method for forming a semiconductor structure according to claim 1, wherein The number of the epitaxial layers is greater than or equal to 3, and satisfies at least one or more of the following: A first epitaxial layer for forming a first source / drain doping layer; A second epitaxial layer for forming a channel layer; A third epitaxial layer for forming a second source / drain doping layer.

6. The method for forming a semiconductor structure according to claim 5, wherein, The first source / drain doping layer is one of the source or the drain, and the second source / drain doping layer is the other of the source or the drain.

7. The method for forming a semiconductor structure according to claim 5, wherein, The first source / drain doping layer and / or the second source / drain doping layer satisfy at least one or more of the following: The doping type of the first source / drain doping layer is different from the doping type of the channel layer; The doping concentration of the first source / drain doping layer is greater than the doping concentration of the channel layer; The doping type of the second source / drain doping layer is different from the doping type of the channel layer; The doping type of the second source / drain doping layer is greater than the doping concentration of the channel layer.

8. The method for forming a semiconductor structure according to claim 7, wherein, The epitaxial layer in contact with the gate structure includes the channel layer.

9. The method for forming a semiconductor structure according to claim 5 or 7, wherein The first source / drain doping layer and / or the second source / drain doping layer satisfy at least one or more of the following: The doping concentration of the first source / drain doping layer is 10 times to 100 times that of the channel layer; The doping concentration of the first source / drain doping layer is 10 times to 100 times that of the channel layer.

10. The method for forming a semiconductor structure according to claim 5, wherein Satisfying at least one or more of the following: The thickness of the first source / drain doping layer is from 500 angstroms to 1000 angstroms; The doping concentration of the first source-drain doping layer is 1E 14 atom / cm 3 to 1E 15 atom / cm 3 ; The thickness of the second source / drain doping layer is from 500 angstroms to 1000 angstroms; The doping concentration of the second source-drain doping layer is 1E 14 atom / cm 3 to 1E 15 atom / cm 3 ; The thickness of the channel layer is from 10 nanometers to 50 nanometers; The doping concentration of the channel layer is 1E 12 atom / cm 3 to 1E 13 atom / cm 3 .

11. The method for forming a semiconductor structure according to claim 1, wherein The steps of forming the gate structure include: Forming a first trench that penetrates through part or all of the epitaxial layers, and the first trench exposes the sidewalls of the penetrated epitaxial layers; Forming a gate material layer on the topmost epitaxial layer, and the gate material layer fills the first trench; Removing the gate material layer higher than the topmost epitaxial layer, and using the gate material layer remaining in the first trench as the gate structure.

12. The method for forming a semiconductor structure according to claim 11, wherein, The steps of forming the gate structure further include: A gate oxide layer is formed on the outermost epitaxial layer, and the gate oxide layer covers the sidewalls and the bottom of the first trench; The gate structure also covers the gate oxide layer.

13. The method for forming a semiconductor structure according to claim 1, wherein, At least one of the following is satisfied: For each epitaxial layer in part or all of the epitaxial layers, at least one first conductive structure is formed, and each first conductive structure is electrically connected to the corresponding epitaxial layer; A second conductive structure is formed, and the second conductive structure is electrically connected to the gate structure.

14. The method for forming a semiconductor structure according to claim 13, wherein, The step of forming at least one first conductive structure includes: Forming a second trench that at least exposes a partial sidewall of the epitaxial layer electrically connected to the first conductive structure; Forming an insulating layer on the sidewalls of the second trench; Forming a first conductive plug at least in the remaining space of the second trench, the first conductive plug being electrically connected to the epitaxial layer, and the first conductive plug and the insulating layer serving as the first conductive structure.

15. The method for forming a semiconductor structure according to claim 14, wherein When the epitaxial layer electrically connected to the first conductive structure is the outermost epitaxial layer, the second trench only exposes a partial sidewall of the epitaxial layer; When the epitaxial layer electrically connected to the first conductive structure is not the outermost epitaxial layer, the second trench exposes a partial sidewall of the epitaxial layer and the sidewalls of other epitaxial layers located on the epitaxial layer.

16. A semiconductor structure, characterized in that, Comprising: A substrate; Multiple epitaxial layers, located on the substrate, and each epitaxial layer has its own doping type and doping concentration; A gate structure that penetrates through part or all of the epitaxial layers and contacts the sidewalls of part or all of the epitaxial layers.

17. The semiconductor structure according to claim 16, wherein, The number of the epitaxial layers is greater than or equal to 3, and at least one of the following is satisfied: A first epitaxial layer that serves as a first source / drain doping layer; A second epitaxial layer that serves as a channel layer; A third epitaxial layer that serves as a second source / drain doping layer.

18. The semiconductor structure according to claim 17, wherein The first source / drain doping layer is one of the source or the drain, and the second source / drain doping layer is the other of the source or the drain.

19. The semiconductor structure according to claim 17, wherein, At least one of the following is satisfied: The doping type of the first source / drain doping layer is different from the doping type of the channel layer; The doping concentration of the first source / drain doping layer is greater than the doping concentration of the channel layer; The doping type of the second source / drain doping layer is different from the doping type of the channel layer; The doping type of the second source / drain doping layer is greater than the doping concentration of the channel layer.

20. The semiconductor structure according to claim 17 or 19, characterized in that, At least one of the following is satisfied: The doping concentration of the first source / drain doping layer is 10 to 100 times the doping concentration of the channel layer; The doping concentration of the first source / drain doping layer is 10 to 100 times the doping concentration of the channel layer.

21. The semiconductor structure according to claim 17, wherein, At least one of the following is satisfied: The thickness of the first source / drain doping layer is 500 angstroms to 1000 angstroms; The doping concentration of the first source-drain doping layer is 1E 14 atom / cm 3 to 1E 15 atom / cm 3 ; The thickness of the second source / drain doping layer is 500 angstroms to 1000 angstroms; The doping concentration of the second source-drain doping layer is 1E 14 atom / cm 3 to 1E 15 atom / cm 3 ; The thickness of the channel layer is 10 nanometers to 50 nanometers; The doping concentration of the channel layer is 1E 12 atom / cm 3 to 1E 13 atom / cm 3 .

22. The semiconductor structure according to claim 16, wherein Further comprising: At least one first conductive structure that is electrically connected to the corresponding epitaxial layer; Forming a second conductive structure that is electrically connected to the gate structure.

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