Semiconductor structure and forming method thereof

Abstract

The invention provides a semiconductor structure and a forming method thereof, and the forming method comprises the steps: providing a substrate; forming a first epitaxial layer structure and a second epitaxial layer structure on the substrate; and forming a gate structure at the junction of the first epitaxial layer structure and the second epitaxial layer structure, the gate structure covering the side walls of the first epitaxial layer structure and the second epitaxial layer structure. By adopting the technical scheme, the size of the semiconductor structure can be reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular, to a semiconductor structure and a method for forming the same. Background Art

[0002] Complementary Metal Oxide Semiconductor (CMOS) is one of the most important components in modern electronic technology, featuring high integration, low power consumption, and strong compatibility. It is widely applied in fields such as computers, communications, consumer electronics, automotive electronics, industrial control, and medical devices.

[0003] CMOS improves integration and processing speed by supporting smaller manufacturing processes, bringing better energy efficiency and cost-effectiveness. However, limited by the process node, the size of CMOS cannot be further reduced. Summary of the Invention

[0004] In view of this, the present invention provides a semiconductor structure and a method for forming the same, which can reduce the size of the semiconductor structure.

[0005] The present invention provides a method for forming a semiconductor structure, including: providing a substrate; forming a first epitaxial layer structure and a second epitaxial layer structure on the substrate; and forming a gate structure at the junction of the first epitaxial layer structure and the second epitaxial layer structure, the gate structure covering the sidewalls of the first epitaxial layer structure and the second epitaxial layer structure.

[0006] The present invention further provides a semiconductor structure, including: a substrate; a first epitaxial layer structure located on the substrate; a second epitaxial layer structure located on the substrate and adjacent to the first epitaxial layer structure; and a gate structure located between the first epitaxial layer structure and the second epitaxial layer structure and covering the sidewalls of the first epitaxial layer structure and the second epitaxial layer structure.

[0007] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0008] In the method for forming a semiconductor structure provided by the present invention, a first epitaxial layer structure and a second epitaxial layer structure are formed on the substrate. By arranging along the normal direction of the substrate, the sizes of the first epitaxial layer structure and the second epitaxial layer structure are reduced, and better doping density and uniformity are achieved. Thus, when at least one layer of the first epitaxial layer is used as the first channel layer and at least one layer of the second epitaxial layer is used as the second channel layer, the influence of the short channel effect can be reduced, and the gate structure is simultaneously in contact with the sidewalls of the first epitaxial layer structure and the second epitaxial layer structure. The first epitaxial layer structure and the second epitaxial layer structure share the gate structure, and therefore the size of the semiconductor structure can be reduced.

[0009] In the semiconductor structure provided by the present invention, by arranging along the normal direction of the substrate, the sizes of the first epitaxial layer structure and the second epitaxial layer structure are reduced, and it has better doping density and uniformity. Therefore, when at least one of the first epitaxial layers is used as the first channel layer and at least one of the second epitaxial layers is used as the second channel layer, the influence of the short-channel effect can be reduced, and the gate structure is simultaneously in contact with the sidewalls of the first epitaxial layer structure and the second epitaxial layer structure. The first epitaxial layer structure and the second epitaxial layer structure share the gate structure, so that the size of the semiconductor structure can be reduced. Description of the Drawings

[0010] Figures 1 to 17 Shows the structural schematic diagrams corresponding to the steps in an embodiment of the method for forming the semiconductor structure of the present invention. Detailed Description of the Invention

[0011] As described in the background art, limited by the process node, the size of the CMOS cannot be further reduced because: the cross-sectional size of the CMOS can be approximated as the cross-sectional size of the NMOS + isolation layer + PMOS. With the further reduction of the process node, limited by the lithography machine and etching process, the sizes of the conductive channels in the NMOS and PMOS cannot meet the process requirements, and blindly reducing the channel size will generate the short-channel effect, affecting the device quality, making the size of the CMOS unable to be further reduced.

[0012] To solve the above technical problems, the present invention provides a method for forming a semiconductor structure, including: providing a substrate; forming a first epitaxial layer structure and a second epitaxial layer structure on the substrate; forming a gate structure at the junction of the first epitaxial layer structure and the second epitaxial layer structure, and the gate structure covers the sidewalls of the first epitaxial layer structure and the second epitaxial layer structure.

[0013] Adopting the method for forming the semiconductor structure provided by the present invention, a first epitaxial layer structure and a second epitaxial layer structure are formed on the substrate. By arranging along the normal direction of the substrate, the sizes of the first epitaxial layer structure and the second epitaxial layer structure are reduced, and it has better doping density and uniformity. Therefore, when at least one of the first epitaxial layers is used as the first channel layer and at least one of the second epitaxial layers is used as the second channel layer, the influence of the short-channel effect can be reduced, and the gate structure is simultaneously in contact with the sidewalls of the first epitaxial layer structure and the second epitaxial layer structure. The first epitaxial layer structure and the second epitaxial layer structure share the gate structure, so that the size of the semiconductor structure can be reduced.

[0014] To make the above objects, features and advantages of the present invention more obvious and understandable, the present invention will be described by way of examples with reference to the accompanying drawings.

[0015] Figures 1 to 17 These are the schematic diagrams of the structures corresponding to the steps in an embodiment of the method for forming a semiconductor structure of the present invention. Among them, Figure 17 is a top view structural schematic diagram of the semiconductor structure in an embodiment of the present invention, Figure 11 and Figure 12 is Figure 17 a cross-sectional view along the A-A1 direction, Figure 13 and Figure 14 is Figure 17 a cross-sectional view along the B-B1 direction, Figure 15 and Figure 16 is Figure 17 a cross-sectional view along the C-C1 direction.

[0016] Refer to Figure 1 , and provide a substrate 100.

[0017] Provide a substrate 100. Among them, the semiconductor structure may include CMOS transistors.

[0018] In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate can also be other types of substrates such as a silicon-on-insulator substrate or a germanium-on-insulator substrate. The material of the substrate can be a material suitable for process requirements or easy to integrate.

[0019] The semiconductor substrate can also be a silicon-on-insulator structure, such as silicon-on-insulator (SOI), and can also be a germanium-on-insulator structure, such as germanium-on-insulator; the semiconductor substrate can also include an alloy semiconductor structure, such as GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or a combination thereof; the semiconductor substrate can also be a lightly doped substrate or a substrate with an epitaxial layer grown thereon.

[0020] Refer to Figures 1 to 7 , and form a first epitaxial layer structure 112 and a second epitaxial layer structure 124 on the substrate 100.

[0021] The first epitaxial layer structure 112 can serve as the source, drain, and channel layer in the first type of transistor.

[0022] And the first epitaxial layer structure 112 is laid out along the normal direction of the substrate 100, which can reduce the size of the epitaxial layer, is not limited by the lithography machine, and the source, drain, and channel layer are all located above the substrate 100, which can reduce the short-channel effect.

[0023] The second epitaxial layer structure 124 can serve as the source, drain, and channel layer in the second type of transistor.

[0024] Moreover, the second epitaxial layer structure 124 is arranged along the normal direction of the substrate 100, which can reduce the size of the epitaxial layer, is not limited by the lithography machine, and the source electrode, drain electrode, and channel layer are all located above the substrate 100, which can reduce the short-channel effect.

[0025] In this embodiment, the first epitaxial layer structure 112 and the second epitaxial layer structure 124 are adjacent to each other, and the doping types of the epitaxial layers corresponding to the adjacent positions are different.

[0026] For example, if the epitaxial layer in the first epitaxial layer structure 112 is doped with n-type ions, the epitaxial layer in the second epitaxial layer structure 124 is doped with p-type ions.

[0027] In this embodiment, the first type of transistor can be an NMOS transistor, and the second type of transistor can be a PMOS transistor. In some other embodiments, the first type of transistor can be a PMOS transistor, and the second type of transistor can be an NMOS transistor.

[0028] In this embodiment, an example is given for illustrative purposes where the first type of transistor can be an NMOS transistor and the second type of transistor can be a PMOS transistor.

[0029] In this embodiment, the first epitaxial layer structure 112 and the second epitaxial layer structure 124 are formed in different steps.

[0030] In a specific embodiment, after forming the first epitaxial layer structure 112, the second epitaxial layer structure 124 is formed.

[0031] Correspondingly, referring to Figures 1 to 7 , the forming method may include:

[0032] Referring to Figures 1 to 3 , a first shielding layer 104 is formed on the substrate 100, and the first shielding layer 104 exposes the surface of the substrate 100 for forming the first epitaxial layer structure 112.

[0033] In other words, the first shielding layer 104 exposes the area for forming the first epitaxial layer structure 112.

[0034] In this embodiment, the first shielding layer 104 is formed by a chemical vapor deposition process. The film layer formed by chemical vapor deposition is thin and uniform, and the structure is dense, which is beneficial to improving the coverage ability of the first shielding layer 104.

[0035] In this embodiment, the material of the first shielding layer 104 is silicon nitride.

[0036] Then referring to Figure 1, before forming the first shielding layer 104, a first covering layer 102 is formed, and the first covering layer 102 is located on the surface of the substrate 100 for forming the first epitaxial layer structure 112.

[0037] By pre-forming the first covering layer 102, it is possible to prevent the first shielding layer 104 from being formed on the substrate 100 for forming the first epitaxial layer structure 112.

[0038] In this embodiment, the first covering layer 102 needs to be removed subsequently, so the first covering layer 102 is made of a material that is easy to remove. For this purpose, in this embodiment, the material of the first covering layer 102 includes photoresist, amorphous carbon, organic dielectric layer material, bottom anti-reflection coating material, dielectric anti-reflection layer material, deep ultraviolet light-absorbing silicon oxide material, or silicon-containing anti-reflection coating material.

[0039] More specifically, after forming the first shielding layer 104 and before forming the first epitaxial layer structure 112, the first covering layer 102 is removed.

[0040] In this embodiment, the first covering layer 102 is removed through a cleaning process.

[0041] See Figure 4 , an epitaxial process is used to form multiple first epitaxial layers (as a non-limiting example, the number of first epitaxial layers is at least 3, for example, the first layer of the first epitaxial layer 106, the second layer of the first epitaxial layer 108, and the third layer of the first epitaxial layer 110), as the first epitaxial layer structure 112.

[0042] Each layer of the first epitaxial layer provides a process basis for the formation of film layers such as channel layers and source / drain doping layers. Or rather, the first epitaxial layer can be used as film layer structures with different or the same functions in a semiconductor structure.

[0043] In this embodiment, each layer of the first epitaxial layer is formed by an epitaxial process, and doping treatment is performed during the epitaxial growth process.

[0044] In other words, when forming any first epitaxial layer, doping operations are performed while the epitaxial process is being carried out. On the one hand, the process parameters of the epitaxial process are controllable, and first epitaxial layers with different thicknesses can be formed, thereby reducing the thickness of some or all of the first epitaxial layers; on the other hand, by synchronously performing the epitaxial process and doping operations, the first epitaxial layer formed by epitaxial growth has better doping density and uniformity, improving the uniformity of the doping concentration at different positions of the same first epitaxial layer, which is beneficial to reducing the short-channel effect.

[0045] In this embodiment, when forming each layer of the first epitaxial layer by epitaxial process, among any two adjacent first epitaxial layers, the upper first epitaxial layer takes the top surface of the lower first epitaxial layer as the growth basis, and the bottommost first epitaxial layer takes the top surface of the substrate as the growth basis.

[0046] In other words, the top surface of the substrate 100 serves as the growth basis of the entire semiconductor structure. The first layer of the first epitaxial layer 106 takes the top surface of the substrate 100 as the growth basis, and the subsequently formed second layer of the first epitaxial layer 108 takes the top surface of the first layer of the first epitaxial layer 106 as the growth basis.

[0047] Moreover, in this solution, the surface of the substrate 100 is relatively flat, making the surface of the first layer of the first epitaxial layer 106 flat. On this basis, the surface of any epitaxial layer is relatively flat, reducing the resistance at the interface between the first epitaxial layer 106 and the substrate 100, as well as the resistance at the interface between adjacent epitaxial layers, and improving the electrical performance of the semiconductor structure.

[0048] In this embodiment, the epitaxial process may include atomic layer deposition process or molecular beam epitaxy process.

[0049] In this embodiment, for any layer of the first epitaxial layer, the forming step may include: sequentially forming a plurality of sub-first epitaxial layers, and performing doping treatment in the step of forming any one sub-first epitaxial layer. Among them, in the steps of each sub-first epitaxial layer, the doping type and doping concentration are the same, so as to further improve the doping uniformity of the first epitaxial layer.

[0050] In this embodiment, each layer of the first epitaxial layer has its own doping type, so that the doping type between adjacent first epitaxial layers can be controlled. Among the three layers of the first epitaxial layer, the doping type of the middle epitaxial layer is different from that of the upper and lower epitaxial layers. In this way, an epitaxial structure with a conductive channel can be formed through the three epitaxial layers with the above doping characteristics, so as to enhance the control ability of the gate structure.

[0051] In this embodiment, the doping concentration of the first epitaxial layer directly affects parameters such as the conductivity and carrier mobility of the semiconductor structure. Therefore, the doping concentration of each layer of the first epitaxial layer can be set based on actual requirements, so that each layer of the first epitaxial layer has its own doping concentration, that is, different first epitaxial layers have the same or different doping concentrations.

[0052] In practical applications, the inventor further found that under the action of temperature, there is a diffusion phenomenon between adjacent first epitaxial layers, and the higher the temperature, the more serious the diffusion phenomenon. Driven by the diffusion effect, the doping ions between adjacent first epitaxial layers will undergo a transfer phenomenon, which will change the characteristics of some or all of the first epitaxial layers, significantly reducing the performance of the semiconductor structure, or the semiconductor structure cannot play its intended role.

[0053] As an example, when the doping concentrations of adjacent first epitaxial layers are different, due to the diffusion phenomenon, the doping concentration of the first epitaxial layer with a higher doping concentration may become lower, while the doping concentration of the first epitaxial layer with a lower doping concentration may increase.

[0054] As another example, when the doping types of adjacent first epitaxial layers are different, due to the diffusion phenomenon, the doping types of these two first epitaxial layers may become the same, resulting in the failure of the semiconductor structure.

[0055] In this embodiment, each layer of the first epitaxial layer and the second epitaxial layer is formed in a lower temperature environment.

[0056] In some embodiments, the formation temperature of each layer of the first epitaxial layer ranges from 600 degrees Celsius to 800 degrees Celsius. For example, 650 degrees Celsius, 700 degrees Celsius, 750 degrees Celsius, etc.

[0057] That is: the formation temperature of any epitaxial layer is not higher than 800 degrees Celsius, so that when forming the second layer and subsequent first epitaxial layers, the diffusion phenomenon is reduced or avoided, enabling each epitaxial layer to maintain its own characteristics and improving the performance of the semiconductor structure.

[0058] In this embodiment, the formation parameters of each layer of the first epitaxial layer may further include: the pressure is from 70 Torr to 90 Torr, the flow rate of Purge MinH2 is from 3200 sccm to 3800 sccm, the flow rate of Purge SlitH2 is from 80 sccm to 120 sccm, the flow rate of the silicon source gas is from 120 sccm to 180 sccm, and the epitaxial rate is at least one of from 200 angstroms per minute to 300 angstroms per minute.

[0059] In other words, by changing the formation temperature of the first epitaxial layer, the foregoing at least one parameter is adaptively adjusted, so that the silicon source gas used in the epitaxial process is adapted to the current temperature, and by reducing the epitaxial rate per unit time, the thickness uniformity of the same epitaxial layer can be improved, and the formation quality of the epitaxial layer can be improved. That is, while reducing the generation temperature, the epitaxial rate also decreases accordingly.

[0060] In this embodiment, the number of the first epitaxial layers is at least 3. By making the number of epitaxial layers greater than or equal to 3, at least a source electrode, a drain electrode, and a channel layer located between the source electrode and the drain electrode can be formed to function as current flow.

[0061] In this embodiment, when the number of epitaxial layers is greater than or equal to 3, the formation method of the semiconductor structure in this solution can satisfy:

[0062] The first first epitaxial layer 106, and the first epitaxial layer 106 is used to form the first source-drain doping layer.

[0063] The first source-drain doping layer can be used as the source or drain of a field-effect transistor. When the field-effect transistor is operating, the first source-drain doping layer can be used to provide a carrier source.

[0064] In this embodiment, when forming an NMOS transistor, the first epitaxial layer 106 of the first layer can include an epitaxial layer doped with N-type ions, and the material of this epitaxial layer can be Si or SiC; when forming a PMOS transistor, the first epitaxial layer 106 of the first layer can include an epitaxial layer doped with P-type ions, and the material of this epitaxial layer is Si or SiGe.

[0065] In a specific embodiment, the material of the first epitaxial layer 106 of the first layer can be Si.

[0066] The second first epitaxial layer 108, and the second first epitaxial layer 108 is used to form the first channel layer.

[0067] The first channel layer is used to provide a flow region for the carrier source.

[0068] In this embodiment, when forming an NMOS transistor, the first channel layer can include an epitaxial layer doped with P-type ions, and the material of the second first epitaxial layer 108 can be Si or SiGe; when forming a PMOS transistor, the first channel layer can include an epitaxial layer doped with N-type ions, and the material of the second first epitaxial layer 108 is Si or SiC.

[0069] In a specific embodiment, the material of the second first epitaxial layer 108 can be Si.

[0070] The third first epitaxial layer 110, and the third first epitaxial layer 110 is used to form the second source-drain doping layer.

[0071] The second source-drain doping layer can be used as the source or drain of a field-effect transistor. When the field-effect transistor is operating, the second source-drain doping layer can be used to provide a carrier source.

[0072] In this embodiment, when forming an NMOS transistor, the third first epitaxial layer 110 can include an epitaxial layer doped with N-type ions, and the material of the third first epitaxial layer 110 can be Si or SiC; when forming a PMOS transistor, the third first epitaxial layer 110 can include an epitaxial layer doped with P-type ions, and the material of the third first epitaxial layer 110 is Si or SiGe.

[0073] In a specific embodiment, the material of the third first epitaxial layer 110 can be Si.

[0074] It should be noted that, first, when the number of the first epitaxial layers is more (for example, greater than 3), adjacent first epitaxial layers play the same role. For example, two consecutive first epitaxial layers serve as source / drain doping layers. Second, the functions of the first first epitaxial layer, the second first epitaxial layer, and the third first epitaxial layer listed in the above examples are only for illustrative purposes, and are used to represent that among three consecutive epitaxial layers, they can serve as the basis for generating the source, drain, and channel layer located between the source and the drain in the semiconductor structure, and should not be construed as a limitation to the present invention.

[0075] In this embodiment, the first source / drain doping layer is one of the source or the drain, and the second source / drain doping layer is the other of the source or the drain.

[0076] In other words, one of the first source / drain doping layer and the second source / drain doping layer serves as the source, and the other serves as the drain.

[0077] For example, the first source / drain doping layer serves as the drain, and the second source / drain doping layer serves as the source. Also for example, the first source / drain doping layer serves as the drain, and the second source / drain doping layer serves as the source.

[0078] In this embodiment, the doping type of the first source / drain doping layer is different from that of the channel layer.

[0079] In a specific embodiment, the doping type of the first source / drain doping layer is N-type, and the doping type of the channel layer is P-type.

[0080] In a specific embodiment, the doping type of the first source / drain doping layer is P-type, and the doping type of the channel layer is N-type.

[0081] In this embodiment, the doping type of the second source / drain doping layer is different from that of the channel layer.

[0082] In a specific embodiment, the doping type of the second source / drain doping layer is N-type, and the doping type of the channel layer is P-type.

[0083] In a specific embodiment, the doping type of the second source / drain doping layer is P-type, and the doping type of the channel layer is N-type.

[0084] It should be noted that, first, this solution does not limit the doping types of the first source / drain doping layer, the second source / drain doping layer, and the channel layer, as long as the doping types of the first source / drain doping layer and the channel layer are different, and the doping types of the second source / drain doping layer and the channel layer are different. Second, in this solution, when the doping type is N-type, the doping ions may include: P, S, or Sb; when the doping type is P-type, the doping ions may include: B, Ga, or In.

[0085] In this embodiment, the doping types of the first source-drain doping layer and the second source-drain doping layer are the same and both are different from that of the first channel layer. When a voltage is applied to the gate structure, the carrier (electron or hole) concentration in the first channel layer region will increase significantly, so that the region adjacent to the gate structure in the channel layer is inverted to form a conductive channel. When a voltage is applied between the first source-drain doping layer and the second source-drain doping layer, the carriers start to move along the conductive channel under the action of the electric field to form a current.

[0086] In this embodiment, the doping concentration of the first source-drain doping layer is greater than that of the first channel layer. Under the same electric field strength, the first source-drain doping layer with a higher doping concentration can provide more carriers and has a stronger current conduction ability.

[0087] In some embodiments, the doping concentration of the first source-drain doping layer is 10 to 100 times that of the first channel layer.

[0088] By making the doping concentration of the first source-drain doping layer 10 to 100 times that of the first channel layer, the selection range of the doping concentration of the first source-drain doping layer is broadened, and a first source-drain doping layer adapted to the doping concentration of the channel layer can be formed based on the doping concentration of the channel layer.

[0089] In a specific embodiment, the doping concentration of the first source-drain doping layer can be 1E 14 om / cm 3 to 1E 15 tom / cm 3 . The doping concentration of the first channel layer can be 1E 12 tom / cm 3 to 1E 13 tom / cm 3 .

[0090] In this embodiment, the doping concentration of the second source-drain doping layer is greater than that of the first channel layer. Under the same electric field strength, the second source-drain doping layer with a higher doping concentration can provide more carriers and has a stronger current conduction ability.

[0091] In some embodiments, the doping concentration of the second source-drain doping layer is 10 to 100 times that of the first channel layer.

[0092] By making the doping concentration of the second source-drain doping layer 10 to 100 times that of the first channel layer, the selection range of the doping concentration of the second source-drain doping layer is broadened, and a second source-drain doping layer adapted to the doping concentration of the channel layer can be formed based on the doping concentration of the channel layer.

[0093] In a specific embodiment, the doping concentration of the second source-drain doping layer can be 1E 14 atom / cm 3 to 1E 15 atom / cm 3 . The doping concentration of the first channel layer can be 1E 12 atom / cm 3 to 1E 13 atom / cm 3 .

[0094] In this embodiment, the thickness of the first channel layer will directly affect the performance of the semiconductor structure, such as conductivity, current driving ability, and switching speed. For example, when the thickness of the first channel layer is relatively thin, the migration time of carriers in the channel layer can be reduced, improving conductivity.

[0095] And in this solution, the first channel layer is in direct contact with the first source-drain doping layer and the second source-drain doping layer, and the short-channel effect is not obvious. The thickness range value of the first channel layer has a large span, so it can be set based on process requirements to cope with different process nodes.

[0096] In a specific embodiment, the thickness of the channel layer is 10 nanometers to 50 nanometers. In this way, a process machine of a large technology node can be used to produce a channel layer equivalent to that of a smaller technology node, reducing the requirements for the process machine.

[0097] It should be noted that the thickness of the channel layer described in the above example is only for illustrative purposes. In the actual manufacturing process, the thickness of the channel layer can be appropriately reduced or increased. For example, the thickness of the channel layer can be 2 nanometers, 7 nanometers, etc.

[0098] In other words, in this solution, the epitaxial process is adopted, and the thickness of the first channel layer is controllable. According to the requirements of the semiconductor structure to be manufactured, by setting the parameters of the epitaxial process, the thickness of the first channel layer can meet the process requirements.

[0099] In this embodiment, the first source-drain doping layer or the second source-drain doping layer serves to provide carriers, and its influence on the performance of the semiconductor structure is less than that of the channel layer. The thickness of the first source-drain doping layer or the second source-drain doping layer can be greater than the thickness of the channel layer.

[0100] In addition, a relatively thick first source-drain doping layer or second source-drain doping layer can usually reduce the contact resistance between it and the channel layer, thereby improving the carrier injection efficiency and the conductivity of the device.

[0101] In a specific embodiment, the thickness of the first source-drain doping layer can be 500 angstroms to 1000 angstroms.

[0102] In a specific embodiment, the thickness of the second source-drain doping layer may be from 500 angstroms to 1000 angstroms.

[0103] Refer to Figure 5 and Figure 6 , remove the first mask layer 104 to expose the surface of the substrate 100 for forming the second epitaxial layer structure 124.

[0104] By removing the first mask layer 104, the substrate 100 on one side of the first epitaxial layer structure 112 can be exposed, facilitating the formation of the second epitaxial layer structure 124.

[0105] In this embodiment, before removing the first mask layer 104, the forming method further includes: forming a second mask layer 114 that covers the surfaces of the first mask layer 104 and the first epitaxial layer structure 112.

[0106] By forming the second mask layer 114, damage to the surface of the first epitaxial layer structure 112 can be avoided during the subsequent step of removing the first mask layer 104, improving the forming quality of the first epitaxial layer structure 112.

[0107] In this embodiment, for the forming method, material and other parameters of the second mask layer 114, reference can be made to the description of the first mask layer 104.

[0108] In some embodiments, after forming the second mask layer 114, a second covering layer 116 is further formed on the second mask layer 114, and the second covering layer 116 exposes the surface of the second mask layer 114 located on the first mask layer 104.

[0109] In this embodiment, for the forming method, material and other parameters of the second covering layer 116, reference can be made to the description of the first covering layer 102.

[0110] In the step of removing the first mask layer 104, the second mask layer 114 above the first mask layer 104 is also removed, thus completely exposing the surface of the substrate 100 for forming the second epitaxial layer structure 124.

[0111] It should be noted that since the second mask layer 114 on the first epitaxial layer structure 112 is covered by the second covering layer 116, when the first mask layer 104 is removed, the second mask layer 114 covered by the second covering layer 116 is retained. Therefore, after forming the second epitaxial layer structure 124, the second mask layer 114 on the first epitaxial layer structure 112 is also removed.

[0112] Refer to Figure 7, an epitaxial process is adopted to form multiple second epitaxial layers (as a non-limiting example, the number of second epitaxial layers is at least 3, for example, the first second epitaxial layer 118, the second second epitaxial layer 120, and the third second epitaxial layer 122), which serve as the second epitaxial layer structure 124.

[0113] The second epitaxial layer provides a process basis for the formation of film layers such as the channel layer and the source / drain doping layer. Or rather, the second epitaxial layer can serve as film layer structures with different or the same functions in a semiconductor structure.

[0114] In this embodiment, each second epitaxial layer is formed by an epitaxial process, and doping treatment is carried out during the epitaxial growth process. Among them, each second epitaxial layer has its own doping type and doping concentration.

[0115] Among them, for more descriptions about forming each second epitaxial layer by an epitaxial process, reference can be made to the content about the first epitaxial layer in the foregoing example.

[0116] In this embodiment, the formation temperature of each second epitaxial layer ranges from 600 degrees Celsius to 800 degrees Celsius.

[0117] Furthermore, the formation parameters of each second epitaxial layer further include: the pressure is from 70 Torr to 90 Torr, the flow rate of PurgeMainH2 is from 3200 sccm to 3800 sccm, the flow rate of Purge SlitH2 is from 80 sccm to 120 sccm, the flow rate of the silicon source gas is from 120 sccm to 180 sccm, and the epitaxial rate is at least one of from 200 angstroms per minute to 300 angstroms per minute.

[0118] In other words, by changing the formation temperature of the second epitaxial layer, the foregoing at least one parameter is adaptively adjusted, so that the silicon source gas used in the epitaxial process is adapted to the current temperature, and by reducing the epitaxial rate per unit time, the thickness uniformity of the same epitaxial layer can be improved, and the formation quality of the epitaxial layer can be improved. That is, when the generation temperature is reduced, the epitaxial rate also decreases accordingly.

[0119] In this embodiment, the number of second epitaxial layers is at least 3. By making the number of epitaxial layers greater than or equal to 3, at least a source electrode, a drain electrode, and a channel layer located between the source electrode and the drain electrode can be formed to play a role in current flow.

[0120] In this embodiment, when the number of epitaxial layers is greater than or equal to 3, the formation method of the semiconductor structure in this solution can satisfy:

[0121] The first second epitaxial layer 118, and the first second epitaxial layer 118 is used to form the third source / drain doping layer.

[0122] The second second epitaxial layer 120 is used to form a second channel layer.

[0123] The third second epitaxial layer 122 is used to form a fourth source / drain doping layer.

[0124] In this embodiment, the thickness of the third source / drain doping layer is 500 angstroms to 1000 angstroms; the doping concentration of the third source / drain doping layer is 1E 14 atom / cm 3 to 1E 15 atom / cm 3 。

[0125] The thickness of the fourth source / drain doping layer is 500 angstroms to 1000 angstroms; the doping concentration of the fourth source / drain doping layer is 1E 14 atom / cm 3 to 1E 15 atom / cm 3 。

[0126] The thickness of the second channel layer is 10 nanometers to 50 nanometers; the doping concentration of the second channel layer is 1E 12 atom / cm 3 to 1E 13 atom / cm 3 。

[0127] Among them, for a more detailed description of the third source / drain doping layer, the second channel layer, and the fourth source / drain doping layer, reference can be made to the foregoing description of the first epitaxial layer structure 112.

[0128] In some embodiments, the difference between the first epitaxial layer structure 112 and the second epitaxial layer structure 124 is only that: the types of doping ions in the contacting epitaxial layers are different.

[0129] In this embodiment, the sidewalls of each second epitaxial layer are in contact with the sidewalls of the corresponding first epitaxial layer.

[0130] It should be noted that the foregoing example is described by taking the formation of the first epitaxial layer structure first and then the second epitaxial layer structure as an example. In some other embodiments, after forming the second epitaxial layer structure, the first epitaxial layer structure is formed. Among them, for the specific formation process, reference can be made to Figures 1 to 7 's description, the difference is that: the second epitaxial layer structure is formed first, and then the first epitaxial layer structure is formed.

[0131] See Figures 8 to 10, at the junction of the first epitaxial layer structure 112 and the second epitaxial layer structure 124, a gate structure 130 is formed, and the gate structure 130 covers the sidewalls of the first epitaxial layer structure 112 and the second epitaxial layer structure 124.

[0132] In other words, between the first epitaxial layer structure 112 and the second epitaxial layer structure 124, a gate structure 130 is formed. The gate structure 130 is adjacent to the first epitaxial layer structure 112 and the second epitaxial layer structure 124 respectively, and covers the sidewalls of the first epitaxial layer structure 112 and the second epitaxial layer structure 124.

[0133] By sharing the gate structure 130 between the first epitaxial layer structure 112 and the second epitaxial layer structure 124, the lateral dimension of the semiconductor device along the surface parallel to the substrate 100 is reduced, and thus the overall size of the semiconductor device can be reduced.

[0134] When the device is operating, the gate structure 130 is used to control the opening and closing of the conductive channel.

[0135] In this embodiment, the gate structure 130 is a polysilicon gate structure or an amorphous silicon gate structure.

[0136] In this embodiment, the steps of forming the gate structure 130 include: forming a gate opening K at the junction of the first epitaxial layer structure 112 and the second epitaxial layer structure 124. The gate opening K exposes the surface of the substrate 100, as well as the sidewalls of the first epitaxial layer structure 112 and the second epitaxial layer structure 124.

[0137] Among them, the gate opening K is formed by patterning.

[0138] A gate material layer 128 is formed to cover the surfaces of the first epitaxial layer structure 112 and the second epitaxial layer structure 124 and fill the gate opening K.

[0139] The gate material layer 128 is used to form the gate structure 130.

[0140] In this embodiment, the gate material layer 128 is formed by chemical vapor deposition process. The film layer formed by chemical vapor deposition is thin and uniform, and the structure is dense, which is beneficial to improving the formation quality of the gate material layer 128.

[0141] In a specific embodiment, the chemical vapor deposition process may be low-pressure chemical vapor deposition (LPCVD).

[0142] The gate material layer 128 above the top of the gate opening K is removed, and the gate material layer 128 remaining in the gate opening K is used as the gate structure 130.

[0143] In this embodiment, the gate material layer above the topmost epitaxial layer is removed by a planarization process (e.g., chemical mechanical polishing CMP).

[0144] It should be noted that during the formation of the gate structure 130, the process temperature should not exceed 800 degrees Celsius. Or rather, the process temperature of the gate structure 130 should be lower than the process temperatures of the first epitaxial layer and the second epitaxial layer.

[0145] In this embodiment, before forming the gate structure, the forming method further includes: forming a gate oxide layer 126 that covers the surfaces of the first epitaxial layer structure 112 and the second epitaxial layer structure 124, as well as the sidewalls of the gate opening.

[0146] The gate oxide layer 126, as an insulating layer, realizes the isolation between the gate structure 130 and the substrate 100, prevents leakage between the gate structure 130 and the first channel and the second channel, and improves the voltage control characteristics.

[0147] In this embodiment, the material of the gate oxide layer 126 includes silicon oxide.

[0148] In this embodiment, a furnace tube process is used to form the gate oxide layer 126.

[0149] It should be noted that during the process of removing the gate material layer 128 above the top of the gate opening K, the gate oxide layer 128 on the first epitaxial layer structure 112 and the second epitaxial layer structure 124 is also removed.

[0150] In this embodiment, after forming the gate structure, a conductive structure can also be formed to lead out the gate structure and the corresponding film layers in the first epitaxial layer structure and the second epitaxial layer structure.

[0151] Specifically, for each first epitaxial layer in some or all of the first epitaxial layer structures, at least one first conductive structure is formed, and each first conductive structure is electrically connected to the corresponding first epitaxial layer.

[0152] In this embodiment, along the normal direction of the substrate surface, multiple first epitaxial layers are stacked. When forming the first conductive structure, there is a case where the first conductive structure is electrically connected to at least two first epitaxial layers. In this case, during the formation of the first conductive structure, the first conductive structure needs to be electrically insulated from the non - electrically - connected epitaxial layers to avoid short - circuit problems caused by the first conductive structure being electrically connected to at least two epitaxial layers.

[0153] The first conductive structure can realize the electrical connection between the first epitaxial layer and other interconnect structures or external circuits.

[0154] To facilitate understanding of the formation process of the first conductive structure in this solution, refer to Figures 11 to 17 , and a brief description is given through an example.

[0155] The steps of forming at least one first conductive structure 138 include:

[0156] Form a first trench G11, and the first trench G11 exposes at least a part of the sidewall of the first epitaxial layer electrically connected to the first conductive structure 138 (in this embodiment, the first conductive structure 138 is electrically connected to the third first epitaxial layer 110).

[0157] In this embodiment, the steps of forming the first trench G11 may include: forming an interlayer dielectric layer 132 on the substrate 100; removing a part of the interlayer dielectric layer 132 to expose the surface of the top first epitaxial layer (in this embodiment, the top first epitaxial layer is the third first epitaxial layer 110); removing a part of the thickness of the third first epitaxial layer 110 to form the first trench G11.

[0158] Among them, the first trench G11 is at least composed of the sidewall and the bottom of the third first epitaxial layer 110, and optionally, also includes the sidewall of the interlayer dielectric layer 132.

[0159] In this embodiment, the interlayer dielectric layer 132 is used to achieve electrical isolation between the first conductive structure, the second conductive structure, the third conductive structure, and the fourth conductive structure, and is also used to achieve electrical isolation between adjacent devices.

[0160] In this embodiment, the material of the interlayer dielectric layer 132 is an insulating material. For example, the material of the interlayer dielectric layer 132 is silicon oxide. In other embodiments, the material of the interlayer dielectric layer may also be other dielectric materials such as silicon nitride or silicon oxynitride.

[0161] Form a first insulating layer 134 on the sidewall of the first trench G11.

[0162] By forming the first insulating layer 134, only the bottom of the first trench G11 is exposed, so that the subsequently formed first conductive plug 136 is only electrically connected to the third first epitaxial layer 110, reducing the probability of short circuit.

[0163] In this embodiment, the steps of forming the first insulating layer 134 include: forming a first insulating material layer in the first trench G11; removing the insulating material layer located at the bottom of the first trench G11, and using the remaining part of the first insulating material layer as the first insulating layer 134.

[0164] In a specific implementation, a conformal coating process is used to form the first insulating material layer, and an etch-back process is used to remove the insulating material layer located at the bottom of the first trench G11.

[0165] In this embodiment, the material of the first insulating layer 134 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, boron nitride, and boron carbonitride.

[0166] At least a first conductive plug 136 is formed in the remaining space of the first trench G11. The first conductive plug 136 is electrically connected to the first epitaxial layer (e.g., the third-layer first epitaxial layer 110). The first conductive plug 136 and the first insulating layer 134 serve as the first conductive structure 138.

[0167] In other words, the sidewall of the third-layer first epitaxial layer 110 is covered by the first insulating layer 134, and the first conductive plug 136 is in contact with the top surface of the third-layer first epitaxial layer 110 to lead out the third-layer first epitaxial layer 110.

[0168] In this embodiment, the depth of the first conductive plug 136 in the third-layer first epitaxial layer 110 is 1 / 2 to 2 / 3 of the thickness of the third-layer first epitaxial layer 110. On the one hand, by making the depth of the first conductive plug 136 in the third-layer first epitaxial layer 110 not exceed 2 / 3 of the thickness of the third-layer first epitaxial layer 110, the isolation degree between the first conductive plug 136 and the underlying device is improved, and the formation difficulty is reduced. On the other hand, by making the depth of the first conductive plug 136 in the third-layer first epitaxial layer 110 not less than 1 / 2 of the thickness of the third-layer first epitaxial layer 110, the distance between the bottom of the first conductive plug 136 and the top of the first epitaxial layer 102 is appropriate, and the first conductive plug 136 is only electrically connected to the third-layer first epitaxial layer 110.

[0169] In this embodiment, the material of the first conductive plug 136 includes conductive materials with good conductivity such as cobalt, copper, aluminum, or tungsten.

[0170] It should be noted that when the epitaxial layer is the topmost epitaxial layer, the first conductive structure 138 can be directly formed in the first trench G11.

[0171] Similarly, for the description of forming the first conductive structure 144 electrically connected to the second-layer first epitaxial layer 108, reference can be made to the foregoing example. The difference is that:

[0172] The first trench G13 is at least composed of the sidewalls of the third-layer first epitaxial layer 110, the sidewalls and the bottom of the second-layer first epitaxial layer 108, and optionally, also includes the sidewalls of the interlayer dielectric layer 132.

[0173] In other words, the bottom of the first trench G13 is located in the second-layer first epitaxial layer 108.

[0174] Correspondingly, the first conductive structure 144 is composed of a first insulating structure 140 and a first conductive plug 142.

[0175] In this embodiment, the reason for leading out the second first epitaxial layer 108 through the first conductive structure 144 is as follows. On the one hand, the second first epitaxial layer 108 is used as a channel layer, and the second first epitaxial layer 108 does not contact the substrate 100, so the substrate 100 cannot be used as a discharge channel for the second first epitaxial layer 108. On the other hand, referring to Figure 17 , in the first conductive structure, there is an overlap along the length direction of the gate structure, the distance between the first conductive structures is relatively close, and there is a problem of charge accumulation in the second first epitaxial layer 108. For the above two reasons, by providing the first conductive structure 144 electrically connected to the second first epitaxial layer 108, the charges in the second first epitaxial layer 108 can be extracted.

[0176] In addition, the first conductive structure 144 can be used as a ground terminal to provide a reference benchmark value for the entire semiconductor structure.

[0177] Similarly, for the description of forming the first conductive structure 150 electrically connected to the first first epitaxial layer 106, reference can be made to the foregoing example. The difference is that:

[0178] The first trench G12 is at least composed of the sidewalls of the third first epitaxial layer 110, the sidewalls of the second first epitaxial layer 108, and the sidewalls and bottom of the first first epitaxial layer 106, and optionally, further includes the sidewalls of the interlayer dielectric layer 132.

[0179] In other words, the bottom of the first trench G12 is located within the first first epitaxial layer 106.

[0180] Correspondingly, the first conductive structure 150 is composed of a first insulating structure 146 and a first conductive plug 148.

[0181] In this embodiment, for each second epitaxial layer in part or all of the second epitaxial layer structures, at least one second conductive structure is formed, and each second conductive structure is electrically connected to the corresponding second epitaxial layer.

[0182] In this embodiment, along the normal direction of the substrate surface, the multiple second epitaxial layers are stacked. When forming the second conductive structure, there is a situation where the second conductive structure is electrically connected to at least two second epitaxial layers. In this case, during the formation of the second conductive structure, the second conductive structure needs to be electrically insulated from the non-electrically connected epitaxial layers to avoid short-circuit problems caused by the second conductive structure being electrically connected to at least two epitaxial layers.

[0183] The second conductive structure can realize the electrical connection between the second epitaxial layer and other interconnection structures or external circuits.

[0184] As an example, referring to Figures 11 to 17, which will be briefly described by an example.

[0185] The step of forming at least one second conductive structure 156 may include:

[0186] Forming a second trench G21, where the second trench G21 exposes at least a part of the sidewall of the top second epitaxial layer (in this embodiment, the second conductive structure 156 is electrically connected to the third second epitaxial layer 122) that is electrically connected to the second conductive structure 156.

[0187] In this embodiment, the step of forming the second trench G21 may include: forming an interlayer dielectric layer 132 on the substrate 100; removing a part of the interlayer dielectric layer 132 to expose the surface of the top second epitaxial layer (in this embodiment, the top second epitaxial layer is the third second epitaxial layer 122); removing a part of the thickness of the third second epitaxial layer 122 to form the second trench G21.

[0188] Wherein, the second trench G21 is at least composed of the sidewall and the bottom of the third second epitaxial layer 122, and optionally, further includes the sidewall of the interlayer dielectric layer 132.

[0189] Forming a second insulating layer 152 on the sidewall of the second trench G21.

[0190] By forming the second insulating layer 152, only the bottom of the second trench G21 is exposed, so that the subsequently formed second conductive plug 154 is only electrically connected to the third second epitaxial layer 122, reducing the probability of short circuit.

[0191] In this embodiment, the step of forming the second insulating layer 152 includes: forming a second insulating material layer in the second trench G21; removing the insulating material layer located at the bottom of the second trench G21, and taking the remaining part of the second insulating material layer as the second insulating layer 152.

[0192] In a specific implementation, a conformal coating process is used to form the second insulating material layer, and an etch-back process is used to remove the insulating material layer located at the bottom of the second trench G21.

[0193] In this embodiment, the material of the second insulating layer 152 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, boron nitride, and carbon boron nitride.

[0194] Forming at least a second conductive plug 154 in the remaining space of the second trench G21, where the second conductive plug 154 is electrically connected to the second epitaxial layer (for example, the third second epitaxial layer 122), and the second conductive plug 154 and the second insulating layer 152 serve as the second conductive structure 156.

[0195] In other words, the sidewalls of the second epitaxial layer 122 of the third layer are covered by the second insulating layer 152, and the second conductive plug 172 is in contact with the top surface of the second epitaxial layer 122 of the third layer to lead out the second epitaxial layer 122 of the third layer.

[0196] In this embodiment, the material of the second conductive plug 172 includes materials with good conductivity such as cobalt, copper, aluminum, or tungsten.

[0197] It should be noted that when the epitaxial layer is the topmost epitaxial layer, the second conductive structure 156 can be directly formed in the second trench G21.

[0198] Similarly, for the description of forming the second conductive structure 162 electrically connected to the second epitaxial layer 120 of the second layer, reference can be made to the foregoing example. The difference is that:

[0199] The second trench G23 is at least composed of the sidewalls of the second epitaxial layer 122 of the third layer, the sidewalls of the second epitaxial layer 120 of the second layer, and the bottom, and optionally, also includes the sidewalls of the interlayer dielectric layer 132.

[0200] In other words, the bottom of the second trench G23 is located within the second epitaxial layer 120 of the second layer.

[0201] Correspondingly, the second conductive structure 162 is composed of a second insulating structure 158 and a second conductive plug 160.

[0202] In this embodiment, the reason for leading out the second epitaxial layer 120 of the second layer through the second conductive structure 162 is that, on the one hand, the second epitaxial layer 120 of the second layer is used as a channel layer, and the second epitaxial layer 120 of the second layer does not contact the substrate 100, so the substrate 100 cannot be used as a discharge channel for the second epitaxial layer 120 of the second layer; on the other hand, referring to Figure 17 , in the first conductive structure, there is an overlap along the length direction of the gate structure, the distance between the second conductive structures is relatively close, and there is a problem of charge accumulation in the second epitaxial layer 120 of the second layer. For the above two reasons, by providing the second conductive structure 162 electrically connected to the second epitaxial layer 120 of the second layer, the charge in the second epitaxial layer 120 of the second layer can be extracted.

[0203] In addition, the second conductive structure 162 can be used as a ground terminal to provide a reference reference value for the entire semiconductor structure.

[0204] Similarly, for the description of forming the second conductive structure 168 electrically connected to the second epitaxial layer 118 of the first layer, reference can be made to the foregoing example. The difference is that: the second trench G22 is at least composed of the sidewalls of the second epitaxial layer 122 of the third layer, the sidewalls of the second epitaxial layer 120 of the second layer, and the sidewalls and bottom of the second epitaxial layer 118 of the first layer, and optionally, also includes the sidewalls of the interlayer dielectric layer 132.

[0205] In other words, the bottom of the second trench G22 is located within the second epitaxial layer 118 of the first layer.

[0206] Correspondingly, the second conductive structure 168 is composed of a second insulating structure 164 and a second conductive plug 166.

[0207] In this embodiment, a third conductive structure 170 is formed, and the third conductive structure 170 is electrically connected to the gate structure 130.

[0208] Among them, the method of forming the third conductive structure 170 may include: forming a third trench G3; forming the third conductive structure 170 within the third trench G3.

[0209] It should be noted that when forming the third conductive structure 170, a part of the gate structure 130 is also removed.

[0210] It should be noted that Figures 11 to 17 The processes of the first conductive structure, the second conductive structure, and the third conductive structure shown are only illustrative examples and should not be construed as limitations on the present invention.

[0211] It should be noted that the above description presents multiple embodiment solutions provided by the embodiments of the present disclosure. Each optional manner introduced in each embodiment solution can be combined and cross-referenced with each other without conflict, thereby extending a variety of possible embodiment solutions, and all of these can be considered as the embodiment solutions disclosed and made public by the present disclosure.

[0212] The present invention also provides a semiconductor structure. Refer to Figures 11 to 17 , the semiconductor structure includes: a substrate 100; a first epitaxial layer structure 112 located on the substrate 100; a second epitaxial layer structure 124 located on the substrate 100; a gate structure 130 located between the first epitaxial layer structure 112 and the second epitaxial layer structure 124 and covering the sidewalls of the first epitaxial layer structure 112 and the second epitaxial layer structure 124.

[0213] The substrate 100 can provide a process operation basis for the formation process of the semiconductor structure. Among them, the semiconductor structure may include CMOS transistors.

[0214] In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium, and the substrate can also be other types of substrates such as a silicon-on-insulator substrate or a germanium-on-insulator substrate. The material of the substrate can be a material suitable for process requirements or easy to integrate.

[0215] The semiconductor substrate may also be a silicon-on-insulator structure, such as silicon-on-insulator (SOI), or a germanium-on-insulator structure, such as germanium-on-insulator; the semiconductor substrate may also include an alloy semiconductor structure, such as GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or a combination thereof; the semiconductor substrate may also be a lightly doped substrate or a substrate with an epitaxial layer grown thereon.

[0216] The first epitaxial layer structure 112 can serve as the source, drain, and channel layer in the first type of transistor, and the second epitaxial layer structure 124 can serve as the source, drain, and channel layer in the second type of transistor.

[0217] Moreover, both the first epitaxial layer structure 112 and the second epitaxial layer structure 124 are arranged along the normal direction of the substrate 100, which can reduce the size of the epitaxial layer without being restricted by the lithography machine, and the source, drain, and channel layers are all located above the substrate 100, which can reduce the short-channel effect.

[0218] In this embodiment, the first type of transistor may be an NMOS transistor, and the second type of transistor may be a PMOS transistor. In some other embodiments, the first type of transistor may be a PMOS transistor, and the second type of transistor may be an NMOS transistor.

[0219] In this embodiment, an example is given for illustrative purposes where the first type of transistor is an NMOS transistor and the second type of transistor is a PMOS transistor.

[0220] In this embodiment, the number of epitaxial layers in the first epitaxial layer structure 112 is at least 3.

[0221] As a specific embodiment, the first epitaxial layer structure 112 may include a first layer of the first epitaxial layer 106 stacked in sequence along the normal direction of the substrate, and the first layer of the first epitaxial layer 106 serves as the first source / drain doping layer.

[0222] The first source / drain doping layer can be used as the source or drain of a field-effect transistor, and when the field-effect transistor is operating, the first source / drain doping layer can be used to provide a carrier source.

[0223] In this embodiment, when forming an NMOS transistor, the first layer of the first epitaxial layer 106 may include an epitaxial layer doped with N-type ions, and the material of this epitaxial layer may be Si or SiC; when forming a PMOS transistor, the first layer of the first epitaxial layer 106 may include an epitaxial layer doped with P-type ions, and the material of this epitaxial layer is Si or SiGe.

[0224] In a specific embodiment, the material of the first layer of the first epitaxial layer 106 may be Si.

[0225] The first epitaxial layer 108 of the second layer, and the first epitaxial layer 108 of the second layer serves as the first channel layer.

[0226] The first channel layer is used to provide a flow region for the carrier source.

[0227] In this embodiment, when forming an NMOS transistor, the first channel layer may include an epitaxial layer doped with P-type ions, and the material of the first epitaxial layer 108 of the second layer may be Si or SiGe; when forming a PMOS transistor, the first channel layer may include an epitaxial layer doped with N-type ions, and the material of the first epitaxial layer 108 of the second layer is Si or SiC.

[0228] In a specific embodiment, the material of the first epitaxial layer 108 of the second layer may be Si.

[0229] The first epitaxial layer 110 of the third layer, and the first epitaxial layer 110 of the third layer serves as the second source / drain doping layer.

[0230] The second source / drain doping layer can be used as the source or drain of the field effect transistor, and when the field effect transistor is working, the second source / drain doping layer can be used to provide the carrier source.

[0231] In this embodiment, when forming an NMOS transistor, the first epitaxial layer 110 of the third layer may include an epitaxial layer doped with N-type ions, and the material of the first epitaxial layer 110 of the third layer may be Si or SiC; when forming a PMOS transistor, the first epitaxial layer 110 of the third layer may include an epitaxial layer doped with P-type ions, and the material of the first epitaxial layer 110 of the third layer is Si or SiGe.

[0232] In a specific embodiment, the material of the first epitaxial layer 110 of the third layer may be Si.

[0233] It should be noted that, first, when the number of the first epitaxial layers is more (for example, greater than 3), there are adjacent first epitaxial layers that play the same role, such as two consecutive first epitaxial layers serving as the source / drain doping layer; second, the functions of the first epitaxial layer of the first layer, the first epitaxial layer of the second layer, and the first epitaxial layer of the third layer listed in the above examples are only for illustrative purposes, and are used to represent that among three consecutive epitaxial layers, they can serve as the basis for generating the source, drain, and the channel layer located between the source and the drain in the semiconductor structure, and should not be construed as a limitation of the present invention.

[0234] In this embodiment, the first source / drain doping layer is one of the source or the drain, and the second source / drain doping layer is the other of the source or the drain.

[0235] In other words, one of the first source / drain doping layer and the second source / drain doping layer serves as the source electrode, and the other serves as the drain electrode.

[0236] In this embodiment, the doping type of the first source / drain doping layer is different from that of the channel layer.

[0237] In a specific embodiment, the doping type of the first source / drain doping layer is N-type, and the doping type of the channel layer is P-type.

[0238] In a specific embodiment, the doping type of the first source / drain doping layer is P-type, and the doping type of the channel layer is N-type.

[0239] In this embodiment, the doping type of the second source / drain doping layer is different from that of the channel layer.

[0240] In a specific embodiment, the doping type of the second source / drain doping layer is N-type, and the doping type of the channel layer is P-type.

[0241] In a specific embodiment, the doping type of the second source / drain doping layer is P-type, and the doping type of the channel layer is N-type.

[0242] It should be noted that, first, this solution does not limit the doping types of the first source / drain doping layer, the second source / drain doping layer, and the channel layer. As long as the doping types of the first source / drain doping layer and the channel layer are different, and the doping types of the second source / drain doping layer and the channel layer are different; second, in this solution, when the doping type is N-type, the doping ions may include: P, As, or Sb; when the doping type is P-type, the doping ions may include: B, Ga, or In.

[0243] In this embodiment, the doping types of the first source / drain doping layer and the second source / drain doping layer are the same and are both different from the first channel layer. When a voltage is applied to the gate structure, the carrier (electron or hole) concentration in the first channel layer region will increase significantly, so that the region adjacent to the gate structure in the channel layer is inverted to form a conductive channel. When a voltage is applied between the first source / drain doping layer and the second source / drain doping layer, the carriers start to move along the conductive channel under the action of the electric field to form a current.

[0244] In this embodiment, the doping concentration of the first source / drain doping layer is greater than that of the first channel layer. Under the same electric field strength, the first source / drain doping layer with a higher doping concentration can provide more carriers, and the current conduction ability is stronger.

[0245] In some embodiments, the doping concentration of the first source / drain doping layer is 10 to 100 times that of the first channel layer.

[0246] By making the doping concentration of the first source-drain doping layer 10 to 100 times that of the first channel layer, the selection range of the doping concentration of the first source-drain doping layer is broadened, and a first source-drain doping layer adapted to the doping concentration of the channel layer can be formed based on the doping concentration of the channel layer.

[0247] In a specific embodiment, the doping concentration of the first source-drain doping layer can be 1E 14 atom / cm 3 to 1E 15 atom / cm 3 . The doping concentration of the first channel layer can be 1E 12 atom / cm 3 to 1E 13 atom / cm 3 .

[0248] In this embodiment, the doping concentration of the second source-drain doping layer is greater than that of the first channel layer. Under the same electric field strength, the second source-drain doping layer with a higher doping concentration can provide more carriers and has a stronger current conduction ability.

[0249] In some embodiments, the doping concentration of the second source-drain doping layer is 10 to 100 times that of the first channel layer.

[0250] By making the doping concentration of the second source-drain doping layer 10 to 100 times that of the first channel layer, the selection range of the doping concentration of the second source-drain doping layer is broadened, and a second source-drain doping layer adapted to the doping concentration of the channel layer can be formed based on the doping concentration of the channel layer.

[0251] In a specific embodiment, the doping concentration of the second source-drain doping layer can be 1E 14 atom / cm 3 to 1E 15 atom / cm 3 . The doping concentration of the first channel layer can be 1E 12 atom / cm 3 to 1E 13 atom / cm 3 .

[0252] In this embodiment, the thickness of the first channel layer will directly affect the performance of the semiconductor structure such as conductivity, current driving ability, and switching speed. For example, when the thickness of the first channel layer is relatively thin, the migration time of carriers in the channel layer can be reduced, improving conductivity.

[0253] Moreover, in this solution, the first channel layer is in direct contact with the first source / drain doping layer and the second source / drain doping layer, and the short-channel effect is not obvious. The thickness range of the first channel layer has a relatively large span, so it can be set based on process requirements to cope with different process nodes.

[0254] In a specific embodiment, the thickness of the first channel layer is 10 nanometers to 50 nanometers. In this way, a process machine of a large technology node can be used to produce a channel layer equivalent to that of a smaller technology node, reducing the requirements for the process machine.

[0255] It should be noted that the thickness of the channel layer described in the above example is only for illustrative purposes. In the actual manufacturing process, the thickness of the channel layer can be appropriately reduced or increased. For example, the thickness of the channel layer can be 2 nanometers, 7 nanometers, etc.

[0256] In other words, in this solution, the epitaxial process is adopted, and the thickness of the first channel layer is controllable. According to the requirements of the semiconductor structure to be manufactured, by setting the parameters of the epitaxial process, the thickness of the first channel layer can meet the process requirements.

[0257] In this embodiment, the first source / drain doping layer or the second source / drain doping layer serves to provide carriers, and its influence on the performance of the semiconductor structure is less than that of the channel layer on the performance of the semiconductor structure. The thickness of the first source / drain doping layer or the second source / drain doping layer can be greater than the thickness of the channel layer.

[0258] In addition, a relatively thick first source / drain doping layer or second source / drain doping layer can usually reduce the contact resistance between it and the channel layer, thereby improving the carrier injection efficiency and the conductivity of the device.

[0259] In a specific embodiment, the thickness of the first source / drain doping layer can be 500 angstroms to 1000 angstroms.

[0260] In a specific embodiment, the thickness of the second source / drain doping layer can be 500 angstroms to 1000 angstroms.

[0261] In this embodiment, the number of the second epitaxial layers in the second epitaxial layer structure 124 is at least 3.

[0262] As a specific embodiment, the second epitaxial layer structure 124 may include a first layer of second epitaxial layer 118 stacked in sequence along the normal direction of the substrate. The first layer of second epitaxial layer 118 serves as the third source / drain doping layer; a second layer of second epitaxial layer 120, and the second layer of second epitaxial layer 120 serves as the second source / drain doping layer; a third layer of second epitaxial layer 122, and the third layer of second epitaxial layer 122 serves as the fourth source / drain doping layer.

[0263] In this embodiment, the first source / drain doping layer is one of the source or drain, and the second source / drain doping layer is the other of the source or drain.

[0264] In this embodiment, the thickness of the third source / drain doping layer is 500 angstroms to 1000 angstroms; the doping concentration of the third source / drain doping layer is 1E 14 atom / cm 3 to 1E 15 atom / cm 3 。

[0265] The thickness of the fourth source / drain doping layer is 500 angstroms to 1000 angstroms; the doping concentration of the fourth source / drain doping layer is 1E 14 atom / cm 3 to 1E 15 atom / cm 3 。

[0266] The thickness of the second channel layer is 10 nanometers to 50 nanometers; the doping concentration of the second channel layer is 1E 12 atom / cm 3 to 1E 13 atom / cm 3 。

[0267] Among them, for a more detailed description of the third source / drain doping layer, the second channel layer, and the fourth source / drain doping layer, reference can be made to the foregoing description of the first epitaxial layer structure 112. In this embodiment, the semiconductor structure may further include: a second barrier layer located between any adjacent second epitaxial layers in the second epitaxial layer structure.

[0268] During device operation, the gate structure 130 is used to control the opening and closing of the first conductive channel.

[0269] During device operation, the gate structure 130 is used to control the opening and closing of the conductive channel.

[0270] In this embodiment, the gate structure 130 is a polysilicon gate structure or an amorphous silicon gate structure.

[0271] In this embodiment, the semiconductor structure may further include: a gate oxide layer 128 that covers the sidewalls of the first epitaxial layer structure 112 and the second epitaxial layer structure 124, as well as the surface of the substrate 100.

[0272] Correspondingly, the gate structure 130 may further cover the sidewalls and the bottom of the gate oxide layer 128.

[0273] The gate oxide layer acts as an insulating layer, achieving isolation between the gate structure 130 and the substrate 100, preventing leakage between the gate structure 130 and the first and second channels, and improving voltage control characteristics.

[0274] In this embodiment, the semiconductor structure may further include: at least one first conductive structure electrically connected to a corresponding first epitaxial layer.

[0275] As an optional example, the semiconductor structure may include: a first conductive structure 138 electrically connected to the third-layer first epitaxial layer 110.

[0276] In this embodiment, the first conductive structure 138 includes: a first insulating layer 134 covering a part of the sidewalls of the third-layer first epitaxial layer 110 and exposing the surface of the third-layer first epitaxial layer 110; a first conductive plug 136 covering the sidewalls of the first insulating layer 134 and contacting the surface of the third-layer first epitaxial layer 110.

[0277] In this embodiment, the material of the first insulating layer 134 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, boron nitride, and boron carbonitride.

[0278] The material of the first conductive plug 136 includes a material with good conductivity such as cobalt, copper, aluminum, or tungsten.

[0279] A first conductive structure 144 electrically connected to the second-layer first epitaxial layer 108.

[0280] In this embodiment, the first conductive structure 144 may include: a first insulating structure 140 covering the sidewalls of the third-layer first epitaxial layer 110 and a part of the sidewalls of the second-layer first epitaxial layer 108 and exposing the surface of the second-layer first epitaxial layer 108; a first conductive plug 142 covering the sidewalls of the first insulating structure 140 and contacting the surface of the second-layer first epitaxial layer 108.

[0281] In this embodiment, the reason for leading out the second-layer first epitaxial layer 108 through the first conductive structure 144 is that, on the one hand, the second-layer first epitaxial layer 108 is used as a channel layer, and the second-layer first epitaxial layer 108 does not contact the substrate 100, so the substrate 100 cannot serve as a discharge channel for the second-layer first epitaxial layer 108; on the other hand, referring to Figure 17 , the first conductive structures overlap with each other along the length direction of the gate structure, and the distance between the first conductive structures is relatively close, resulting in a charge accumulation problem in the second-layer first epitaxial layer 108. For the above two reasons, by providing the first conductive structure 144 electrically connected to the second-layer first epitaxial layer 108, the charges in the second-layer first epitaxial layer 108 can be extracted.

[0282] In addition, the first conductive structure 144 can be used as a ground terminal to provide a reference value for the entire semiconductor structure.

[0283] The first conductive structure 150 is electrically connected to the first epitaxial layer 106 of the first layer.

[0284] In this embodiment, the first conductive structure 150 may include: a first insulating structure 146 that covers the sidewalls of the third first epitaxial layer 110, the sidewalls of the second first epitaxial layer 108, and a part of the first first epitaxial layer 106, and exposes the surface of the first first epitaxial layer 106; a first conductive plug 148 that covers the sidewalls of the first insulating structure 146 and is in contact with the surface of the first first epitaxial layer 106.

[0285] In this embodiment, the semiconductor structure may further include: at least one second conductive structure that is electrically connected to a corresponding second epitaxial layer.

[0286] As an optional example, the semiconductor structure may include: a second conductive structure 156 that is electrically connected to the third second epitaxial layer 122.

[0287] In this embodiment, the second conductive structure 156 includes: a second insulating layer 152 that covers a part of the sidewalls of the third second epitaxial layer 122 and exposes the surface of the third second epitaxial layer 122; a second conductive plug 154 that covers the sidewalls of the second insulating layer 152 and is in contact with the surface of the third second epitaxial layer 122.

[0288] In this embodiment, the material of the second insulating layer 152 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, or silicon carbon oxynitride, boron nitride, and carbon boron nitride.

[0289] The material of the second conductive plug 154 includes a material with good electrical conductivity such as cobalt, copper, aluminum, or tungsten.

[0290] A second conductive structure 162 is electrically connected to the second second epitaxial layer 120.

[0291] In this embodiment, the second conductive structure 162 may include: a second insulating structure 158 that covers the sidewalls of the third second epitaxial layer 122 and a part of the sidewalls of the second second epitaxial layer 120, and exposes the surface of the second second epitaxial layer 120; a second conductive plug 160 that covers the sidewalls of the second insulating structure 158 and is in contact with the surface of the second second epitaxial layer 120.

[0292] In this embodiment, the reason for leading out the second second epitaxial layer 120 of the second layer through the second conductive structure 162 is that, on the one hand, the second second epitaxial layer 120 of the second layer is used as a channel layer, and the second second epitaxial layer 120 of the second layer does not contact the substrate 100, so the substrate 100 cannot be used as a discharge channel for the second second epitaxial layer 120 of the second layer; on the other hand, referring to Figure 17 , the first conductive structures overlap with each other along the length direction of the gate structure, the distance between the second conductive structures is relatively close, and there is a problem of charge accumulation in the second second epitaxial layer 120 of the second layer. For the above two reasons, by providing the second conductive structure 162 electrically connected to the second second epitaxial layer 120 of the second layer, the charges in the second second epitaxial layer 120 of the second layer can be extracted.

[0293] In addition, the second conductive structure 162 can be used as a ground terminal to provide a reference reference value for the entire semiconductor structure.

[0294] A second conductive structure 168 is electrically connected to the first second epitaxial layer 118.

[0295] In this embodiment, the second conductive structure 168 may include: a second insulating structure 164 covering the sidewalls of the third second epitaxial layer 122, the sidewalls of the second second epitaxial layer 120, and part of the sidewalls of the first second epitaxial layer 118, and exposing the surface of the first second epitaxial layer 118; a second conductive plug 166 covering the sidewalls of the second insulating structure 164 and contacting the surface of the first second epitaxial layer 118.

[0296] A third conductive structure 170 is electrically connected to the gate structure 130.

[0297] In this embodiment, the semiconductor structure may further include: an interlayer dielectric layer 132 located on the topmost epitaxial layer and covering the sidewalls of the first conductive structure, the second conductive structure, the third conductive structure, and the fourth conductive structure.

[0298] The interlayer dielectric layer 132 is used to achieve electrical isolation between the first conductive structure, the second conductive structure, the third conductive structure, and the fourth conductive structure, and is also used to achieve electrical isolation between adjacent devices.

[0299] In this embodiment, the material of the interlayer dielectric layer 132 is an insulating material. For example, the material of the interlayer dielectric layer 132 is silicon oxide. In other embodiments, the material of the interlayer dielectric layer may also be other dielectric materials such as silicon nitride or silicon oxynitride.

[0300] It should be noted that the semiconductor structure described in this embodiment may be formed by using the forming method described in the foregoing embodiment, or may be formed by using other forming methods. For the specific description of the semiconductor structure described in this embodiment, reference may be made to the corresponding description in the foregoing embodiment, and details are not repeated herein.

[0301] Although the present specification is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, Comprising: Providing a substrate; Forming a first epitaxial layer structure and a second epitaxial layer structure on the substrate; At the junction of the first epitaxial layer structure and the second epitaxial layer structure, forming a gate structure that covers the sidewalls of the first epitaxial layer structure and the second epitaxial layer structure.

2. The method for forming a semiconductor structure according to claim 1, wherein, After forming the first epitaxial layer structure, forming the second epitaxial layer structure; Or, after forming the second epitaxial layer structure, forming the first epitaxial layer structure.

3. The method for forming a semiconductor structure according to claim 2, wherein When forming the second epitaxial layer structure after forming the first epitaxial layer structure, the forming method includes: Forming a first mask layer on the substrate, and the first mask layer exposes the substrate surface for forming the first epitaxial layer structure; Adopting an epitaxial process to form multiple layers of first epitaxial layers as the first epitaxial layer structure; Removing the first mask layer to expose the substrate surface for forming the second epitaxial layer structure; Adopting an epitaxial process to form multiple layers of second epitaxial layers as the second epitaxial layer structure, and the sidewalls of each layer of the second epitaxial layer are in contact with the sidewalls of the corresponding first epitaxial layer.

4. The method for forming a semiconductor structure according to claim 3, wherein, Before forming the first mask layer, forming a first covering layer, and the first covering layer is located on the substrate surface for forming the first epitaxial layer structure; Before forming multiple layers of first epitaxial layers, also removing the first covering layer; Before removing the first mask layer, the forming method further includes: forming a second mask layer that covers the surface of the first mask layer and the first epitaxial layer structure; In the step of removing the first mask layer, also removing the second mask layer above the first mask layer; After forming the second epitaxial layer structure, removing the second mask layer on the first epitaxial layer structure.

5. The method for forming a semiconductor structure according to claim 3, wherein, Adopting an epitaxial process to form each layer of the first epitaxial layer and / or each layer of the second epitaxial layer, and during the epitaxial growth process, performing doping treatment, wherein each layer of the first epitaxial layer has its own doping type and doping concentration, and each layer of the second epitaxial layer has its own doping type and doping concentration.

6. The method for forming a semiconductor structure according to claim 5, wherein, The formation temperature of each layer of the first epitaxial layer and / or each layer of the second epitaxial layer is between 600 degrees Celsius and 800 degrees Celsius.

7. The method for forming a semiconductor structure according to claim 6, wherein, The formation parameters of each layer of the first epitaxial layer and / or the formation parameters of each layer of the second epitaxial layer further include: the pressure is from 70 Torr to 90 Torr, the flow rate of Purge MainH2 is from 3200 sccm to 3800 sccm, the flow rate of Purge SlitH2 is from 80 sccm to 120 sccm, the flow rate of the silicon source gas is from 120 sccm to 180 sccm, and the epitaxial rate is at least one of from 200 angstroms per minute to 300 angstroms per minute.

8. The method for forming a semiconductor structure according to claim 5, wherein The number of the first epitaxial layers is at least 3, and satisfies at least one or more of the following: the first layer of the first epitaxial layer, the first layer of the first epitaxial layer is used to form a first source / drain doping layer; the second layer of the first epitaxial layer, the second layer of the first epitaxial layer is used to form a first channel layer; the third layer of the first epitaxial layer, the third layer of the first epitaxial layer is used to form a second source / drain doping layer; the first source / drain doping layer is one of the source or the drain, and the second source / drain doping layer is the other of the source or the drain; The number of second epitaxial layers is at least 3 and satisfies at least one or more of the following: a first-layer second epitaxial layer for forming a third source / drain doping layer; a second-layer second epitaxial layer for forming a second channel layer; a third-layer second epitaxial layer for forming a fourth source / drain doping layer; the third source / drain doping layer is one of the source or the drain, and the fourth source / drain doping layer is the other of the source or the drain.

9. The method for forming a semiconductor structure according to claim 1, wherein, The step of forming a gate structure at the junction of the first epitaxial layer structure and the second epitaxial layer structure includes: forming a gate opening at the junction of the first epitaxial layer structure and the second epitaxial layer structure, the gate opening exposing the surface of the substrate and the sidewalls of the first epitaxial layer structure and the second epitaxial layer structure; forming a gate material layer covering the surfaces of the first epitaxial layer structure and the second epitaxial layer structure and filling the gate opening; removing the gate material layer above the top of the gate opening, and using the gate material layer remaining in the gate opening as the gate structure.

10. The method for forming a semiconductor structure according to claim 9, wherein, Before forming the gate structure, the forming method further includes: forming a gate oxide layer covering the surfaces of the first epitaxial layer structure and the second epitaxial layer structure and the sidewalls of the gate opening; during the process of removing the gate material layer above the top of the gate opening, the gate oxide layer on the first epitaxial layer structure and the second epitaxial layer structure is also removed.

11. The method for forming a semiconductor structure according to claim 1, wherein, The forming method further includes: for each first epitaxial layer in part or all of the first epitaxial layer structures, forming at least one first conductive structure, and each first conductive structure is electrically connected to the corresponding first epitaxial layer; for each second epitaxial layer in part or all of the second epitaxial layer structures, forming at least one second conductive structure, and each second conductive structure is electrically connected to the corresponding second epitaxial layer forming a third conductive structure electrically connected to the gate structure.

12. The method for forming a semiconductor structure according to claim 11, wherein, The step of forming at least one first conductive structure includes: forming a first trench that at least exposes a partial sidewall of the first epitaxial layer electrically connected to the first conductive structure; forming a first insulating layer on the sidewall of the first trench; forming at least a first conductive plug in the remaining space of the first trench, the first conductive plug being electrically connected to the first epitaxial layer, and the first conductive plug and the first insulating layer serving as the first conductive structure; The step of forming at least one second conductive structure includes: forming a second trench that at least exposes a partial sidewall of the second epitaxial layer electrically connected to the second conductive structure; forming a second insulating layer on the sidewall of the second trench; forming at least a second conductive plug in the remaining space of the second trench, the second conductive plug being electrically connected to the second epitaxial layer, and the second conductive plug and the second insulating layer serving as the second conductive structure.

13. A semiconductor structure, characterized in that, including: a substrate; a first epitaxial layer structure located on the substrate; a second epitaxial layer structure located on the substrate; A gate structure is located between the first epitaxial layer structure and the second epitaxial layer structure and covers the sidewalls of the first epitaxial layer structure and the second epitaxial layer structure.

14. The semiconductor structure according to claim 13, wherein The number of the first epitaxial layers in the first epitaxial layer structure is at least 3 and satisfies at least one or more of the following: the first first epitaxial layer of the first layer, and the first first epitaxial layer of the first layer serves as a first source / drain doping layer; the second first epitaxial layer of the second layer, and the second first epitaxial layer of the second layer serves as a first channel layer; the third first epitaxial layer of the third layer, and the third first epitaxial layer of the third layer serves as a second source / drain doping layer; the first source / drain doping layer is one of the source or the drain, and the second source / drain doping layer is the other of the source or the drain; The number of the second epitaxial layers in the second epitaxial layer structure is at least 3 and satisfies at least one or more of the following: the first second epitaxial layer of the first layer, and the first second epitaxial layer of the first layer serves as a third source / drain doping layer; the second second epitaxial layer of the second layer, and the second second epitaxial layer of the second layer serves as a second channel layer; the third second epitaxial layer of the third layer, and the third second epitaxial layer of the third layer serves as a fourth source / drain doping layer; the third source / drain doping layer is one of the source or the drain, and the fourth source / drain doping layer is the other of the source or the drain.

15. The semiconductor structure according to claim 13, wherein Satisfy at least one or more of the following: At least one first conductive structure is electrically connected to the corresponding first epitaxial layer; At least one second conductive structure is electrically connected to the corresponding second epitaxial layer; A third conductive structure is electrically connected to the gate structure.

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