Integrated circuit device with enhanced power delivery network therein

Abstract

An integrated circuit device having an enhanced power delivery network therein is provided. The integrated circuit device includes: a substrate; a power transmission network layer on the bottom surface of the substrate, the power transmission network layer including a lower interconnection line; a source / drain pattern on the substrate, the source / drain pattern including a first pattern and a second pattern horizontally spaced apart; a backside conductive structure penetrating the substrate and electrically connecting the first pattern to the power transfer network layer; and a lower insulating pattern extending below the second pattern and contacting a portion of the lower interconnect line.

Description

[0001] This application claims the priority of Korean Patent Application No. 10-2024-0008943, filed on Jan. 19, 2024, the disclosure of which is incorporated herein by reference. Technical Field

[0002] The present disclosure relates to integrated circuit devices, and more particularly, to integrated circuit devices having highly integrated field effect transistors and methods of forming the integrated circuit devices. Background Art

[0003] Integrated circuit devices include integrated circuits composed of metal oxide semiconductor field effect transistors (MOSFETs). To meet the growing demand for integrated circuit devices with small pattern sizes and reduced design rules, MOSFETs are being actively scaled down. The scaling down of MOSFETs can lead to deterioration in the operating properties of integrated circuit devices. Various studies are underway to overcome the technical limitations associated with the scaling down of integrated circuit devices and to achieve higher performance therein. Summary of the Invention

[0004] Embodiments of the inventive concept provide an integrated circuit device having improved electrical characteristics and improved reliability.

[0005] According to an embodiment of the inventive concept, an integrated circuit device may include: a substrate; a power delivery network layer on a bottom surface of the substrate, the power delivery network layer having lower interconnects; and source / drain patterns including spaced-apart first and second patterns. A backside conductive structure is disposed to penetrate the substrate and electrically connect the first pattern to the power delivery network layer, and a lower insulating pattern is disposed under the second pattern. In some embodiments, the lower insulating pattern may contact a portion of the lower interconnects.

[0006] According to an embodiment of the inventive concept, an integrated circuit device may include: a substrate; a power delivery network layer on the bottom surface of the substrate; and source / drain patterns on the substrate, the source / drain patterns including spaced-apart first and second patterns. A channel pattern is disposed on a side surface of at least one of the first and second patterns and includes a plurality of semiconductor patterns vertically stacked and spaced apart from each other. A gate electrode is disposed between the semiconductor patterns, and a backside active contact is disposed to penetrate the substrate and electrically connect the first pattern to the power delivery network layer. A lower insulating pattern may also be disposed under the second pattern, and an uppermost surface of the lower insulating pattern may be located at a level lower than or equal to an uppermost surface of the backside active contact.

[0007] According to an embodiment of the inventive concept, a semiconductor device may include: a substrate; and a power delivery network layer on a bottom surface of the substrate, the power delivery network layer including lower interconnects. Source / drain patterns may be provided together with a channel pattern, the source / drain patterns including first and second patterns spaced horizontally apart, the channel pattern extending on side surfaces of one or more of the source / drain patterns and including a stack of spaced semiconductor patterns. A gate electrode is provided, the gate electrode extending between the semiconductor patterns. The gate electrode includes first, second, and third inner electrodes extending between adjacent semiconductor patterns among the semiconductor patterns and an outer electrode provided on a topmost semiconductor pattern among the semiconductor patterns. A gate insulating pattern is provided on the gate electrode, and a gate covering pattern is provided on a top surface of the outer electrode. A first interlayer insulating layer is provided on the source / drain patterns, a second interlayer insulating layer is provided on the first interlayer insulating layer and the gate covering pattern, and a third interlayer insulating layer is provided on the second interlayer insulating layer and includes a metal pattern and a via. An active contact is provided to penetrate the first and second interlayer insulating layers and electrically connect the second pattern of the source / drain patterns to the metal pattern. A backside conductive structure is provided, the backside conductive structure penetrating the substrate and electrically connecting the first pattern of the source / drain patterns to the power delivery network layer. A lower insulating pattern is provided, the lower insulating pattern extending under the second pattern. A bottom surface of the lower insulating pattern and a bottom surface of the backside conductive structure may be substantially coplanar with each other, and a top surface of the lower insulating pattern may be at a level lower than (or equal to) a top surface of the backside conductive structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a plan layout view showing an integrated circuit device according to an embodiment of the inventive concept.

[0009] Figures 2A to 2E are cross-sectional views taken along lines A-A', B-B', C-C', D-D', and E-E' of Figure 1 respectively.

[0010] Figure 3 is a cross-sectional view showing Figure 2A another example of the integrated circuit device.

[0011] Figures 4A to 11B is a view showing a method of manufacturing an integrated circuit device according to an embodiment of the inventive concept. DETAILED DESCRIPTION

[0012] Example embodiments of the inventive concept will now be described more fully with reference to the accompanying drawings, in which example embodiments are shown. Like reference numerals in the drawings denote like elements, and thus their redundant description will be omitted.

[0013] Figure 1 is a plan view showing a planar layout of an integrated circuit device according to an embodiment of the inventive concept; and Figures 2A to 2E are cross-sectional views taken along lines A-A', B-B', C-C', D-D', and E-E' of Figure 1 respectively. Referring to Figure 1 and Figures 2A to 2E , a substrate 105 including a PMOSFET region PR and an NMOSFET region NR can be provided. In an embodiment, the substrate 105 may include a silicon-based insulating layer. That is, the substrate 105 may be an insulating substrate. For example, the substrate 105 may include at least one of silicon oxide (SiO2), silicon nitride (SiN), and silicon oxynitride (SiON). In this specification, each of the expressions "A or B", "at least one of A and B", "at least one of A or B", "A, B, or C", "at least one of A, B, and C", and "at least one of A, B, or C" can be used to represent one of the elements listed in the expression or any possible combination of the listed elements.

[0014] The PMOSFET region PR and the NMOSFET region NR may extend in a first direction D1 and may be spaced apart from each other in a second direction D2. The first direction D1 and the second direction D2 may be parallel to the bottom surface of the substrate 105 and may not be parallel to each other (e.g., orthogonal to each other). The insulating pattern may be defined by a trench TR of the substrate 105. When observed in a plan view, the insulating pattern may be a part of the substrate 105. This part of the substrate 105 may protrude in a third direction D3. The third direction D3 may be perpendicular to the bottom surface of the substrate 105.

[0015] The device isolation pattern ST may be disposed between the insulating patterns to fill the trench TR. The device isolation pattern ST may surround the insulating patterns. The device isolation pattern ST may include an insulating material. The device isolation pattern ST may be formed of or include silicon oxide (SiO2).

[0016] The first channel pattern CH1 may be disposed on the PMOSFET region PR of the substrate 105, and the second channel pattern CH2 may be disposed on the NMOSFET region NR of the substrate 105. In other words, the first channel pattern CH1 and the second channel pattern CH2 may be disposed on the insulating pattern. In an embodiment, a plurality of first channel patterns CH1 may be disposed to be spaced apart from each other in the first direction D1. In an embodiment, a plurality of second channel patterns CH2 may be disposed to be spaced apart from each other in the first direction D1. Each of the first channel pattern CH1 and the second channel pattern CH2 may include a first semiconductor pattern SP1, a second semiconductor pattern SP2, and a third semiconductor pattern SP3 that are adjacent to each other in the third direction D3, but the inventive concept is not limited to this example. In an embodiment, each of the first channel pattern CH1 and the second channel pattern CH2 may include four or more semiconductor patterns. In an embodiment, each of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 may be formed of or include crystalline silicon.

[0017] The first recess RS1, which will be described below, may be defined between the first channel patterns CH1 adjacent to each other in the first direction D1. The second recess RS2, which will be described below, may be defined between the second channel patterns CH2 adjacent to each other in the first direction D1.

[0018] The first source / drain pattern SD1 may be disposed on the PMOSFET region PR of the substrate 105, and the second source / drain pattern SD2 may be disposed on the NMOSFET region NR of the substrate 105. In an embodiment, the first source / drain pattern SD1 and the second source / drain pattern SD2 may be disposed on the insulating pattern. The first source / drain pattern SD1 may be disposed to fill the first recess RS1, and the second source / drain pattern SD2 may be disposed to fill the second recess RS2. Each of the first source / drain pattern SD1 and the second source / drain pattern SD2 may be electrically connected to the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3. The first source / drain pattern SD1 may be an impurity region of a first conductivity type (e.g., p-type), and the second source / drain pattern SD2 may be an impurity region of a second conductivity type (e.g., n-type). A pair of first source / drain patterns SD1 may be electrically connected to each other through the first channel pattern CH1. A pair of second source / drain patterns SD2 may be electrically connected to each other through the second channel pattern CH2.

[0019] The first source / drain pattern SD1 may be formed of a semiconductor material (e.g., SiGe) whose lattice constant is larger than that of the first channel pattern CH1, or include a semiconductor material (e.g., SiGe) whose lattice constant is larger than that of the first channel pattern CH1. In this case, a pair of first source / drain patterns SD1 may apply compressive stress to the first channel pattern CH1 therebetween. The second source / drain pattern SD2 may be formed of the same semiconductor element as the semiconductor element of the second channel pattern CH2 (e.g., Si), or include the same semiconductor element as the semiconductor element of the second channel pattern CH2 (e.g., Si).

[0020] The first source / drain pattern SD1 may include a buffer layer BFL covering the inner surface of the first recess RS1 and a main layer MAL filling most of the remainder of the first recess RS1. In an embodiment, each of the buffer layer BFL and the main layer MAL may be formed of or include silicon germanium (SiGe). The buffer layer BFL may contain a relatively low concentration of germanium (Ge). The main layer MAL may contain a relatively high concentration of germanium. In an embodiment, the buffer layer BFL may contain only silicon (Si).

[0021] The first source / drain pattern SD1 and the second source / drain pattern SD2 may include a first pattern T1 electrically connected to a power delivery network layer PDN to be described below and a second pattern T2 electrically connected to an active contact AC to be described below.

[0022] The gate electrode GE may be disposed on the first channel pattern CH1 and the second channel pattern CH2 to cross the first channel pattern CH1 and the second channel pattern CH2. In an embodiment, a plurality of gate electrodes GE may be disposed. The gate electrode GE may extend in a second direction D2 and may be spaced apart from each other in a first direction D1. As shown, the gate electrode GE may include inner electrodes GE1 to GE3 and an outer electrode GE4. The inner electrodes GE1 to GE3 of the gate electrode GE may be disposed between respective semiconductor patterns among a plurality of semiconductor patterns SP1, SP2, SP3 and between the first semiconductor pattern SP1 and the substrate 105. The outer electrode GE4 of the gate electrode GE may be disposed on the uppermost semiconductor pattern. In an embodiment, the inner electrodes GE1 to GE3 of the gate electrode GE may include a first inner electrode GE1, a second inner electrode GE2, and a third inner electrode GE3, but the inventive concept is not limited to this example. In an embodiment, the inner electrodes of the gate electrode GE may include four or more inner electrodes. Specifically, the first inner electrode GE1 may be disposed between the substrate 105 and the first semiconductor pattern SP1. The second inner electrode GE2 may be disposed between the first semiconductor pattern SP1 and the second semiconductor pattern SP2. The third inner electrode GE3 may be disposed between the second semiconductor pattern SP2 and the third semiconductor pattern SP3. The outer electrode GE4 of the gate electrode GE may be disposed on the third semiconductor pattern SP3.

[0023] The gate electrode GE may include a first metal pattern and a second metal pattern on the first metal pattern. The first metal pattern may include a work function metal, which may be used to adjust the threshold voltage of the transistor. The first metal pattern may be formed of at least one of a metal material (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, and Co) and a metal nitride material (e.g., a nitride material of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, and Co), or include at least one of a metal material (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, and Co) and a metal nitride material (e.g., a nitride material of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, and Co). In an embodiment, the first metal pattern may further include carbon (C). The first metal pattern may be formed of at least one of metal materials having different work functions or include at least one of metal materials having different work functions. In an embodiment, the second metal pattern may be formed of at least one of metal materials (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, and Co) whose resistance is lower than that of the first metal pattern, or include at least one of metal materials (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, and Co) whose resistance is lower than that of the first metal pattern. The first inner electrode GE1, the second inner electrode GE2, and the third inner electrode GE3 of the gate electrode GE may include the first metal pattern. In an embodiment, the outer electrode GE4 of the gate electrode GE may include the first metal pattern and the second metal pattern.

[0024] The gate capping pattern GC may be disposed on the top surface of the gate electrode GE. Specifically, the gate capping pattern GC may be disposed on the outer electrode GE4 of the gate electrode GE. In an embodiment, the gate capping pattern GC may be formed of at least one of SiON, SiCN, SiOCN, and SiN, or include at least one of SiON, SiCN, SiOCN, and SiN.

[0025] The gate spacer GS may be disposed on the side surface of the outer electrode GE4 of the gate electrode GE and may extend to the side surface of the gate capping pattern GC. The gate spacer GS may include a single layer or a composite layer. In an embodiment, the gate spacer GS may be formed of at least one of SiON, SiCN, SiOCN, and SiN, or include at least one of SiON, SiCN, SiOCN, and SiN.

[0026] The gate insulating pattern GI may be disposed between the gate electrode GE and the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3. The gate insulating pattern GI may cover the top surface, the bottom surface, and the opposite side surfaces of each of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3. The gate insulating pattern GI may cover the top surface of the device isolation pattern ST under the gate electrode GE. The gate insulating pattern GI may be disposed between the external electrode GE4 and the gate spacer GS. The gate insulating pattern GI may be formed of at least one of silicon oxide (SiO2), silicon oxynitride (SiON), and a high-k dielectric material, or may include at least one of silicon oxide (SiO2), silicon oxynitride (SiON), and a high-k dielectric material. In the present specification, the high-k dielectric material may be defined as a material having a dielectric constant higher than that of silicon oxide.

[0027] Although not shown, an inner spacer may be disposed between the side surface of the second source / drain pattern SD2 and the side surface of the gate electrode GE. In an embodiment, the inner spacer may be disposed between the first inner electrode GE1 to the third inner electrode GE3 and the second source / drain pattern SD2. The inner spacer may include an insulating material.

[0028] The first interlayer insulating layer ILD1 may be disposed on the substrate 105. The first interlayer insulating layer ILD1 may cover the gate spacer GS and the first source / drain pattern SD1 and the second source / drain pattern SD2. The top surface of the first interlayer insulating layer ILD1 may be located at substantially the same level as the top surface of the gate covering pattern GC and the top surface of the gate spacer GS. The second interlayer insulating layer ILD2 may be disposed on the first interlayer insulating layer ILD1 to cover the gate covering pattern GC. The third interlayer insulating layer ILD3 may be disposed on the second interlayer insulating layer ILD2. In an embodiment, the first interlayer insulating layer ILD1, the second interlayer insulating layer ILD2, and the third interlayer insulating layer ILD3 may be formed of silicon oxide (SiO2) or may include silicon oxide (SiO2).

[0029] The active contact AC may penetrate the first interlayer insulating layer ILD1 and the second interlayer insulating layer ILD2 in the third direction D3. In an embodiment, a plurality of active contacts AC may be provided, and the lower portion of each of the active contacts AC may be buried in the upper portion of the second pattern T2 of the source / drain pattern SD1 or SD2. That is, the active contact AC may be a contact formed through the front surface of the substrate 105.

[0030] The active contact AC may include a conductive pattern CP that penetrates the first interlayer dielectric layer ILD1 and the second interlayer dielectric layer ILD2, and a barrier pattern BM that surrounds the conductive pattern CP. In an embodiment, the conductive pattern CP may be formed of at least one of metal materials (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, and Co) or include at least one of metal materials (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, and Co). As an example, the barrier pattern BM may be formed of at least one of metal nitride materials (e.g., nitride materials of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, and Co) or include at least one of metal nitride materials (e.g., nitride materials of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, and Co).

[0031] The ohmic pattern OM may be disposed between the active contact AC and the second pattern T2 of the source / drain pattern SD1 or SD2. Accordingly, the contact resistance characteristics between the active contact AC and the second pattern T2 of the source / drain pattern SD1 or SD2 may be improved. In an embodiment, the ohmic pattern OM may be formed of at least one of metal silicide materials (e.g., silicide materials of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, and Co) or include at least one of metal silicide materials (e.g., silicide materials of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, and Co).

[0032] As Figures 2A to 2E shown in the cross-section of

[0033] The power delivery network layer PDN may be disposed on the bottom surface of the substrate 105. The power delivery network layer PDN may include a plurality of lower interconnects PRP, and the plurality of lower interconnects PRP electrically connect the backside conductive structure BCS, which will be described below, to the source / drain patterns SD1 and SD2. In an embodiment, the power delivery network layer PDN may include an interconnect network for applying a source voltage. In an embodiment, the power delivery network layer PDN may include an interconnect network for applying a drain voltage.

[0034] The backside conductive structure BCS may be disposed in the substrate 105. The backside conductive structure BCS may penetrate the substrate 105 and may be disposed between the first pattern T1 of the source / drain pattern SD1 or SD2 and the power delivery network layer PDN. The backside conductive structure BCS may be arranged to electrically connect the first pattern T1 of the source / drain pattern SD1 or SD2 to the power delivery network layer PDN. Different from the above-mentioned active contact AC, the backside conductive structure BCS may be a backside active contact formed through the backside surface of the substrate 105.

[0035] The bottom surface of the backside conductive structure BCS may be in direct contact with the lower interconnect PRP of the power delivery network layer PDN. The top surface of the backside conductive structure BCS may be in direct contact with the first pattern T1 of the source / drain pattern SD1 or SD2. The top surface of the backside conductive structure BCS may be a curved surface protruding toward the first pattern T1. The width of the backside conductive structure BCS in the first direction D1 may decrease as the distance to the first pattern T1 decreases.

[0036] The backside conductive structure BCS may include a backside conductive pattern BT and a backside barrier pattern BBM surrounding the backside conductive pattern BT. In an embodiment, the backside conductive pattern BT may be formed of at least one of metal materials (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, and Co) or include at least one of metal materials (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, and Co). The backside barrier pattern BBM may be formed of at least one of metal nitride materials (e.g., nitrides of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, and Co) or include at least one of metal nitride materials (e.g., nitrides of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, and Co).

[0037] The lower insulating pattern DRP may be disposed in the substrate 105. In other words, the lower insulating pattern DRP may be buried in the substrate 105. The lower insulating pattern DRP may be disposed below the second pattern T2 of the source / drain pattern SD1 or SD2. The second pattern T2 of the source / drain pattern SD1 or SD2 may vertically overlap the lower insulating pattern DRP and may be in contact with the lower insulating pattern DRP.

[0038] The lower insulating pattern DRP may be in direct contact with the lower interconnect PRP of the power delivery network layer PDN. Specifically, the lower insulating pattern DRP may be in direct contact with a part of the lower interconnect PRP. The bottom surface of the lower insulating pattern DRP may be in direct contact with the lower interconnect PRP of the power delivery network layer PDN. For example, the level of the bottom surface of the lower insulating pattern DRP may be substantially equal (e.g., substantially the same) to the level of the bottom surface of the backside conductive structure BCS. The bottom surface of the lower insulating pattern DRP and the bottom surface of the backside conductive structure BCS may be substantially coplanar with each other. The opposite side surfaces of the lower insulating pattern DRP may have a curved shape. The opposite side surfaces may protrude towards the substrate 105.

[0039] The lower insulating pattern DRP may have a first height DRP_H in the third direction D3. The backside conductive structure BCS may have a second height BCS_H in the third direction D3. The first height DRP_H may be defined as the vertical distance from the bottom surface of the lower insulating pattern DRP to the uppermost surface of the lower insulating pattern DRP. The second height BCS_H may be defined as the vertical distance from the bottom surface of the backside conductive structure BCS to the uppermost surface of the backside conductive structure BCS. The second height BCS_H may be greater than the first height DRP_H. In an embodiment, the second height BCS_H may be substantially equal to the first height DRP_H.

[0040] The uppermost surface of the lower insulating pattern DRP may be at a level lower than the uppermost surface of the backside conductive structure BCS. In an embodiment, the uppermost surface of the lower insulating pattern DRP and the uppermost surface of the backside conductive structure BCS may be at the same level. The uppermost surface of the lower insulating pattern DRP may be at a level substantially the same as the bottom surface of the gate insulating pattern GI surrounding the first inner electrode GE1. The uppermost surface of the backside conductive structure BCS may be at a level higher than the bottom surface of the gate insulating pattern GI and lower than the top surface of the gate insulating pattern GI.

[0041] The uppermost surface of the lower insulating pattern DRP may be at a first level LV1 in the third direction D3, and the uppermost surface of the backside conductive structure BCS may be at a second level LV2 in the third direction D3. The first level LV1 may be defined as the vertical position of the uppermost surface of the lower insulating pattern DRP in the third direction D3. The second level LV2 may be defined as the vertical position of the uppermost surface of the backside conductive structure BCS in the third direction D3. The second level LV2 may be higher than the first level LV1. In an embodiment, the second level LV2 and the first level LV1 may be substantially equal to each other (e.g., substantially the same). The second level LV2 may be higher than the bottom surface of the first inner electrode GE1 and lower than the top surface of the first inner electrode GE1.

[0042] The lower insulating pattern DRP may be formed of an insulating material different from that of the substrate 105 or may include an insulating material different from that of the substrate 105. In an embodiment, the lower insulating pattern DRP and the substrate 105 may be formed of the same insulating material or may include the same insulating material. The lower insulating pattern DRP may be formed of at least one of silicon oxide (SiO2), silicon nitride (SiN), aluminum oxide (Al2O3), and aluminum nitride (AlN), or may include at least one of silicon oxide (SiO2), silicon nitride (SiN), aluminum oxide (Al2O3), and aluminum nitride (AlN). As described above, the substrate 105 may include at least one of silicon oxide (SiO2), silicon nitride (SiN), and silicon oxynitride (SiON).

[0043] Since the lower insulating pattern DRP includes an insulating material, a short-circuit phenomenon may not occur even when the lower insulating pattern DRP is in direct contact with the lower interconnect line PRP of the power delivery network layer PDN. In other words, it is possible to prevent a short-circuit phenomenon between the power delivery network layer PDN and the source / drain patterns SD1 and SD2. Accordingly, the reliability characteristics of the integrated circuit device may be improved.

[0044] Although not shown, the width of the lower insulating pattern DRP in the first direction D1 may increase as the distance to the power delivery network layer PDN decreases. This may be because a chamfering process is performed to remove a portion of the lower insulating pattern DRP that is vulnerable to an overhang problem. After the chamfering process, the opposing side surfaces of the lower insulating pattern DRP may be formed to include at least one curved portion and a flat portion having a specific slope. In this case, the maximum width of the lower insulating pattern DRP in the first direction D1 may be greater than the maximum width of the backside conductive structure BCS in the first direction D1.

[0045] Hereinafter, an integrated circuit device according to an embodiment of the inventive concept will be described with reference to Figure 3 FIG. Figure 3 is a cross-sectional view showing an integrated circuit device according to an embodiment of the inventive concept. In the following description, for simplicity of description, elements described previously may be identified by the same reference numerals without repeating their overlapping descriptions. Referring to Figure 3 , the backside conductive structure BCS may include a backside conductive pattern. The backside conductive pattern may be formed of at least one of metal materials (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, and Co) or may include at least one of metal materials (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, and Co). The backside conductive structure BCS may not include a backside barrier pattern. That is, the side surface of the backside conductive pattern of the backside conductive structure BCS may be in direct contact with the substrate 105.

[0046] Figures 4A to 11B is a diagram showing a method of manufacturing an integrated circuit device according to an embodiment of the inventive concept. Refer to Figure 1 , Figure 4A and Figure 4B , a semiconductor substrate 100 including a PMOSFET region PR and an NMOSFET region NR may be provided. In an embodiment, the semiconductor substrate 100 may be a single crystal silicon substrate, a silicon germanium substrate, or a semiconductor substrate including a semiconductor material (e.g., a silicon-on-insulator (SOI) substrate). A stacked pattern STP may be formed on the PMOSFET region PR and the NMOSFET region NR. In an embodiment, the formation of the stacked pattern STP may include alternately stacking a semiconductor layer SL and a sacrificial layer SAL on the semiconductor substrate 100, forming a mask pattern (not shown) extending in a first direction D1, and performing a patterning process using the mask pattern as an etching mask. During the patterning process, a portion of the semiconductor substrate 100 may be removed to form trenches TR defining a first active pattern AP1 and a second active pattern AP2.

[0047] The first active pattern AP1 may be formed on the PMOSFET region PR, and the second active pattern AP2 may be formed on the NMOSFET region NR. The first active pattern AP1 and the second active pattern AP2 may extend in the first direction D1. A device isolation pattern ST may be formed to fill the trenches TR.

[0048] The sacrificial layer SAL may include a material having an etching selectivity with respect to the semiconductor layer SL. Thus, in a subsequent process of removing the sacrificial layer SAL, the semiconductor layer SL may be substantially not removed. The semiconductor layer SL and the sacrificial layer SAL may be formed of or include at least one of silicon (Si), germanium (Ge), and silicon germanium (SiGe), but the material of the sacrificial layer SAL may be different from the material of the semiconductor layer SL.

[0049] Refer to Figure 1 , Figure 5A and Figure 5B , a sacrificial pattern PP extending in a second direction D2 may be formed on the semiconductor substrate 100. The sacrificial pattern PP may be formed to cover the top surface of the device isolation pattern ST and the side and top surfaces of the stacked pattern STP. In an embodiment, the formation of the sacrificial pattern PP may include forming a sacrificial layer (not shown) on the semiconductor substrate 100, forming a hard mask pattern MP on the sacrificial layer, and removing a portion of the sacrificial layer using the hard mask pattern MP as an etching mask to form the sacrificial pattern PP. In an embodiment, the sacrificial pattern PP may be formed of or include polysilicon. Next, a gate spacer GS may be formed on the side surface of the sacrificial pattern PP.

[0050] Refer toFigure 1 and Figures 6A to 6C , a first recess RS1 may be formed in a stacked pattern STP on a first active pattern AP1. A second recess RS2 may be formed in the stacked pattern STP on a second active pattern AP2. In an embodiment, the first recess RS1 and the second recess RS2 may be formed by removing a portion of the stacked pattern STP by using a hard mask pattern MP as an etch mask.

[0051] A semiconductor layer SL on the first active pattern AP1 may be divided by the first recess RS1 into first channel patterns CH1 spaced apart from each other in a first direction D1. A semiconductor layer SL on the second active pattern AP2 may be divided by the second recess RS2 into second channel patterns CH2 spaced apart from each other in the first direction D1. Each of the first channel patterns CH1 and the second channel patterns CH2 may include a first semiconductor pattern SP1, a second semiconductor pattern SP2, and a third semiconductor pattern SP3.

[0052] A portion of a sacrificial layer SAL exposed through the second recess RS2 may be replaced with an insulating material. As a result, an inner spacer ISP may be formed on opposite side surfaces of the sacrificial layer SAL. A first lower recess LRS1 may be provided below the first recess RS1. A second lower recess LRS2 may be provided below the second recess RS2. A backside alignment pattern BA may be formed by a SEG process in which a semiconductor substrate 100 is used as a seed layer to fill the first lower recess LRS1 and the second lower recess LRS2. In an embodiment, the backside alignment pattern BA may be formed of or include silicon germanium (SiGe).

[0053] A first source / drain pattern SD1 may be formed in the first recess RS1. The first source / drain pattern SD1 may be formed by a SEG process in which the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 on a PMOSFET region PR and the backside alignment pattern BA are used as seed layers. In an embodiment, during the formation of the first source / drain pattern SD1, a p-type impurity (e.g., boron, gallium, or indium) may be implanted into the first source / drain pattern SD1 in an in-situ doping manner. As another example, after the formation of the first source / drain pattern SD1, an impurity may be implanted into the first source / drain pattern SD1.

[0054] A second source / drain pattern SD2 may be formed in the second recess RS2. The second source / drain pattern SD2 may be formed by a SEG process using a first semiconductor pattern SP1, a second semiconductor pattern SP2, a third semiconductor pattern SP3, and a backside alignment pattern BA on the NMOSFET region NR as seed layers. In an embodiment, during the formation of the second source / drain pattern SD2, an n-type impurity (e.g., phosphorus, arsenic, or antimony) may be implanted into the second source / drain pattern SD2 in an in-situ doping manner. In another embodiment, after the formation of the second source / drain pattern SD2, an impurity may be implanted into the second source / drain pattern SD2.

[0055] Referring Figure 1 , Figure 7A and Figure 7B , a first interlayer insulating layer ILD1 may be formed to cover the first source / drain pattern SD1, the second source / drain pattern SD2, the hard mask pattern MP, and the gate spacer GS. Thereafter, the first interlayer insulating layer ILD1 on the top surface of the sacrificial pattern PP may be removed. In an embodiment, a removal process may be performed to remove the hard mask pattern MP and thus expose the sacrificial pattern PP.

[0056] After that, the exposed sacrificial pattern PP may be removed to form an outer region ORG. The first channel pattern CH1, the second channel pattern CH2, and the sacrificial layer SAL may be exposed to the outside through the outer region ORG.

[0057] Next, the exposed sacrificial layer SAL may be selectively removed. Here, due to the high etching selectivity between the sacrificial layer SAL and the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3, it is possible to prevent or inhibit the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 from being removed during the process of removing the sacrificial layer SAL.

[0058] The inner region IRG may be an empty region formed by removing the sacrificial layer SAL. Specifically, the inner region IRG may be formed between the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3. The inner region IRG may include a first inner region IRG1, a second inner region IRG2, and a third inner region IRG3 spaced apart from each other in the third direction D3.

[0059] A gate insulating pattern GI may be formed in each of the inner region IRG and the outer region ORG. The gate insulating pattern GI may be formed to surround each of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3. The gate insulating pattern GI may be formed to have a constant thickness.

[0060] Referring Figure 8and Figures 9A to 9C A gate electrode GE may be formed on the gate insulating pattern GI. The gate electrode GE may include inner electrodes (e.g., a first inner electrode GE1, a second inner electrode GE2, and a third inner electrode GE3) respectively formed in a first inner region IRG1, a second inner region IRG2, and a third inner region IRG3, and an outer electrode GE4 formed in an outer region ORG. Next, a gate capping pattern GC may be formed on the outer electrode GE4.

[0061] A second interlayer insulating layer ILD2 may be formed on the first interlayer insulating layer ILD1 and the gate capping pattern GC. Active contacts AC may be formed to penetrate the first interlayer insulating layer ILD1 and the second interlayer insulating layer ILD2, and may be respectively connected to a first source / drain pattern SD1 and a second source / drain pattern SD2. Each of the first source / drain pattern SD1 and the second source / drain pattern SD2 may include a first pattern T1 not connected to the active contact AC and a second pattern T2 electrically connected to the active contact AC. A backside alignment pattern BA may include a first backside alignment pattern BA1 under the first pattern T1 and a second backside alignment pattern BA2 under the second pattern T2.

[0062] A gate contact GT may be formed to penetrate the second interlayer insulating layer ILD2 and the gate capping pattern GC, and may be connected to the gate electrode GE. The formation of the active contacts AC and the gate contact GT may include forming a barrier pattern BM and forming a conductive pattern CP on the barrier pattern BM. An ohmic pattern OM may be further formed between the active contact AC and the second pattern T2 of each of the first source / drain pattern SD1 and the second source / drain pattern SD2. A third interlayer insulating layer ILD3 may be formed on the second interlayer insulating layer ILD2 and the active contacts AC. Metal patterns MT and vias VI may be formed in the third interlayer insulating layer ILD3.

[0063] Figure 4A and Figure 4B The semiconductor substrate 100 of and may be inverted after a back-end-of-line (BEOL) process. Since Figure 4A the semiconductor substrate 100 in is inverted, in the following description of Figures 8 to 11B the terms "top surface" and "upper" may respectively mean "bottom surface" and "lower" in the final structure of the integrated circuit device described with reference to Figures 2A to 2E while the terms "bottom surface" and "lower" may respectively mean "top surface" and "upper" in the final structure of the integrated circuit device described with reference to Figures 2A to 2E Returning to reference

[0064] Returning to reference Figures 9A to 9C, after the BEOL process, the semiconductor substrate 100 can be inverted so that the bottom surface of the semiconductor substrate 100 is exposed to the outside. The exposed semiconductor substrate 100 can be completely removed. In an embodiment, the removal of the semiconductor substrate 100 can include performing a planarization process on the bottom surface of the semiconductor substrate 100 to reduce the thickness of the semiconductor substrate 100, performing a cleaning process to selectively remove silicon (Si) on the semiconductor substrate 100, and performing an etching process to selectively remove silicon (Si) in the first active pattern AP1 and the second active pattern AP2. The cleaning process can be performed until the device isolation pattern ST is exposed to the outside. The etching process can be a dry etching process or a wet etching process. When the etching process is completed, the backside alignment pattern BA can be left. Since the semiconductor substrate 100 is removed, a first backside trench can be formed in the region where the first active pattern AP1 is located. Since the semiconductor substrate 100 is removed, a second backside trench can be formed in the region where the second active pattern AP2 is located (e.g., see Figure 9B and Figure 9C ).

[0065] Referring to Figure 1 and Figures 10A to 10C , a substrate 105 can be formed to fill the empty region, and the empty region is formed by removing Figure 4A the semiconductor substrate 100 and Figure 4A the first active pattern AP1 and the second active pattern AP2. Specifically, the substrate 105 can be formed to fill the first backside trench and the second backside trench. In an embodiment, the substrate 105 can be formed by filling an insulating material to a level higher than the empty region formed by removing Figure 4A the semiconductor substrate 100. That is, the substrate 105 can be formed to cover the backside alignment pattern BA. Next, a chemical mechanical polishing (CMP) process using the backside alignment pattern BA as a stop layer can be performed on the substrate 105. The substrate 105 and the backside alignment pattern BA can have top surfaces that are substantially coplanar with each other.

[0066] The backside alignment pattern BA can be removed, and then, a lower insulating pattern DRP can be formed. The formation of the lower insulating pattern DRP can include performing a cleaning process to selectively remove the backside alignment pattern BA surrounded by the substrate 105, and performing a deposition process to fill the recessed region formed by the cleaning process. The cleaning process can be a wet etching process selected to selectively remove silicon germanium. The deposition process can be a chemical vapor deposition (CVD) process, a low-pressure CVD (LPCVD) process, a physical vapor deposition (PVD) process, or an atomic layer deposition (ALD) process.

[0067] The lower insulating pattern DRP may include a first lower insulating pattern DRP1 on a first pattern T1 of each of the source / drain patterns SD1 and SD2 and a second lower insulating pattern DRP2 on a second pattern T2 of each of the source / drain patterns SD1 and SD2. The lower insulating pattern DRP may include an insulating material. For example, the insulating material may be formed of at least one of silicon oxide (SiO2), silicon nitride (SiN), aluminum oxide (Al2O3), and aluminum nitride (AlN), or may include at least one of silicon oxide (SiO2), silicon nitride (SiN), aluminum oxide (Al2O3), and aluminum nitride (AlN).

[0068] Referring Figure 1 and Figures 11A to 11B , a back contact hole BCH may be formed on the first pattern T1 to penetrate the substrate 105. Here, the back contact hole BCH may be formed to further recess an upper portion of the first pattern T1 of each of the first source / drain pattern SD1 and the second source / drain pattern SD2. Specifically, the formation of the back contact hole BCH may include forming a hard mask pattern on the substrate 105, performing a dry etching process on the first lower insulating pattern DRP1 using the hard mask pattern, and removing the hard mask pattern. In this case, the lower insulating pattern DRP on the second pattern T2 may not be removed and may be left.

[0069] Return to reference Figure 1 and Figures 2A to 2D , a back conductive structure BCS may be formed to fill the back contact hole BCH. The formation of the back conductive structure BCS may include forming a back barrier pattern BBM to conformally cover an inner surface and an inner bottom surface of the back contact hole BCH, and forming a back conductive pattern BT on the back barrier pattern BBM to fill a remaining region of the back contact hole BCH. In an embodiment, the back conductive pattern BT may be formed by a single process, and in this case, an interface may not be formed in the back conductive pattern BT. As a result, the back conductive pattern BT may have a relatively small resistance, which may enable improvement of electrical characteristics of the integrated circuit device. Next, a power delivery network layer PDN may be formed on a bottom surface of the substrate 105.

[0070] In a three-dimensional field effect transistor according to an embodiment of the inventive concept, a lower insulating pattern may be formed under the source / drain pattern, and thus, a via pattern for connecting an interconnection to a contact pattern may be omitted. In this case, it may be possible to reduce a time required to send a signal from the power delivery network layer to the contact pattern, and thus, an operation speed of the integrated circuit device may be increased. In addition, the contact pattern may be formed to have a reduced thickness, which may enable reduction of contact resistance. Accordingly, electrical characteristics of the integrated circuit device may be improved.

[0071] In a three-dimensional field-effect transistor according to an embodiment of the inventive concept, the lower insulating pattern may include an insulating material (e.g., SiO x , SiN, AlO x or AlN), and in this case, it may be possible to prevent a short-circuit problem between the power delivery network layer and the source / drain pattern. That is, even when the interconnect line of the power delivery network layer contacts the lower insulating pattern, there may be no leakage current. Accordingly, the reliability characteristics of the integrated circuit device may be improved.

[0072] Although example embodiments of the inventive concept have been specifically shown and described, those of ordinary skill in the art will understand that changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. An integrated circuit device, comprising: a substrate; a power delivery network layer on a bottom surface of the substrate, the power delivery network layer including lower interconnects; a source / drain pattern on the substrate, the source / drain pattern including a first pattern and a second pattern spaced horizontally apart; a backside conductive structure penetrating the substrate and electrically connecting the first pattern to the power delivery network layer; and a lower insulating pattern extending under the second pattern and contacting a portion of the lower interconnects.

2. The integrated circuit device according to claim 1, wherein, The backside conductive structure includes a backside conductive pattern and a backside barrier pattern surrounding the backside conductive pattern.

3. The integrated circuit device according to claim 1, further comprising an active contact electrically connected to the second pattern.

4. The integrated circuit device according to claim 1, wherein, The lower insulating pattern has a first height in a direction perpendicular to the bottom surface of the substrate; and wherein the backside conductive structure has a second height in a direction perpendicular to the bottom surface of the substrate, the second height being greater than or equal to the first height.

5. The integrated circuit device according to claim 4, wherein, The first height and the second height are equal.

6. The integrated circuit device according to claim 1, wherein, A horizontal level of a bottom surface of the lower insulating pattern is the same as a horizontal level of a bottom surface of the backside conductive structure.

7. The integrated circuit device according to claim 1, wherein, Opposite side surfaces of the lower insulating pattern have a curved shape.

8. The integrated circuit device according to claim 7, wherein, The opposite side surfaces have a shape protruding toward the substrate.

9. The integrated circuit device according to claim 1, wherein, The substrate and the lower insulating pattern include different insulating materials relative to each other.

10. The integrated circuit device according to claim 1, wherein, The substrate and the lower insulating pattern include the same material.

11. The integrated circuit device according to claim 1, wherein, The substrate includes at least one of silicon oxide, silicon nitride, and silicon oxynitride, and the lower insulating pattern includes at least one of silicon oxide, silicon nitride, aluminum oxide, and aluminum nitride.

12. An integrated circuit device, comprising: a substrate; a power delivery network layer on a bottom surface of the substrate; a source / drain pattern on the substrate, including a first pattern and a second pattern spaced horizontally apart; a channel pattern extending on a side surface of at least one of the first pattern and the second pattern and including a stack of a plurality of semiconductor patterns spaced apart in a direction perpendicular to the bottom surface of the substrate; a gate electrode crossing the plurality of semiconductor patterns; a backside active contact penetrating the substrate and electrically connecting the first pattern to the power delivery network layer; and a lower insulating pattern extending under the second pattern, the lower insulating pattern having a top surface located at a level lower than or the same as a top surface of the backside active contact.

13. The integrated circuit device according to claim 12, wherein, The top surface of the lower insulating pattern is located at a first level in a direction perpendicular to the bottom surface of the substrate; wherein the top surface of the backside active contact is located at a second level in a direction perpendicular to the bottom surface of the substrate; and wherein the second level is higher than or the same as the first level.

14. The integrated circuit device according to claim 13, wherein, The gate electrode includes a first inner electrode, a second inner electrode, a third inner electrode, and an outer electrode, the first inner electrode extending between the lowermost semiconductor pattern of the plurality of semiconductor patterns and the substrate, the second inner electrode and the third inner electrode extending between adjacent semiconductor patterns of the plurality of semiconductor patterns, the outer electrode disposed on the uppermost semiconductor pattern of the plurality of semiconductor patterns; and wherein the second level is higher than a bottom surface of the first inner electrode and lower than a top surface of the first inner electrode.

15. The integrated circuit device according to claim 12, wherein, The gate electrode includes a first inner electrode, a second inner electrode, a third inner electrode, and an outer electrode. The first inner electrode extends between the lowermost semiconductor pattern among the plurality of semiconductor patterns and the substrate. The second inner electrode and the third inner electrode extend between adjacent semiconductor patterns among the plurality of semiconductor patterns. The outer electrode is disposed on the uppermost semiconductor pattern among the plurality of semiconductor patterns. Wherein, the integrated circuit device further includes a gate insulating pattern that surrounds the first inner electrode. And wherein, the uppermost surface of the lower insulating pattern is at the same level as the bottom surface of the gate insulating pattern.

16. The integrated circuit device according to claim 15, wherein, The uppermost surface of the backside active contact is at a level higher than the bottom surface of the gate insulating pattern and lower than the top surface of the gate insulating pattern.

17. The integrated circuit device according to claim 12, wherein, The backside active contact includes at least one of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, and Co.

18. An integrated circuit device, comprising: A substrate; A power delivery network layer on the bottom surface of the substrate, the power delivery network layer including lower interconnects; Source / drain patterns on the substrate, the source / drain patterns including horizontally spaced-apart first and second patterns; A channel pattern extending on a side surface of at least one of the first and second patterns and including a stack of a plurality of semiconductor patterns spaced apart in a direction perpendicular to the bottom surface of the substrate; A gate electrode intersecting the semiconductor patterns, the gate electrode including a first inner electrode, a second inner electrode, a third inner electrode, and an outer electrode. The first inner electrode extends between the lowermost semiconductor pattern of the semiconductor patterns and the substrate. The second inner electrode and the third inner electrode extend between adjacent semiconductor patterns of the semiconductor patterns. The outer electrode is disposed on the uppermost semiconductor pattern of the semiconductor patterns; A gate insulating pattern on the gate electrode; A gate capping pattern on the top surface of the outer electrode; A first interlayer insulating layer on the source / drain patterns; A second interlayer insulating layer on the first interlayer insulating layer and the gate capping pattern; A third interlayer insulating layer on the second interlayer insulating layer, in which a metal pattern and a via are provided; An active contact penetrating the first interlayer insulating layer and the second interlayer insulating layer and electrically connecting the second pattern to the metal pattern; A backside conductive structure penetrating the substrate and electrically connecting the first pattern to the power delivery network layer; And A lower insulating pattern extending under the second pattern, wherein, the bottom surface of the lower insulating pattern and the bottom surface of the backside conductive structure are coplanar with each other, and wherein, the uppermost surface of the lower insulating pattern is at a level lower than or the same as the uppermost surface of the backside conductive structure.

19. The integrated circuit device according to claim 18, wherein, The lower insulating pattern and the backside conductive structure are in direct contact with the lower interconnects.

20. The integrated circuit device according to claim 18, wherein, The lower insulating pattern has a first height in a direction perpendicular to the bottom surface of the substrate. Wherein, the backside conductive structure has a second height in a direction perpendicular to the bottom surface of the substrate. Wherein, the second height is greater than the first height. And wherein, the lower insulating pattern includes at least one of silicon oxide, silicon nitride, aluminum oxide, and aluminum nitride.

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