Monolithic photovoltaic solar panel with microPV cells and integrated monolithic bypass diode

Abstract

The invention relates to a monolithic photovoltaic solar panel with microPV cells and an integrated monolithic bypass diode. The PV solar panel is made of a plurality of microPV cells, where each microPV cell has its own integrated monolithic bypass diode. Each microPV cell is a multi-junction solar cell of approximately 1 cm on one side. An array of approximately 50 microPV cells all connected in series constitutes a single "PV device" that produces 90 to 100 V at low current. The PV solar panel comprises a plurality of strings of these PV devices connected in parallel, which produce a high light current of 90 to 100 V. A multi-junction microPV cell may be made from a stacked layer of Ge, GaAs, and InGaP PN.

Description

Technical Field

[0001] The present disclosure relates to a multi-junction photovoltaic (PV) micro-PV cell array with integrated monolithic bypass diodes for PV solar panels. Specifically, the present disclosure relates to multi-junction PV solar cells for PV solar panels of satellites and spacecrafts. Background Art

[0002] Figure 1 A plan view of an example of a PV solar panel 2 using large PV solar cells 4, 4', etc. mounted on a substrate 6 is schematically shown. Each PV solar cell 4, PV solar cell 4', etc. is approximately half of a 150 mm circular wafer and has an area close to 75 cm 2 . The larger cells pose challenges for high photocurrent and electrostatic discharge (ESD) and finding a useful layout on a given panel. This example shows a layout of 15 x 5 solar cell positions, where 3 cells are removed for an "out-of-panel area" 7 (which includes a tubular structural member 8). The panel can accommodate a total of 72 solar cells. The output voltage of the system and mission details may require 20 to 60 solar cells in series. Here, the example is drawn with 28 cells in series to form a circuit with a voltage of approximately 56 V (2 V per cell). The 72-cell configuration is divided into three circuits (identified by three different shadings). There are two 28-cell circuits (Circuit A and B) and one 16-cell circuit (Circuit C). The 16 cells of Circuit C produce only about half of the required voltage (i.e., 32 V). Therefore, the cells of Circuit C do not contribute any power to the system and will thus be removed from the panel 2. Complex arrangements can be designed to combine partial circuits across multiple panels. This can be somewhat helpful, but even the best has 14 cell strings and 2 cells will be left out of the panel. This shows that fully utilizing the solar energy from the entire area of a space PV solar panel can be challenging. The challenge is that a PV solar panel consists of circuits that require multiple solar cells. Each circuit requires a certain area. The area of the panel is set by other constraints. The circuits may not fully fill the area of the solar panel, which reduces the potential power output. Summary of the Invention

[0003] In one example, a micro PV cell includes: a right side and a left side; a first layer including a first semiconductor material; a second layer disposed on the first layer; a multi-junction micro PV cell stack disposed on a portion of the second layer; a first trench extending downward into the first layer and disposed on the left side of the micro PV cell; a second trench extending downward into the first layer and disposed on the right side of the micro PV cell; a third trench disposed adjacent to the second trench and extending downward into the second layer, wherein the third trench is disposed on the right side of the micro PV cell adjacent to the left side of the second trench; a first left shoulder disposed on the left side of the micro PV cell at the bottom of the first trench; a second right shoulder disposed on the right side of the micro PV cell at the bottom of the second trench; a third right shoulder disposed on the right side of the micro PV cell at the bottom of the third trench; and an integrated monolithic bypass diode including the second layer disposed on the first layer.

[0004] In another example, a photovoltaic (PV) micro PV cell includes: a left side and a right side; a first layer including a first semiconductor material; a second layer including a first semiconductor material and disposed on the first layer; a third layer including a first semiconductor material and disposed on the second layer; a fourth layer including a first semiconductor material and disposed on the third layer; a fifth layer including a second semiconductor material and disposed on the fourth layer; a sixth layer including a second semiconductor material and disposed on the fifth layer; a seventh layer including a third semiconductor material and disposed on the sixth layer; an eighth layer including a third semiconductor material and disposed on the seventh layer; a first trench extending downward into the first layer and disposed on the left side of the micro PV cell; a second trench extending downward into the first layer and disposed on the right side of the micro PV cell; a third trench extending downward into the second layer and disposed on the left side of the micro PV cell adjacent to the first trench; a fourth trench extending downward into the fourth layer and disposed adjacent to the second trench on the right side of the micro PV cell; a first left shoulder disposed on the left side of the micro PV cell at the bottom of the second trench; a second right shoulder disposed on the right side of the micro PV cell at the bottom of the fourth trench; an integrated monolithic bypass diode including the fourth layer disposed on the third layer.

[0005] In another example, the PV device includes a string of three identical micro PV cells connected in series. The string of micro PV cells includes: a first micro PV cell disposed on a common substrate; a second micro PV cell disposed on the common substrate and electrically connected in series to the first micro PV cell; a third micro PV cell disposed on the common substrate and electrically connected in series to the second micro PV cell; wherein each of the first micro PV cell, the second micro PV cell, and the third micro PV cell includes: a right side and a left side; a first layer including a first semiconductor material; a second layer disposed on the first layer; a multi-junction micro PV cell stack disposed on a portion of the second layer; a first trench extending downward into the first layer and disposed on the left side of the micro PV cell; a second trench extending downward into the first layer and disposed on the right side of the micro PV cell; a third trench disposed adjacent to the second trench and extending downward into the second layer, wherein the third trench is disposed on the right side of the micro PV cell adjacent to the left side of the second trench; a first left shoulder disposed on the left side of the micro PV cell at the bottom of the first trench; a second right shoulder disposed on the right side of the micro PV cell at the bottom of the second trench; a third right shoulder disposed on the right side of the micro PV cell at the bottom of the third trench; an integrated monolithic bypass diode including a buried PN junction disposed between the second layer and the first layer; wherein the first micro PV cell includes a first top surface; wherein the second micro PV cell includes a second top surface; wherein the third micro PV cell includes a third top surface; and a first conductor electrically connects the first layer to the first top surface of the first micro PV cell; a second conductor electrically connects the third right shoulder of the first micro PV cell to the second top surface of the second micro PV cell; a third conductor electrically connects the third right shoulder of the second micro PV cell to the third top surface of the third micro PV cell; wherein the common substrate is the first layer.

[0006] In another example, the PV device includes a string of three identical micro PV cells connected in series. The string of micro PV cells includes: a first micro PV cell disposed on a common substrate; a second micro PV cell disposed on the common substrate and electrically connected in series to the first micro PV cell; a third micro PV cell disposed on the common substrate and electrically connected in series to the second micro PV cell; wherein each of the first micro PV cell, the second micro PV cell, and the third micro PV cell includes: a left side and a right side; a first layer including a first semiconductor material; a second layer including the first semiconductor material and disposed on the first layer; a third layer including the first semiconductor material and disposed on the second layer; a fourth layer including the first semiconductor material and disposed on the third layer; a fifth layer including a second semiconductor material and disposed on the fourth layer; a sixth layer including the second semiconductor material and disposed on the fifth layer; a seventh layer including a third semiconductor material and disposed on the sixth layer; an eighth layer including the third semiconductor material and disposed on the seventh layer; a first trench extending downward into the first layer and disposed on the left side of the micro PV cell; a second trench extending downward into the first layer and disposed on the right side of the micro PV cell; a third trench extending downward into the second layer and disposed adjacent to the first trench on the left side of the micro PV cell; a fourth trench extending downward into the fourth layer and disposed adjacent to the second trench on the right side of the micro PV cell; a first left shoulder disposed on the left side of the micro PV cell at the bottom of the second trench; a second right shoulder disposed on the right side of the micro PV cell at the bottom of the fourth trench; an integrated monolithic bypass diode including a buried PN junction disposed between the fourth layer and the third layer; wherein the first micro PV cell includes a first top surface; wherein the second micro PV cell includes a second top surface; wherein the third micro PV cell includes a third top surface; a first conductor electrically connecting the first layer to the first top surface of the first micro PV cell; a second conductor electrically connecting the second right shoulder of the first micro PV cell to the second top surface of the second micro PV cell; a third conductor electrically connecting the second right shoulder of the second micro PV cell to the third top surface of the third micro PV cell; a fourth conductor electrically connecting the second right shoulder of the first micro PV cell to the first left shoulder of the second micro PV cell; a fifth conductor electrically connecting the second right shoulder of the second micro PV cell to the first left shoulder of the third micro PV cell; wherein the integrated monolithic bypass diode of each micro PV cell includes a PN junction disposed between the fourth layer and the third layer of each micro PV cell; and wherein the common substrate is the first layer.

[0007] In another example, the PV device includes an array of a plurality of micro PV cells disposed on a common substrate and electrically connected in series; wherein each micro PV cell includes: a right side and a left side; a first layer including a first semiconductor material; a second layer disposed on the first layer; a multi-junction micro PV cell stack disposed on a portion of the second layer; a first trench extending downward into the first layer and disposed on the left side of the micro PV cell; a second trench extending downward into the first layer and disposed on the right side of the micro PV cell; a third trench disposed adjacent to the second trench and extending downward into the second layer, wherein the third trench is disposed on the right side of the micro PV cell adjacent to the left side of the second trench; a first left shoulder disposed on the left side of the micro PV cell at the bottom of the first trench; a second right shoulder disposed on the right side of the micro PV cell at the bottom of the second trench; a third right shoulder disposed on the right side of the micro PV cell at the bottom of the third trench; an integrated monolithic bypass diode including a second layer disposed on the first layer; wherein the common substrate is the first layer.

[0008] In another example, the PV device includes an array of a plurality of micro PV cells disposed on a common substrate and electrically connected in series; wherein each micro PV cell includes: a left side and a right side; a first layer, the first layer including a first semiconductor material; a second layer, the second layer including the first semiconductor material and disposed on the first layer; a third layer, the third layer including the first semiconductor material and disposed on the second layer; a fourth layer, the fourth layer including the first semiconductor material and disposed on the third layer; a fifth layer, the fifth layer including a second semiconductor material and disposed on the fourth layer; a sixth layer, the sixth layer including the second semiconductor material and disposed on the fifth layer; a seventh layer, the seventh layer including a third semiconductor material and disposed on the sixth layer; an eighth layer, the eighth layer including the third semiconductor material and disposed on the seventh layer; a first trench, the first trench extending downward into the first layer and disposed on the left side of the micro PV cell; a second trench, the second trench extending downward into the first layer and disposed on the right side of the micro PV cell; a third trench, the third trench extending downward into the second layer and disposed adjacent to the first trench on the left side of the micro PV cell; a fourth trench, the fourth trench extending downward into the fourth layer and disposed adjacent to the second trench on the right side of the micro PV cell; a first left shoulder, the first left shoulder disposed on the left side of the micro PV cell at the bottom of the second trench; a second right shoulder, the second right shoulder disposed on the right side of the micro PV cell at the bottom of the fourth trench; an integrated monolithic bypass diode, the integrated monolithic bypass diode including the fourth layer disposed on the third layer; wherein the common substrate is the first layer.

[0009] In another example, the PV solar panel includes an array of a plurality of PV devices, wherein each PV device includes an array of a plurality of micro PV cells disposed on a common substrate and electrically connected in series; wherein each micro PV cell includes: a right side and a left side; a first layer including a first semiconductor material; a second layer disposed on the first layer; a multi-junction micro PV cell stack disposed on a part of the second layer; a first trench extending downward into the first layer, the first trench being disposed on the left side of the micro PV cell; a second trench extending downward into the first layer and disposed on the right side of the micro PV cell; a third trench disposed adjacent to the second trench and extending downward into the second layer, wherein the third trench is disposed on the right side of the micro PV cell adjacent to the left side of the second trench; a first left shoulder disposed on the left side of the micro PV cell at the bottom of the first trench; a second right shoulder disposed on the right side of the micro PV cell at the bottom of the second trench; a third right shoulder disposed on the right side of the micro PV cell at the bottom of the third trench; an integrated monolithic bypass diode including a second layer disposed on the first layer; wherein the common substrate is the first layer.

[0010] In another example, a PV solar panel includes an array of a plurality of PV devices, wherein each PV device includes an array of a plurality of micro PV cells disposed on a common substrate and electrically connected in series; wherein each micro PV cell includes: a left side and a right side; a first layer, the first layer including a first semiconductor material; a second layer, the second layer including the first semiconductor material and disposed on the first layer; a third layer, the third layer including the first semiconductor material and disposed on the second layer; a fourth layer, the fourth layer including the first semiconductor material and disposed on the third layer; a fifth layer, the fifth layer including a second semiconductor material and disposed on the fourth layer; a sixth layer, the sixth layer including the second semiconductor material and disposed on the fifth layer; a seventh layer, the seventh layer including a third semiconductor material and disposed on the sixth layer; an eighth layer, the eighth layer including the third semiconductor material and disposed on the seventh layer; a first trench, the first trench extending downward into the first layer and disposed on the left side of the micro PV cell; a second trench, the second trench extending downward into the first layer and disposed on the right side of the micro PV cell; a third trench, the third trench extending downward into the second layer and disposed adjacent to the first trench on the left side of the micro PV cell; a fourth trench, the fourth trench extending downward into the fourth layer and disposed adjacent to the second trench on the right side of the micro PV cell; a first left shoulder, the first left shoulder disposed on the left side of the micro PV cell at the bottom of the second trench; a second right shoulder, the second right shoulder disposed on the right side of the micro PV cell at the bottom of the fourth trench; an integrated monolithic bypass diode, the integrated monolithic bypass diode including the fourth layer disposed on the third layer; wherein the common substrate is the first layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 A schematic plan view showing an example of a PV solar panel is shown.

[0012] Figure 2A A schematic plan view showing an example of a PV solar panel according to the present disclosure is shown.

[0013] Figure 2B Shows according to the present disclosure Figure 2A A schematic plan view showing an example of a bottom electrical interconnect of a PV solar panel of.

[0014] Figure 3 Shows according to the present disclosure Figure 2A A schematic cross-sectional side view showing an example of a PV solar panel of.

[0015] Figure 4A A schematic plan view showing an example of a PV solar device according to the present disclosure is shown.

[0016] Figure 4BShows a schematic plan view of an example of a PV solar device according to the present disclosure, showing Figure 4A 45 micro PV solar cells connected in series in the device shown.

[0017] Figure 4C Shows a schematic plan view of an example of a PV solar device according to the present disclosure, which shows the continuous photocurrent path I flowing through Figure 4B forty-five micro PV cells connected in series in a series serpentine manner in the device shown device .

[0018] Figure 5A Shows a schematic plan view of an example of a pair of adjacent PV solar devices according to the present disclosure.

[0019] Figure 5B Shows an example according to the present disclosure Figure 5A Schematic close-up plan view of an example of an electrical connection between a pair of adjacent PV solar devices shown.

[0020] Figure 6A Shows a schematic cross-sectional side view of an example of a single multi-junction micro PV cell with an integrated monolithic bypass diode according to the present disclosure.

[0021] Figure 6B Shows a schematic cross-sectional side view of an example of a single multi-junction micro PV cell with an integrated monolithic bypass diode according to the present disclosure.

[0022] Figure 7A Shows a schematic cross-sectional side view of an example of a PV solar cell device according to the present disclosure, the PV solar cell device including three multi-junction micro PV cells with integrated monolithic bypass diodes all connected in series.

[0023] Figure 7B Shows a schematic cross-sectional side view of an example of a PV solar cell device according to the present disclosure, the PV solar cell device including three multi-junction micro PV cells with integrated monolithic bypass diodes all connected in series.

[0024] Figure 8A Shows a schematic cross-sectional side view of an example of a single multi-junction micro PV cell with an integrated monolithic bypass diode according to the present disclosure.

[0025] Figure 8B Shows a schematic cross-sectional side view of an example of a single multi-junction micro PV cell with an integrated monolithic bypass diode according to the present disclosure.

[0026] Figure 9AShows a schematic cross-sectional side view of an example of a PV solar cell device according to the present disclosure, the PV solar cell device including three multi-junction micro PV cells with integrated monolithic bypass diodes all connected in series.

[0027] Figure 9B Shows a schematic cross-sectional side view of an example of a PV solar cell device according to the present disclosure, the PV solar cell device including three multi-junction micro PV cells with integrated monolithic bypass diodes all connected in series.

[0028] Figure 10A Shows a schematic cross-sectional side view of an example of five multi-junction micro PV cells with integrated monolithic bypass diodes all connected in series according to the present disclosure.

[0029] Figure 10B Shows a schematic cross-sectional side view of an example of five multi-junction micro PV cells with integrated monolithic bypass diodes according to the present disclosure, all the integrated monolithic bypass diodes being connected in series with a single shaded micro PV cell.

[0030] Figure 11 Shows a schematic perspective view of an extraterrestrial satellite with a pair of PV solar panels attached to the satellite according to the present disclosure, wherein each PV solar panel includes a plurality of multi-junction PV solar devices with integrated monolithic bypass diodes (too small to be seen).

[0031] Figure 12 Shows an example of a flowchart according to the present disclosure showing the steps for manufacturing a PV solar panel.

[0032] Figure 13A Shows a schematic cross-sectional side view of an example of a single multi-junction micro PV cell with an integrated monolithic bypass diode according to the present disclosure.

[0033] Figure 13B Shows a schematic cross-sectional side view of an example of a single multi-junction micro PV cell with an integrated monolithic bypass diode according to the present disclosure.

[0034] Figure 14A Shows a schematic cross-sectional side view of an example of a PV solar cell device according to the present disclosure, the PV solar cell device including three multi-junction micro PV cells with integrated monolithic bypass diodes all connected in series.

[0035] Figure 14B Shows a schematic cross-sectional side view of an example of a PV solar cell device according to the present disclosure, the PV solar cell device including three multi-junction micro PV cells with integrated monolithic bypass diodes all connected in series.

[0036] Figure 15A A schematic cross-sectional side view showing an example of a single multi-junction micro-PV cell with an integrated monolithic bypass diode according to the present disclosure.

[0037] Figure 15B A schematic cross-sectional side view showing an example of a single multi-junction micro-PV cell with an integrated monolithic bypass diode according to the present disclosure.

[0038] Figure 16A A schematic cross-sectional side view showing an example of a PV solar cell device according to the present disclosure, the PV solar cell device including three multi-junction micro-PV cells with integrated monolithic bypass diodes all connected in series.

[0039] Figure 16B A schematic cross-sectional side view showing an example of a PV solar cell device according to the present disclosure, the PV solar cell device including three multi-junction micro-PV cells with integrated monolithic bypass diodes all connected in series. DETAILED DESCRIPTION

[0040] The terms "PV solar cell", "solar cell", and "cell" are used interchangeably. The terms "micro-PV cell" and "micro-cell" are used interchangeably. The terms "PV solar device", "solar device", and "device" are used interchangeably. The terms "first", "second", etc. refer to different positions among structural elements. The terms "right" and "right side" are interchangeable, and "left" and "left side" are interchangeable, and both refer to their respective positions as shown in the figure.

[0041] Figure 2A A schematic plan view showing an example of a PV solar panel 58 according to the present disclosure. The PV solar panel 58 includes a plurality of individual PV solar devices 64, 64', 64", etc. arranged in a regular array across a substrate 60. The graded shading of each PV solar device 64, 64', 64", etc. indicates the presence of a local voltage gradient that varies across each device 64, 64', 64", etc. from V- (in the lightly shaded area) to V+ (in the darkly shaded area). In other words, the shading from light to dark follows the voltage gradient across an individual device (e.g., device 64). In this example, the PV solar panel 58 includes five parallel rows and eight columns of devices 64, 64', 64", etc., for a total of 38 PV solar devices (note: two PV solar devices have been removed from the "removal area" 68 to make room for the tubular structural member 70). Each individual PV solar device 64, 64', 64", etc. includes a very small (e.g., 1 cm 2) An interconnected array of “micro” PV solar cells (e.g., 45 micro PV cells, not shown in this figure), all connected in series to produce a high output voltage (e.g., 90V) across each of the devices 64, 64’, 64”, etc. In some examples, the manufacturing device can have an area of approximately 150 cm 2 The details of the “device” will be described in more depth in Figure 4A , Figure 4B and Figure 4C . Each PV solar device 64, 64’, 64”, etc. includes a pair of electrical connectors (voltage tabs) 90 and 90’ located at opposite corners of the device 64, and voltage tabs 91 and 91’ located at opposite corners of the device 64’, etc. The voltage tabs 90 and 91 conduct negative voltage, and the voltage tabs 90’ and 91’ conduct positive voltage, and so on. Each PV solar device 64, 64’, 64”, etc. is shown as having a square shape with cut corners. PV solar devices 64, 64’, 64”, etc. of other shapes (including rectangles, triangles, or hexagons or combinations thereof) can be used.

[0042] Still referring to Figure 2A , in this example, the orientation of each row of eight devices 64, 64’, 64”, etc. is reversed on alternating rows. In other words, the devices 64, 64’, 64”, etc. are arranged such that the V-regions of adjacent devices 66, 66’, 66”, etc. are adjacent to each other, and the V+ regions of adjacent devices are adjacent to each other. This alternating configuration minimizes the problem of electrostatic discharge (ESD). Below the 40 PV solar devices is a finger-like array of electrical interconnects (hidden from view by the PV solar devices 64, 64’, 64”, etc.), which respectively include a negative electrical bus 62 and a positive electrical bus 63 (shown in more detail in Figure 2B ). The negative electrical bus 62 has a voltage = V-, and the positive electrical bus 63 has a voltage = V+. In this example, V- = 0V and V+ = 90V. Compared with traditional PV solar cells, each PV solar device 64, 64’, 64”, etc. generates a relatively high voltage and a relatively low photocurrent. Then each device is connected in parallel such that the entire solar panel generates a high voltage and a high photocurrent. The positive voltage tabs 90’ (V+) of each PV solar device 64, 64’, 64”, etc. are connected together across eight devices in a given row, and the negative voltage tabs 90 (V-) of each PV solar device 64, 64’, 64”, etc. are connected together across eight devices in the same row, such that the entire PV solar panel 58 generates a relatively high photocurrent at a high voltage (e.g., 90V).

[0043] Figure 2B Shows according to the present disclosure Figure 2ASchematic plan view of an example of the bottom electrical interconnection structure 71 of the PV solar panel 58. The interconnection structure 71 includes a pair of interdigital electrical conductors disposed on an insulating substrate 60 and connected to a positive electrical bus 63 and a negative electrical bus 62. The positive electrical bus 63 includes three parallel strips 72, 72', and 72" connected to the positive electrical bus 63. The negative electrical bus 62 includes three parallel strips 74, 74', 74" connected to the negative electrical bus 62, and the three parallel strips 74, 74', 74" are disposed between three positive electrical parallel strips 72, 72' (i.e., interdigitated between the three positive electrical parallel strips 72, 72', and 72'). A pair of PV solar devices 64 and 64' are shown. Negative voltage tabs 90 and 91 are electrically connected to the negative electrical strip 74, and positive voltage tabs 90' and 91' are electrically connected to the positive electrical strip 72.

[0044] Figure 3 An example according to the present disclosure is shown Figure 2A Schematic cross-sectional side view of an example of the PV solar panel 58. By placing the conductor under the device 64, a larger exposed area can be dedicated to power generation. The PV solar device 64 is glued to the insulating substrate 60 at two positions with a left adhesive strip 80 and a right adhesive strip 80', and the left adhesive strip 80 and the right adhesive strip 80' can be, for example, about 6 to 10 mils thick respectively. A gap 78 is defined by the device 64 and the substrate 60. A copper conductor 50 (which can be a "2 ounce" copper foil, tape, or wire) is disposed in the gap 78. The copper conductor 50 is located on top of an insulating polymer layer 86 (such as, for example, polyimide). The insulating polymer layer 86 can be, for example, about 1 to 2 mils thick. The copper conductor 50 is encapsulated in an upper layer 84 of adhesive. The upper adhesive layer (such as the upper layer 84) can be, for example, about 2 to 4 mils thick. An upper layer 82 of insulating polymer (such as, ) is disposed above the upper layer 84 of adhesive. The upper insulating polymer layer 82 can be, for example, about 1 to 2 mils thick. The insulated copper conductor 50 is partially embedded in the right adhesive strip 80'. A material such as Dupont Pyralux AP is a good choice for coating Cu . This can be laminated with Dupont Pyralux LF, which is an adhesive layer on . This material group can be widely obtained from suppliers and can be fabricated into the assembly. Similar materials are available from other suppliers based on polyimide as well as PEEK and ETFE plastics. A variety of adhesives can be used to attach such a flexible circuit to the panel. These can be acrylic adhesives such as 3M 9460PC or 3M 966, or silicones such as NUSIL CV4-1161-5. The thickness of the upper adhesive layer 84 can be thicker than the copper conductor 50.

[0045] Figure 4A Shows a schematic plan view of an example of a PV solar device 64 according to the present disclosure. The device 64 includes a plurality of semiconductor-based multi-junction micro PV cells 100, 102, 104, 188 (i.e., through a dual port) defined by a square network of vertical trenches 92 and horizontal trenches 94. Conductive voltage tabs 90 and 90' are provided at opposite corners of the device 64.

[0046] Figure 4B Shows a schematic plan view of an example of a PV solar device according to the present disclosure, which shows all Figure 4A Forty-five micro PV cells 100, 102, 104, 188 connected in series with the device shown. Conductive voltage tabs 90 and 90' are provided at opposite corners of the device 64. Conductive voltage tabs 96, 96', 96", etc. are interconnected with adjacent micro PV cells 100, 102, 104, etc. respectively. Conductive voltage tabs 98 and 98' are interconnected with multi-diagonal micro PV cells 108 to 110 and 178 to 180 respectively. These voltage tabs can be, for example, metal conductors added to the completed PV device by wire or tape bonding. Alternatively, these conductors can be realized through multiple steps of patterning insulators and conductors in the wafer manufacturing process.

[0047] Figure 4C Shows a schematic plan view of an example of a PV solar device according to the present disclosure, which shows the continuous photocurrent path 190I Figure 4B flowing through all of the forty-five micro PV cells 100, 102, 104, 188 connected in series in a series serpentine manner in the device shown device . For example, using a multi-junction cell, if the size of each micro cell 100 is 1 cm 2 , then each micro cell 100 will generate a photocurrent of approximately 20 mA. Therefore, for a power output of 0.04 W per micro cell, each micro cell will generate a photocurrent of approximately 20 mA and increase by 2 V. This will continue across the forty-five micro PV cells connected in series such that at the lower right corner, the output voltage tab 90' of the device 64 will deliver electrical power at 90 V, 20 mA flowing through the circuit, and 1.8 W of power for each device 64. For example, in the case where eight devices 64, 64', etc. are connected in parallel across a single horizontal row of the PV solar panel 58 (see Figure 2A),An array of 8 devices in parallel will produce 0.16 A at an electrical power of 90 V or 14 W. A solar panel 58 with 5 rows (each row having 8 devices) will produce 0.8 A at a power of 90 V or 72 W. A series array of 45 micro PV cells 100, 102, 104, etc. that produce 90 V is referred to as a "device", and each sub - cell that produces 2 V is referred to as a "micro PV cell" or "micro - cell". The term "micro - cell" refers to a solar cell having a size (area) of approximately 1 cm 2 of solar cell.

[0048] In orbit, solar cells can be shaded. When they are shaded, the circuit voltage will reverse - bias the cells. Thus, in this example, shading (which is common) will reverse - bias the solar cell device by up to 40 V. The breakdown voltage of a triple - junction PV solar cell is 20 volts, so reverse - biasing can damage the device. A bypass diode for each solar cell device can prevent this damage and will be further discussed in the appendix Figure 6A and Figure 6B below.

[0049] Figure 5A FIG. shows a schematic plan view of an example of a pair of adjacent PV solar devices 64 and 64' according to the present disclosure. The area defined by the dashed circle 200 is enlarged and shown in Figure 5B below. This pair of devices 64 and 64' are electrically interconnected to extensions 97 and 97' of the negative electrical strip 74 via voltage tabs 90 and 91, respectively. This pair of devices 64 and 64' are electrically interconnected to the positive electrical strip 72 via voltage tabs 90' and 91'. Electrical strips 7 and 72 are disposed above polymer strips 95 and 95', respectively. A discrete blocking diode 218 is connected to the right - hand strip 216', and the right - hand strip 216' is connected to a conductive extension 212 of the positive electrical strip 72.

[0050] Figure 5B FIG. shows an example of an electrical connection (shown by the dashed circle 200) between a pair of adjacent PV solar devices 64 and 64' according to the present disclosure Figure 5A in a schematic enlarged plan view. The PV solar device 64 is connected to the positive electrical strip 72 via a voltage tab 90', the voltage tab 90' is connected to a conductor 220, the conductor 220 is connected to the left - hand strip 216, the left - hand strip 216 is connected to a discrete blocking diode 218, the discrete blocking diode 218 is connected to the right - hand strip 216', and the right - hand strip 216' is connected to a conductive extension 212 of the positive electrical strip 72. A blocking diode located between the PV device and the bus wiring is an industry standard for protecting these devices in parallel in the event that one of these devices is defective.

[0051] Figure 6AA schematic cross-sectional side view showing an example of a single multi-junction micro PV cell 100 with an integrated monolithic bypass diode 10 according to the present disclosure is shown. The p-doped first layer 12 with width = E includes a first semiconductor material and serves as a substrate for fabricating the micro cell 100 thereon. The n-doped second layer 14 with width = A includes a first semiconductor material and is disposed on the p-doped first layer 12. The multi-junction PV solar cell stack 16 with width = B is disposed on the n-doped second layer 14. The first vertical trench 22 with width = D extends downward to the left side of the p-doped first layer 12. The second vertical trench 22' with width = D extends downward to the right side of the p-doped first layer 12. The third vertical trench 52 with width C extends downward into the n-doped second layer 14 on the right side of layer 14. Sunlight 20 irradiates on the upper surface 18 of the PV solar cell stack 16 and generates a photocurrent I pc . The PN junction 15 is disposed between the p-doped first layer 12 and the n-doped second layer 14. The bypass diode 10 includes the PN junction 15. The first shoulder 26 is disposed on the left side of the n-doped second layer 14, and the second shoulder 24 is disposed on the right side of the n-doped second layer 14. The multi-junction PV solar cell stack 16 may include 1 or 2 or 3 or more PN junctions. A < E, B < A, C < B, D < B, A = B + C, E = B + C + 2D.

[0052] Figure 6B A schematic cross-sectional side view showing an example of a single multi-junction micro PV cell 100 with an integrated monolithic bypass diode 10 according to the present disclosure is shown. This stack shows two solar cell PN junctions on top of the bypass diode PN junction. Both the solar cell and the bypass junction have P-on-N polarity. The p-doped first layer 12 with width = E includes germanium (Ge) and serves as a substrate for fabricating the micro cell 100 thereon. The n-doped second layer 14 with width = A includes Ge and is disposed on the p-doped first layer 12. The multi-junction PV solar cell stack 16 with width = B is disposed on the n-doped second layer 14. The PV solar cell stack 16 includes four stacked semiconductor layers 42, 44, 46, and 48. The p-doped third layer 42 with width = B includes gallium arsenide (GaAs) and is disposed on the n-doped second layer 14. The n-doped fourth layer 44 with width = B includes gallium arsenide (GaAs) and is disposed on the p-doped third layer 42. The p-doped fifth layer 46 with width = B includes indium gallium phosphide (InGaP) and is disposed on the n-doped fourth layer 44. The n-doped sixth layer 48 with width = B includes indium gallium phosphide (InGaP) and is disposed on the p-doped fifth layer 46.

[0053] Figure 6BThe example shown is almost identical to a typical triple-junction solar cell. The difference lies in the wiring. As is typical, the negative connection comes from the surface facing the sun (N side). Instead of coming from the typical bottom p side, the positive connection comes from the n side of the bottom PN junction (e.g., the second shoulder 24). This wiring configuration enables the bottom PN junction to function as a bypass diode. Now change the Ge structure of the triple-junction solar cell. The Ge layer is no longer used as the third solar cell but is used to create the bypass diode 10. The top and middle PN junctions, composed of layers 48 and 46 and 44 and 42 respectively, are configured such that the N side of the PN junction faces the sun. The light absorbed in the top and middle PV cells will generate a photocurrent I flowing downward to the p-doped (Ge) first layer 12. pc . The top cell and the middle cell are connected by a tunnel junction (not shown). Similarly, the bottom p side of the middle cell will then be a tunnel junction connection to the n-doped (Ge) second layer 14. Thus, the photocurrent flows into the n-doped (Ge) second layer 14.

[0054] Still referring to Figure 6B , the Ge wafer (first layer 12) will be etched and fabricated to have each micro PV cell 100 on its own mesa. Each mesa is a separate multi-junction micro PV cell 100. The p-Ge first layer 12 is located below the n-Ge second layer 14. This PN Ge diode blocks the flow of photocurrent from the multi-junction micro PV cell 100 into the p-Ge first layer 12. The mesa is etched into the n-Ge second layer 14 and through the n-Ge second layer 14. Thus, each multi-junction micro cell 100 generates a photocurrent separately. The sides of the mesa will have a stepped edge (shoulder 24), where a portion of the n-Ge second layer 14 is exposed. An electrical connection is formed between the n-Ge second layer 14 and the top surface 18' of the n-type top cell electrode of an adjacent micro PV cell 102 (see Figure 7B ). This allows multiple multi-junction micro PV cells 100, 102, 104, etc. to be connected in series to generate a higher output voltage. These micro PV cells 100, 102, 104, etc. are all located on a single common Ge substrate 12. This common Ge substrate defines the device 64, where multiple multi-junction micro PV cells 100, 102, 104, etc. are connected in series.

[0055] Still referring to Figure 6B, a first vertical groove 22 with width = D extends to the left side of the p-doped first Ge layer 12. A second vertical groove 22' with width = D extends to the right side of the p-doped first germanium layer (i.e., the first Ge layer 12). A third vertical groove 52 with width = C extends into the n-doped second Ge layer 14 on the right side of layer 14. Sunlight 20 irradiates on the upper surface 18 of the PV solar cell stack 16. A PN junction 15 is disposed between the p-doped first Ge layer 12 and the n-doped second Ge layer (e.g., the n-doped second layer 14). The bypass diode 10 includes the PN junction 15. A first shoulder 26 is disposed on the left side of the n-doped second Ge layer (e.g., the n-doped second layer 14), and a second shoulder 24 is disposed on the right side of the n-doped second Ge layer (e.g., the n-doped second layer 14).

[0056] Figure 7A A schematic cross-sectional side view showing an example of a PV solar cell device 64 according to the present disclosure is presented. The PV solar cell device 64 includes three multi-junction micro PV cells 100, 102, 104 all connected in series with integrated monolithic bypass diodes 10, 10', 10". A p-doped first layer 12 with width = F including a first semiconductor material serves as a common substrate 600 (i.e., the p-doped first layer 12) for supporting all three micro PV cells 100, 102, 104. The first micro cell 100 includes a first PV solar cell stack 16 with width = B disposed on an n-doped second layer 14 with width + A. The n-doped second layer is disposed on the p-doped first layer 12. The micro PV cells 102 and 104 are the same as the micro cell 100, and their descriptions are not repeated here.

[0057] Still referring to Figure 7A , a first conductor 28 connects the first shoulder 26 (e.g., the left shoulder) of the p-doped first layer 12 to the upper surface 18 of the PV solar cell stack 16. A second conductor 30 connects the right shoulder (e.g., the second shoulder 24) on the n-doped second layer 14 to the upper surface 18' of the second PV solar cell stack 16' (of the micro cell 102). A third conductor 30' connects the right shoulder 24' on the n-doped second layer 14' to the upper surface 18" of the third PV solar cell stack 16" (of the micro cell 104). Thus, the micro PV cells 100, 102, and 104 are all connected in series. Note: V1 < V2 < V3. The conductor 30" is the positive voltage terminal of the circuit and extends to an electrical load (not shown). The conductor 31 is the negative voltage terminal of the circuit and extends to an electrical load (not shown).

[0058] Figure 7BSchematic cross-sectional side view showing an example of a PV solar cell device 64 according to the present disclosure, including three multi-junction micro PV cells 100, 102, 104, the three multi-junction micro PV cells 100, 102, 104 having integrated monolithic bypass diodes all connected in series. The micro PV cells 100, 102, and 104 and their interconnects are the same as the micro PV cells shown in Figure 7A , except as follows. Figure 7B The PV solar cell stacks 16, 16', and 16'' are the same as the PV solar cell stack 16 previously described in Figure 6B . Therefore, their details will not be repeated here.

[0059] Still referring to Figure 7B , the multi-junction micro PV cells 100, 102, 104 each have their own built-in integrated bypass diodes 10, 10', 10'' respectively. The p-Ge substrate 12 is located below each micro PV cell 100, 102, 104 and is connected to the V-bus (not shown, which is achieved by adding a wire (e.g., conductor 31) next to a conductor (e.g., the first conductor 28)). The N-Ge second layer 14 of each micro PV cell is at a more positive voltage. Thus, the Ge PN junction is reverse-biased and no photocurrent flows. When any micro PV cell is shaded, the photocurrent no longer flows through the micro cell. Then, from the other illuminated micro PV cells on the device, the device becomes negatively biased, and the Ge PN junction of the dark micro cell is forward-biased with photocurrent flowing. The circuit photocurrent I pc is maintained using the Ge PN bypass diode, preventing a dangerous reverse-biased condition of the micro cell. The Ge bypass diodes 10, 10', 10'' bypass all the cells from the V-side of the circuit to the dark (shaded) micro cell (e.g., micro cell 102). When a micro cell is shaded, the output voltage of the circuit will drop. The devices 64, 64', etc. will be protected, and when the light returns, the output voltage and power will return. In other words, the shaded micro cell 100 is at risk of a dangerous reverse bias with the circuit minus one or more dark micro cells. Thus, an example of a device with 45 micro cells may have one dark micro cell across which is reverse-biased 88V. The bypass diode reduces this reverse bias to the voltage of the bypass diode (for a Ge diode, the voltage is ~0.2V).

[0060] The bypass junction composed of the Ge PN junction is similar to a conventional multi-junction solar cell and is easy to form. The Ge PN junction may have limited ability as a bypass diode. The Ge bypass diode does not need to be photosensitive. Also, the bypass diode will require a reverse breakdown voltage greater than the circuit voltage. When operating Figure 7BWhen all three micro PV cells are in [a certain state], the bypass diode 10" will be reverse biased by 4V. In practical applications, the circuit voltage will be 20V, 100V or higher. It is difficult to make the Ge PN junction have a breakdown voltage at this level. A bypass diode made of GaAs or InGaP material will have a larger breakdown voltage than Ge. Therefore, the second layer (for example, the n-doped second layer 14) can be replaced with a GaAs or InGaP PN junction. Exchanging the p-Ge first layer 12 for a semi-insulating (SI) GaAs first layer 12 further improves the protection and operation of the circuit.

[0061] Figure 8A FIG. [number] shows a schematic cross-sectional side view of an example of a single multi-junction micro PV cell 100 with an integrated monolithic bypass diode 10 according to the present disclosure. The semi-insulating (SI) first layer 412 having a width = G includes a first semiconductor material and serves as a substrate for fabricating the micro cell 100 thereon. The change to the semi-insulating substrate (the first SI layer 412) prevents photocurrent from flowing between adjacent micro PV cells 100, 102, 104, etc. The p-doped third layer 32 having a width = E includes a second semiconductor material and is disposed on the n-doped second layer 14. The n-doped fourth layer 34 having a width = E includes a second semiconductor material and is disposed on the p-doped third layer 32. The multi-junction PV solar cell stack 16 having a width = B is disposed on the n-doped fourth layer 34 and may include 1 or 2 or 3 PN junctions.

[0062] Still referring to Figure 8A , a first vertical trench 22 having a width = F extends to the left of the SI first layer 412. A second vertical trench 22' having a width = F extends to the right of the SI first layer 412. A third vertical trench 36 having a width = C extends into the n-doped second layer 14 on the right side of the layer 14. A fourth vertical trench 38 having a width = D extends into the n-doped fourth layer 34 on the right side of the fourth layer 34. Sunlight 20 irradiates on the upper surface 18 of the PV solar cell stack 16. The PN junction 17 is disposed between the p-doped third layer 32 and the n-doped fourth layer 34. The bypass diode 10 includes the PN junction 17. A first shoulder 26 is disposed on the left side of the SI first layer 412, and a second shoulder 26' is disposed on the right side of the SI first layer 12. A third shoulder 54 is disposed on the left side of the n-doped second layer 14. A fourth shoulder 40 is disposed on the right side of the n-doped fourth layer 34. The multi-junction PV solar cell stack 16 may include 1, 2, or 3 PN junctions. A < E, B < A, C < B, D < B, E < G, E = B + D, A = C + B + D, and G = B + C + D + 2F.

[0063] Figure 8BA schematic cross-sectional side view of an example of a single multi-junction micro PV cell 100 with an integrated monolithic bypass diode 10 in accordance with the present disclosure is shown. A multi-junction PV solar cell stack 16 of width = B is disposed on an n-doped fourth layer 34 and includes four semiconductor layers 42, 44, 46, and 48. A p-doped fifth layer 42 of width = B includes gallium arsenide (GaAs) and is disposed on an n-doped GaAs fourth layer (e.g., n-doped fourth layer 34). An n-doped sixth layer 44 of width = B includes gallium arsenide (GaAs) and is disposed on the p-doped GaAs fifth layer 42. A p-doped seventh layer 46 of width = B includes indium gallium phosphide (InGaP) and is disposed on the n-doped GaAs sixth layer 44. An n-doped eighth layer 48 of width = B includes indium gallium phosphide (InGaP) and is disposed on the p-doped InGaP seventh layer 46.

[0064] Still referring to Figure 8B , this example will achieve a higher breakdown voltage and each micro PV cell 100 is bypassed independently. This is achieved by using a semi-insulating GaAs substrate (e.g., SI first layer 412). Each micro cell 100 is an InGaP+GaAs multi-junction P-on-N type micro PV cell. The bypass diode 10 is a P-on-N type GaAs diode. Each mesa has a micro PV cell 100 electrically connected in parallel to the bypass diode 10. If the micro PV cell 100 does not flow photocurrent, the bypass diode 10 will allow the photocurrent to flow. The substrate (SI first layer 412) can be lightly doped or semi-insulating GaAs to prevent photocurrent from flowing in the substrate (SI first layer 412). Note that shoulders (e.g., fourth shoulder 40 and third shoulder 54) are used for electrical connections to adjacent micro PV cells. Current from the micro cell (~1 cm 2 ) laterally moves to these connection points. Therefore, the sheet resistance of the layers (e.g., n-doped fourth layer 34 and n-doped second layer 14) needs to be low to have a low voltage loss. The mobility of n-GaAs is much higher than that of p-GaAs, resulting in a much lower sheet resistance for the n-GaAs layer to carry current laterally. Connections (e.g., third shoulder 54) can be made to the layer (e.g., p-doped third layer 32), but the connection (e.g., third shoulder 54) will have a large voltage loss across the p-GaAs layer (e.g., p-doped third layer 32). By adding a tunnel junction and an n-GaAs layer (e.g., n-doped second layer 14), this resistance and voltage drop are reduced.

[0065] Figure 9ASchematic cross-sectional side view showing an example of a PV solar cell device 64 according to the present disclosure, the PV solar cell device 64 including three multi-junction micro PV cells 100, 102, 104, each having integrated monolithic bypass diodes 10, 10', 10" all connected in series. Each micro PV cell 100, 102, 104 includes a design identical to the design shown in Figure 8A , except that the SI first semiconductor layer (e.g., SI first layer 412) extends across the bases (i.e., common substrate 600) of all three micro PV cells 100, 102, 104. In Figure 9A , a first conductor 28 interconnects the third shoulder 54 of the first micro cell 100 to the upper surface 18 of the PV solar cell stack 16. A second conductor 76 interconnects the fourth shoulder 40 of the micro cell 100 to the upper surface 18' of the second micro cell 102. A third conductor 78 interconnects the fourth shoulder 40 to the third shoulder 54' of the second micro cell 102. The second conductor 76 carries the photocurrent between the series-connected solar cells, while the third conductor 78 connects the micro PV cell 100 to the bypass diode 10'. These interconnects are repeated for the next set of connections between the second micro cell 102 and the third micro cell 104 all connected in series. Note: V1 < V2 < V3.

[0066] Figure 9B Schematic cross-sectional side view showing an example of a PV solar cell device 64 according to the present disclosure including three multi-junction micro PV cells 100, 102, 104 having integrated monolithic bypass diodes all connected in series. The micro PV cells 100, 102, and 104 and their interconnects are the same as the micro PV cells shown in Figure 9A , except as follows. Figure 9B The PV solar cell stacks 16, 16', and 16" are the same as the PV solar cell stack 16 previously described in Figure 8B . Therefore, their details will not be repeated here.

[0067] The wiring between the micro PV cells and the bypass diodes can be achieved by wafer manufacturing processes, by wire or tape bonding processes, printing metals, or other methods known in device manufacturing. Each micro PV cell 100, 102, 104 has GaAs PN bypass diodes 10, 10', 10" respectively below the PV solar cell stack 16.

[0068] Figure 10AFIG. 0 shows a schematic cross-sectional side view of an example of a PV solar cell device 64 according to the present disclosure. The PV solar cell device 64 includes five multi-junction micro PV cells 100, 102, 104, 106, and 108, which respectively have integrated monolithic bypass diodes 10, 10', 10", 10"', 10"", and are all connected in series. Each of the five micro PV cells 100, 102, 104, 106, and 108 has the same structure and electrical interconnects, which are the same as those previously described in Figure 6A and Figure 7A and are further discussed herein. In the case where each micro cell generates approximately 2 volts per cell, when all the micro PV cells are fully illuminated by light, the final voltage of the last micro cell 108 in the series of the five micro PV cells 100, 102, 104, 106, and 108 is equal to 10V.

[0069] Figure 10B FIG. 8 shows a schematic cross-sectional side view of an example of a PV solar cell device 64 according to the present disclosure. The PV solar cell device 64 includes five multi-junction micro PV cells 100, 102, 104, 106, and 108, which respectively have integrated monolithic bypass diodes 10, 10', 10", 10"', 10"", all connected in series with a single shaded micro PV cell 106. In this example, when the fourth micro cell 106 is shaded, the bypass diode 10"' is activated. The bypass diode 10"' prevents the shaded micro cell 106 from being reverse biased in this case, which causes the photocurrent I pc to bypass through the shaded micro cell 106. The p-Ge SI first layer 412 is common to all the bypass diodes. Therefore, all the micro PV cells from the V-side are bypassed to the dark micro cell. In this example, the bypass current follows the dotted arrow line through the p-Ge SI first layer 412 to bypass the micro cells 100, 102, 104, 106. The bypass current flows through the p-Ge SI first layer 412, and then the dark micro cell 106 forward biases the bypass diode 10", and the bypass current then transitions to the remaining illuminated micro PV cells. In this example, that cell is the micro cell 108. In the case where V- is assumed to be 0V, the voltage drop of the bypass diode results in a negative voltage at the negative side of the micro cell 108. If the bypass diode is GaAs, the voltage will be close to -1V. The illuminated micro cell 108 then adds 2V, resulting in the circuit generating 1V. This is a lower voltage and lower output power. However, this is only the case when shaded. The circuit is fully protected, so when the shading is removed, the circuit will return to full power. And in this novel configuration, the 90V circuit has an area of 150 cm 2 which is much smaller than a conventional solar cell array.

[0070] In an example with a semi-insulating substrate, each micro-PV cell has a wire carrying the photocurrent on the negative and positive ends. The bypass current is transmitted through the substrate (e.g., the SI first layer 412) to the darkened cell. The SI substrate (e.g., the SI first layer 412) does not allow current to flow, so a third conductor 78 is needed between the micro-PV cells. Then, each bypass diode is independent of the substrate (e.g., the SI first layer 412), and it is easier to use GaAs or InGaP materials to fabricate high-quality bypass diodes with low leakage current and high breakdown voltage. Each bypass diode is now connected to an adjacent cell. When the circuit is operating normally, each bypass diode will be reverse-biased by the micro-cell (which is close to 2V). It is important to minimize any reverse-bias leakage current through the bypass diode as it reduces the power output of the circuit. The SI substrate (e.g., the SI first layer 412) causes the bypass diode to be reverse-biased at 2V where the leakage current is low. A configuration with a p-Ge substrate (e.g., the SI first layer 412) results in the reverse bias of the bypass diode being as high as the circuit voltage, leading to a larger leakage current.

[0071] In some examples, no metal coating is used or required on the back surface of the p-doped first layer 12.

[0072] In some examples, each micro-PV cell has a buried Ge PN junction as a bypass diode.

[0073] Figure 11 A schematic perspective view of an example of an extraterrestrial satellite 500 according to the present disclosure having a pair of PV solar panels 510, 510' is shown, the pair of PV solar panels 510, 510' being attached to the satellite 500 using a pair of structural members 520, 520' respectively, wherein each PV solar panel 510, 510' includes a plurality of multi-junction PV solar devices 64, 64', etc. having integrated monolithic bypass diodes (too small to be seen). The PV solar devices 64, 64', etc. are fabricated using the same configurations and semiconductor processes disclosed herein.

[0074] An example of method steps for fabricating a PV solar panel 58 using micro-PV cells 100, 102, 104, etc. respectively having integrated monolithic bypass diodes 10, 10', and 10'' (reference Figure 6A and Figure 7A ) is as follows:

[0075] Step 300 provides a p-doped Ge wafer;

[0076] Step 310 forms an n-doped Ge second layer over the p-doped Ge wafer;

[0077] Step 320 fabricates a multi-junction PV solar cell stack having 1 to 3 PN junctions;

[0078] Step 330: Etch the pads epitaxially for subsequent tape bonding;

[0079] Step 340: Cut trenches through the second n-doped Ge layer down to the p-doped Ge wafer;

[0080] Step 350: Deposit front-side metal on the second n-doped Ge layer;

[0081] Step 360: Bond multiple micro PV cells in series with a tape;

[0082] Step 370: Cut individual devices from the fabricated p-doped Ge wafer into multiple trimmed squares;

[0083] Step 380: Weld interconnects between the multiple trimmed squares;

[0084] Step 390: Assemble the interconnected devices into a solar panel; and

[0085] Step 400: Encapsulate the assembled solar panel.

[0086] Figure 12 An example of a flowchart illustrating the above steps 300 to 400 for manufacturing the PV solar panel 58 is shown.

[0087] Figure 13A A schematic cross-sectional side view of an example of a single multi-junction micro PV cell 100 with an integrated monolithic bypass diode 10 according to the present disclosure is shown. This example is the same as the example shown in Figure 6A except as follows. An additional semiconductor layer (layer 56) is inserted between the second layer 14 and the PV solar cell stack 16. In this example, the second layer 14 may include a p-doped second semiconductor material, and the additional layer 56 may include an n-doped layer of the same second semiconductor material. A PN junction 19 can be seen at the intersection of the second layer 14 and the third layer 56. The multi-junction PV solar cell stack 16 may include 1 or 2 or 3 PN junctions.

[0088] Figure 13B A schematic cross-sectional side view of an example of a single multi-junction micro PV cell 100 with an integrated monolithic bypass diode 10 according to the present disclosure is shown. This example is the same as the example shown in Figure 6BThe example shown is the same, except as follows. Here, an additional layer (i.e., the third layer 56) is inserted between the second layer 14 and the third layer 42 of the PV solar cell stack 16. In this example, the second semiconductor material is GaAs. The first layer 12 is p-Ge, the second layer 14 is p-GaAs (not n-Ge as in the previous example), and the third layer 56 is n-GaAs. Since the additional layer 56 is inserted into the micro PV cell 100, the total number of layers increases to 7. The bypass diode 10 includes a GaAs PN junction 19, which includes the intersection of the p-GaAs second layer 14 and the n-GaAs third layer 56.

[0089] Still referring to Figure 13B , Figure 13B the use of the GaAs bypass diode 10 in provides a much higher breakdown voltage than Figure 6B the Ge PN diode 10 previously used in. To prevent light from irradiating the GaAs bypass diode 10, the GaAs second micro PV cell (i.e., layers 42 and 44) can be thick enough to effectively block the incident sunlight 20 from reaching the GaAs bypass diode 10. Alternatively or additionally, a distributed Bragg reflector (DBR) (not shown) can be inserted above the GaAs bypass diode 10 to prevent unwanted irradiation of the GaAs bypass diode 10. The p-GaAs of the bypass diode 10 enables the photocurrent to flow into the Ge substrate 12. This can be achieved with the p-Ge base layer 12.

[0090] Figure 14A FIG. shows a schematic cross-sectional side view of an example of a PV solar cell device 63 according to the present disclosure, the PV solar cell device 63 including three multi-junction micro PV cells 100, 102, 104 all connected in series with integrated monolithic bypass diodes 10, 10', 10". Figure 14A Same as Figure 7A , except as follows. An additional semiconductor layer (layer 56) is inserted between the second layer 14 and the PV solar cell stack 16. In this example, the second layer 14 may include a p-doped second semiconductor material, and the layer 56 may include an n-doped layer of the same second semiconductor material.

[0091] Figure 14B FIG. shows a schematic cross-sectional side view of an example of a PV solar cell device 63 according to the present disclosure, the PV solar cell device 63 including three multi-junction micro PV cells 100, 102, 104 all connected in series with integrated monolithic bypass diodes 10, 10', 10". Figure 14B Same as Figure 7BThe same, with the differences as follows. In this example, the second semiconductor material is GaAs. Here, an additional n-GaAs layer 56 is inserted between the p-doped GaAs second layer 14 and the p-GaAs third layer 42. Due to the insertion of the additional layer 56 into the micro PV cell 100, the total number of layers increases to 7.

[0092] Figure 15A FIG. shows a schematic cross-sectional side view of an example of a single multi-junction micro PV cell 100 with an integrated monolithic bypass diode 10 according to the present disclosure. The semi-insulating (SI) first layer 412 having a width = G includes a first semiconductor material and serves as a substrate for fabricating the micro cell 100 thereon. The n-doped second layer 14 having a width = A includes a second semiconductor material and is disposed on the SI first layer 12. The p-doped third layer 32 having a width = E includes a p-doped second semiconductor material and is disposed on the n-doped second layer 14. The n-doped fourth layer 34 having a width = E includes a second semiconductor material and is disposed on the p-doped third layer 32. The multi-junction PV solar cell stack 16 having a width = B is disposed on the n-doped fourth layer 34, and the stack 16 may include 1 or 2 or 3 PN junctions. Figure 15A The other features are the same as Figure 8A and will not be repeated here.

[0093] Figure 15B FIG. shows a schematic cross-sectional side view of an example of a single multi-junction micro PV cell 100 with an integrated monolithic bypass diode 10 according to the present disclosure. This example is the same as Figure 8B except for the following differences. In this example, both the first semiconductor material and the second semiconductor material are GaAs. The second layer 14 includes p-GaAs (not n-GaAs as Figure 8B shown).

[0094] Figure 16A FIG. shows a schematic cross-sectional side view of an example of a PV solar cell device 64 according to the present disclosure, the PV solar cell device 64 including three multi-junction micro PV cells 100, 102, 104, which respectively have integrated monolithic bypass diodes 10, 10', 10'' all connected in series. Each micro cell 100, 102, 104 includes a design the same as the design shown in Figure 8A except that the first SI semiconductor layer 12 extends across the bases (i.e., the common substrate 600) of all three micro PV cells 100, 102, 104. In Figure 16AIn [the figure], a first conductor 28 interconnects a third shoulder 54 of a first microcell 100 to an upper surface 18 of a PV solar cell stack 16. A second conductor 76 interconnects a fourth shoulder 40 of the microcell 100 to an upper surface 18' of a second microcell 102. A third conductor 78 interconnects the fourth shoulder 40 to a third shoulder 54' of the second microcell 102. These interconnects are repeated for the next set of connections between all of the serially-connected second microcells 102 and third microcells 104. Note: V1 < V2 < V3. In this example, the second layers 14, 14', 14'' comprise a p-doped second semiconductor material.

[0095] Figure 16B FIG. [number] shows a schematic cross-sectional side view of an example of a PV solar cell device 64 in accordance with the present disclosure, the PV solar cell device 64 including three multi-junction micro PV cells 100, 102, 104 that are all serially-connected and have integrated monolithic bypass diodes. The micro PV cells 100, 102, and 104 and their interconnects are the same as Figure 9A the micro PV cells 100, 102, 104 shown in [reference], except as follows. Figure 16B The PV solar cell stacks 16, 16', and 16'' of [the figure] are the same as the PV solar cell stacks 16, 16', 16'' previously described in Figure 9B [reference]. In this example, the second layers 14, 14', 14'' comprise p-doped GaAs (not n-GaAs as in Figure 9B [reference]).

[0096] In some examples, the surface area of the sun (or other light source) exposed to a single micro PV cell can be in the range of about 0.5 to about 2 cm 2 . In some examples, the surface area of a single micro PV cell can be less than or equal to about 1 cm 2 .

[0097] In some examples, the surface area of the sun (or other light source) exposed to a single PV device can be in the range of about 20 to about 100 cm 2 . In some examples, the surface area of a single PV device can be greater than or equal to about 45 cm 2 .

[0098] Further, the present invention includes the following examples:

[0099] Example 1. A photovoltaic (PV) micro PV cell, the photovoltaic (PV) micro PV cell comprising: a left side and a right side; a first layer, the first layer comprising a p-doped first semiconductor material; a second layer, the second layer comprising an n-doped first semiconductor material and disposed on the first layer; a multi-junction micro PV cell stack, the multi-junction micro PV cell stack disposed on a portion of the second layer; a first trench, the first trench extending downwardly into the first layer and disposed on the left side of the micro PV cell; a second trench, the second trench extending downwardly into the first layer and disposed on the right side of the micro PV cell; a third trench, the third trench disposed adjacent to the second trench and extending downwardly into the second layer, wherein the third trench is disposed on the right side of the micro PV cell adjacent to the left side of the second trench; a first left shoulder, the first left shoulder disposed on the left side of the micro PV cell at the bottom of the first trench; a second right shoulder, the second right shoulder disposed on the right side of the micro PV cell at the bottom of the third trench; and an integrated monolithic bypass diode, the integrated monolithic bypass diode comprising a buried PN junction disposed between the second layer and the first layer.

[0100] Example 2. The micro PV cell according to Example 1, wherein the multi-junction micro PV cell stack comprises 1 or 2 or 3 PN junctions.

[0101] Example 3. The micro PV cell according to Example 1 or 2, wherein no metal is disposed on the back surface of the first layer.

[0102] Example 4. The micro PV cell according to any one of Example 1, Example 2 or Example 3, the micro PV cell further comprising: a third layer, the third layer comprising a p-doped second semiconductor material and disposed on the second layer; a fourth layer, the fourth layer comprising an n-doped second semiconductor material and disposed on the third layer; a fifth layer, the fifth layer comprising a p-doped third semiconductor material and disposed on the fourth layer; and a sixth layer, the sixth layer comprising an n-doped third semiconductor material and disposed on the fifth layer.

[0103] Example 5a. The micro PV cell according to Example 4, wherein: the first layer comprises p-Ge; the second layer comprises n-Ge; the third layer comprises p-GaAs; the fourth layer comprises n-GaAs; the fifth layer comprises p-InGaP; and the sixth layer comprises n-InGaP.

[0104] Example 5b. The micro PV cell according to Example 4, wherein: the first layer comprises p-Ge; the second layer comprises n-GaAs on p-GaAs; the third layer comprises p-GaAs; the fourth layer comprises n-GaAs; the fifth layer comprises p-InGaP; and the sixth layer comprises n-InGaP.

[0105] Example 6. A photovoltaic (PV) micro PV cell, the photovoltaic (PV) micro PV cell comprising: a left side and a right side; a first layer, the first layer comprising a first semi-insulating semiconductor material; a second layer, the second layer comprising an n-doped first semiconductor material and disposed on the first layer; a third layer, the third layer comprising a p-doped first semiconductor material and disposed on the second layer; a fourth layer, the fourth layer comprising an n-doped first semiconductor material and disposed on the third layer; a fifth layer, the fifth layer comprising a p-doped second semiconductor material and disposed on the fourth layer; a sixth layer, the sixth layer comprising an n-doped second semiconductor material and disposed on the fifth layer; a seventh layer, the seventh layer comprising a p-doped third semiconductor material and disposed on the sixth layer; an eighth semiconductor layer, the eighth semiconductor layer comprising an n-doped third semiconductor material and disposed on the seventh semiconductor layer; a first trench, the first trench extending downward into the first layer and disposed on the left side of the micro PV cell; a second trench, the second trench extending downward into the first layer and disposed on the right side of the micro PV cell; a third trench, the third trench extending downward into the second layer and disposed adjacent to the first trench on the left side of the micro PV cell; a fourth trench, the fourth trench extending downward into the fourth layer and disposed adjacent to the second trench on the right side of the micro PV cell; a first left shoulder, the first left shoulder disposed on the left side of the micro PV cell at the bottom of the second trench; a second right shoulder, the second right shoulder disposed on the right side of the micro PV cell at the bottom of the fourth trench; an integrated monolithic bypass diode, the integrated monolithic bypass diode comprising a buried PN junction disposed between the fourth layer and the third layer.

[0106] Example 7. The micro PV cell of Example 6, wherein the first semiconductor material comprises GaAs; the second semiconductor material comprises GaAs; the third semiconductor material comprises InGaP.

[0107] Example 8. The micro PV cell according to Example 6 or 7, wherein the first layer comprises semi-insulating GaAs; the second layer comprises n-GaAs; the third layer comprises p-GaAs; the fourth layer comprises n-GaAs; the fifth layer comprises p-GaAs; the sixth layer comprises n-GaAs; the seventh layer comprises p-InGaP; and the eighth layer comprises n-InGaP.

[0108] Example 9. The micro PV cell according to any one of Example 6, Example 7 or Example 8, wherein the first layer comprises semi-insulating GaAs; the second layer comprises p-GaAs; the third layer comprises p-GaAs; the fourth layer comprises n-GaAs; the fifth layer comprises p-GaAs; the sixth layer comprises n-GaAs; the seventh layer comprises p-InGaP; and the eighth layer comprises n-InGaP.

[0109] Example 10. A photovoltaic (PV) device, the PV device comprising a string of at least three micro PV cells having the same layer structure connected in series, the string of at least three micro PV cells comprising: a first micro PV cell disposed on a common substrate; a second micro PV cell disposed on the common substrate and electrically connected in series to the first micro PV cell; a third micro PV cell disposed on the common substrate and electrically connected in series to the second micro PV cell; wherein each of the first micro PV cell, the second micro PV cell, and the third micro PV cell comprises: a left side and a right side; a first layer comprising a p-doped first semiconductor material; a second layer comprising an n-doped first semiconductor material and disposed on the first layer; a multi-junction micro PV cell stack disposed on a portion of the second layer; a first trench extending downward into the first layer and disposed on the left side of the micro PV cell; a second trench extending downward into the first layer and disposed on the right side of the micro PV cell; a third trench disposed adjacent to the second trench and extending downward into the second layer, wherein the third trench is disposed on the right side of the micro PV cell, adjacent to the left side of the second trench; a first left shoulder disposed on the left side of the micro PV cell at the bottom of the first trench; a second right shoulder disposed on the right side of the micro PV cell at the bottom of the third trench; an integrated monolithic bypass diode comprising a buried PN junction disposed between the second layer and the first layer; wherein the first micro PV cell comprises a first top surface; wherein the second micro PV cell comprises a second top surface; wherein the third micro PV cell comprises a third top surface; a first conductor electrically connecting the first layer to the first top surface of the first micro PV cell; a second conductor electrically connecting the second right shoulder of the first micro PV cell to the second top surface of the second micro PV cell; a third conductor electrically connecting the second right shoulder of the second micro PV cell to the third top surface of the third micro PV cell; wherein the common substrate is the first layer.

[0110] Example 11. The PV device according to Example 10, wherein the PV device is configured to be attached to a photovoltaic micro solar panel of an extraterrestrial satellite.

[0111] Example 12. The PV device according to Example 10 or 11, wherein the multi-junction micro PV cell stack of each micro PV cell comprises: a third layer comprising a p-doped second semiconductor material and disposed on the second layer; a fourth layer comprising an n-doped second semiconductor material and disposed on the third layer; a fifth layer comprising a p-doped third semiconductor material and disposed on the fourth layer; and a sixth layer comprising an n-doped third semiconductor material and disposed on the fifth layer.

[0112] Example 13. The PV device of Example 12, wherein the first layer comprises p-Ge; and the second layer of each micro PV cell comprises n-Ge.

[0113] Example 14. The PV device according to Example 12 or 13, wherein: the second semiconductor material comprises GaAs; and the third semiconductor material comprises GaAs.

[0114] Example 15. The PV device according to any one of Examples 12 and 14, wherein: the first layer comprises p-Ge; the second layer of each micro PV cell comprises n-Ge; the third layer of each micro PV cell comprises p-GaAs; the fourth layer of each micro PV cell comprises n-GaAs; the fifth layer of each micro PV cell comprises p-InGaP; and the sixth layer of each micro PV cell comprises n-InGaP.

[0115] Example 16. A photovoltaic (PV) device, the PV device comprising a string of at least three identical micro PV cells connected in series, the string of micro PV cells comprising: a first micro PV cell disposed on a common substrate; a second micro PV cell disposed on the common substrate and electrically connected in series to the first micro PV cell; a third micro PV cell disposed on the common substrate and electrically connected in series to the second micro PV cell; wherein each of the first micro PV cell, the second micro PV cell, and the third micro PV cell comprises: a left side and a right side; a first layer comprising a first semiconductor material; a second layer comprising the first semiconductor material and disposed on the first layer; a third layer comprising the first semiconductor material and disposed on the second layer; a fourth layer comprising the first semiconductor material and disposed on the third layer; and a fifth layer comprising a second semiconductor material and disposed on the fourth layer; a sixth layer comprising the second semiconductor material and disposed on the fifth layer; a seventh layer comprising a third semiconductor material and disposed on the sixth layer; an eighth layer comprising the third semiconductor material and disposed on the seventh layer; a first trench extending downward into the first layer and disposed on the left side of the micro PV cell; a second trench extending downward into the first layer and disposed on the right side of the micro PV cell; a third trench extending downward into the second layer and disposed adjacent to the first trench on the left side of the micro PV cell; a fourth trench extending downward into the fourth layer and disposed adjacent to the second trench on the right side of the micro PV cell; a first left shoulder disposed on the left side of the micro PV cell at the bottom of the second trench; a second right shoulder disposed on the right side of the micro PV cell at the bottom of the fourth trench; an integrated monolithic bypass diode comprising a buried PN junction disposed between the fourth layer and the third layer; wherein the first micro PV cell comprises a first top surface; wherein the second micro PV cell comprises a second top surface; wherein the third micro PV cell comprises a third top surface; and a first conductor electrically connecting the first layer to the first top surface of the first micro PV cell; a second conductor electrically connecting the second right shoulder of the first micro PV cell to the second top surface of the second micro PV cell; a third conductor electrically connecting the second right shoulder of the second micro PV cell to the third top surface of the third micro PV cell; a fourth conductor electrically connecting the second right shoulder of the first micro PV cell to the first left shoulder of the second micro PV cell; a fifth conductor electrically connecting the second right shoulder of the second micro PV cell to the first left shoulder of the third micro PV cell; wherein the integrated monolithic bypass diode of each micro PV cell comprises a PN junction disposed between the fourth layer and the third layer of each micro PV cell; and wherein the common substrate is the first layer.

[0116] Example 17. The PV device according to Example 16, wherein: the first layer comprises semi-insulating GaAs; the second layer of each micro-PV cell comprises n-GaAs; the third layer of each micro-PV cell comprises p-GaAs; the fourth layer of each micro-PV cell comprises n-GaAs; the fifth layer of each micro-PV cell comprises p-GaAs; the sixth layer of each micro-PV cell comprises n-GaAs; the seventh layer of each micro-PV cell comprises p-InGaP; and the eighth layer of each micro-PV cell comprises n-InGaP.

[0117] Example 18. A photovoltaic (PV) device, the photovoltaic (PV) device comprising an array of a plurality of micro-PV cells disposed on a common substrate and electrically connected in series; wherein each micro-PV cell comprises: a left side and a right side; a first layer, the first layer comprising a p-doped first semiconductor material; a second layer, the second layer comprising an n-doped first semiconductor material and disposed on the first layer; a multi-junction micro-PV cell stack, the multi-junction micro-PV cell stack disposed on a portion of the second layer; a first trench, the first trench extending downward into the first layer and disposed on the left side of each micro-PV cell; a second trench, the second trench extending downward into the first layer and disposed on the right side of each micro-PV cell; a third trench, the third trench disposed adjacent to the second trench and extending downward into the second layer, wherein the third trench is disposed on the right side of each micro-PV cell adjacent to the left side of the second trench; a first left shoulder, the first left shoulder disposed on the left side of each micro-PV cell at the bottom of the first trench; a second right shoulder, the second right shoulder disposed on the right side of each micro-PV cell at the bottom of the third trench; an integrated monolithic bypass diode, the integrated monolithic bypass diode comprising a PN junction disposed between the second layer and the first layer; wherein the common substrate is the first layer.

[0118] Example 19. The PV device according to Example 18, wherein the PV device comprises greater than or equal to forty-five micro-PV cells all connected in series, and the PV device has an output voltage greater than about 90V.

[0119] Example 20. The PV device according to Example 18 or Example 19, wherein the surface area of a single micro-PV cell in the PV device is less than or equal to about 1 cm 2 。

[0120] Example 21. The PV device according to any one of Example 18, Example 19 or Example 20, the PV device further comprising a pair of voltage tabs disposed at opposite corners of the PV device.

[0121] Example 22. The PV device according to any one of Examples 18, 19, 20, or 21, wherein the photocurrent generated by the array of multiple micro PV cells when irradiated flows through the PV device in a serial serpentine manner.

[0122] Example 23. The PV device according to any one of Examples 18, 19, 20, 21, or 22, wherein the PV device has an octagonal shape.

[0123] Example 24. The PV device according to any one of Examples 18, 19, 20, 21, 22, or 23, wherein the PV device has a surface area greater than or equal to about 45 cm 2 The surface area.

[0124] Example 25. The PV device according to any one of Examples 18, 19, 20, 21, 22, 23, or 24, wherein the common substrate comprises p-Ge.

[0125] Example 26. A photovoltaic (PV) device comprising an array of multiple micro PV cells disposed on a common substrate and electrically connected in series; wherein each micro PV cell comprises: a left side and a right side; a first layer comprising a first semiconductor material; a second layer comprising the first semiconductor material and disposed on the first layer; a third layer comprising the first semiconductor material and disposed on the second layer; a fourth layer comprising the first semiconductor material and disposed on the third layer; a fifth layer comprising a second semiconductor material and disposed on the fourth layer; a sixth layer comprising the second semiconductor material and disposed on the fifth layer; a seventh layer comprising a third semiconductor material and disposed on the sixth layer; an eighth layer comprising the third semiconductor material and disposed on the seventh layer; a first trench extending downward into the first layer and disposed on the left side of the micro PV cell; a second trench extending downward into the first layer and disposed on the right side of the micro PV cell; a third trench extending downward into the second layer and disposed adjacent to the first trench on the left side of the micro PV cell; a fourth trench extending downward into the fourth layer and disposed adjacent to the second trench on the right side of the micro PV cell; a first left shoulder disposed on the left side of the micro PV cell at the bottom of the second trench; a second right shoulder disposed on the right side of the micro PV cell at the bottom of the fourth trench; an integrated monolithic bypass diode comprising a buried PN junction disposed between the fourth layer and the third layer; wherein the common substrate is the first layer.

[0126] Example 27. The PV device of Example 26, wherein the common substrate comprises semi-insulating GaAs.

[0127] Example 28. A photovoltaic (PV) solar panel, the PV solar panel comprising an array of a plurality of PV devices, wherein each PV device comprises an array of a plurality of micro PV cells disposed on a common substrate and electrically connected in series; wherein each micro PV cell comprises: a right side and a left side; a first layer, the first layer comprising a p-doped first semiconductor material; a second layer, the second layer comprising an n-doped first semiconductor material and disposed on the first layer; a multi-junction micro PV cell stack disposed on a portion of the second layer; a first trench extending downward into the first layer and disposed on the left side of the micro PV cell; a second trench extending downward into the first layer and disposed on the right side of the micro PV cell; a third trench disposed adjacent to the second trench and extending downward into the second layer, wherein the third trench is disposed on the right side of the micro PV cell, adjacent to the left side of the second trench; a first left shoulder disposed on the left side of the micro PV cell at the bottom of the first trench; a second right shoulder disposed on the right side of the micro PV cell at the bottom of the third trench; an integrated monolithic bypass diode comprising a second layer disposed on the first layer; wherein the common substrate is the first layer.

[0128] Example 29. The PV solar panel according to Example 28, the PV solar panel further comprising: a positive polarity electrical bus comprising an interdigitated pattern of positive voltage conductors; and a negative polarity electrical bus comprising an interdigitated pattern of negative polarity voltage conductors; wherein the positive polarity electrical bus and the negative polarity electrical bus are electrically connected to the array of a plurality of PV devices.

[0129] Example 30. The PV solar panel according to Example 28 or 29, the PV solar panel comprising one or more rows of PV devices, wherein each row comprises a plurality of PV devices electrically connected in parallel.

[0130] Example 31. The PV solar panel according to Example 30, wherein each PV device comprises a negative voltage tab and a positive voltage tab disposed on opposite sides of the PV device; and wherein the first positive voltage tab of the first PV device disposed on the first row of the PV solar panel is directly opposite the second positive voltage tab of the adjacent second PV device disposed on the adjacent second row of the PV solar panel.

[0131] Example 32. The PV solar panel according to Example 31, wherein each PV device includes a negative voltage sheet and a positive voltage sheet disposed on opposite sides of the PV device; and wherein the first negative voltage sheet of the first PV device disposed on the first row of the PV solar panel is located directly opposite the second negative voltage sheet of the adjacent second PV device disposed on the adjacent second row of the PV solar panel.

[0132] Example 33. The PV solar panel according to any one of Examples 30, 31 or 32, the PV solar panel further comprising: a discrete blocking diode disposed between the PV solar device and the positive polarity electrical bus.

[0133] Example 34. A photovoltaic (PV) solar panel comprising an array of a plurality of PV devices, wherein each PV device includes an array of a plurality of micro PV cells disposed on a common substrate and electrically connected in series; wherein each micro PV cell includes: a left side and a right side; a first layer including a first semiconductor material; a second layer including the first semiconductor material and disposed on the first layer; a third layer including the first semiconductor material and disposed on the second layer; a fourth layer including the first semiconductor material and disposed on the third layer; a fifth layer including a second semiconductor material and disposed on the fourth layer; a sixth layer including the second semiconductor material and disposed on the fifth layer; a seventh layer including a third semiconductor material and disposed on the sixth layer; an eighth layer including the third semiconductor material and disposed on the seventh layer; a first trench extending downward into the first layer and disposed on the left side of the micro PV cell; a second trench extending downward into the first layer and disposed on the right side of the micro PV cell; a third trench extending downward into the second layer and disposed adjacent to the first trench on the left side of the micro PV cell; a fourth trench extending downward into the fourth layer and disposed adjacent to the second trench on the right side of the micro PV cell; a first left shoulder disposed on the left side of the micro PV cell at the bottom of the second trench; a second right shoulder disposed on the right side of the micro PV cell at the bottom of the fourth trench; an integrated monolithic bypass diode including the fourth layer disposed on the third layer; wherein the common substrate is the first layer.

[0134] Clause 1. A photovoltaic PV micro PV cell (100), the PV micro PV cell comprising:

[0135] A first layer (12) including a p-doped first semiconductor material;

[0136] A second layer (14), the second layer including an n-doped first semiconductor material and being disposed on the first layer (12);

[0137] A multi-junction PV micro-PV battery stack (16), the multi-junction PV micro-PV battery stack being disposed on a portion of the second layer (14);

[0138] A first trench (22), the first trench extending downward into the first layer (12) and being disposed on the left side of the PV micro-PV battery (100);

[0139] A second trench (22'), the second trench extending downward into the first layer (12) and being disposed on the right side of the PV micro-PV battery (100);

[0140] A third trench (52), the third trench being disposed adjacent to the second trench (22') and extending downward into the second layer (14), wherein the third trench (52) is disposed on the right side of the PV micro-PV battery (100) adjacent to the left side of the second trench (22');

[0141] A first left shoulder (26), the first left shoulder being disposed on the left side of the PV micro-PV battery (100) at the bottom of the first trench (22);

[0142] A second right shoulder (24), the second right shoulder being disposed on the right side of the PV micro-PV battery (100) at the bottom of the third trench (52); and

[0143] An integrated monolithic bypass diode, the integrated monolithic bypass diode including a buried PN junction (15) disposed between the second layer (14) and the first layer (12).

[0144] Clause 2. The PV micro-PV battery (100) according to Clause 1, wherein the multi-junction PV micro-PV battery stack (16) includes one or two or three PN junctions (15, 17, 19).

[0145] Clause 3. The PV micro-PV battery (100) according to Clause 1, wherein no metal is disposed on the back surface of the first layer (12).

[0146] Clause 4. The PV micro-PV battery (100) according to Clause 1, the PV micro-PV battery further comprising:

[0147] A third layer (42), the third layer including a p-doped second semiconductor material and being disposed on the second layer (14);

[0148] The fourth layer (44), which includes an n-doped second semiconductor material and is disposed on the third layer (42);

[0149] The fifth layer (46), which includes a p-doped third semiconductor material and is disposed on the fourth layer (44); and

[0150] The sixth layer (48), which includes an n-doped third semiconductor material and is disposed on the fifth layer (46).

[0151] Clause 5. The PV micro-PV cell (100) according to clause 4, wherein:

[0152] The first layer (12) includes p-Ge;

[0153] The second layer (14) includes n-Ge;

[0154] The third layer (42) includes p-GaAs;

[0155] The fourth layer (44) includes n-GaAs;

[0156] The fifth layer (46) includes p-InGaP; and

[0157] The sixth layer (48) includes n-InGaP.

[0158] Clause 6. The PV micro-PV cell (100) according to clause 4, wherein:

[0159] The first layer (12) includes p-Ge;

[0160] The second layer (14) includes n-GaAs on p-GaAs;

[0161] The third layer (42) includes p-GaAs;

[0162] The fourth layer (44) includes n-GaAs;

[0163] The fifth layer (46) includes p-InGaP; and

[0164] The sixth layer (48) includes n-InGaP.

[0165] Clause 7. A photovoltaic PV device (64), the PV device including an array of a plurality of PV micro-PV cells (100, 102, 104, etc.), the array of the plurality of PV micro-PV cells (100, 102, 104, etc.) being disposed on a common substrate (600) and electrically connected in series;

[0166] Wherein, each PV micro-PV cell (100, 102, 104, etc.) includes:

[0167] A first layer (12), the first layer including a p-doped first semiconductor material;

[0168] A second layer (14), the second layer including an n-doped first semiconductor material and disposed on the first layer (12);

[0169] A multi-junction PV micro-PV cell stack (16), the multi-junction PV micro-PV cell stack disposed on a portion of the second layer (14);

[0170] A first trench (22), the first trench extending downward into the first layer (12) and disposed on the left side of each PV micro-PV cell (100);

[0171] A second trench (22'), the second trench extending downward into the first layer (12) and disposed on the right side of each PV micro-PV cell (100, 102, 104, etc.);

[0172] A third trench, the third trench being disposed adjacent to the second trench (22') and extending downward into the second layer (14), wherein the third trench is disposed on the right side of each PV micro-PV cell (100, 102, 104, etc.) adjacent to the left side of the second trench (22');

[0173] A first left shoulder (26), the first left shoulder being disposed on the left side of each PV micro-PV cell (100, 102, 104, etc.) at the bottom of the first trench (22);

[0174] A second right shoulder (24), the second right shoulder being disposed on the right side of each PV micro-PV cell (100, 102, 104, etc.) at the bottom of the third trench; and

[0175] An integrated monolithic bypass diode, the integrated monolithic bypass diode including the second layer (14) disposed on the first layer (12);

[0176] Wherein, the common substrate (600) is the first layer (12).

[0177] Clause 8. The PV device (64) according to Clause 7, wherein the PV device (64) includes greater than or equal to forty-five PV micro-PV cells (100, 102, 104, etc.) all connected in series, and the PV device (64) has an output voltage greater than about 90V.

[0178] Clause 9. The PV device (64) according to Clause 7, wherein the surface area of a single PV micro-PV cell (100, 102, 104, etc.) in the PV device (64) is less than or equal to about 1 cm 2 .

[0179] Clause 10. The PV device (64) according to Clause 7, the PV device further comprising: a pair of voltage tabs (90, 90'), the pair of voltage tabs being disposed at opposite corner portions of the PV device (64).

[0180] Clause 11. The PV device (64) according to Clause 7, wherein the photocurrent generated by the array of PV micro-PV cells (100, 102, 104, etc.) in the PV device (64) when irradiated flows through the PV device (64) in a serial serpentine manner.

[0181] Clause 12. The PV device (64) according to Clause 7, wherein the PV device (64) has an octagonal shape.

[0182] Clause 13. The PV device (64) according to Clause 7, wherein the PV device (64) has a surface area greater than or equal to about 45 cm 2 of surface area.

[0183] Clause 14. The PV device (64) according to Clause 7, wherein the common substrate (600) comprises p-Ge.

[0184] Clause 15. A photovoltaic PV solar panel (58), the PV solar panel comprising an array of a plurality of PV devices (64), wherein each PV device (64) comprises an array of a plurality of PV micro-PV cells (100, 102, 104, etc.) disposed on a common substrate (600) and electrically connected in series;

[0185] wherein each PV micro-PV cell (100, 102, 104, etc.) comprises:

[0186] a first layer (12), the first layer comprising a first semiconductor material;

[0187] a second layer (14), the second layer being disposed on the first layer (12);

[0188] a multi-junction PV micro-PV cell stack (16), the multi-junction PV micro-PV cell stack being disposed on a portion of the second layer (14);

[0189] a first trench (22), the first trench extending downward into the first layer (12) and being disposed on the left side of the PV micro-PV cell (100);

[0190] A second groove (22'), which extends downward into the first layer (12) and is provided on the right side of the PV micro PV cell (100);

[0191] A third groove (52), which is provided adjacent to the second groove (22') and extends downward into the second layer (14), wherein the third groove (52) is provided on the right side of the PV micro PV cell (100) adjacent to the left side of the second groove (22');

[0192] A first left shoulder (26), which is provided on the left side of the PV micro PV cell (100) at the bottom of the first groove (22);

[0193] A second right shoulder (26'), which is provided on the right side of the PV micro PV cell (100) at the bottom of the second groove (22');

[0194] A third right shoulder (24), which is provided on the right side of the PV micro PV cell (100) at the bottom of the third groove (52); and

[0195] An integrated monolithic bypass diode (15), which includes the second layer (14) provided on the first layer (12);

[0196] Wherein, the common substrate (600) is the first layer (12).

[0197] Clause 16. The PV solar panel (58) according to clause 15, the PV solar panel further includes: an interdigitated pattern of a positive-polarity conductive bus (72) and a negative-polarity conductive bus (74), the positive-polarity conductive bus and the negative-polarity conductive bus are provided below the array of the plurality of PV devices (64, 64') and are electrically connected to the array of the plurality of PV devices (64, 64').

[0198] Clause 17. The PV solar panel (58) according to clause 15, the PV solar panel includes one row or more rows of PV devices (64, 64'), wherein each row includes a plurality of PV devices (64, 64') connected in parallel electrically.

[0199] Clause 18. The PV solar panel (58) according to clause 17

[0200] Wherein, each PV device (64) includes a negative voltage sheet (90) and a positive voltage sheet (90') provided at opposite corners of the PV device (64); and

[0201] Among them, the first positive voltage plate (90') of the first PV device (64) disposed on the first row (A) of the PV solar panel (58) is located directly opposite the second positive voltage plate (92') of the adjacent second PV device (66') disposed on the adjacent second row (B) of the PV solar panel.

[0202] Clause 19. The PV solar panel (58) according to Clause 18,

[0203] Among them, the first negative voltage plate (93) of the third PV device (66') disposed on the second row (B) of the PV solar panel (58) is located directly opposite the second negative voltage plate (94) of the adjacent fourth PV device (69') disposed on the adjacent third row (C) of the PV solar panel (58).

[0204] Clause 20. The PV solar panel (58) according to Clause 17, the PV solar panel further comprising: a discrete blocking diode (218), the discrete blocking diode (218) being disposed between adjacent pairs of PV solar devices (64, 64') connected in parallel along a single row (A).

[0205] In this disclosure, various aspects are referred to. However, it should be understood that this disclosure is not limited to the specifically described aspects. Instead, any combination of features and elements, whether or not related to different aspects, is expected to implement and practice the teachings provided herein. Additionally, when elements of aspects are described in the form of "at least one of A and B", it will be understood that aspects including only element A, only element B, and including both element A and B are all expected. Furthermore, although some aspects may achieve advantages over other possible solutions and / or over the prior art, whether a given aspect achieves a particular advantage does not limit this disclosure. Thus, the aspects, features, aspects, and advantages disclosed herein are merely illustrative and are not to be considered elements or limitations of the appended claims, unless expressly recited in the claims. Similarly, references to "the present invention" should not be construed as a generalization of any inventive subject matter disclosed herein and should not be considered an element or limitation of the appended claims, unless expressly recited in the claims.

[0206] Unless otherwise specified, the terms "first", "second", etc. are used herein only as labels and are not intended to impose sequential, positional, or hierarchical requirements on the items referred to by these terms. Additionally, references to, for example, a "second" item do not require or preclude the existence of, for example, a "first" or lower-numbered item or a "third" or higher-numbered item.

[0207] For ease of description, spatial relative terms such as "under", "below", "lower", "above", "upper", etc. may be used herein to describe the relationship of one component and / or feature to another component and / or feature or other components and / or features, as shown in the figures. It should be understood that spatial relative terms are intended to cover different orientations of the device in use or operation, in addition to the orientation depicted in the figures.

[0208] The term "comprising" in this document is intended to be optionally replaced by the terms "consisting essentially of" and "consisting of" respectively in each case. To the extent that the terms "comprising", "having", "including" and their variants are used in this document, such terms are intended to be included in a manner similar to the term "comprising" as an open transitional word without excluding any additional or other elements.

Claims

1. A photovoltaic PV micro-PV cell (100), the PV micro-PV cell comprising: A first layer (12), the first layer comprising a p-doped first semiconductor material; A second layer (14), the second layer comprising an n-doped first semiconductor material and disposed on the first layer (12); A multi-junction PV micro-PV cell stack (16), the multi-junction PV micro-PV cell stack disposed on a portion of the second layer (14); A first trench (22), the first trench extending downward into the first layer (12) and disposed on the left side of the PV micro-PV cell (100); A second trench (22'), the second trench extending downward into the first layer (12) and disposed on the right side of the PV micro-PV cell (100); A third trench (52), the third trench disposed adjacent to the second trench (22') and extending downward into the second layer (14), wherein the third trench (52) is disposed on the right side of the PV micro-PV cell (100) adjacent to the left side of the second trench (22'); A first left shoulder (26), the first left shoulder disposed on the left side of the PV micro-PV cell (100) at the bottom of the first trench (22); A second right shoulder (24), the second right shoulder disposed on the right side of the PV micro-PV cell (100) at the bottom of the third trench (52); and An integrated monolithic bypass diode, the integrated monolithic bypass diode comprising a buried PN junction (15) disposed between the second layer (14) and the first layer (12).

2. The PV micro PV cell (100) according to claim 1, wherein, The multi-junction PV micro-PV cell stack (16) comprises one or two or three PN junctions (15, 17, 19).

3. The PV micro PV cell (100) according to claim 1, wherein, No metal is disposed on the back surface of the first layer (12).

4. The PV micro-PV cell (100) according to claim 1, the PV micro-PV cell further comprising: A third layer (42), the third layer comprising a p-doped second semiconductor material and disposed on the second layer (14); A fourth layer (44), the fourth layer comprising an n-doped second semiconductor material and disposed on the third layer (42); A fifth layer (46), the fifth layer comprising a p-doped third semiconductor material and disposed on the fourth layer (44); And A sixth layer (48), the sixth layer comprising an n-doped third semiconductor material and disposed on the fifth layer (46).

5. The PV micro-PV cell (100) according to claim 4, wherein: The first layer (12) comprises p-Ge; The second layer (14) comprises n-Ge; The third layer (42) comprises p-GaAs; The fourth layer (44) comprises n-GaAs; The fifth layer (46) comprises p-InGaP; and The sixth layer (48) comprises n-InGaP.

6. The PV micro-PV cell (100) according to claim 4, wherein: The first layer (12) comprises p-Ge; The second layer (14) includes n-GaAs on p-GaAs; The third layer (42) includes p-GaAs; The fourth layer (44) includes n-GaAs; The fifth layer (46) includes p-InGaP; and The sixth layer (48) includes n-InGaP.

7. A photovoltaic PV device (64), the PV device including an array of a plurality of PV micro-PV cells (100, 102, 104), the array of the plurality of PV micro-PV cells (100, 102, 104) being disposed on a common substrate (600) and electrically connected in series; Among them, Each PV micro-PV cell (100, 102, 104) includes: A first layer (12), the first layer including a p-doped first semiconductor material; A second layer (14), the second layer including an n-doped first semiconductor material and being disposed on the first layer (12); A multi-junction PV micro-PV cell stack (16), the multi-junction PV micro-PV cell stack being disposed on a part of the second layer (14); A first trench (22), the first trench extending downward into the first layer (12) and being disposed on the left side of each PV micro-PV cell (100); A second trench (22’), the second trench extending downward into the first layer (12) and being disposed on the right side of each PV micro-PV cell (100, 102, 104, etc.); A third trench, the third trench being disposed adjacent to the second trench (22’) and extending downward into the second layer (14), wherein the third trench is disposed on the right side of each PV micro-PV cell (100, 102, 104) adjacent to the left side of the second trench (22’); A first left shoulder (26), the first left shoulder being disposed on the left side of each PV micro-PV cell (100, 102, 104, etc.) at the bottom of the first trench (22); A second right shoulder (24), the second right shoulder being disposed on the right side of each PV micro-PV cell (100, 102, 104, etc.) at the bottom of the third trench; and An integrated monolithic bypass diode, the integrated monolithic bypass diode including the second layer (14) disposed on the first layer (12); Wherein, the common substrate (600) is the first layer (12).

8. The PV device (64) according to claim 7, wherein, The PV device (64) includes greater than or equal to forty-five PV micro-PV cells (100, 102, 104) all connected in series, and the PV device (64) has an output voltage greater than about 90V.

9. The PV device (64) according to claim 7, wherein, The surface area of an individual PV micro PV cell (100, 102, 104) in the PV device (64) is less than or equal to about 1 cm 2 .

10. A photovoltaic PV solar panel (58), the PV solar panel comprising an array of a plurality of PV devices (64), wherein, Each PV device (64) includes an array of a plurality of PV micro-PV cells (100, 102, 104) disposed on a common substrate (600) and electrically connected in series; Wherein, each PV micro-PV cell (100, 102, 104) includes: A first layer (12), the first layer including a first semiconductor material; A second layer (14), the second layer being disposed on the first layer (12); Multi-junction PV micro-PV battery stack (16), the multi-junction PV micro-PV battery stack being disposed on a portion of the second layer (14); First trench (22), the first trench extending downward into the first layer (12) and being disposed on the left side of the PV micro-PV cell (100); Second trench (22'), the second trench extending downward into the first layer (12) and being disposed on the right side of the PV micro-PV cell (100); Third trench (52), the third trench being disposed adjacent to the second trench (22') and extending downward into the second layer (14), wherein the third trench (52) is disposed on the right side of the PV micro-PV cell (100) adjacent to the left side of the second trench (22'); Left first shoulder (26), the left first shoulder being disposed on the left side of the PV micro-PV cell (100) at the bottom of the first trench (22); Right second shoulder (26'), the right second shoulder being disposed on the right side of the PV micro-PV cell (100) at the bottom of the second trench (22'); Right third shoulder (24), the right third shoulder being disposed on the right side of the PV micro-PV cell (100) at the bottom of the third trench (52); and Integrated monolithic bypass diode (15), the integrated monolithic bypass diode including the second layer (14) disposed on the first layer (12); wherein the common substrate (600) is the first layer (12).

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