Display substrate and preparation method thereof

Abstract

The invention provides a display substrate and a preparation method thereof, belongs to the technical field of display, and can solve the problems of poor dark spots and the like caused by short circuit between an anode and a cathode due to the fact that an anode film layer at a T position of a tip structure is easy to fall off or adsorb foreign matters and the like, and a light-emitting layer is easy to pierce. The display substrate comprises a substrate body, an interlayer dielectric layer and a pixel unit, wherein the interlayer dielectric layer and the pixel unit are arranged on the substrate body. The pixel unit comprises a plurality of concave microstructures formed on the interlayer dielectric layer and a light-emitting device located on the side, away from the substrate body, of the interlayer dielectric layer. Wherein for each pixel unit, a first area is defined by the multiple concave microstructures which are arranged adjacently, and the orthographic projection of the first electrode of the light-emitting device and the orthographic projection of the first area on the substrate do not overlap.

Description

Technical Field

[0001] The present disclosure belongs to the field of display technology, and particularly relates to a display substrate and a preparation method thereof. Background Art

[0002] As AMOLED (Active-matrix organic light emitting diode) display products gradually develop in the direction of high resolution and high brightness, higher light extraction efficiency is required. However, since the light emitted by the light-emitting components in OLED display products needs to pass through many film layers to enter the external environment, there are differences in refractive index between these film layers, which causes some light to be reflected in these film layers and cause light loss. In order to improve the luminous brightness of OLED products, the current mainstream technology is to introduce MLA (Microlens Array) technology in the substrate preparation process, and improve the light extraction effect by preparing the reflective surface into a concave mirror. However, how to form a regular concave shape faces many technical challenges. A common technical means is to etch the interlayer dielectric layer to form many regular and densely packed pits, and then deposit the anode after patterning to also have a concave shape. The subsequent light-emitting layer and cathode, etc., are all concave, so they will have a good divergence effect on the light emitted by the light-emitting layer, thereby significantly improving the light extraction effect, and then significantly improving the display quality of the display product. Summary of the invention

[0003] The present disclosure aims to solve at least one of the technical problems existing in the prior art, and to provide a display substrate and a preparation method thereof that can significantly improve the light extraction effect while avoiding problems such as dark spots.

[0004] In a first aspect, the present disclosure provides a display substrate comprising a base substrate, an interlayer dielectric layer and a pixel unit arranged on the base substrate, wherein the pixel unit comprises a plurality of concave microstructures formed on the interlayer dielectric layer, and a light-emitting device located on a side of the interlayer dielectric layer away from the base substrate; wherein:

[0005] For at least one of the pixel units, the plurality of adjacently arranged concave microstructures define a first region, and the first electrode of the light-emitting device has no overlap with the orthographic projection of the first region on the substrate.

[0006] Preferably, each of the concave microstructures and the two concave microstructures closest thereto define the first region.

[0007] Preferably, the width of the first region between adjacent concave microstructures is greater than or equal to 1 micrometer.

[0008] Preferably, the pixel unit further comprises a pixel driving circuit electrically connected to the first electrode of the light emitting device, the pixel driving circuit comprises a thin film transistor, and the thin film transistor is a top-gate thin film transistor.

[0009] Preferably, the pixel unit further includes a shading layer, which is arranged on a side of the active layer of the thin film transistor close to the base substrate, and the orthographic projection of the shading layer on the base substrate covers the orthographic projection of the active layer of the thin film transistor on the base substrate.

[0010] Preferably, the thin film transistor in the pixel unit includes a driving transistor, and a source of the driving transistor is electrically connected to the first electrode of the light emitting device and the light shielding layer.

[0011] Preferably, the display substrate further comprises a color resist layer disposed on a side of the interlayer dielectric layer close to the base substrate, and the orthographic projection of the color resist layer on the base substrate at least partially overlaps with the orthographic projection of the concave microstructure on the base substrate.

[0012] In a second aspect, the present disclosure further provides a method for preparing a display substrate, comprising:

[0013] Providing a substrate;

[0014] A pixel driving circuit in each pixel unit is formed on the substrate; the pixel driving circuit includes a thin film transistor, and the thin film transistor is a top-gate thin film transistor;

[0015] Forming various color resist layers on a side of the layer where the pixel driving circuit is located away from the base substrate, wherein the color resist layers have no overlap with the orthographic projection of the pixel driving circuit on the base substrate;

[0016] An interlayer dielectric layer and a pixel unit are formed on a side of the color resist layer away from the base substrate; wherein forming the pixel unit comprises:

[0017] Patterning the interlayer dielectric layer portion to form a concave microstructure, wherein a plurality of adjacently arranged concave microstructures define a first region;

[0018] A first electrode of the light-emitting device is formed on a side of the interlayer dielectric layer away from the base substrate, and the first electrode in the pixel unit has no overlap with the orthographic projection of the first region on the base substrate.

[0019] Preferably, before the step of forming the thin film transistor, a step of forming a light-shielding layer is further included; the light-shielding layer is disposed on a side of the active layer of the thin film transistor close to the substrate, and a positive projection of the light-shielding layer on the substrate covers a positive projection of the active layer of the thin film transistor on the substrate.

[0020] Preferably, each of the concave microstructures and the two nearest concave microstructures thereto define the first region. Preferably, a width of the first region between the adjacent concave microstructures is greater than or equal to 1 micrometer.

[0021] In a third aspect, the present disclosure further provides a display device, which includes the above-mentioned display substrate. Description of the Drawings

[0022] Figure 1 is a top view of an existing microlens array;

[0023] Figure 2 is a schematic structural diagram of a microlens array substrate in the prior art;

[0024] Figure 3 is a schematic structural diagram of a display substrate provided by an embodiment of the present disclosure;

[0025] Figure 4 is Figure 3 a top view of a first electrode of a display substrate disclosed;

[0026] Figure 5 is a schematic structural diagram of a pixel driving circuit of a display substrate provided by an embodiment of the present disclosure;

[0027] Figure 6 is a schematic structural diagram of another display substrate provided by an embodiment of the present disclosure;

[0028] Figure 7a is a schematic diagram of an intermediate product of step S1 of a method for manufacturing a display substrate provided by an embodiment of the present disclosure;

[0029] Figure 7b is a schematic diagram of an intermediate product of step S2 of a method for manufacturing a display substrate provided by an embodiment of the present disclosure;

[0030] Figure 7c is a schematic diagram of an intermediate product of step S3 of a method for manufacturing a display substrate provided by an embodiment of the present disclosure;

[0031] Figure 7d is a schematic diagram of an intermediate product of step S4 of a method for manufacturing a display substrate provided by an embodiment of the present disclosure;

[0032] Figure 7e Schematic diagram of an intermediate product in step S5 of a method for manufacturing a display substrate provided by an embodiment of the present disclosure;

[0033] Figure 7f Schematic diagram of an intermediate product in step S7 of a method for manufacturing a display substrate provided by an embodiment of the present disclosure;

[0034] Figure 7g Schematic diagram of an intermediate product in step S7 of a method for manufacturing a display substrate provided by an embodiment of the present disclosure. Detailed implementation manners

[0035] To make the objectives, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only some, but not all, of the embodiments of the present disclosure. The components of the embodiments of the present disclosure usually described and illustrated in the drawings here can be arranged and designed in various different configurations. Therefore, the detailed description of the embodiments of the present disclosure provided in the drawings below is not intended to limit the scope of the claimed present disclosure, but merely represents selected embodiments of the present disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of the present disclosure without creative efforts fall within the scope of protection of the present disclosure.

[0036] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should have the ordinary meanings understood by those of ordinary skill in the field to which the present disclosure belongs. The "first", "second" and similar terms used in the present disclosure do not denote any order, quantity or importance, but are only used to distinguish different components. Similarly, the terms such as "a", "an" or "the" do not denote a quantity limitation, but mean that there is at least one. The terms such as "include" or "comprise" mean that the elements or objects appearing before the term cover the elements or objects listed after the term and their equivalents, without excluding other elements or objects. The terms such as "connect" or "couple" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The terms such as "upper", "lower", "left" and "right" are only used to represent relative positional relationships, and when the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0037] As used in the present disclosure, "a plurality or several" means two or more. "And / or" describes the association relationship of associated objects and indicates that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. The character " / " generally represents an "or" relationship between the associated objects before and after.

[0038] As AMOLED display products gradually develop in the direction of high resolution and high brightness, a higher light extraction rate is required. However, since the light emitted by the light-emitting components in OLED display products needs to pass through many film layers before entering the external environment, there are differences in the refractive index between these film layers, causing part of the light to be reflected in these film layers and causing light loss. In the prior art, in order to improve the luminous brightness of OLED products, MLA (Microlens Array) technology is mainly used in the substrate preparation process, and the light extraction effect is improved by preparing the reflective surface into a concave mirror. Figure 1 and Figure 2 As shown, the commonly used concave mirrors are regularly distributed on hemispherical surfaces, and the hemispheres are closely packed with each other so that they present a regular hexagonal distribution when viewed from above. A relatively high tip structure T is formed at the intersection of the three hemispheres. Subsequently, the anode film layer at the tip structure T is easy to fall off or absorb foreign matter, etc., which can easily lead to piercing the light-emitting layer and causing a short circuit between the anode and the cathode, thereby causing problems such as dark spots.

[0039] In the first aspect, the embodiment of the present disclosure provides a display substrate, which includes a base substrate 1, an interlayer dielectric layer 17 disposed on the base substrate 1, and a pixel unit, wherein the pixel unit includes a plurality of concave microstructures 18 formed on the interlayer dielectric layer 17, and a light-emitting device located on the side of the interlayer dielectric layer 17 away from the base substrate 1. For each pixel unit, when the width of the first region 19 between adjacent concave microstructures 18 is less than 1 micron, the adjacent multiple concave microstructures 18 define a first region 19, wherein the first region 19 includes a tip structure T formed by extrusion of the multiple adjacent concave microstructures 18. The first electrode 20 of the light-emitting device and the tip structure T of the first region 19 have no overlap in their orthographic projection on the base substrate 1. The above-mentioned patterning method can well avoid the problem that the first electrode 20 at the first region 19 is easy to fall off or adsorb foreign matter, which causes the piercing of the light-emitting layer 21, resulting in a short circuit between the first electrode 20 and the second electrode 22, thereby causing problems such as dark spots. In addition, the interlayer dielectric layer 17 is etched to form many regularly and closely packed concave microstructures 18. Since the concave microstructure 18 has a concave shape, the first electrode 20 after deposition and patterning also has a concave shape. The light-emitting layer 21 and the second electrode 22 formed in sequence subsequently have a concave shape. Therefore, they have a good divergent effect on the light emitted by the light-emitting layer, thereby significantly improving the light extraction effect, and further significantly improving the display quality of the display product.

[0040] It should be noted that the interlayer dielectric layer 17 is a planarization layer, and the concave microstructure 18 is obtained by etching the side of the planarization layer away from the substrate base plate 1 .

[0041] To make the embodiments of the present disclosure clearer, the following will be described with specific examples.

[0042] The embodiments of the present disclosure provide a display substrate. As Figure 3 shown, it includes a substrate 1, an interlayer dielectric layer 17 disposed on the substrate 1, a color group layer 16 disposed on one side of the interlayer dielectric layer 17 close to the substrate 1, and pixel units. Among them, the pixel unit includes a light-shielding layer 2, a pixel driving circuit, a concave microstructure 18, and a light-emitting device. Among them, the light-emitting device includes a first electrode 20, a light-emitting layer 21, and a second electrode 22 arranged in sequence. For each pixel unit, a plurality of adjacent concave microstructures 18 define a first region 19, and the positive projection of the first electrode 20 of the light-emitting device on the substrate 1 does not overlap with the first region 19. Adopting the above composition method can well avoid problems such as the first electrode 20 at the first region 19 being easily detached or adsorbing foreign objects, resulting in piercing the light-emitting layer 21, causing a short circuit between the first electrode 20 and the second electrode 22, and thus causing problems such as dark spot defects. The interlayer dielectric layer 17 is etched to form many regularly arranged and densely packed concave microstructures 18. Since the concave microstructures 18 have a concave shape, the first electrode 20 after deposition and patterning also has a concave shape, and the subsequent light-emitting layer 21 and second electrode 22 formed in sequence all have a concave shape. Therefore, it has a good diverging effect on the light emitted by the light-emitting layer, thereby significantly improving the light extraction effect and further significantly improving the display quality of the display product.

[0043] It should be noted here that the pixel driving circuit of the display substrate in the embodiments of the present disclosure adopts a Figure 5 pixel driving circuit with a 3T1C structure as shown. It includes: a first transistor T1, a second transistor T2, a third transistor T3, a capacitor Cst, and a light-emitting device OLED, and the light-emitting device OLED can be an organic light-emitting diode. Among them, the source electrode of the first transistor T1 is connected to the gate line DATA, the gate electrode is connected to the first gate line G1, and the data line is connected to the gate electrode of the third transistor T3; the source electrode of the second transistor T2 is connected to the source electrode of the third transistor T3, the gate electrode is connected to the second gate line G2, and the drain electrode is connected to the detection interface Sense; the source electrode of the third transistor T3 is connected to the light-emitting device OLED, the gate electrode is connected to the first transistor T1, and the drain electrode is connected to the first power supply voltage VDD; the first plate of the capacitor Cst is connected to the drain electrode of the first transistor T1, and the second plate is connected to the source electrode of the second transistor T2; the first pole of the light-emitting device OLED is connected to the ground electrode VSS, and the second pole is connected to the source electrode of the third transistor T3. The third transistor T3 is a driving transistor. The embodiments of the present application adopt a pixel driving circuit with a 3T1C structure to effectively compensate the threshold voltage of the driving transistor in each pixel, use fewer components, have a simple and stable structure, and save costs.

[0044] In some examples, such as Figure 6 shown, the width of the gap between adjacent concave microstructures 18 is greater than or equal to 1 micron. Since there is no overlap between the concave microstructures 18, a plurality of flat structures F are formed at the gaps between the plurality of adjacent concave microstructures 18, thereby preventing the adjacent concave microstructures 18 from squeezing to form a tip structure T in the first region 19, fundamentally eliminating the problems such as the first electrode 20 at the first region 19 being easily detached or adsorbing foreign objects, piercing the light-emitting layer 21, causing a short circuit between the first electrode 20 and the second electrode 22, and thus causing dark spot defects.

[0045] In some examples, the pixel driving circuit includes a thin-film transistor, and the thin-film transistor is a top-gate thin-film transistor. The top-gate thin-film transistor has the characteristic of a short channel, so its on-state current can be effectively increased, thus significantly improving the display effect and effectively reducing the power consumption. Moreover, the overlapping area between the gate 6 and the source-drain of the top-gate thin-film transistor is small, so the parasitic capacitance generated is small, and the possibility of dark spot defects also decreases.

[0046] In some examples, the light-shielding layer 2 is disposed on the side of the active layer 4 of the thin-film transistor close to the substrate 1, and the orthographic projection of the light-shielding layer 2 on the substrate 1 covers the orthographic projection of the active layer of the thin-film transistor on the substrate 1. In addition, the part of the orthographic projection of the active layer 4 on the substrate 1 that does not overlap with the orthographic projection of the gate insulating layer 5 on the substrate 1 is conductorized to form a conductor layer 7. By using the lateral diffusion phenomenon during the conductorization of the active layer 4, the contact yield between the source electrode 10, the drain electrode 9 and the conductor layer 7 is increased, that is, the contact yield with the edge of the active layer 4 is increased, thereby greatly improving the conduction characteristics of the thin-film transistor device.

[0047] In some examples, the material of the active layer 4 of the thin-film transistor includes indium gallium zinc oxide (IGZO), which has the advantages of high carrier mobility, large-area preparation, good uniformity, stable device performance, etc., and is compatible with the current amorphous silicon thin-film transistor process, and is an ideal material in the display field.

[0048] In some examples, the color group layer 16 may include color filters of multiple colors, including: red color filter, green color filter and blue color filter. The color filters can generate the three primary colors of red (R), green (G) and blue (B) by means of light filtering, and then mix the three primary colors in different proportions to generate various colors, so that the display substrate presents colors.

[0049] In some examples, the source electrode 10 of the driving transistor is electrically connected to the first electrode 20 of the light-emitting device and the light-shielding layer 2. In the embodiments of the present disclosure, the driving transistor can be used to regulate the current and further control the light emission.

[0050] In some examples, the materials of the first electrode 20 and the second electrode 22 include carbon nanotubes. Carbon nanotubes have a one-dimensional hollow tubular structure. The tube wall is surrounded by single-layer or multi-layer graphene sheets. The tube diameter is at the nanometer scale, and the tube length is at the micrometer scale, with a huge aspect ratio. Their properties will change due to different curling methods of the graphene sheets, showing metallic or semiconductor properties and having good electrical conductivity. Secondly, carbon nanotubes have good thermal conductivity, with an axial thermal conductivity of 2000 - 3000 W / mK, about 10 times that of copper and 3 times that of diamond. Thirdly, carbon nanotubes have an extremely large specific surface area and strong adsorption performance; at the same time, they have good properties such as electromagnetic wave absorption.

[0051] In a second aspect, the embodiments of the present disclosure further provide a method for manufacturing a display substrate, as Figure 6 shown, including:

[0052] S1, as Figure 7a shown, provide a substrate 1.

[0053] S2, as Figure 7b shown, form a patterned light-shielding layer 2 on the substrate 1.

[0054] In some examples, step S2 may specifically include:

[0055] S21, form a light-shielding layer 2 on the substrate 1.

[0056] S22, pattern the light-shielding layer 2 through a lithography process to form a patterned light-shielding layer 2.

[0057] Optionally, step S21 may specifically include:

[0058] Form a light-shielding layer 2 on the substrate 1 by physical vapor deposition (PVD) or chemical vapor deposition (CVD) or sputtering process, and process the light-shielding layer 2 using a chemical mechanical polishing process, leaving only the required part of the light-shielding layer 2 to form a patterned light-shielding layer 2.

[0059] S3, as Figure 7c shown, form a buffer layer 3 covering the light-shielding layer 2 on the side of the light-shielding layer 2 facing away from the substrate 1.

[0060] Optionally, step S3 may specifically include:

[0061] Form a buffer layer 3 covering the light-shielding layer 2 on the side of the light-shielding layer 2 facing away from the substrate 1 by physical vapor deposition (PVD) or chemical vapor deposition (CVD) or sputtering process on the substrate 1.

[0062] S4, as Figure 7dAs shown, a thin film transistor including a driving transistor and an interlayer insulating layer 8 are formed on a side of the buffer layer 3 facing away from the substrate 1.

[0063] In some examples, step S4 may specifically include:

[0064] S41. Form a patterned active layer 4 on a side of the buffer layer 3 facing away from the substrate 1.

[0065] In some examples, step S41 may specifically include:

[0066] S411. Form an active layer 4 on a side of the buffer layer 3 facing away from the substrate 1.

[0067] S412. Pattern the active layer 4 through a lithography process, and the positive projection of the light-shielding layer 2 on the substrate 1 covers the positive projection of the active layer 4 on the substrate 1.

[0068] Optionally, step S411 may specifically include:

[0069] Form an active layer 4 on a side of the buffer layer 3 facing away from the substrate 1 by physical vapor deposition (PVD) process or chemical vapor deposition (CVD) process or sputtering process, and process the active layer 4 by chemical mechanical polishing process, leaving only the required part of the active layer 4 to form a patterned active layer 4.

[0070] S42. Form a gate insulating layer 5 on a side of the active layer 4 facing away from the substrate 1.

[0071] Optionally, step S42 may specifically include:

[0072] Form a gate insulating layer 5 on a side of the active layer 4 facing away from the substrate 1 by physical vapor deposition (PVD) process or chemical vapor deposition (CVD) process or sputtering process.

[0073] S43. Form a gate 6 on a side of the gate insulating layer 5 facing away from the substrate 1.

[0074] Optionally, step S42 may specifically include:

[0075] Form a gate 6 on a side of the gate insulating layer 5 facing away from the substrate 1 by physical vapor deposition (PVD) process or chemical vapor deposition (CVD) process or sputtering process.

[0076] S44. Conductify the part where the positive projection of the active layer 4 on the substrate 1 does not overlap with the positive projection of the gate insulating layer 5 on the substrate 1 to form a conductor layer 7.

[0077] Optionally, step S44 may specifically include:

[0078] A process of forming a conductor layer 7 by subjecting the regions on the active layer 4 in contact with the source electrode 10 and the drain electrode 9 to plasma treatment with gases such as Ar (argon) and He (helium) to achieve conductorization of the active layer 4.

[0079] By utilizing the lateral diffusion phenomenon during the conductorization of the active layer 4, the contact yield between the source electrode 10, the drain electrode 9 and the edge of the active layer 4 is increased, thus greatly improving the conduction characteristics of the thin-film transistor device.

[0080] S45. Form an interlayer insulating layer 8 on the side of the conductor layer 7 and the gate electrode 6 facing away from the substrate 1, perform a patterning process on the interlayer insulating layer 8 to form vias, and form a drain electrode 9 and a source electrode 10 electrically connected to the conductor layer 7.

[0081] In some examples, step S45 may specifically include:

[0082] S451. Form an interlayer insulating layer 8 on the side of the conductor layer 7 and the gate electrode 6 facing away from the substrate 1.

[0083] S452. Perform a patterning process on the interlayer insulating layer 8 through a lithography process to form a first via 11 and a second via 12 electrically connected to the conductor layer 7, and a third via 13 connected to the light-shielding layer 2.

[0084] S453. Form a drain electrode 9 and a source electrode 10 on the side of the interlayer insulating layer 8 facing away from the substrate 1. The drain electrode 9 is electrically connected to the conductor layer 7 through the first via 11, the source electrode 10 is electrically connected to the conductor layer 7 through the second via 12, and the source electrode 10 is also electrically connected to the light-shielding layer 2 through the third via 13.

[0085] Optionally, step S451 may specifically include:

[0086] Form an interlayer insulating layer 8 on the side of the conductor layer 7 and the gate electrode 6 facing away from the substrate 1 by physical vapor deposition (PVD) process or chemical vapor deposition (CVD) process or sputtering process.

[0087] Optionally, step S452 may specifically include:

[0088] Perform a patterning process on the side of the interlayer insulating layer 8 facing away from the substrate 1 through an etching process to form a first via 11 and a second via 12 electrically connected to the conductor layer 7, and a third via 13 connected to the light-shielding layer 2.

[0089] S5. As Figure 7e shown, form a passivation layer 15 on the side of the interlayer insulating layer 8 facing away from the substrate 1.

[0090] Optionally, step S5 may specifically include:

[0091] A passivation layer 15 is formed on the side of the interlayer insulating layer 8 facing away from the substrate 1 by a physical vapor deposition process (PVD), a chemical vapor deposition process (CVD), or a sputtering process.

[0092] S6. As Figure 7f shown, a color group layer 16 is formed on the side of the passivation layer 15 facing away from the substrate 1, and the orthographic projection of the color group layer 16 on the substrate 1 does not overlap with the orthographic projection of the light-shielding layer 2 on the substrate 1.

[0093] In some examples, step S6 may specifically include:

[0094] S61. A red filter, a green filter, and a blue filter are formed on the side of the passivation layer 15 facing away from the substrate 1.

[0095] Optionally, step S6 may specifically include:

[0096] A color group layer 16 is formed on the side of the passivation layer 15 facing away from the substrate 1 by a physical vapor deposition process (PVD), a chemical vapor deposition process (CVD), or a sputtering process.

[0097] S7. As Figure 7g shown, an interlayer dielectric layer 17 is formed on the side of the passivation layer 15 and the color group layer 16 facing away from the substrate 1, and the interlayer dielectric layer 17 on the side facing away from the color group layer 16 is patterned to form a concave microstructure 18, and the orthographic projection of the concave microstructure 18 on the substrate 1 does not overlap with the orthographic projection of the light-shielding layer 2 on the substrate 1.

[0098] In some examples, step S7 may specifically include:

[0099] S71. An interlayer dielectric layer 17 is formed on the side of the passivation layer 15 and the color group layer 16 facing away from the substrate 1.

[0100] S72. The interlayer dielectric layer 17 and the passivation layer 15 are patterned by a lithography process to form a fourth via 14 connected to the source electrode 10. The interlayer dielectric layer 17 on the side facing away from the color group layer 16 is patterned to form a concave microstructure 18.

[0101] Optionally, step S71 may specifically include:

[0102] An interlayer dielectric layer 17 is formed on the side of the passivation layer 15 and the color group layer 16 facing away from the substrate 1 by a physical vapor deposition process (PVD), a chemical vapor deposition process (CVD), or a sputtering process.

[0103] Since the interlayer dielectric layer is etched to form many regularly densely arranged concave microstructures 18 with a concave shape, the first electrode 20 after deposition and patterning also has a concave shape, and the subsequently formed light-emitting layer 21, second electrode 22, etc. all have a concave shape. Therefore, it has a good light-diverging effect on the light emitted by the light-emitting layer 21, thus significantly improving the light extraction effect and further significantly improving the display quality of the display product.

[0104] Optionally, step S72 may specifically include:

[0105] The interlayer dielectric layer 17 is patterned by an etching process to form a fourth via 14 connected to the source electrode 10. The passivation layer 15 is patterned by an etching process to form concave microstructures 18.

[0106] S8, as Figure 3 shown, a light-emitting device is formed on the side of the interlayer dielectric layer 17 facing away from the substrate 1.

[0107] In some examples, step S8 may specifically include:

[0108] S81. A first electrode 20 is formed on the side of the interlayer dielectric layer 17 facing away from the substrate 1. A plurality of adjacent concave microstructures 18 define a first region 19, and the first electrode 20 and the positive projection of the first region 19 on the substrate 1 do not overlap.

[0109] In some examples, step S81 may specifically include:

[0110] S811. A first electrode 20 is formed on the side of the interlayer dielectric layer 17 facing away from the substrate 1.

[0111] S812. Through a patterning process, the first electrode 20 located on the first region 19 and the first electrode 20 whose positive projection on the substrate 1 overlaps with the positive projection of the light-shielding layer 2 on the substrate 1 are removed to form a first electrode 20 located inside the fourth via 14 and on the side of the concave microstructures 18 facing away from the substrate 1.

[0112] Optionally, step S811 may specifically include:

[0113] The first electrode 20 is formed on the side of the interlayer dielectric layer 17 facing away from the substrate 1 by physical vapor deposition (PVD) process, chemical vapor deposition (CVD) process or sputtering process.

[0114] Optionally, step S812 may specifically include:

[0115] The first electrode 20 is patterned by an etching process to form a first electrode 20 located inside the fourth via 14 and on the side of the concave microstructures 18 facing away from the substrate 1.

[0116] For each pixel unit, when the width of the first region 19 between the adjacent concave microstructures 18 is less than 1 μm, the adjacent concave microstructures 18 define the first region 19, wherein the first region 19 includes a tip structure T formed by extrusion of a plurality of adjacent concave microstructures 18. By adopting the above composition method, problems such as the first electrode 20 at the first region 19 being easily detached or adsorbing foreign matters, which may cause the light-emitting layer 21 to be punctured, resulting in a short circuit between the first electrode 20 and the second electrode 22, and thus causing problems such as dark spots, can be well avoided.

[0117] S82. Form a light-emitting layer 21 on a side of the first electrode 20 away from the substrate 1.

[0118] S83. Form a second electrode 22 on a side of the light-emitting layer 21 away from the substrate 1.

[0119] Optionally, step S82 may specifically include:

[0120] Form the light-emitting layer 21 on a side of the first electrode 20 away from the substrate 1 by physical vapor deposition (PVD) process or chemical vapor deposition (CVD) process or sputtering process.

[0121] Optionally, step S83 may specifically include:

[0122] Form the second electrode 22 on a side of the light-emitting layer 21 away from the substrate 1 by physical vapor deposition (PVD) process or chemical vapor deposition (CVD) process or sputtering process.

[0123] Here, it should be noted that the pixel driving circuit of the display substrate in the embodiments of the present disclosure adopts, for example Figure 5The pixel driving circuit of the 3T1C structure shown includes: a first transistor T1, a second transistor T2, a third transistor T3, a capacitor Cst, and a light-emitting device OLED, and the light-emitting device OLED can be an organic light-emitting diode. Among them, the source of the first transistor T1 is connected to the gate line DATA, the gate is connected to the first gate line G1, and the data line is connected to the gate of the third transistor T3; the source of the second transistor T2 is connected to the source of the third transistor T3, the gate is connected to the second gate line G2, and the drain is connected to the detection interface Sense; the source of the third transistor T3 is connected to the light-emitting device OLED, the gate is connected to the first transistor T1, and the drain is connected to the first power supply voltage VDD; the first plate of the capacitor Cst is connected to the drain of the first transistor T1, and the second plate is connected to the source of the second transistor T2; the first pole of the light-emitting device OLED is connected to the ground electrode VSS, and the second pole is connected to the source of the third transistor T3. The third transistor T3 is a driving transistor. In the embodiment of the present application, the pixel driving circuit of the 3T1C structure effectively compensates the threshold voltage of the driving transistor in each pixel, uses fewer components, has a simple and stable structure, and saves costs.

[0124] In some examples, such as Figure 6 shown, the width of the gap between adjacent concave microstructures 18 is greater than or equal to 1 micrometer. Since there is no overlap between the concave microstructures 18, a plurality of flat structures F are formed at the gaps between the plurality of adjacent concave microstructures 18, thus avoiding the formation of a tip structure T by the adjacent concave microstructures 18 squeezing in the first region 19, fundamentally eliminating problems such as the first electrode 20 at the first region 19 being easily detached or adsorbing foreign objects, piercing the light-emitting layer 21, causing a short circuit between the first electrode 20 and the second electrode 22, and thus causing dark spot defects.

[0125] In some examples, the pixel driving circuit includes a thin-film transistor, and the thin-film transistor is a top-gate thin-film transistor. The top-gate thin-film transistor has the characteristic of a short channel, so its on-state current can be effectively increased, thus significantly improving the display effect and effectively reducing power consumption. Moreover, the overlapping area between the gate 6 and the source-drain of the top-gate thin-film transistor is small, so the parasitic capacitance generated is small, and the possibility of dark spot defects also decreases.

[0126] In some examples, the light-shielding layer 2 is disposed on a side of the active layer 4 of the thin-film transistor close to the substrate 1, and the orthographic projection of the light-shielding layer 2 on the substrate 1 covers the orthographic projection of the active layer of the thin-film transistor on the substrate 1. In addition, a portion of the orthographic projection of the active layer 4 on the substrate 1 that does not overlap with the orthographic projection of the gate insulating layer 5 on the substrate 1 is conductorized to form a conductor layer 7. By utilizing the lateral diffusion phenomenon during the conductorization of the active layer 4, the contact yield between the source electrode 10, the drain electrode 9, and the conductor layer 7 is increased, that is, the contact yield with the edge of the active layer 4 is increased, thereby greatly improving the conduction characteristics of the thin-film transistor device.

[0127] In some examples, the material of the active layer 4 of the thin-film transistor includes indium gallium zinc oxide (IGZO), which has the advantages of high carrier mobility, large-area preparation feasibility, good uniformity, stable device performance, etc., and is compatible with the current amorphous silicon thin-film transistor process, making it an ideal material in the display field.

[0128] In some examples, the color group layer 16 may include color filters of multiple colors. The color filters can generate the three primary colors of red (R), green (G), and blue (B) by means of light filtering, and then mix the three primary colors in different proportions to produce various colors, enabling the display substrate to present colors.

[0129] In some examples, the source electrode 10 of the driving transistor is electrically connected to the first electrode 20 of the light-emitting device and the light-shielding layer 2. In the embodiments of the present disclosure, the driving transistor can be used to regulate current and further control light emission.

[0130] In some examples, the materials of the first electrode 20 and the second electrode 22 include carbon nanotubes. Carbon nanotubes have a one-dimensional hollow tubular structure, the tube wall is surrounded by single-layer or multi-layer graphene sheets, the tube diameter is nanoscale, the tube length is micron-scale, and the length-to-diameter ratio is extremely large. Their properties will change due to different curling methods of the graphene sheets, showing metallic or semiconductor properties and having good electrical conductivity. Secondly, carbon nanotubes have good thermal conductivity, with an axial thermal conductivity of 2000 - 3000 W / mK, about 10 times that of copper and 3 times that of diamond. Thirdly, carbon nanotubes have an extremely large specific surface area and strong adsorption performance; at the same time, they have good electromagnetic wave absorption and other properties.

[0131] The embodiments of the present disclosure also provide a display device, which includes the display substrate in any one of the above embodiments. The display device can be, for example, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a vehicle-mounted device, or any other product with a display function. Other essential components of the display device should be understood by those of ordinary skill in the art and will not be elaborated herein, nor should they be regarded as a limitation to the present disclosure.

[0132] It is understandable that the above embodiments are merely exemplary embodiments adopted to illustrate the principles of the present disclosure. However, the present disclosure is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and essence of the present disclosure, and these modifications and improvements are also regarded as the protection scope of the present disclosure.

Claims

1. A display substrate, comprising a substrate substrate, an interlayer dielectric layer and pixel units disposed on the substrate substrate, wherein the pixel units include a plurality of concave microstructures formed on the interlayer dielectric layer, and a light-emitting device located on a side of the interlayer dielectric layer facing away from the substrate substrate; wherein, For at least one of the pixel units, a plurality of adjacent concave microstructures define a first region, and a first electrode of the light-emitting device has no overlap with a positive projection of the first region on the substrate substrate.

2. The display substrate according to claim 1, wherein, Each of the concave microstructures and the two nearest concave microstructures thereto define the first region.

3. The display substrate according to claim 1, wherein, The width of the first region between adjacent concave microstructures is greater than or equal to 1 micrometer.

4. The display substrate according to claim 1, wherein, The pixel unit further includes a pixel driving circuit electrically connected to the first electrode of the light-emitting device, and the pixel driving circuit includes a thin-film transistor, and the thin-film transistor is a top-gate thin-film transistor.

5. The display substrate according to claim 4, wherein, The pixel unit further includes a light-shielding layer, the light-shielding layer is disposed on a side of the active layer of the thin-film transistor close to the substrate substrate, and a positive projection of the light-shielding layer on the substrate substrate covers a positive projection of the active layer of the thin-film transistor on the substrate substrate.

6. The display substrate according to claim 5, wherein, The thin-film transistor in the pixel unit includes a driving transistor, and a source electrode of the driving transistor is electrically connected to the first electrode of the light-emitting device and the light-shielding layer.

7. The display substrate according to claim 1, wherein, It further includes a color-resist layer disposed on a side of the interlayer dielectric layer close to the substrate substrate, and at least a part of a positive projection of the color-resist layer on the substrate substrate overlaps with a positive projection of the concave microstructures on the substrate substrate.

8. A method for preparing a display substrate, wherein, Comprising: Providing a substrate substrate; Forming a pixel driving circuit in each pixel unit on the substrate substrate; The pixel driving circuit includes a thin-film transistor, and the thin-film transistor is a top-gate thin-film transistor; Forming a color-resist layer on a side of the layer where the pixel driving circuit is located and facing away from the substrate substrate, and the color-resist layer has no overlap with a positive projection of the pixel driving circuit on the substrate substrate; Forming an interlayer dielectric layer and pixel units on a side of the color-resist layer facing away from the substrate substrate; wherein, forming the pixel units includes: Performing patterning on a part of the interlayer dielectric layer to form concave microstructures, wherein a plurality of adjacent concave microstructures define a first region; Forming a first electrode of a light-emitting device on a side of the interlayer dielectric layer facing away from the substrate substrate, and the first electrode in the pixel unit has no overlap with a positive projection of the first region on the substrate substrate.

9. The manufacturing method of the display substrate according to claim 8, wherein, Before the step of forming the thin-film transistor, there is also a step of forming a light-shielding layer; the light-shielding layer is disposed on a side of the active layer of the thin-film transistor close to the substrate substrate, and a positive projection of the light-shielding layer on the substrate substrate covers a positive projection of the active layer of the thin-film transistor on the substrate substrate.

10. The manufacturing method of the display substrate according to claim 8, wherein, Each of the concave microstructures and the two nearest concave microstructures thereto define the first region.

11. The manufacturing method of the display substrate according to claim 8, wherein, The width of the first region between adjacent concave microstructures is greater than or equal to 1 micrometer.

12. A display device, wherein, Including the display substrate according to any one of claims 1 to 7.

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