Method and system for software-based prefetching of low buffer depth sequential read traffic

Abstract

A system and related method includes a storage circuit and a control circuit to receive at least one instruction in an instruction stream of a storage device when executing a storage device driver. The control circuitry determines that a hardware buffer of the storage device is storing less than two instructions. In response to a determination that a hardware buffer of the storage device is storing fewer than two instructions, the control circuitry accesses data associated with an address of a memory of the storage device, where the address is predicted based on an analysis of the flow of instructions, and causes the data to be stored in one of the plurality of buffers. The control circuitry executes the instructions in the instruction stream using at least the data stored in the buffer.

Description

Technical Field

[0001] The present disclosure relates to host device systems and related methods for software-based prefetching with low hardware buffer depth in storage devices, where the host device is executing a storage device driver. More particularly, the present disclosure relates to analyzing received read instructions by host software to predict the instruction stream and prefetching data from memory based on the prediction to improve the latency of a spatially sequential read instruction stream. Summary of the Invention

[0002] According to the present disclosure, systems and methods for software-based prefetching operating on a host device are provided. More particularly, when the host device is executing a storage device driver, the host device is communicatively coupled to a storage circuit, such as on a solid state drive (SSD) having a low instruction hardware buffer depth. In some embodiments, the storage circuit (e.g., SSD device) may be located within the host device or connected to the host via a suitable cable. For example, the storage host device may include a storage circuit (e.g., SSD device), a control circuit, and additional memory (e.g., RAM that is faster than SSD memory). In some embodiments, the storage circuit may be an SSD or other suitable storage non-volatile memory drive that includes a hardware buffer.

[0003] In one method, current techniques are performed when the hardware buffer includes fewer than two outstanding hardware instructions (e.g., exactly one hardware instruction). Software-based prefetching may be implemented at least in part on the control circuit using software, hardware, or a combination thereof. In some embodiments, when the hardware buffer of the storage circuit has a low buffer depth (e.g., one outstanding hardware instruction is stored in the hardware buffer), without software-based prefetching, the control circuit must directly access data for incoming hardware instructions from the storage device without the benefits of pipelining or prefetching, which may cause greater latency. To address this issue, prefetching may be initiated by host-level software (e.g., by the storage device driver) when the number of outstanding hardware instructions in the hardware buffer is low. This method reduces the latency of accessing memory by storing data in a buffer provided on a memory device (e.g., RAM memory) having a shorter access time, thereby reducing the total latency of storage access.

[0004] In some embodiments, software (e.g., driver)-based prefetching may be used to improve the instruction processing efficiency of any suitable host device at low hardware buffer depth, where the any suitable host device has a control circuit that executes a device driver and is coupled to a hardware buffer. In some embodiments, the device may be, for example, any suitable host device that is executing a memory device driver.

[0005] In some embodiments, a host device is provided with a control circuit and a storage circuit communicatively coupled to each other. In some embodiments, the control circuit includes a processor, a software instruction buffer, and a storage device driver having a plurality of buffers. In some embodiments, the control circuit (e.g., when executing the storage device driver) is configured to incrementally receive a stream of read instructions to be executed by the control circuit. The control circuit further determines, when executing the storage device driver, that the hardware buffer of the storage circuit currently stores less than two hardware instructions (i.e., either exactly one hardware instruction). In some embodiments, when the control circuit determines that the hardware buffer currently stores less than two hardware instructions (i.e., either exactly one hardware instruction), the control circuit predicts the address of a future read instruction based on the received read instruction in the instruction stream. The control circuit then accesses data associated with the predicted address of the memory of the storage circuit and stores the data in the software buffer. In some embodiments, when the control circuit later receives the predicted software read instruction, the control circuit implements it by prefetching at least the data stored in the software buffer. In some embodiments, the received instruction stream can be received from the host's operating system, from another application executing on the host, or from a device other than the host device. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The following description includes a discussion of the figures, which have illustrations given by way of example of implementations of embodiments of the present invention. The drawings should be understood as examples and not as limitations. As used herein, reference to one or more "embodiments" should be understood to describe specific features, structures, and / or characteristics included in at least one implementation. Thus, phrases such as "in one embodiment" or "in an alternative embodiment" that appear herein describe various embodiments and implementations and do not necessarily all refer to the same embodiment. However, they are not necessarily mutually exclusive either.

[0007] Figure 1 An illustrative diagram of a system of a host device system having a storage circuit, a control circuit, and a storage device driver, according to some embodiments of the present disclosure; Figure 2 An illustrative diagram of an operating system that disposes of multiple applications when executing a storage device driver, according to some embodiments of the present disclosure; Figure 3 A diagram of a buffer of a storage device driver, in which an instruction stream is detected to prefetch data of a predicted instruction stream when the hardware buffer has a small number of hardware instructions, according to some embodiments of the present disclosure; Figure 4Illustrative diagrams of a storage device driver at two different times (time t1 and time t2) according to some embodiments of the present disclosure; Figure 5 Illustrative diagrams of two timelines for executing instructions with prefetching disabled and prefetching enabled according to some embodiments of the present disclosure; Figure 6 A flowchart according to some embodiments of the present disclosure, which illustrates a process for accessing data associated with an address in a memory of a host device and executing instructions in an instruction stream using at least prefetch data stored in a buffer; Figure 7 A flowchart according to some embodiments of the present disclosure, which illustrates a process for marking an identified expired buffer for reuse; Figure 8 A flowchart according to some embodiments of the present disclosure, which illustrates a process for determining a buffer for reuse among a plurality of buffers when each of the plurality of buffers has been allocated to data associated with a determined instruction stream; Figure 9 A flowchart according to some embodiments of the present disclosure, which illustrates a process for handling incoming instructions using software-based prefetching; and Figure 10 A flowchart according to some embodiments of the present disclosure, which illustrates a process for performing an independent multi-plane read operation using a snapshot read caused by a sequential read command. Detailed Description

[0008] According to the present disclosure, a host device system and method are provided for software-based (e.g., storage device driver-based) prefetching with low hardware buffer depth in a storage circuit to improve the quality of operation of the host system (e.g., improve latency when the hardware buffer has a small number of outstanding hardware instructions). In some embodiments, the hardware buffer (e.g., of the storage circuit) can be an instruction stack or instruction queue for the storage circuit. In some embodiments, the hardware buffer and the storage circuit can be located outside the host device (e.g., via a suitable cable connection). The host device can have a control circuit that executes a storage device driver for controlling the storage device. The storage device driver can provide multiple buffers (e.g., using the host device's RAM). In some embodiments, the control circuit of the host device can include a processing unit (e.g., a processor) that can operate on instructions in an instruction stream (e.g., a sequential instruction stream), where the control circuit receives the instruction stream (e.g., when executing the storage device driver). In some embodiments, the spatially sequential stream of read instructions includes instructions stored at sequential memory addresses. In some embodiments, the execution of an instruction can be divided into four timing categories of stages, which include: software send / complete instruction, hardware process instruction, software idle time while the hardware processes the instruction, and software copy prefetch buffer.

[0009] In some embodiments, for each instruction in the instruction stream, the operations run sequentially with respect to clock cycles. In a single-processor example, the hardware processing of a second instruction may not necessarily start before the hardware processing of a first instruction is complete. By analyzing a specific number of instructions in the instruction stream and predicting which prefetch data is to be accessed based on the identified instruction stream, the latency of accessing data by the host device is improved. In some embodiments, the storage control circuit analyzes a portion or a specific number of incoming instructions when executing the storage device driver to predict the instruction stream associated with the prefetch data stored in the multiple buffers. Software-based prefetching for the host device driver can enable improvement in the latency of the host device when driving instructions or requests.

[0010] In one method, when the hardware buffer has a small number of hardware instructions (e.g., fewer than two or only one hardware instruction), instructions can be driven, and due to the inability to fully utilize the pipeline of the storage device, there may be additional latency between each instruction request received by the control circuit.

[0011] To address this issue, the operation of the host device can cause software (e.g., a storage device driver) to predict and prefetch data associated with at least one instruction, such that the storage device driver does not have to idle between receiving each instruction. Thus, the storage device driver predicts the instruction stream and prefetches data associated with the predicted instruction stream before receiving any additional requests. In this way, the latency of the host device is reduced in the case where the number of instructions in the hardware buffer is less than two hardware instructions (i.e., either exactly one instruction).

[0012] In some embodiments, the processor of the control circuit can be a highly parallelized processor capable of quickly disposing of high-bandwidth instructions (e.g., by processing while starting a new instruction before completing a previous instruction).

[0013] In some embodiments, the systems and methods of the present disclosure can refer to a host device communicatively coupled to an SSD storage system, where the host device is executing a storage device driver having a plurality of buffers (such as non-volatile random access memory (NVMe) buffers) for a network protocol interface.

[0014] An SSD is a data storage device that uses integrated circuit assemblies as memory to persistently store data. The SSD has no moving mechanical components, and this feature differentiates the SSD from traditional electromechanical disks (such as hard disk drives (HDDs) or floppy disks), which contain rotating disks and movable read / write heads. Compared to electromechanical disks, SSDs are generally more resistant to physical shock, quiet in operation, have shorter access times, and less latency.

[0015] Many types of SSDs use NAND-based flash memory, which retains data without power and includes a type of non-volatile storage technology. The quality of service (QoS) of an SSD may be related to the predictability of low latency and the consistency of high input / output operations per second (IOPS) when servicing read / write input / output (I / O) workloads. This means that the latency or I / O command completion time needs to be within a specified range without unexpected outliers. The throughput or I / O rate may also need to be tightly regulated without causing a sudden drop in the performance level.

[0016] By reference Figures 1 - 9 , the subject matter of the present disclosure can be better understood.

[0017] Figure 1Illustrative diagram of a host device system 100 having a storage circuit 104, a control circuit 106, and a storage device driver 118 in accordance with some embodiments of the present disclosure. In some embodiments, the host device system 100 may include a host device 102, and the host device 102 includes a control circuit 106 and a storage circuit 104. In some embodiments, the control circuit 106 may include a processor 120, a software instruction buffer (e.g., retained in a memory 124), and a storage device driver 118 having a plurality of buffers 116 (e.g., retained in the memory 124). In some embodiments, the plurality of buffers 116 and the software instruction buffer may use a memory 124 other than the storage circuit 104 (e.g., the memory 124 may be a RAM memory having a lower access latency than the storage circuit 104).

[0018] In some embodiments, each buffer 114 is configured to store data associated with an instruction in a determined instruction stream (e.g., prefetch data from a predicted address of an instruction stream in the storage circuit 104) to manage instruction stream detection for software-based prefetching. In some embodiments, when the control circuit 106 is analyzing and predicting an instruction stream while executing the storage device driver 118, the software instruction buffer 122 is used as a temporary software buffer to store received software instructions. In some embodiments, the storage circuit 104 includes a hardware buffer 112 configured to store hardware instructions. The host device 102 may also include a memory 124, such as a volatile memory, such as a RAM memory (e.g., dynamic random access memory (DRAM)), which has a faster access time compared to the access time of the storage circuit 104 (e.g., SSD). It will be understood that embodiments of the present disclosure are not limited to SSDs. For example, in some embodiments, in addition to or instead of the storage circuit 104, the host device system 100 may include a hard disk drive (HDD) device.

[0019] In some embodiments, the host device system 100 may receive an instruction stream 110 from a source, where the source is external to the host device 102 or within the host device 102 (e.g., from an application). In some embodiments, when the control circuit 106 receives a read request for a number (e.g., five or ten or any other suitable number) of sequential addresses in the storage circuit 104, the control circuit 106 may identify the instruction stream 110.

[0020] In some embodiments, the memory 124 includes any one or more of non-volatile memories such as phase change memory (PCM), PCM and switches (PCMS), ferroelectric random access memory (FeRAM) or ferroelectric transistor random access memory (FeTRAM), and magnetoresistive random access memory (MRAM), any other suitable memory, or any combination thereof. In some embodiments, the memory 124 includes any one of non-volatile memory, volatile memory, or any combination thereof. In some embodiments, the control circuit 106 is communicatively coupled to the hardware buffer 112 of the storage circuit 104 to receive information about the outstanding hardware instructions stored in the hardware buffer 112. Additionally, the control circuit 106 is communicatively coupled to the memory 124. In some embodiments, a data bus interface is used to transfer instructions (e.g., instruction 108) or an address or data associated with the instruction. The data bus between the memory 124 and the control circuit 106 provides a network bus for reading or writing data through the memory 124. The processor 120 of the control circuit 106 may include a hardware processor, a software processor (e.g., a processor emulated using a virtual machine), or any combination thereof. The processor 120 may include any suitable software, hardware, or both for controlling the storage device driver 118, instruction stream prediction, and prefetching of data associated with the predicted instruction stream. The memory 124 may include hardware elements for non-transitory storage of commands or instructions.

[0021] In some embodiments, the memory 124 is a multi-plane or three-dimensional (3D) memory array. In some embodiments, the memory 124 includes floating gate NAND gates. The control circuit 106 may receive a sequential read command that causes a read operation. The read operation may be a snapshot read operation that is used to access 4K, 8K, or 16K of data from the memory 124. In some embodiments, the snapshot read operation is used to access any other suitable size of data from the memory 124. In some embodiments, the sequential read command may cause a read that accesses multiple planes of the memory 124. The control circuit 106 may cause a multi-plane read by using independent multi-plane read operations (IMPRO) that access portions of at least two different planes of the memory 124. To improve the efficiency of IMPRO, the control circuit 106 may be configured to perform IMPRO using snapshot reads. This allows the control circuit 106 to perform a multi-plane snapshot read to access at least two planes of the memory 124.

[0022] The control circuit 106, when executing the storage device driver 118, is configured to receive an instruction 108 in the instruction stream 110 and determine how many outstanding hardware instructions are stored within the hardware buffer 112. When the control circuit 106, while executing the storage device driver 118, determines that there is a low hardware buffer 112 depth (e.g., a hardware buffer depth of exactly one hardware instruction), the control circuit 106 may prefetch data associated with an address of the memory 124, where the address is predicted based on reading the instruction stream 110. In some embodiments, the control circuit 106, when executing the storage device driver 118, stores the prefetched data of the instruction stream 110 in the buffer 114 among the plurality of buffers 116. When the control circuit 106 receives an instruction 108 that is part of the instruction stream 110, if the instruction matches the data prefetched based on the prediction, the storage device driver 118 implements the instruction 108 directly from the buffer 114 without further accessing the storage circuit 104.

[0023] The storage circuit 104 (e.g., an SSD device) may include one or more non-volatile memory die packages, where each die includes memory cells. In some embodiments, the memory cells are organized into pages, and the pages are organized into blocks. Each memory cell may store one or more bits of information.

[0024] It will be understood that although the host device system 100 depicts an embodiment in which the host device 102, when executing the storage device driver 118, is configured to have a software-based prefetching capability in accordance with the present disclosure, any other suitable device may have software-based prefetching in a similar manner.

[0025] For purposes of clarity and conciseness, and not by way of limitation, the present disclosure is provided in the context of software-based prefetching at low hardware buffer depth, which provides the features and functionality disclosed herein. Software-based prefetching may be configured by any suitable software, hardware, or both for implementing such features and functionality. Software-based prefetching may be implemented at least in part, for example, in the host device system 100 (e.g., as part of the host device 102, or any other suitable device on which efficiency may be improved at low hardware buffer depth), while executing the storage device driver 118. For example, for a host device 102 communicatively coupled to a solid-state storage device (i.e., the storage circuit 104), software-based prefetching may be implemented in the control circuit 106 while executing the storage device driver 118. In some embodiments, software-based prefetching may be implemented at least in part as part of an operating system of the host device system in which the storage device driver 118 is integrated.

[0026] Figure 2Illustrative diagrams of an operating system 202 that disposes multiple applications (e.g., a first application 210, a second application 212, and a third application 214) when executing a storage device driver 204 according to some embodiments of the present disclosure are shown. Although three applications (210, 212, and 214) are shown in Figure 2 , any suitable number of applications may be included in some embodiments. In some embodiments, the operating system 202 is loaded on the control circuit 106 of the host device 102 (as seen in Figure 1 ). In some embodiments, the storage device driver 204 includes multiple buffers 206, where each buffer 208 is configured to store data associated with a determined instruction stream for software-based prefetching. In some embodiments, each buffer 208 may store prefetch data of the streams from the applications 210 - 214 in a memory faster than the storage circuit 216 (e.g., in the memory 124 of Figure 1 ). In some embodiments, the storage device driver 204, the multiple buffers 206, the buffer 208, and the storage circuit 216 respectively correspond to the storage device driver 118, the multiple buffers 116, the buffer 114, and the storage circuit 104 in Figure 1 . The storage device driver 204 may be communicatively coupled to the storage circuit 216.

[0027] In some embodiments, the storage device driver 204 receives instruction streams from multiple applications, such as a first read instruction stream from the first application 210, a second read instruction stream from the second application 212, and a third read instruction stream from the third application 214. The storage device driver 204 may also receive an instruction stream 110 from the operating system 202 or from outside the operating system 202, as shown in the system 100 of Figure 1 . In some embodiments, the storage device driver 204 may receive more than three different read instruction streams from more than three applications.

[0028] In some embodiments, each buffer 208 among the plurality of buffers 206 may store data associated with an instruction stream prefetched from the storage circuit 216. In some embodiments, when executing the storage device driver 204, the control circuit 106 may track whether the buffer 208 storing data associated with a partial instruction stream or a complete instruction stream is storing valid data by configuring a valid bit map. In some embodiments, each buffer 208 among the plurality of buffers 206 may correspond to one bit in the bitmap, where the bitmap includes flag bits for each buffer 208 among the plurality of buffers 206. When each buffer 208 among the plurality of buffers 206 is storing data associated with a partial instruction stream or a complete instruction stream, the valid bit may be useful when determining which buffer 208 to clear or overwrite.

[0029] Figure 3 A diagram of the buffer 208 of the storage device driver 204 according to some embodiments of the present disclosure is shown, in which an instruction stream 302 is detected to prefetch data at predicted addresses of the instruction stream (e.g., 306, 308, 310, 312, 314, 316, 318, 320) when the hardware buffer has a small number of hardware instructions. In some embodiments, the storage device driver 204 and the buffer 208 respectively correspond to the storage device driver 118 and the buffer 114 in Figure 1 the.

[0030] The storage device driver 204 includes a buffer 208 that stores data associated with an instruction stream (e.g., 306, 308, 310, 312, 314, 316, 318, and 320). As shown, the control circuit 106 incrementally receives incoming instructions 302 (e.g., a read instruction at address 1001, a read instruction at address 1002, a read instruction at address 1003, a read instruction at address 1004, and a read instruction at address 1005). In some embodiments, when executing the storage device driver 204, the control circuit 106 analyzes a specific number of incoming instructions 302 to predict the instruction stream. In some embodiments of the present disclosure, the number of incoming instructions and the number of buffers are not limited to Figure 3The number of incoming instructions 302 and the number of buffers 208 shown in. For example, the control circuit 106 predicts the instruction stream when executing the storage device driver 204 because the storage device driver 204 receives a specific number (e.g., five or ten) of requests to read data from five addresses (e.g., addresses 1001 - 1005). In some embodiments, the control circuit 106 prefetches data associated with the predicted addresses of the instruction stream when executing the storage device driver 204. The control circuit 106 does not prefetch any data until a spatially sequential read instruction stream (e.g., addresses 1001 - 1005) is detected when executing the storage device driver 204. For example, the control circuit 106 can predict the address of the instruction stream after sequentially receiving the read instruction at address 1001 to the read instruction at address 1005 (so the control circuit 106 can predict that the stream will have read requests for addresses after address 100 (i.e., addresses 1006, 1007, 1008... etc.) in the future). Thus, the control circuit 106 prefetches data 304 associated with future instructions of the predicted addresses of the instruction stream (e.g., 308, 310, 312, 314, 316, 318, and 320) when executing the storage device driver 204. As shown, the data prefetched from the predicted addresses 1006 - 1013 is stored in the buffer 208 before the instruction stream 302 requests data from the predicted addresses. By using software-based prefetching, the data associated with the predicted addresses of the instruction stream is more accessible with a smaller access latency when stored in the buffer 208 compared to when stored in the host memory 124.

[0031] Figure 4 Illustrative diagrams 400, 401, and 402 of the storage device driver 204 at three different times (time t1, time t2, and time t3) in accordance with some embodiments of the present disclosure are shown. For example, the buffer at time t1 can be associated with Figure 3is the same as buffer 208. As shown at time t1, the buffer stores data prefetched from spatial sequential addresses 1006-1037 (e.g., 406, 408, 410, 412, 414, 416, and 418). In one example, when the prefetched data from address 1037 is stored in the last entry in buffer 418, there is no more space in the buffer to store the prefetched data, and the prefetching may have been temporarily suspended or continue to prefetch data into another available buffer. In the example shown, the prediction is correct, and the sequential read instruction stream 404 begins to request data from address 1006 to address 1037. Since the data has been prefetched, the storage device driver 204 may have provided the data from the buffer. When the data from address 1037 is requested, the control circuit provides the stored prefetched data from buffer entry 418 when executing the storage device driver 204, and determines that the last prefetched data in the buffer has been requested by the sequential read instruction stream 404. Thus, the buffer can be reused to further prefetch data at the predicted sequential addresses of the read instruction stream 404 (e.g., for a read instruction at address 1038, a read instruction at address 1039, a read instruction at address 1040, etc.). In some embodiments of the present disclosure, the number of incoming instructions is not limited to Figure 4 the number of incoming instructions of the sequential read instruction stream 404 shown in

[0032] At time t2, the control circuit marks the buffer entries as expired and available for reuse. Thus, the buffer entries of the buffer can be used to store data associated with a newly identified instruction stream or continue to prefetch the currently identified sequential read instruction stream. At time t3, the control circuit resumes prefetching the predicted instructions of the sequential read instruction stream 404 when executing the storage device driver (e.g., by prefetching data from addresses 1038-1069 into the previously expired buffer). In some embodiments, the buffer entries (e.g., 420, 422, 424, 426, 428, 430, and 432) are no longer marked as expired by setting the corresponding valid bits of a valid bitmap to indicate valid data. In another example, the buffer can be used for a newly predicted instruction stream. For example, if another requested instruction stream reads from addresses 2500-2505, the buffer can prefetch data from address 2506 to 2537 for faster data access when processing the instructions.

[0033] In certain embodiments, the valid bitmap indicating each buffer in a plurality of buffers may be a valid buffer or an expired buffer. At time t2, the "*" symbol in the buffer entry of buffer 204 indicates the corresponding valid bit of the buffer 208 in the bitmap of a plurality of buffers. When each buffer in a plurality of buffers is storing data associated with a partial instruction stream or data associated with a complete instruction stream, these valid bits may be useful for determining which buffer memory to clear or overwrite. Therefore, at time t2, buffer 208 is marked as an expired buffer, and can be used for control circuitry to be reused for storing data associated with the instruction stream of a new identifier.

[0034] Figure 5 An illustrative diagram of two timelines of executing instructions (e.g., 501, 502, 503, 504, 511, 512, 513, and 514) with prefetch disabled 500 and prefetch enabled 510 according to some embodiments of the present disclosure is shown. To illustrate the comparison between the two timelines 500 and 510, four instructions are shown in each timeline, each of which is a sequential read instruction. In addition, each timeline has instructions corresponding to the opposite timeline. For example, instruction 501 is assumed to be exactly the same instruction as instruction 511, but in a different implementation for instruction processing.

[0035] In some embodiments, executing instructions can be divided into four stages of timing categories, including: software sends / completes instructions, hardware processes instructions, software idles time when hardware processes instructions, and software copies pre-fetch buffers. However, in general, for each instruction in the instruction stream, operations must be run sequentially with respect to clock cycles. In the single processor example, the hardware processing of the second instruction 502 may not necessarily start before the hardware processing of the first instruction 501 is completed.

[0036] In some embodiments of the present disclosure, the no-prefetch timeline 500 indicates a loop pattern of instruction processing, where the consistent idle time of the software of the storage device waits for the instruction processing in the hardware to be completed. However, once the control circuit predicts the instruction stream, when executing the storage device driver (as seen in the prefetch timeline), the control circuit can prefetch the data associated with the predicted instruction stream of the second instruction 512 before the second instruction is received and sent for processing. As expected, the latency of each of the first instructions 501 and 511 of the two timelines is the same. Since the latency associated with accessing one of the multiple buffers is much smaller than accessing the host memory (e.g., RAM memory), the latency of subsequent instructions is reduced. By prefetching the data at the predicted sequential address into the buffer, the control circuit can quickly access the data when the data is requested. Although the latency of the subsequent instructions (e.g., 512, 513, and 514) of the prefetch timeline 510 is reduced, the latency of the first instruction remains the same because the control circuit has not prefetched any data for the first instruction 511 and will use the first instruction 511 to determine the predicted instruction stream.

[0037] Figure 6 A flowchart according to some embodiments of the present disclosure is shown, which illustrates a process 600 for accessing data associated with an address of a memory of a storage device and executing instructions in an instruction stream using at least the data stored in a buffer. In some embodiments, the control circuit, storage device driver, instructions in the instruction stream, storage device, hardware buffer, memory, and buffer referred to may be implemented as the control circuit 106, storage device driver 118, instructions 108 in the instruction stream 110, storage device 102, hardware buffer 112, memory 124, and buffer 114, respectively. In some embodiments, the process 600 may be modified by, for example, rearranging, changing, adding, and / or removing steps.

[0038] In step 602, the control circuit receives at least one instruction in the instruction stream of the storage device when executing the storage device driver. In some embodiments of the present disclosure, the instruction stream may be an external source outside the storage device. In some embodiments, the instruction stream may be an internal source within an operating system (e.g., operating system 202), such as an application having multiple output instructions to be executed. In some embodiments, the control circuit is capable of receiving multiple instruction streams from a source located inside or outside the storage device when executing the storage device driver. In some embodiments, the instruction stream is a sequential instruction stream, where at least one instruction is a sequential read instruction. After receiving the instruction stream, in step 604, the control circuit then determines that the hardware buffer of the storage circuit (e.g., storage circuit 104) stores less than two uncompleted hardware instructions when executing the storage device driver.

[0039] In step 604, the control circuit determines whether the hardware buffer of the storage device is currently storing fewer than two instructions when executing the storage device driver. In some examples, when there are unfinished hardware instructions with a low depth in the hardware buffer (e.g., exactly one hardware instruction is stored in the hardware buffer), the amount of time to access data associated with the unfinished instruction stored in one of the multiple buffers can be less than the latency of the subsequent instructions of the received instruction stream. In examples without prefetching, the storage device driver and the control circuit have a large latency for accessing data associated with the unfinished instruction from the memory. In some embodiments, this increase in latency is detrimental to the efficiency of the processing power of the host device.

[0040] In step 606, the control circuit determines the next step of process 600 based on whether the hardware buffer is currently storing fewer than two hardware instructions in 604 when executing the storage device driver. In 602, if the hardware buffer is storing two or more hardware instructions, the control circuit will continue to receive the instruction stream when executing the storage device driver while executing the unfinished hardware instructions in the hardware buffer without any instruction stream prediction or software-based prefetching. In some embodiments, in 608, if the hardware buffer is currently storing only one hardware instruction or is not currently storing any instructions, the control circuit will perform stream prediction by accessing data associated with the address of the memory of the storage device when executing the storage device driver.

[0041] In step 608, the control circuit accesses data associated with the address of the memory of the storage device when executing the storage device driver, where the address is predicted based on the analysis of the received instruction stream. In some embodiments, the control circuit determines the predicted instruction stream based on the unfinished hardware instructions in the hardware buffer and by analyzing a specific number of the received instruction stream. In such embodiments, the control circuit can determine one of the multiple buffers, where the corresponding instruction stream associated with the data stored in the buffer matches the predicted instruction stream. Once the control circuit determines the buffer, in 610, the control circuit stores the data into the buffer when executing the storage device driver.

[0042] In step 610, the control circuit causes data to be stored in a buffer when executing a storage device driver. In some embodiments, the buffer is one of a plurality of available buffers. In some embodiments, the determined buffer may contain data associated with an incomplete instruction stream such that any data associated with newly detected instructions in the sequential instruction stream can be stored in the determined buffer. In such embodiments, the determined buffer is capable of storing additional data associated with an instruction until the instruction stream has terminated or the buffer reaches full memory capacity. In some embodiments, the control circuit may maintain data associated with the corresponding instruction stream associated with each of the plurality of buffers when executing a storage device driver until each buffer has data associated with at least a portion of the instruction stream stored for software-based prefetching. In some embodiments of the present disclosure, the control circuit is capable of marking a buffer as expired or reusable for storing data associated with a newly identified instruction stream when executing a storage device driver. According to the present disclosure, at 612, data associated with at least one instruction in the predicted instruction stream stored in the determined buffer is executed by the control circuit when executing a storage device driver.

[0043] In step 612, the control circuit executes instructions in the instruction stream using at least the data stored in the determined buffer when executing a storage device driver. In some embodiments, the control circuit will be able to execute the instruction stream more efficiently by prefetching data rather than waiting for longer access times to access data associated with each sequential instruction stored in memory. In some embodiments, the instruction stream is a sequential read instruction stream.

[0044] Figure 7 A flowchart in accordance with some embodiments of the present disclosure is shown that illustrates a process 700 for marking an identified expired buffer for reuse. In some embodiments, the control circuit, storage device driver, instructions in the instruction stream, storage device, and one of the plurality of buffers referenced may be implemented as control circuit 106, storage device driver 118, instructions 108 in instruction stream 110, storage device 102, and buffer 114 in plurality of buffers 116, respectively. In some embodiments, process 700 may be modified by, for example, having steps rearranged, changed, added, and / or removed.

[0045] In step 702, the control circuit configures a plurality of buffers when executing a storage device driver, where each of the plurality of buffers can be allocated data associated with an instruction in a corresponding instruction stream among a plurality of instruction streams received by the storage device driver. In some embodiments, the plurality of buffers are configured to be wrapped in the storage device driver. Each buffer is to be configured such that if the control circuit, when executing the storage device driver, detects that an additional instruction within the received instruction matches the instruction stream of the buffer, the data associated with the additional instruction can be appended to the end of the buffer. Additionally, in some embodiments, each of the plurality of buffers can store data associated with an address that points to data associated with an instruction. In some embodiments, each of the plurality of buffers can correspond to a bitmap, where the bitmap includes flag bits for each of the plurality of buffers. In some embodiments, a corresponding bitmap is used to track whether a buffer that is storing data associated with a partial instruction stream or data associated with a complete instruction stream is still valid. The valid bit can be useful when determining which buffer memory to clear or overwrite when each of the plurality of buffers is storing data associated with a partial instruction stream or data associated with a complete instruction stream. In some embodiments, the valid bitmap uses a single bit for each corresponding data structure (e.g., each buffer), where in some implementations, a valid bit value of 1 means that the buffer should not be cleared, and a valid bit value of 0 indicates that the instruction stream of the buffer may no longer need to be detected.

[0046] In step 704, the control circuit identifies an instruction stream when executing a storage device driver by detecting a specific number of sequential read instructions. In some embodiments, the control circuit determines a predicted instruction stream when executing the storage device driver by analyzing a specific number of received instruction streams. In such an embodiment, the control circuit can determine one of the plurality of buffers when executing the storage device driver, where the corresponding instruction stream associated with the stored data in the buffer matches the predicted instruction stream based on the analysis of the specific number of instructions in the received instruction streams. As seen in step 706, the control circuit can then determine that the buffer is expired among the plurality of buffers when executing the storage device driver.

[0047] In step 706, the control circuit identifies an expired buffer among a plurality of buffers when executing a storage device driver. After identifying the buffer and completing software-based prefetching of a given predicted instruction stream, the control circuit can determine the source of the instruction stream (such as an application that is no longer running) when executing the storage device driver, and thus at least one of the plurality of buffers stores data associated with the instruction stream of that source. Once the control circuit identifies the expired buffer, in step 708, the control circuit then marks the identified expired buffer when executing the storage device driver.

[0048] In step 708, the control circuit marks the identified buffer as available for reuse when executing the storage device driver. In some embodiments of the present disclosure, the control circuit marks the identified buffer as expired when executing the storage device driver, for example, by toggling a corresponding valid bit in a valid bitmap to indicate that the data in the identified buffer is no longer valid for use. According to the present disclosure, the marked buffer can be reused by the control circuit for data associated with a newly identified instruction stream.

[0049] Figure 8 A flowchart according to some embodiments of the present disclosure is shown, which illustrates a process 800 for determining a buffer available for reuse among a plurality of buffers when each of the plurality of buffers has been allocated to data associated with a determined instruction stream. In some embodiments, the control circuit, storage device driver, instructions in the instruction stream, storage device, and a buffer among the plurality of buffers mentioned can be implemented as the control circuit 106, storage device driver 118, instructions 108 in the instruction stream 110, storage device 102, and buffer 114 among the plurality of buffers 116, respectively. In some embodiments, the process 800 can be modified by, for example, rearranging, changing, adding, and / or removing steps.

[0050] In step 802, the control circuit identifies a new stream when executing the storage device driver. In some embodiments, the control circuit can detect a new instruction stream when executing the storage device driver, and the new instruction stream does not match any of the instruction streams associated with the stored data of the plurality of buffers. Thus, data associated with the newly identified instruction stream is to be stored in a buffer to help reduce latency for subsequent instruction streams. In some embodiments, at 804, the control circuit then determines whether all buffers have been allocated to valid data associated with an instruction stream when executing the storage device driver.

[0051] In step 804, the control circuit determines whether all of the plurality of buffers have been allocated to data associated with a corresponding instruction stream when executing the storage device driver. In some embodiments, the control circuit may determine whether each valid bit of a valid bitmap associated with the plurality of buffers is set to valid when executing the storage device driver. In 806, the control circuit then determines the next step of process 800 based on whether all of the plurality of buffers have been allocated to valid data associated with the instruction stream when executing the storage device driver.

[0052] In step 806, the control circuit determines the next step of process 800 based on whether all of the plurality of buffers have been allocated to data associated with a corresponding instruction stream when executing the storage device driver. In some embodiments, if the control circuit determines that all of the plurality of buffers have been allocated to valid data associated with the instruction stream, then in 808, the control circuit determines the buffers to be reused among the plurality of buffers when executing the storage device driver. However, if the control circuit determines that there are available, unallocated buffers or expired buffers when executing the storage device driver, then in 810, the control circuit allocates one of the unallocated buffers or expired buffers to data associated with a new instruction stream.

[0053] At step 808, the control circuit determines a buffer to be reused among a plurality of buffers when executing a storage device driver. In some embodiments, when each buffer among the plurality of buffers is determined to store valid data associated with an instruction stream, the control circuit may have to determine which is the least recently used buffer, the least frequently used buffer for the control circuit to access data associated with a predicted instruction stream, or the buffer storing data at an address close to the predicted address of a new instruction stream. The least recently used buffer is the buffer that has been the longest time since the last access by the control circuit, which in some examples may indicate that the control circuit is unlikely to receive an instruction stream that will match the instruction stream corresponding to the stored data associated with the least recently used buffer when executing the storage device driver. Additionally, other embodiments of the present disclosure may enable the control circuit to determine the buffer to be reused based on the least frequently used buffer when executing the storage device driver. In such an embodiment, the control circuit may maintain a counter for each buffer when executing the storage device driver, where the counter is incremented whenever the control circuit accesses data associated with the corresponding buffer when executing the storage device driver. Thus, the control circuit can determine the least frequently used buffer as indicated by the buffer with the smallest corresponding counter value. In some embodiments, the control circuit may use a combination of least frequently used and least recently used when executing the storage device driver to determine the buffer to be reused. In some embodiments, the buffer storing data at an address close to the predicted address of a new instruction stream may be the buffer that prefetches the first part of the predicted address of the instruction stream. However, the data of the second part of the predicted address also needs to be prefetched. In some embodiments, if there is no other available buffer, the control circuit reuses the buffer storing the prefetched data of the first part of the predicted address to store the prefetched data of the second part of the predicted address. Once the buffer is determined, the determined data stored on the buffer is cleared to store data associated with the newly identified instruction stream.

[0054] In step 810, the control circuit, when executing the storage device driver, assigns one of the unallocated buffers or expired buffers among the plurality of buffers to the data associated with the new instruction stream. When the control circuit determines that there is at least one unallocated buffer or expired buffer when executing the storage device driver, the control circuit may store the data associated with the newly identified buffer onto the unallocated buffer when executing the storage device driver, or clear the expired buffer to allow the storage of the data associated with the newly identified buffer. However, for example, if there is one unallocated buffer and one expired buffer available, the control circuit may determine to store the data associated with the newly identified instruction stream onto the unallocated buffer when executing the storage device driver because it requires fewer steps to store the data associated with the new instruction stream.

[0055] Figure 9 FIG. 4 shows a flowchart in accordance with some embodiments of the present disclosure, which illustrates a process 900 for utilizing software-based prefetching to handle incoming instructions. In some embodiments, the control circuit, storage device driver, instructions in the instruction stream, hardware buffer, and one buffer among the plurality of buffers referenced may be implemented as control circuit 106, storage device driver 118, instructions 108 in instruction stream 110, hardware buffer 112, and buffer 114 among the plurality of buffers 116, respectively. In some embodiments, process 900 may be modified by, for example, rearranging, changing, adding, and / or removing steps.

[0056] In step 902, the control circuit identifies an incoming instruction when executing the storage device driver. In some embodiments, when executing the storage device driver, the incoming instruction may be one of the instructions in the instruction stream detected by the control circuit. In some embodiments, at 904, the control circuit then determines the next step of process 900 based on whether the hardware buffer is storing less than two hardware instructions (i.e., either exactly one instruction) when executing the storage device driver.

[0057] In step 904, the control circuit determines whether the hardware buffer is storing less than two hardware instructions when executing the storage device driver. In some embodiments, if the control circuit determines that the hardware buffer is storing at least two hardware instructions when executing the storage device driver, then at 908, the control circuit disposes of the incoming instruction without software-based prefetching. In other embodiments, when the control circuit determines that the hardware buffer is storing less than two hardware instructions when executing the storage device driver, at 906, the control circuit then determines the next step of process 900 based on whether the instruction is a read instruction of an appropriate size.

[0058] In step 906, the control circuit determines the next step of process 900 based on whether the instruction is a read instruction of an appropriate size (e.g., 4KB, 8KB, …, 128KB) when executing the storage device driver. In some embodiments, if the control circuit determines that the instruction is not a read instruction or does not have an appropriate size when executing the storage device driver, then at 908, the control circuit processes the incoming instruction without software-based prefetching. In other embodiments, when the control circuit determines that the instruction is a read instruction of an appropriate size when executing the storage device driver, at 910, the control circuit then determines the next step of process 900 by determining whether there is an identified buffer in the plurality of buffers that is storing data associated with the matching instruction stream.

[0059] In step 908, the control circuit processes the incoming instruction without software-based prefetching when executing the storage device driver. In some embodiments, hardware buffers with a depth greater than two hardware instructions may not take advantage of software-based prefetching. Additionally, prefetching data associated with an instruction stream that includes write instructions does not guarantee accurate prefetch data because write instructions may change the data that has already been prefetched.

[0060] In step 910, the control circuit determines the next step of process 900 by determining whether there is an identified buffer in the plurality of buffers that is storing data associated with the matching instruction stream when executing the storage device driver. In some embodiments, if the control circuit determines that there is an identified buffer storing data associated with the matching instruction stream when executing the storage device driver, then at 912, the control circuit uses the data stored in the identified buffer to at least process the instruction. In other embodiments, when the control circuit determines that there is no identified buffer storing data associated with the matching instruction stream when executing the storage device driver, at 914, the control circuit then determines the next step of process 900 by determining whether sequential instruction detection is in progress.

[0061] In step 912, the control circuit uses the data stored in the identified buffer to at least process the incoming instruction when executing the storage device driver. In some embodiments, the data associated with the identified buffer has an instruction stream that matches the incoming instruction stream.

[0062] In step 914, the control circuit determines the next step of process 900 by detecting whether sequential detection is in progress when executing the storage device driver. In some embodiments, the control circuit, when executing the storage device driver, is configured to monitor a specific number of sequential instructions in the instruction stream before determining the buffer from which to prefetch data. If the control circuit determines that sequential detection is in progress when executing the storage device driver, then at 916, the control circuit processes incoming instructions as part of the sequential detection. In some embodiments, when the control circuit determines that sequential detection is not in progress when executing the storage device driver, then at 918, the control circuit determines the next step of process 900 by determining whether there is an available or reusable / expired buffer among a plurality of buffers.

[0063] In step 916, the control circuit processes incoming instructions as part of the sequential detection when executing the storage device driver. In some embodiments, the control circuit processes and uses the instructions when executing the storage device driver to determine a predicted instruction stream for software-based prefetching.

[0064] In step 918, the control circuit determines the next step of process 900 by determining whether there is an available or reusable / expired buffer among a plurality of buffers when executing the storage device driver. In some embodiments, one of the plurality of buffers may be empty or currently not storing any data associated with the instruction stream. In some embodiments, the corresponding valid bit in the valid bitmap may indicate that one of the plurality of buffers is expired. The data stored in the expired buffer may be cleared or deleted and used for other data associated with the new instruction stream. In some embodiments, when the control circuit determines that there is an available buffer or a reusable / expired buffer among the plurality of buffers when executing the storage device driver, at 920, the control circuit initializes the available or reusable / expired buffer to store data associated with the instruction stream. In some embodiments, when the control circuit determines that there is no available or reusable / expired buffer among the plurality of buffers when executing the storage device driver, then at 908, the control circuit disposes of the incoming instructions without software-based prefetching.

[0065] In step 920, the control circuit initializes the available or reusable / expired buffer to store data associated with the instruction stream when executing the storage device driver. In some embodiments, to initialize the expired buffer, the control circuit deletes or clears the stored expired data or overwrites the expired data with new data associated with the instruction stream.

[0066] Figure 10A flowchart according to some embodiments of the present disclosure is shown, which illustrates a process 1000 for performing an independent multi-plane read operation using snapshot reads caused by sequential read commands. In some embodiments, the referenced control circuit and memory may be implemented as control circuit 106 and memory 124. Performing process 1000 may improve the efficiency of accessing memory 124. In some embodiments, process 1000 may be modified by, for example, rearranging, changing, adding, and / or removing steps.

[0067] In step 1002, control circuit 106 receives a read command. In some embodiments, the read command may be from an external source outside the device.

[0068] In step 1004, control circuit 106 determines whether the read command is a sequential read command. If the read command is a sequential read command, then in step 1006, control circuit 106 determines whether control circuit 106 can request a cache read. If the read command is not a sequential read command, then control circuit 106 issues an independent multi-plane read operation (IMPRO) to memory 124 using snapshot reads.

[0069] In step 1006, control circuit 106 determines whether control circuit 106 can request a cache read. In some embodiments, there may be no available cache for control circuit 106. If there is no readable cache available for control circuit 106, then in step 1010, control circuit 106 issues an IMPRO to memory 124 using snapshot reads. If control circuit 106 can access the cache, then in step 1008, control circuit 106 issues a multi-plane sequential read to the memory.

[0070] In step 1008, control circuit 106 issues a multi-plane sequential read to memory 124. In some embodiments, the multi-plane sequential read is an independent multi-plane read operation (IMPRO) that accesses portions of at least two different planes of memory 124. Once the IMPRO is complete and control circuit 106 has accessed the requested data, at 1012, control circuit 106 responds to the received read command.

[0071] In step 1010, control circuit 106 issues an IMPRO to memory 124 using snapshot reads. Control circuit 106 is configured to perform an IMPRO using snapshot reads. This allows control circuit 106 to perform multi-plane snapshot reads to access at least two planes of memory 124. Snapshot reads are used to access 4K, 8K, or 16K of data from memory 124. In some embodiments, snapshot reads may be used to access any other suitable size of data from memory 124. Once the IMPRO using snapshot reads is complete and control circuit 106 has accessed the requested data, at 1012, control circuit 106 responds to the received read command.

[0072] In step 1012, control circuit 106 generates a response to the received read command using the data accessed from step 1008 or step 1010. The destination of the response is the same as the source of the received read command.

[0073] The terms "one embodiment", "an embodiment", "embodiments", "the embodiment", "the embodiments", "one or more embodiments", "some embodiments", and "an embodiment" mean "one or more (but not all) embodiments" unless otherwise expressly specified.

[0074] The terms "comprising", "including", "having", and variations thereof mean "including but not limited to" unless otherwise expressly specified.

[0075] A list of items enumerated does not mean that any or all of the items are mutually exclusive unless otherwise expressly specified.

[0076] The terms "a", "an", and "the" mean "one or more" unless otherwise expressly specified.

[0077] Devices that communicate with each other need not communicate with each other continuously unless otherwise expressly specified. Additionally, devices that communicate with each other may communicate directly or indirectly through one or more intermediaries.

[0078] A description of embodiments in which several components communicate with each other does not mean that all such components are required. Instead, various optional components are described to illustrate a wide variety of possible embodiments. Further, although process steps, method steps, algorithms, etc. may be described in sequential order, such processes, methods, and algorithms may be configured to work in an alternating order. In other words, any order or sequence of steps that may be described does not necessarily indicate a requirement to perform those steps in that order. The steps of the processes described herein may be performed in any practical order. Further, some steps may be performed simultaneously.

[0079] When a single device or article is described herein, it will be readily apparent that more than one device / article (whether or not they cooperate) may be used in place of the single device / article. Similarly, where more than one device or article is described herein (whether or not they cooperate), it will be readily apparent that a single device / article may be used in place of the more than one device or article, or that a different number of devices / articles may be used in place of the shown number of devices or procedures. The functionality and / or features of a device may alternatively be embodied by one or more other devices that are not explicitly described as having such functionality / features. Accordingly, other embodiments need not include the device itself.

[0080] At least certain operations that may have been illustrated in the various figures show specific events occurring in a specific order. In alternative embodiments, the specific operations may be performed in a different order, modified, or removed. Additionally, steps may be added to the foregoing logic and still conform to the described embodiments. Further, the operations described herein may occur sequentially, or the specific operations may be processed in parallel. Still further, the operations may be performed by a single processing unit or by distributed processing units.

[0081] The foregoing description of the various embodiments has been presented for purposes of illustration and description. It is not intended to be exhaustive or limited to the precise forms disclosed. Many modifications and variations are possible in light of the above teachings.

Claims

1. A method, comprising: Receiving, by a control circuit while executing a storage device driver, at least one instruction in an instruction stream of a storage device; Determining, by the control circuit while executing the storage device driver, that a hardware buffer of the storage device is storing less than two instructions; In response to determining that the hardware buffer of the storage device is storing less than two instructions: Accessing data associated with an address of a memory of the storage device, wherein the address is predicted based on an analysis of the instruction stream; and Storing the data in the buffer; And Executing at least the instructions in the instruction stream using at least the data stored in the buffer.

2. The method according to claim 1, the method further comprising: Receiving a sequential read command for reading data from a memory of the storage device, wherein: The memory of the storage device includes at least one floating-gate NAND-based memory device, and The at least one floating-gate NAND-based memory device includes at least two planes; and Performing a read operation based on the sequential read command without referring to a data cache, wherein the read operation includes a snapshot read across the at least two planes.

3. The method according to claim 1, wherein the hardware buffer of the storage device is storing exactly one instruction.

4. The method according to claim 1, wherein executing the instructions in the instruction stream by the control circuit while executing the storage device driver further comprises: Scheduling a prefetch command into the hardware buffer of the storage device.

5. The method according to claim 1, further comprising: Identifying, by the control circuit while executing the storage device driver, the instruction stream by detecting a specific number of sequential read instructions.

6. The method according to claim 5, further comprising: Configuring, by the control circuit while executing the storage device driver, a plurality of buffers, wherein each buffer in the plurality of buffers is assigned a corresponding instruction stream among a plurality of instruction streams received by the driver of the storage device; Identifying an expired buffer among the plurality of buffers; And Marking the identified expired stream as pending reuse.

7. The method according to claim 6, further comprising: Identifying a new stream; Determining that all buffers in the plurality of buffers have been assigned to instruction streams; And In response to identifying a new stream and determining that all buffers in the plurality of buffers have been assigned to instruction streams: Determining a buffer for reuse in the plurality of buffers.

8. The method according to claim 7, wherein determining a buffer for reuse in the plurality of buffers comprises: Determining the least recently used buffer for reuse in the plurality of buffers.

9. The method according to claim 7, wherein determining a buffer for reuse in the plurality of buffers comprises: Determining a buffer in the plurality of buffers associated with a data address closest to the current data address of the at least one instruction in the instruction stream.

10. The method according to claim 1, further comprising: Configuring, by the control circuit while executing the storage device driver, a plurality of buffers; Identifying a new stream; And Assigning one of the unassigned buffers in the plurality of buffers to the new stream.

11. The method according to claim 1, further comprising: Configuring, by a control circuit when executing a storage device driver, a plurality of buffers, wherein each buffer of the plurality of buffers is assigned a corresponding instruction stream among a plurality of instruction streams received by the storage device driver; Receiving a first read instruction as part of an instruction stream of a storage device; Identifying a buffer among the plurality of buffers associated with the instruction stream; And Accessing data associated with an address of a memory of the storage device, and Storing the data in the identified buffer among the plurality of buffers.

12. The method according to claim 11, further comprising: Determining that the identified buffer is full; In response to determining that the identified buffer is full: Stopping prefetching of the instruction stream; Receiving an instruction that hits the last storage location of the identified buffer as part of an instruction stream of a storage device; In response to receiving an instruction that hits the last storage location of the identified buffer as part of an instruction stream of a storage device: Resuming prefetching of additional data into the identified buffer.

13. The method according to claim 11, further comprising: Scheduling, by a control circuit when executing a storage device driver, an additional access to second data from a second address of a storage device, the additional access being predicted by analyzing the at least one instruction in the instruction stream.

14. The method according to claim 13, further comprising: Receiving, by a storage device driver, a second read instruction as part of an instruction stream of a storage device; And Implementing the second read instruction by returning a accessed value stored in the identified buffer among the plurality of buffers.

15. A system, comprising: A storage circuit; And A control circuit, which when executing a storage device driver of a storage device is configured to: Receive at least one instruction in an instruction stream of a storage device; Determine that a hardware buffer of the storage device is storing less than two instructions; In response to determining that the hardware buffer of the storage device is storing less than two instructions: Access data associated with an address of a memory of the storage device, wherein the address is predicted based on an analysis of the instruction stream, and Store the data in one buffer among a plurality of buffers; And Execute at least the instructions in the instruction stream using the data stored in the buffer.

16. The system according to claim 15, wherein the control circuit is further configured to: Receive a sequential read command for reading data from a memory of a storage device, wherein: The memory of the storage device includes at least one floating-gate NAND-based memory device, and The at least one floating-gate NAND-based memory device includes at least two planes; and Perform a read operation based on the sequential read command without referring to a data cache, wherein the read operation includes a snapshot read across the at least two planes.

17. The system according to claim 15, wherein the hardware buffer of the storage device is storing exactly one instruction.

18. The system according to claim 15, wherein in order to execute the instructions in the instruction stream, the control circuit is further configured to: Schedule prefetch commands into a hardware buffer of a storage device.

19. The system of claim 15, wherein the control circuit is further configured to: Identify an instruction stream by detecting a specific number of sequential read instructions.

20. The system of claim 19, wherein the control circuit is further configured to: Configure a plurality of buffers, wherein each of the plurality of buffers is assigned a corresponding instruction stream among a plurality of instruction streams received by a driver of the storage device; Identify an expired buffer among the plurality of buffers; And Mark the identified expired stream as pending reuse.

21. The system of claim 20, wherein the control circuit is further configured to: Identify a new stream; Determine that all of the plurality of buffers have been assigned to instruction streams; and In response to the identification of the new stream and the determination that all of the plurality of buffers have been assigned to instruction streams: Determine a buffer for reuse among the plurality of buffers.

22. The system of claim 21, wherein, in order to determine a buffer among the plurality of buffers, the control circuit is configured to: Determine the least recently used buffer for reuse among the plurality of buffers.

23. The system of claim 22, wherein the least recently used buffer among the plurality of buffers is a buffer storing the oldest data to be accessed by a storage device driver.

24. A non-transitory computer-readable medium having non-transitory computer-readable instructions for a storage device driver encoded thereon, the non-transitory computer-readable instructions, when executed by a control circuit, cause the control circuit, when executing instructions of the storage device driver of the storage device: Receive at least one instruction in an instruction stream of the storage device; Determine that a hardware buffer of the storage device is storing fewer than two instructions; In response to the determination that the hardware buffer of the storage device is storing fewer than two instructions: Access data associated with an address of a memory of the storage device, wherein the address is predicted based on an analysis of the instruction stream, and Cause the data to be stored in one of a plurality of buffers, and Execute at least instructions in the instruction stream using at least the data stored in the buffer.

25. The non-transitory computer-readable medium of claim 24, wherein the control circuit is further configured to: Receive a sequential read command for reading data from a memory of the storage device, wherein: The memory of the storage device includes at least one floating-gate NAND-based memory device, and The at least one floating-gate NAND-based memory device includes at least two planes; and Cause a read operation to be performed based on the sequential read command without referencing a data cache, wherein the read operation includes a snapshot read across the at least two planes.

26. The non-transitory computer-readable medium of claim 24, wherein the hardware buffer of the storage device is storing exactly one instruction.

27. The non-transitory computer-readable medium of claim 24, wherein, in order to execute instructions in the instruction stream, the control circuit is further configured to: Schedule a prefetch command into a hardware buffer of a storage device.

28. The non-transitory computer-readable medium according to claim 24, wherein the control circuit is further configured to: Identify an instruction stream by detecting a specific number of sequential read instructions.

29. The non-transitory computer-readable medium according to claim 28, wherein the control circuit is further configured to: Configure a plurality of buffers, wherein each buffer of the plurality of buffers is assigned a corresponding instruction stream among a plurality of instruction streams received by a driver of the storage device; Identify an expired buffer among the plurality of buffers; And Mark the identified expired stream as pending reuse.

30. The non-transitory computer-readable medium according to claim 29, wherein the control circuit is further configured to: Identify a new stream; Determine that all of the plurality of buffers have been assigned to instruction streams; and In response to the identified new stream and the determination that all of the plurality of buffers have been assigned to instruction streams: Determine a buffer for reuse among the plurality of buffers.

31. The non-transitory computer-readable medium according to claim 30, wherein, in order to determine a buffer among the plurality of buffers, the control circuit is configured to: Determine the least recently used buffer for reuse among the plurality of buffers.

32. The non-transitory computer-readable medium according to claim 31, wherein the least recently used buffer among the plurality of buffers is a buffer storing the oldest data to be accessed by a storage device driver.

33. The non-transitory computer-readable medium according to claim 30, wherein, in order to determine a buffer among the plurality of buffers, the control circuit is configured to: Determine a buffer among the plurality of buffers associated with a data address closest to a data address of an instruction in a closest instruction stream.

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