Highly textured buffer layer for YBiPt (110) growth for spintronic applications

Abstract

The present disclosure generally relates to spintronic material stacks and devices. Various disclosed embodiments of a spin orbit torque (SOT) stack based on YBiPt are useful for high temperature applications. Disclosed herein are various buffer and / or interlayer configurations in spin electron stacks that can facilitate growth of YBiPt in a (110) orientation to facilitate high spin Hall angle (SHA) in SOT applications. One embodiment is a spin electron stack comprising: a buffer layer comprising one or more layers, each of the one or more layers individually comprising: MgO (100), TiN (100), Ta, Nb, HfN, Ta3W2 (110), TaW2 (100), Ta3W2N, TaW2N, or heated YPt, and one or more of the one or more layers, each of the one or more layers individually comprising: MgO (100), TiN (100), Ta, Nb, HfN, Ta3W2 (110), TaW2 (100), Ta3W2N, TaW2N, or heated YPt; an SOT layer, the SOT layer comprising YBiPt in the (110) orientation; an interlayer including one or more of MgO, Ta3WN, TaW3N, Ta3W (110), TaW3 (100), YPt (110), NiFeGeN, NiAlN, NiAl, NiFeGe, NiAlGe, or HfN, and an outer layer including one or more of MgO, Ta3WN, TaW3N, Ta3W (110), TaW3 (100), YPt (110), NiFeGeN, NiAlN, NiAl, NiFeGe, NiAlGe, or HfN; and a ferromagnetic layer.

Description

[0001] Cross - reference to related applications

[0002] This application claims the benefit of U.S. Patent Application Serial No. 18 / 740,054, filed on June 11, 2024, which claims the benefit of U.S. Provisional Patent Application Serial No. 63 / 508,164, filed on June 14, 2023, which is incorporated herein by reference. Background Art Technical Field

[0003] Embodiments of the present disclosure generally relate to spintronic devices having a textured buffer layer for growing a topological semimetal material.

[0004] Description of Related Art

[0005] Spintronic devices have been used in various sensors, data storage devices, memories, and logic applications and have shown promise in recent years for supporting devices for artificial intelligence applications. In searching for effective spin - Hall - effect (SHE) materials for such devices, various materials have been tried, among which are various topological insulator materials having a high spin - Hall angle.

[0006] The YPtBi layer is a narrow - band - gap topological semimetal with a giant spin - Hall effect and high electrical conductivity. YPtBi is a material that has been proposed for various spin - orbit - torque (SOT) device applications, such as a spin - Hall layer for magnetic random - access memory (MRAM) devices, magnetic recording read heads, sensors, and energy - assisted magnetic recording (EAMR) magnetic recording heads. However, there may be several obstacles to utilizing the YPtBi material in commercial SOT applications. For example, the YPtBi material requires specific buffer layers and / or interlayers, as well as optimal processing conditions, to achieve the desired orientation.

[0007] Accordingly, there is a need for an improved SOT device that utilizes a TSM layer having a desired crystal orientation. Summary of the Invention

[0008] The present disclosure generally relates to spintronic material stacks and devices. Various disclosed embodiments of YBiPt - based spin - orbit - torque (SOT) stacks can be used for high - temperature applications. Various buffer and / or interlayer configurations in spintronic stacks are disclosed herein, which can facilitate the growth of YBiPt in the (110) orientation to promote a high spin - Hall angle (SHA) in SOT applications. One embodiment is a spintronic stack that includes a buffer layer that includes a textured layer that includes a bcc alloy that has a composition in the range of about to Lattice spacings within a range, including one or more materials selected from the group consisting of Ta, Nb, Hf, Mo, V, and W. The alloy options include: (1) forming a (110) or (100) texture such as Ta-rich Ta-W alloy Ta3W2(110); (2) W-rich TaW2(100); and (3) using these elements to have an fcc(100) texture nitride alloy with lattice spacings in the range of to such as Ta3W2N, TaW2N, or HfN. The buffer layer may also include one or more growth template layers of MgO(100), TiN(100), or RuAl(100), or on a thin layer of heated YPt. The spin electron stack further includes: a SOT layer including YBiPt oriented in (110), disposed above the buffer layer; an optional interlayer disposed above the SOT layer; a ferromagnetic layer disposed above the interlayer; and a capping layer disposed above the ferromagnetic layer.

[0009] In one embodiment, a spin electron stack includes: a buffer layer including a textured layer including Ta or Nb; a spin-orbit torque (SOT) layer including YBiPt oriented in (110), disposed above the buffer layer; an interlayer disposed above the SOT layer; and a ferromagnetic layer disposed above the interlayer.

[0010] In another embodiment, a spin electron stack includes: a buffer layer including a bcc alloy including HfN, Ta3W(110), TaW3(100), Ta3WN, TaW3N, MgO(100), TiN(100), or YPt; a spin-orbit torque (SOT) layer including YBiPt oriented in (110), disposed above the buffer layer; an interlayer disposed above the SOT layer; a ferromagnetic layer disposed above the interlayer; and a capping layer disposed above the ferromagnetic layer.

[0011] In yet another embodiment, a spintronic stack includes: at least one amorphous non-magnetic migration barrier layer including CoX, CoFeX, NiX, or NiFeX, where X is one of Ta, W, Hf, or Ge; a buffer layer disposed on the at least one amorphous non-magnetic migration barrier layer, the buffer layer including: (1) a texture template layer including MgO(100), TiN(100), RuAl(100), or YPt, disposed above the at least one amorphous non-magnetic migration barrier layer; and (2) two or more texture sub-layers disposed above the texture template layer, each of the two or more texture sub-layers individually including a material selected from the group consisting of bcc alloys of Ta, W, Nb, V, and Hf, and fcc alloy nitride compounds of Ta, W, Nb, V, and Hf; a spin-orbit torque (SOT) layer including YBiPt in a (110) orientation, disposed above the buffer layer; a sandwich layer disposed above the SOT layer, the sandwich layer including a first sub-layer and a second sub-layer, the first sub-layer including a material selected from the group consisting of Ta3WN, TaW3N, Ta3W(110), TaW3(100), YPt(110), NiFeGeN, NiAlN, NiAl, NiFeGe, NiAlGe, and HfN, and the second sub-layer being an oxide layer; a ferromagnetic layer disposed above the second sub-layer of the sandwich layer; and a capping layer disposed above the ferromagnetic layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Accordingly, by reference to the embodiments, a manner of obtaining a detailed understanding of the above features of the present disclosure, a more specific description of the present disclosure, and the above brief summary can be obtained. Some of these embodiments are illustrated in the drawings. It should be noted, however, that the drawings merely illustrate typical embodiments of the present disclosure and should not be considered as limiting its scope, as the present disclosure may permit other equally effective embodiments.

[0013] Figure 1 is a schematic diagram of certain embodiments of a magnetic media drive including a magnetic recording head having a spintronic device.

[0014] Figure 2 is a partial cross-sectional view of certain embodiments of a read / write head having a spintronic device.

[0015] Figures 3A to 3D is a schematic diagram of a spintronic material stack according to various embodiments.

[0016] Figure 4A is a schematic diagram of the lattice matching of YBiPt(110) with α-Ta(110).

[0017] Figure 4B Illustrates the out-of-plane XRD patterns of Ta3W(110) and TaW2(100) textured buffer layers in a (110)-textured TSM SOT stack according to one embodiment.

[0018] Figure 4C Illustrates the out-of-plane XRD patterns of various textured templates, buffer layers, interlayers, and capping layers of a (110)-textured TSM stack according to another embodiment.

[0019] Figure 5A Is a schematic cross-sectional view of an SOT device used in a MAMR magnetic recording head such as Figure 1 in a drive of or other suitable magnetic medium drive's MAMR magnetic recording head.

[0020] Figures 5B to 5C Is a schematic MFS view of certain embodiments of a portion of a MAMR magnetic recording head of an SOT device having Figure 5A

[0021] Figure 6 Is a schematic cross-sectional view of an SOT MTJ used as an MRAM device.

[0022] Figure 7 Illustrates a schematic diagram of a simplified deep neural network (DNN) or logic device according to one embodiment.

[0023] Figure 8 Illustrates a spin-orbit - spin-orbit (SO-SO) device according to one embodiment.

[0024] For ease of understanding, wherever possible, the same reference numerals are used to denote the same elements common to the drawings. It is contemplated that elements disclosed in one embodiment may be advantageously used in other embodiments without specific recitation. Detailed Description

[0025] In the following text, reference is made to embodiments of the present disclosure. However, it should be understood that the present disclosure is not limited to the specifically described embodiments. Instead, any combination of the following features and elements (whether or not associated with different embodiments) is contemplated to implement and practice the present disclosure. Additionally, although embodiments of the present disclosure may achieve advantages over other possible solutions and / or over the prior art, whether a given embodiment achieves a particular advantage is not a limitation of the present disclosure. Thus, the following aspects, features, embodiments, and advantages are merely illustrative and are not to be considered elements or limitations of the appended claims unless expressly recited in the claims. Similarly, references to "the present disclosure" should not be construed as a generalization of any inventive subject matter disclosed herein and should not be considered an element or limitation of the appended claims unless expressly recited in the claims.

[0026] The present disclosure generally relates to spintronic material stacks and devices. Various disclosed embodiments of YBiPt-based spin-orbit torque (SOT) stacks can be used for high-temperature applications (>300 °C - 600 °C), such as for magnetic sensors, logic designs, and memory cells (e.g., MRAM (magnetoresistive random access memory)). Such applications require the materials to withstand the high-temperature manufacturing and use environments. Various buffer and interlayer configurations in spintronic stacks are disclosed herein, which can facilitate the growth of YBiPt with a (110) orientation to promote a high spin Hall angle (SHA) in SOT applications.

[0027] In one embodiment, a spintronic stack is disclosed that includes: a buffer layer including a texture layer including Ta, Nb, HfN, Ta3W(110), TaW3(100), or YPt(110); a spin-orbit torque (SOT) layer including YBiPt with a (110) orientation disposed over the buffer layer; an interlayer disposed over the SOT layer; and a ferromagnetic layer disposed over the interlayer.

[0028] Figure 1 FIG. 100 is a schematic illustration of certain embodiments of a magnetic media drive 100 including a magnetic recording head having an SOT MTJ device. Such magnetic media drives can be a single drive or include multiple drives. For illustration, a single disk drive 100 is shown in accordance with certain embodiments. As shown, at least one rotatable disk 112 is supported on a spindle 114 and rotated by a drive motor 118. The magnetic recording on each disk 112 is in the form of any suitable pattern of data tracks, such as a concentric data track (not shown) annular pattern on the disk 112.

[0029] At least one slider 113 is positioned near the disk 112, and each slider 113 supports one or more head assemblies 121 including SOT devices. As the disk 112 rotates, the slider 113 moves radially in and out above the disk surface 122 so that the head assembly 121 can access different tracks of the disk 112 for writing desired data. Each slider 113 is attached to the actuator arm 119 by a suspension 115. The suspension 115 provides a slight spring force that biases the slider 113 toward the disk surface 122. Each actuator arm 119 is attached to an actuator member 127. As Figure 2 shown, the actuator member 127 can be a voice coil motor (VCM). The VCM includes a coil that can move within a fixed magnetic field, and the direction and speed of the coil movement are controlled by a motor current signal supplied by the control unit 129.

[0030] During operation of the disk drive 100, the rotation of the disk 112 generates an air bearing between the slider 113 and the disk surface 122, and the air bearing exerts an upward force or lift on the slider 113. Thus, during normal operation, the air bearing counteracts the slight spring force of the suspension 115 and supports the slider 113 at a small, substantially constant spacing away from and slightly above the disk surface 122.

[0031] The various components of the disk drive 100 are operated by control signals (such as access control signals and internal clock signals) generated by the control unit 129. The control unit 129 generally includes a logic control circuit, a storage component, and a microprocessor. The control unit 129 generates control signals for controlling various system operations, such as a drive motor control signal on line 123 and a head position and seek control signal on line 128. The control signal on line 128 provides a desired current distribution to optimally move and position the slider 113 to a desired data track on the disk 112. Write signals and read signals are communicated to and from the write head and read head on the component 121 through the recording channel 125.

[0032] The above description of a typical magnetic medium drive and Figure 1 the accompanying drawings are for illustrative purposes only. It should be apparent that a magnetic medium drive can include a large number of media or disks and actuators, and each actuator can support multiple sliders.

[0033] Figure 2 is a partial cross-sectional side view of certain embodiments of a read / write head 200 having SOT devices. The read / write head 200 faces the magnetic medium 112. The read / write head 200 can correspond to Figure 1The head assembly 121 described in Figure 2 As shown, the magnetic medium 112 moves past the write head 210 in the direction shown by arrow 232, and the read / write head 200 moves in the direction indicated by arrow 234.

[0034] In some embodiments, the magnetic read head 211 is a magnetoresistive (MR) read head having an MR sensing element 204 located between MR shields S1 and S2. In other embodiments, the magnetic read head 211 is an MTJ read head including a magnetic tunnel junction (MTJ) sensing device 204 disposed between MR shields S1 and S2. The magnetic fields of adjacent magnetized regions in the disk 112 can be detected as recorded bits by the MR (or MTJ) sensing element 204. SOT devices of various embodiments can be incorporated into the read head 211 as sensing elements. Examples of SOT read heads are described in the co-pending U.S. patent application Ser. No. 17 / 828,226, filed May 31, 2022, entitled "Topological Insulator Based Spin Torque Oscillator Reader", assigned to the same assignee as this application, which is incorporated herein by reference. Another example of an SOT read head is described in the co-pending U.S. patent application Ser. No. 18 / 367,877, filed Sep. 13, 2023, entitled "Non-Localized Spin Valve Reader Hybridized With Spin Orbit Torque Layer", and the co-pending U.S. patent application Ser. No. 18 / 367,882, filed Sep. 13, 2023, entitled "Non-Localized Spin Valve Multi-Free-Layer Reader Hybridized With Spin Orbit Torque Layers", which are incorporated herein by reference.

[0035] The write head 210 includes a center pole or main pole 220, a front shield 206, a tail shield 240, an optional spin orbit torque (SOT) device 250, and a coil 218 that excites the main pole 220. The coil 218 can have a "pancake" structure rather than Figure 2The "spiral" structure shown, where the "pancake-shaped" structure is wound around the back contact portion between the main pole 220 and the tail shield 240. For example, when included to achieve, e.g., a microwave-assisted magnetic recording (MAMR) effect, the SOT device 250 is formed in the gap 254 between the main pole 220 and the tail shield 240. In some embodiments, the read / write head 200 further includes means (not shown) for supporting heat-assisted magnetic recording (HAMR), which may include a waveguide coupled to a light source and a near-field transducer (NFT) placed adjacent to the main pole 220 and coupled to the waveguide to convert the transmitted light into a heating spot on the medium.

[0036] The main pole 220 includes a tail cone 242 and a front cone 244. The tail cone 242 extends from a position recessed in the MFS 212 to the MFS 212. The front cone 244 extends from a position recessed in the MFS 212 to the MFS 212. The tail cone 242 and the front cone 244 may have the same taper, and the taper is measured with respect to the longitudinal axis 260 of the main pole 220. In some embodiments, the main pole 220 does not include the tail cone 242 and the front cone 244. Instead, the main pole 220 includes a tail side (not shown) and a front side (not shown), and the tail side and the front side are substantially parallel. The main pole 220 may be a magnetic material, such as a FeCo alloy. The front shield 206 and the tail shield 240 may include a magnetic material (such as a NiFe alloy).

[0037] Figures 3A to 3D Spin-electronic stacks 300a - 300d according to various embodiments are illustrated. Each spin-electronic stack 300a - 300d can be used for Figure 1 the magnetic medium drive 100, Figure 2 the reader and / or writer portion of the head 200, or other suitable magnetic medium drives. Each spin-electronic stack 300a - 300d can be used as a memory cell element in MRAM or as a logic unit, e.g., as disclosed in Figures 6 to 7 . Aspects of the spin-electronic stacks 300a - 300d can be used in combination with each other.

[0038] Figure 3ASchematic diagram of a spintronic stack 300a according to one embodiment. The spintronic stack 300a includes an amorphous layer 302a, a buffer layer 302b, a SOT layer 304 disposed above the buffer layer 302b, an optional interlayer 306 disposed above the SOT layer 304, a ferromagnetic (FM) layer 308 disposed above the interlayer 306, and a capping layer 310 disposed above the FM layer 308. Although the FM layer 308 is shown above the SOT layer 304, in some embodiments, the SOT layer 304 may be above the FM layer 308. In such embodiments, the positions of the SOT layer 304 and the FM layer 308 are exchanged.

[0039] Stack 300a includes an amorphous layer 302a, which includes NiTa, NiW, NiFeTa, NiFeW, CoFeTa, or NiFeGe, which may have high-resistance properties. In some embodiments, the amorphous layer 302a may be doped with nitrogen. This layer may be disposed on other seed layers or substrate layers.

[0040] The buffer layer 302b includes multiple layers, such as three sub-layers. In one embodiment, the first buffer sub-layer 302b-1 and the second sub-buffer layer 302b-2 each independently include Ta3W(110), TaW3(100), Ta3WN, TaW3N, Ta3W2(110), TaW2(100), Ta3W2N, TaW2N, MgO(100), TiN(100), or YPt(110), each of which provides a (110) texture for the third sub-buffer layer 302b-3 and the SOT layer 304. The first buffer sub-layer 302b-1 may have a thickness of about to about and the second buffer sub-layer 302b-2 may have a thickness of about to about . In such embodiments, the third sub-buffer layer 302b-3 includes HfN, Ta3W(110), TaW3(100), Ta3WN, TaW3N, or YPt(110). The third sub-layer 302b-3 may include HfN, Ta3WN, or TiN, which has a high resistivity. The third buffer sub-layer 302b-3 has a thickness of about to about .

[0041] Each of the first sub-buffer layer 302b-1, the second sub-buffer layer 302b-2, and the third sub-buffer layer 302b-3 includes a different material. For example, the first sub-buffer layer 302b-1 may include MgO or TiN, the second sub-buffer layer 302b-2 may include Ta3W or Ta3WN, and the third sub-buffer layer 302b-3 may include HfN or TiN. As another example, the first sub-buffer layer 302b-1 may include YPt, TaW3, or TaW3N, the second sub-buffer layer 302b-2 may include Ta3W, Ta3WN, or HfN, and the third sub-buffer layer 302b-3 may include HfN, TiN, Ta3W, or Ta3WN.

[0042] In one embodiment, an interlayer 306 including Ta (e.g., α-Ta) or Nb (a material similar to or the same as the buffer sub-layer 302b-3) is disposed on the SOT layer 304. In another embodiment, the interlayer 306 includes Ta3W(110), TaW3(100), YPt(110), NiFeGeN, NiAlN, NiAl, NiFeGe, or HfN, which are high resistivity materials that provide a shunt barrier for the FM layer 308. In some embodiments, the interlayer 306 may further include MgO, such as NiFeGe / MgO, NiFeGeN / MgO, Ta3WN / MgO, or HfN / MgO. The interlayer 306 may be a multi-layer structure, as described below in Figures 3C to 3D The interlayer 306 inherits the (110) orientation from the underlying layer.

[0043] The FM layer 308 disposed on the interlayer 306 includes Co, CoFeB, NiFe, CoFe, CoFeN, CoFeHf, or other suitable ferromagnetic materials or alloys. Finally, the capping layer 310 may be a plurality of layers disposed on the FM layer 308, including: (1) a material selected from the group consisting of high-resistance amorphous SiN, Al2O3, SiO2, NiFeTa, NiTa, NiW, NiFeW, NiFeGe, HfN, and NiFeGeN, or (2) a high-resistance crystalline ceramic material, such as a TiO layer, an MgO layer, an MgTiO layer, or (3) a lower-resistance transition heavy metal, such as Pt, Co, Cu, Ni, Ru, Ta, Cr, Au, and Rh and their alloys (when used in combination with a higher-resistance capping layer), or (4) other non-magnetic materials, or a combination thereof. The SOT layer 304 includes a topological semimetal (TSM), such as YBiPt(110).

[0044] Figure 3BSchematic diagram of a spintronic stack 300b according to one embodiment. The spintronic stack 300b is similar to the stack 300a, except that the buffer layer includes different sublayers 302b-2 and materials. The amorphous layer 302a is typically an amorphous or nanocrystalline migration inhibition layer. The first sublayer 302b-1 is a texture template layer including a B2 alloy of RuAl, heated YPt, fcc MgO, or TiN. The second sublayer 302b-2a is typically a bcc alloy including elements selected from the group consisting of Ta, Hf, W, Nb, V, and Zr, or a bcc nitride alloy forming an fcc compound, such as HfN or TaWN. The sublayers 302b-3, 302-2b, and 302b-2a have similar materials including a bcc alloy or a bcc nitride alloy, thereby forming an fcc phase with a larger lattice parameter. The order of these layers is selected to reduce strain while increasing the layer resistance, or to improve the migration in and out of the TSM SOT layer 304. Together they form a strain reducing layer that can easily force the (110) orientation growth as described above, thereby achieving the purpose of growing a highly textured (110) YBiPt Heusler film.

[0045] Figure 3C Schematic diagram of a spintronic stack 300c according to one embodiment. The spintronic stack 300c is similar to Figure 3A the stack 300a; however, the buffer layer 302b includes two sublayers 302b-1 and 302b-2, and the interlayer 306 is a multilayer structure. The first sublayer 302b-1 of the buffer layer 302b may include Ta3W(110), TaW3(100), Ta3W2N, TaW3N, MgO(100), TiN(100), or YPt(110), each of which provides a (110) texture for the second sub-buffer layer 302b-2 and the SOT layer 304. The second buffer sublayer 302b-2 includes HfN, Ta3W(110), Ta3WN, TaW3(100), TaW3N, or YPt(110). In one embodiment, the second buffer sublayer 302b-2 includes HfN having a high resistivity. The first buffer sublayer 302b-1 may have a thickness of about to about , and the second buffer sublayer 302b-2 may have a thickness of about to about .

[0046] Each of the first sub-buffer layer 302b-1 and the second sub-buffer layer 302b-2 includes a different material. For example, the first sub-buffer layer 302b-1 may include MgO or TiN, and the second sub-buffer layer 302b-2 may include Ta3W or TaW3. As another example, the first sub-buffer layer 302b-1 may include YPt, TaW3, or TaW3N, and the second sub-buffer layer 302b-2 may include Ta3W, Ta3WN, or HfN.

[0047] The interlayer 306 includes two sub-interlayers 306a and 306b. In some embodiments, the first sub-layer 306a is a metal protection layer, and the second sub-layer 306b is an oxide layer. The first sub-interlayer 306a may include HfN, Ta3W(110), TaW3(100), or YPt(110). The second sub-interlayer 306b may include MgO, TiO, MgTiO, HfN, Ta3W(110), TaW3(100), or YPt(110). The first sub-interlayer 3026a may have about to about (such as about ) in thickness, and the second sub-interlayer 306b may have about to about (such as about ) in thickness.

[0048] Each of the first sub-interlayer 306a and the second sub-interlayer 306b includes Ta3W(110), TaW3(100), Ta3W2N, TaW2N, YPt(110), NiFeGeN, NiAlN, NiAl, NiFeGe, or HfN. In some embodiments, the first sub-interlayer 306a and the second sub-interlayer 306b may also include MgO, such as NiFeGe / MgO, NiFeGeN / MgO, Ta3WN / MgO, or HfN / MgO. For example, the first sub-interlayer 306a may include Ta3W(110), TaW3(100), YPt(110), NiFeGeN, NiAlN, NiAl, NiFeGe, or HfN, and the second sub-interlayer 306b may include Ta3W or TaW3.

[0049] Figure 3D is a schematic diagram of a spintronic stack 300d according to one embodiment. The spintronic stack 300d is similar to Figure 3C the stack 300c; however, the buffer layer 302b is a single layer, and the interlayer 306 is a multi-layer structure. The buffer layer 302b may include HfN, Ta3W(110), TaW3(100), Ta3W2N, TaW2N, or YPt(110). The buffer layer 302b may have about to about The thickness. The first sub-interlayer 306a of the interlayer 306 may include HfN, Ta3W(110), TaW3(100), or YPt(110). The second sub-interlayer 306b may include MgO, HfN, Ta3W(110), TaW3(100), or YPt(110). The first sub-interlayer 306a may have a thickness of about to about , and the second sub-interlayer 306b may have a thickness of about to about .

[0050] Each of the first sub-interlayer 306a and the second sub-interlayer 306b includes different materials. In some embodiments, the first sub-layer 306a is a metal protection layer, and the second sub-layer 306b is an oxide layer. For example, the first sub-interlayer 306a may include HfN, Ta3W, or TaW3, and the second sub-interlayer 306b may include YPt, MgO, TiO, or MgTiO.

[0051] Figure 4A is a schematic diagram 400 of the lattice matching of YBiPt(110) with α-Ta(110) (the highly textured sub-layer of the above buffer layer). The molecules of YbiPt shown are labeled as Y(202), Bi(204), and Pt(206). YBiPt(110) has a surface, and the half-size of this (110) surface is Therefore, α-Ta(110) having a size (as shown in the illustration 408) provides an excellent lattice matching film. Table 410 shows the sizes of the above other materials that can be used in various buffer and / or interlayer embodiments.

[0052] Figure 4B Illustrates the out-of-plane XRD patterns of the Ta3W(110) and TaW2(100) textured buffer layers in a (110) textured TSM SOT stack according to one embodiment. As shown, the buffer layer including Ta3W can provide a (110) texture to the SOT layer (such as the Figures 3A to 3D SOT layer 304). The buffer layer including TaW2 can provide a (100) texture to the SOT layer 304.

[0053] Figure 4C Illustrates the out-of-plane XRD patterns of various texture templates, buffer layers, interlayers, and capping layers of a (110) textured TSM stack according to another embodiment. Line 402 represents including a thick MgO layer, thick TaW2 layer, thick YPtBi layer, thick CoFe layer and Stacking of thick NiFeGe layers. Line 404 represents a stack including a thick CoFeTaN layer, a thick YPt layer, a thick HfN layer, a thick Ta3W2 layer, a thick YPtBi layer, a thick CoFeB layer, a thick NiFeGe layer and a thick HfN layer. Line 406 represents a stack including a thick YPt layer, an HfN layer, a thick Ta3W2 layer, a thick YPtBi layer, a thick CoFe layer, a thick NiFeGe layer and a thick HfN layer. Line 408 represents a stack including a thick CoFeTaN layer, a thick MgO layer, a thick Ta3W2 layer, a thick YPtBi layer, a thick CoFeB layer, a thick NiAlGeN layer, a thick NiFeGe layer and a thick HfN layer. Line 410 represents a stack including a thick CoFeTaN layer, a thick YPt layer, a thick Ta3W2N layer, a thick YPtBi layer, a thick CoFeB layer, a thick NiFeGe layer and a thick HfN layer.

[0054] Note that while Figures 3A to 3D an example stack of a single pair of SOT layer and FM layer is provided, in various sensor, memory, and logic applications, other such embodiments may include stacks containing different numbers of SOT layers and FM layers, and the buffer layers and interlayers used above to facilitate the growth properties discussed may be used accordingly to support those different embodiments.

[0055] Figure 5A is a schematic cross-sectional view of an SOT device 500 used in a MAMR magnetic recording head such as Figure 1 in a drive 100 or other suitable magnetic medium drive's MAMR magnetic recording head. The SOT device 500 includes an SOT layer 304 orientation formed above a buffer layer 302b formed above a substrate 501, such asFigures 3A to 3D The SOT layer 304 and the buffer layer 302b. Thus, the SOT layer 304 may include YPtBi having a (110) orientation. A spin torque layer (STL) 570 is formed above the SOT layer 304. The STL 570 includes ferromagnetic materials, such as one or more layers of CoFe, CoIr, NiFe, and CoFeX alloys, where X = B, Ta, Re, or Ir.

[0056] In certain embodiments, a current shunting barrier layer 560 is disposed between the SOT layer 304 and the STL 570. The current shunting barrier layer 560 reduces the current flowing from the SOT layer 304 to the STL 570, but allows spin-orbit coupling between the SOT layer 304 and the STL 570. In certain embodiments, the current shunting barrier layer 560 includes a magnetic material that provides greater spin-orbit coupling between the SOT layer 304 and the STL 570 compared to a non-magnetic material. In certain embodiments, the current shunting barrier layer 560 includes a magnetic material of FeCo, FeCoM, FeCoMO, FeCoMMeO, FeCoM / MeO stack, FeCoMNiMnMgZnFeO, FeCoM / NiMnMgZnFeO stack, multiple layers / stacks thereof, or a combination thereof, where M is one or more of B, Si, P, Al, Hf, Zr, Nb, Ti, Ta, Mo, Mg, Y, Cu, Cr, and Ni. Me is one or more of Si, Al, Hf, Zr, Nb, Ti, Ta, Mg, Y, or Cr. In certain embodiments, the current shunting barrier layer 560 is formed to be about to about in thickness. In certain aspects, a current shunting barrier layer 560 having a thickness greater than can reduce the spin-orbit coupling between the SOT layer 304 and the STL 570. In certain aspects, a current shunting barrier layer having a thickness less than may not sufficiently reduce the current from the SOT layer 304 to the STL 570.

[0057] In certain embodiments, additional layers, such as a spacer layer 580 and a pinning layer 590, are formed above the STL 570. The pinning layer 590 may partially pin the STL 570. The pinning layer 590 may include a single layer or multiple layers of PtMn, NiMn, IrMn, IrMnCr, CrMnPt, FeMn, other antiferromagnetic materials, or a combination thereof. The spacer layer 580 includes a single layer or multiple layers of magnesium oxide, aluminum oxide, other non-magnetic materials, or a combination thereof.

[0058] Figures 5B to 5C is with Figure 5ASchematic MFS view of some embodiments of a portion of the MAMR magnetic recording head 210 of the SOT device 500. The MAMR magnetic recording head 210 can be Figure 2 a magnetic recording head of Figure 1 the drive 100 or other suitable magnetic recording heads in other suitable magnetic medium drives such as tape drives. The MAMR magnetic recording head 210 includes a main pole 220 and a trailing shield 240 along the track direction. The SOT device 500 is disposed in the gap between the main pole and the trailing shield 240.

[0059] During operation, a spin current is generated in the YPtBi layer by a charge current through the SOT layer 304 that acts as a spin Hall layer. The spin-orbit coupling of the YPtBi layer and the spin torque layer (STL) 570 causes switching or precession of the magnetization of the STL 570 through the spin-orbit coupling of the spin current from the SOT layer 304. The switching or precession of the magnetization of the STL 570 can generate an auxiliary alternating field for the write field. Compared with a spin-transfer torque-based MAMR magnetic recording head, the SOT-based energy-assisted magnetic recording head has several times the power efficiency. As Figure 5B shown, due to the shape anisotropy of the STL 570, due to Figure 5A the pinned layer 590 and / or due to the hard bias element close to the STL 570, the easy axis of magnetization direction of the STL 570 is perpendicular to the MFS. As Figure 5C shown, due to the shape anisotropy of the STL 570, due to Figure 5A the pinned layer 590 and / or due to the complex bias element close to the STL 570, the easy axis of magnetization direction of the STL 570 is parallel to the MFS.

[0060] Figure 6 is a schematic cross-sectional view of the SOT MTJ 601 used as the MRAM device 600. The MRAM device 600 includes a reference layer (RL) 610, a spacer layer 620 above the RL 610, a recording layer 630 above the spacer layer 620, a buffer layer 302b above the current shunt blocking layer 640 above the recording layer 630, and an SOT layer 304 above the buffer layer 302b. The SOT layer 304 and the buffer layer 302b can be Figures 3A to 3D the SOT layer 304 and the buffer layer 302b of

[0061] The RL 610 includes a single layer or multiple layers of CoFe, other ferromagnetic materials, and combinations thereof. The spacer layer 620 includes a single layer or multiple layers of magnesium oxide, aluminum oxide, other dielectric materials, or combinations thereof. The recording layer 630 includes a single layer or multiple layers of CoFe, NiFe, other ferromagnetic materials, or combinations thereof.

[0062] As described above, in certain embodiments, a current shunting barrier layer 640 is disposed between the buffer layer 302b and the recording layer 630. The current shunting barrier layer 640 reduces the current flowing from the SOT layer 304 to the recording layer 630. The current shunting barrier layer 640 still allows spin-orbit coupling between the SOT layer 304 and the recording layer 630. For example, writing to the MRAM device can be achieved through spin-orbit coupling of the TSM layer and the recording layer 630, which allows switching of the magnetization of the recording layer 630 through spin-orbit coupling of the spin current from the SOT layer 304. In certain embodiments, the current shunting barrier layer 640 includes a magnetic material that provides greater spin-orbit coupling between the SOT layer 304 and the recording layer 630 compared to non-magnetic materials. In certain embodiments, the current shunting barrier layer 640 includes a magnetic material of FeCoM, FeCoMO, FeCoMMeO, FeCoM / MeO stack, FeCoMNiMnMgZnFeO, FeCoM / NiMnMgZnFeO stack, multiple layers / stacks thereof, or a combination thereof, where M is one or more of B, Si, P, Al, Hf, Zr, Nb, Ti, Ta, Mo, Mg, Y, Cu, Cr, and Ni; and Me is Si, Al, Hf, Zr, Nb, Ti, Ta, Mg, Y, or Cr.

[0063] Figure 6 The MRAM device 600 may include other layers, such as a pinned layer, a pinning structure (e.g., a synthetic antiferromagnetic (SAF) pinning structure), electrodes, gates, and other structures. The SOT layer 304 above the buffer layer 302b can be utilized to form other MRAM devices in addition to Figure 6 the structures to form the SOT MTJ 601.

[0064] Figure 7 FIG. illustrates a schematic diagram of a simplified deep neural network (DNN) or logic unit 700 according to one embodiment. The DNN 700 includes a plurality of units or neural nodes 702a, 702b, 702c, 702d, 702e (collectively referred to herein as neural nodes 702). Each neural node 702 includes a plurality of spin-orbit-spin-orbit (SO-SO) units, where each SO-SO unit is a three-terminal device including a control or weight, an input, and an output. Each SO-SO unit may include Figures 3A to 3D one or more of the spintronic stacks 300a-300d of

[0065] Then, the output of each neural node 702a in the input layer is output as an input to each neural node 702b in the first hidden layer (h1) of the DNN 700, where each input received at each neural node 702b is then multiplied by a corresponding weight for the corresponding input to each neural node 702b. The weights can conceptually represent the strength of the connection between a neural node (e.g., neural node 702a) in one layer and another neural node (e.g., neural node 702b) in the next layer. The results of the multiplications are added together and fed to a non-linear activation function (not shown here), such as a step function or a rectified linear unit (ReLU) function, which determines the final output of that neural node 702b. Then, this sequence of multiplication, summation, and activation function processes is repeated in the various layers h2, h3, etc. of the entire DNN. Although three hidden layers are shown, the DNN 700 can include any number of hidden layers. Finally, the output of the last hidden layer (here, the third hidden layer) is output as a final result to the output neural node 702e of the output layer (o).

[0066] Figure 8 An example of a spin-orbit - spin-orbit (SO-SO) device 800 according to one embodiment is illustrated. The SO-SO device 800 can be utilized within Figure 7 the DNN 700, such as an SO-SO cell. The various layers of the SO-SO device 800 are not drawn to scale and are only intended for illustrative purposes. The SO-SO device may be referred to herein as an SOT device. A plurality of SO-SO devices 800 can be configured to be used as Figure 7 the neural node 102. Thus, a collection of SO-SO devices can be configured to represent Figure 7 the layers (i, h1, h2, h3, o) of the DNN.

[0067] In some embodiments, the SO-SO device 800 includes a seed layer 802, a first spin-orbit torque (SOT) layer 304-1 (SOT1) disposed on the seed layer 802, a first sandwich layer 306-1 disposed on the first SOT layer 304-1, a ferromagnetic (FM) layer 308 disposed on the first sandwich layer 306-1, an oxide layer 810 (e.g., MgO layer) disposed on the FM layer 308, a second sandwich layer 306-2 disposed on the oxide layer 810, a second SOT layer 304-2 (SOT2) disposed on the second sandwich layer 306-2, a buffer layer 302b disposed on the second SOT layer 304-2, and a capping layer 818 disposed on the buffer layer 302b. The oxide layer 810 may include other materials, such as oxides of Ti, V, Cr, Mn, Fe, Ni, Zr, nitrides of Sc, Ti, V, Cr, Fe, Zr, Ta, Hf, W, carbides of Sc, Ti, V, Zr, Ta, Hf, W, and alloy combinations thereof.

[0068] The first sandwich layer 306-1 and the second sandwich layer 306-2 may each independently be Figures 3A to 3D the sandwich layer 306. The buffer layer 302 may be Figures 3A to 3D any buffer layer 302b. The SOT1 304-1 and the SOT2 304-2 may each independently be Figures 3A to 3D the SOT layer 304. The FM layer 308 may be Figures 3A to 3D the FM layer 308.

[0069] In some embodiments, the SO-SO device 800 includes three terminals or interconnects. The first SOT layer 304-1 is coupled to the interconnect or terminal 1. The second SOT layer 304-2 is coupled to the interconnect or terminal 3, where the interconnect or terminal 3 is coupled to the first SOT layer 304-1 of the second SO-SO device via the terminal 1. An input current is applied to the terminal 2 (representing the input X n current to the neural node), and it flows out-of-plane (current perpendicular to the plane (CPP)) through the entire stack towards the seed layer 802. According to some embodiments, the arrows associated with the terminals indicate the direction of current flow. The interconnects or terminals serve as connection points for joining two or more SO-SO devices. Thus, multiple SO-SO devices 800-800 may be arranged to build various circuits.

[0070] By using the above materials for the buffer layer and / or sub-buffer layer, the SOT layer can grow in the (110) orientation while maintaining a high resistivity. Additionally, by using the above materials for the sandwich layer and / or sub-sandwich layer, the sandwich layer has a high resistivity and can be used as a shunt blocking layer.

[0071] In one embodiment, a spintronic stack includes: a buffer layer including a textured layer including Ta or Nb; a spin-orbit torque (SOT) layer including YBiPt oriented in (110), disposed above the buffer layer; an interlayer disposed above the SOT layer; and a ferromagnetic layer disposed above the interlayer.

[0072] The buffer layer further includes: a first sublayer including Ta; a second sublayer disposed above the first sublayer and including Cr; and a third sublayer, i.e., the textured layer, disposed above the second sublayer and including Ta or Nb. The Ta in the first sublayer is β-Ta, and the Ta in the third sublayer is α-Ta. The β-Ta of the third sublayer is thicker than the α-Ta of the first sublayer. The buffer layer further includes: a first sublayer including Ta; a second sublayer disposed above the first sublayer and including Cr, V, Mo, or an alloy thereof; a third sublayer disposed above the second sublayer and including Mo, W, WTi, or an alloy thereof; and a fourth sublayer, i.e., the textured layer, disposed above the third sublayer and including Ta or Nb. The Ta in the first sublayer is β-Ta, and the Ta in the fourth sublayer is α-Ta. The β-Ta of the fourth sublayer is thicker than the α-Ta of the first sublayer. The spintronic stack further includes an amorphous layer including CoX, CoFeX, NiX, or NiFeX, where X is one or more of Ta, W, Hf, and Ge, where the amorphous layer is nitrided, and where the buffer layer is disposed above the amorphous layer. The interlayer includes Ta or Nb. A memory cell includes the spintronic stack. A logic unit includes the spintronic stack. A magnetic sensor includes the spintronic stack.

[0073] In another embodiment, a spintronic stack includes: a buffer layer including Ta3W(110), TaW3(100), Ta3WN, TaW3N, MgO(100), TiN(100), or YPt; a spin-orbit torque (SOT) layer including YBiPt oriented in (110), disposed above the buffer layer; an interlayer disposed above the SOT layer; and a ferromagnetic layer disposed above the interlayer.

[0074] The buffer layer is a multi-layer stack. The buffer layer further includes: a first sub-layer including Ta3W(110), TaW3(100), or YPt(110); and a second sub-layer including HfN, Ta3W(110), TaW3(100), or YPt(110). The second sub-layer includes HfN, and the first sub-layer and the second sub-layer include different materials. The buffer layer further includes a third sub-layer disposed between the first sub-layer and the second sub-layer, the third sub-layer including Ta3WN(110), TaW3N(100), TiN, or YPt(110). The interlayer includes one or more materials selected from the group consisting of: HfN, Ta3W(110), TaW3(100), NiFeGe, NiAlGe, or YPt(110), MgO, TiN, TiO, MgTiO, or MgTiN. The memory cell includes a spintronic stack. The logic unit includes a spintronic stack. The magnetic sensor includes a spintronic stack.

[0075] In yet another embodiment, a spintronic stack includes: at least one amorphous non-magnetic migration barrier layer including CoX, CoFeX, NiX, or NiFeX, where X is one of Ta, W, Hf, or Ge; a buffer layer disposed on the at least one amorphous non-magnetic migration barrier layer, the buffer layer including: (1) a texture template layer including MgO(100), TiN(100), RuAl(100), or YPt, disposed above the at least one amorphous non-magnetic migration barrier layer; and (2) two or more texture sub-layers disposed above the texture template layer, the two or more texture sub-layers each individually including a bcc alloy selected from the group consisting of Ta, W, Nb, V, and Hf, or an fcc alloy nitride compound of Ta, W, Nb, V, and Hf; a spin-orbit torque (SOT) layer including YBiPt in a (110) orientation, disposed above the buffer layer; an interlayer disposed above the SOT layer, the interlayer including a first sub-layer and a second sub-layer, the first sub-layer including a material selected from the group consisting of Ta3WN, TaW3N, Ta3W(110), TaW3(100), YPt(110), NiFeGeN, NiAlN, NiAl, NiFeGe, NiAlGe, and HfN, and the second sub-layer being an oxide layer; a ferromagnetic layer disposed above the second sub-layer of the interlayer; and a capping layer disposed above the ferromagnetic layer.

[0076] The first sub-layer of the two or more textured sub-layers comprises Ta3W(110), TaW3(100), or YPt(110), and wherein the second sub-layer of the two or more textured sub-layers comprises HfN, Ta3W(110), TaW3(100), or YPt(110). The buffer layer further comprises a third sub-layer disposed between the first sub-layer and the second sub-layer, the third sub-layer comprising Ta3WN(110), TaW3N(100), TiN, or YPt(110), and wherein the third sub-layer comprises a material different from the first sub-layer and the second sub-layer. The sandwich layer comprises two or more sub-sandwich layers. The first sub-sandwich layer comprises HfN, Ta3W(110), TaW3(100), or YPt(110), and the second sub-sandwich layer comprises MgO, HfN, Ta3W(110), TaW3(100), or YPt(110). The sandwich layer further comprises a third sub-sandwich layer, the third sub-sandwich layer comprising MgO, HfN, Ta3W(110), TaW3(100), or YPt(110), and wherein the first sub-sandwich layer, the second sub-sandwich layer, and the third sub-sandwich layer each comprise different materials. The sandwich layer further comprises one or more of TiN, TiO, MgTiO, or MgTiN. The memory cell comprises a spintronic stack. The logic cell comprises a spintronic stack. The magnetic sensor comprises a spintronic stack.

[0077] While the foregoing is directed to embodiments of the present disclosure, other and additional embodiments of the present disclosure may be envisioned without departing from the basic scope of the present disclosure, and the scope of the present disclosure is determined by the appended claims.

Claims

1. A spintronic stack, the spintronic stack comprising: A buffer layer, the buffer layer comprising a texture layer, the texture layer comprising Ta or Nb; A spin-orbit torque (SOT) layer, the spin-orbit torque (SOT) layer comprising YBiPt oriented in (110), disposed above the buffer layer; An interlayer, the interlayer disposed above the SOT layer; And A ferromagnetic layer, the ferromagnetic layer disposed above the interlayer.

2. The spintronic stack according to claim 1, wherein the buffer layer further comprises: A first sub-layer, the first sub-layer comprising Ta; A second sub-layer, the second sub-layer disposed above the first sub-layer, the second sub-layer comprising Cr; And A third sub-layer, i.e., the texture layer, the third sub-layer disposed above the second sub-layer, the third sub-layer comprising Ta or Nb.

3. The spintronic stack according to claim 2, wherein the Ta in the first sub-layer is β-Ta, and the Ta in the third sub-layer is α-Ta.

4. The spintronic stack according to claim 3, wherein the β-Ta of the third sub-layer is thicker than the α-Ta of the first sub-layer.

5. The spintronic stack according to claim 1, wherein the buffer layer further comprises: A first sub-layer, the first sub-layer comprising Ta; A second sub-layer, the second sub-layer disposed above the first sub-layer, the second sub-layer comprising Cr, V, Mo, or an alloy thereof; A third sub-layer, the third sub-layer disposed above the second sub-layer, the third sub-layer comprising Mo, W, WTi, or an alloy thereof; And A fourth sub-layer, i.e., the texture layer, the fourth sub-layer disposed above the third sub-layer, the fourth sub-layer comprising Ta or Nb.

6. The spintronic stack according to claim 5, wherein the Ta in the first sub-layer is β-Ta, and the Ta in the fourth sub-layer is α-Ta.

7. The spintronic stack according to claim 5, wherein the β-Ta of the fourth sub-layer is thicker than the α-Ta of the first sub-layer.

8. The spintronic stack according to claim 1, the spintronic stack further comprising an amorphous layer, the amorphous layer comprising CoX, CoFeX, NiX, or NiFeX, wherein X is one or more of Ta, W, Hf, and Ge, wherein the amorphous layer is nitrided, and wherein the buffer layer is disposed above the amorphous layer.

9. The spintronic stack according to claim 1, wherein the interlayer comprises Ta or Nb.

10. A memory cell, the memory cell comprising the spintronic stack according to claim 1.

11. A logic unit, the logic unit comprising the spintronic stack according to claim 1.

12. A magnetic sensor, the magnetic sensor comprising the spintronic stack according to claim 1.

13. A spintronic stack, the spintronic stack comprising: A buffer layer, the buffer layer comprising HfN, Ta3W(110), TaW3(100), Ta3WN, TaW3N, MgO(100), TiN(100), or YPt; A spin-orbit torque (SOT) layer, the spin-orbit torque (SOT) layer comprising YBiPt in a (110) orientation, disposed above the buffer layer; An interlayer, the interlayer disposed above the SOT layer; and A ferromagnetic layer, the ferromagnetic layer disposed above the interlayer.

14. The spintronic stack according to claim 13, wherein the buffer layer is a multi-layer stack.

15. The spintronic stack according to claim 13, wherein the buffer layer further comprises: A first sub-layer, the first sub-layer comprising Ta3W(110), TaW3(100), or YPt(110); and A second sub-layer, the second sub-layer comprising HfN, Ta3W(110), TaW3(100), or YPt(110).

16. The spintronic stack according to claim 15, wherein the second sub-layer comprises HfN, and wherein the first sub-layer and the second sub-layer comprise different materials.

17. The spintronic stack according to claim 15, wherein the buffer layer further comprises a third sub-layer disposed between the first sub-layer and the second sub-layer, the third sub-layer comprising Ta3WN(110), TaW3N(100), TiN, or YPt(110).

18. The spintronic stack according to claim 13, wherein the interlayer comprises one or more materials selected from the group consisting of: HfN, Ta3W(110), TaW3(100), NiFeGe, NiAlGe, or YPt(110), MgO, TiN, TiO, MgTiO, or MgTiN.

19. A memory cell, the memory cell comprising the spintronic stack according to claim 13.

20. A logic unit, the logic unit comprising the spintronic stack according to claim 13.

21. A magnetic sensor, the magnetic sensor comprising the spintronic stack according to claim 13.

22. A spintronic stack, the spintronic stack comprising: An amorphous layer, the amorphous layer comprising CoX, CoFeX, NiX, or NiFeX, where X is one or more of Ta, W, Hf, and Ge; A buffer layer disposed above the amorphous layer, the buffer layer comprising: A buffer layer disposed on at least one amorphous non-magnetic migration barrier layer, the buffer layer comprising: (1) A texture template layer, the texture template layer comprising MgO(100), TiN(100), RuAl(100), or YPt, disposed above the at least one amorphous non-magnetic migration barrier layer; and (2) Two or more textured sub-layers, the two or more textured sub-layers being disposed above the textured template layer, each of the two or more textured sub-layers individually comprising a material selected from the group consisting of bcc alloys of Ta, W, Nb, V, and Hf, and fcc alloy nitride compounds of Ta, W, Nb, V, and Hf; A spin-orbit torque (SOT) layer, the spin-orbit torque (SOT) layer comprising YBiPt oriented in the (110) direction, disposed above the buffer layer; A sandwich layer, the sandwich layer being disposed above the SOT layer, the sandwich layer comprising a first sub-layer and a second sub-layer, the first sub-layer comprising a material selected from the group consisting of Ta3WN, TaW3N, Ta3W(110), TaW3(100), YPt(110), NiFeGeN, NiAlN, NiAl, NiFeGe, NiAlGe, and HfN, and the second sub-layer being an oxide layer; A ferromagnetic layer, the ferromagnetic layer being disposed above the second sub-layer of the sandwich layer; and A capping layer, the capping layer being disposed above the ferromagnetic layer.

23. The spintronic stack according to claim 22, wherein the first sub-layer of the two or more textured sub-layers comprises Ta3W(110), TaW3(100), or YPt(110), and wherein the second sub-layer of the two or more textured sub-layers comprises HfN, Ta3W(110), TaW3(100), or YPt(110).

24. The spintronic stack according to claim 23, wherein the buffer layer further comprises a third sub-layer disposed between the first sub-layer and the second sub-layer, the third sub-layer comprising Ta3WN(110), TaW3N(100), TiN, or YPt(110), and wherein the third sub-layer comprises a material different from the first sub-layer and the second sub-layer.

25. The spintronic stack according to claim 22, wherein the sandwich layer comprises two or more sub-sandwich layers.

26. The spintronic stack according to claim 25, wherein the first sub-sandwich layer comprises HfN, Ta3W(110), TaW3(100), or YPt(110), and wherein the second sub-sandwich layer comprises MgO, HfN, Ta3W(110), TaW3(100), or YPt(110).

27. The spintronic stack according to claim 26, wherein the sandwich layer further comprises a third sub-sandwich layer, the third sub-sandwich layer comprising MgO, HfN, Ta3W(110), TaW3(100), or YPt(110), and wherein the first sub-sandwich layer, the second sub-sandwich layer, and the third sub-sandwich layer each comprise different materials.

28. The spintronic stack according to claim 26, wherein the sandwich layer further comprises one or more of TiN, TiO, MgTiO, or MgTiN.

29. A memory cell, the memory cell comprising the spintronic stack according to claim 22.

30. A logic unit, the logic unit comprising a spintronic stack according to claim 22.

31. A magnetic sensor, the magnetic sensor comprising a spintronic stack according to claim 22.

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