Built-in self-test circuit and temperature measurement circuit including same

Abstract

A temperature measuring circuit includes: a bandgap reference circuit configured to generate a fixed bandgap reference voltage independent of an operating temperature; a reference voltage generator circuit configured to generate a measurement reference voltage by adjusting the bandgap reference voltage; the sensing circuit is configured to generate temperature change voltage based on bias current, and the temperature change voltage changes according to the working temperature; an analog-to-digital converter circuit configured to generate a first digital code indicative of the operating temperature based on the measured reference voltage and the temperature varying voltage; and an analog built-in self-test (BIST) circuit configured to generate a plurality of flag signals indicating whether each of the bandgap reference voltage, the measurement reference voltage, and a bias voltage corresponding to the bias current is included within a predetermined range.

Description

[0001] This application is a divisional application of Chinese Patent Application No. 202011054017.7, "Built-in Self-Test Circuit and Temperature Measurement Circuit Including the Built-in Self-Test Circuit". Cross-reference to Related Applications

[0002] This application claims the priority of Korean Patent Application No. 10-2019-0175903, filed with the Korean Intellectual Property Office (KIPO) on December 27, 2019, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] Exemplary embodiments of the inventive concept generally relate to semiconductor integrated circuits, and more particularly, to a built-in self-test (BIST) circuit and a temperature measurement circuit including the BIST circuit. Background Art

[0004] The operating temperature can be monitored and measured to improve the performance of semiconductor integrated circuits. For example, based on the measured operating temperature, the power level of an electronic device can be controlled, the refresh cycle of a storage device can be controlled, circuit damage can be prevented, and so on. As the operating speed and performance level increase, heat management becomes more important. An on-chip temperature sensor integrated in the same semiconductor die as the integrated circuit can be used to detect the temperature of each junction of the integrated circuit. If the on-chip temperature sensor malfunctions, the performance of the semiconductor integrated circuit may degrade or the semiconductor integrated circuit may be damaged due to incorrect information about the operating temperature. Specifically, incorrect temperature information of semiconductor integrated circuits used in vehicles may directly affect the life of the vehicle driver. Summary of the Invention

[0005] According to an exemplary embodiment of the inventive concept, a temperature measurement circuit includes: a bandgap reference circuit configured to generate a fixed bandgap reference voltage independent of the operating temperature; a reference voltage generator circuit configured to generate a measurement reference voltage by adjusting the bandgap reference voltage; a sensing circuit configured to generate a temperature-varying voltage based on a bias current, wherein the temperature-varying voltage varies according to the operating temperature; an analog-to-digital converter circuit configured to generate a first digital code indicating the operating temperature based on the measurement reference voltage and the temperature-varying voltage; and an analog built-in self-test (BIST) circuit configured to generate a plurality of flag signals indicating whether each of the bandgap reference voltage, the measurement reference voltage, and a bias voltage corresponding to the bias current is included within a predetermined range.

[0006] According to an exemplary embodiment of the inventive concept, a temperature measurement circuit includes: a temperature detection circuit and an analog built-in self-test (BIST) circuit. The temperature detection circuit includes: an analog circuit configured to generate a fixed measurement reference voltage independent of the operating temperature and a temperature-varying voltage that varies according to the operating temperature; and an analog-to-digital converter circuit configured to generate a digital code indicating the operating temperature based on the measurement reference voltage and the temperature-varying voltage. The analog BIST circuit generates a plurality of flag signals indicating whether each of a plurality of voltages of the analog circuit is included within a predetermined range.

[0007] According to an exemplary embodiment of the inventive concept, an built-in self-test (BIST) circuit configured to monitor a temperature detection circuit including an analog circuit and an analog-to-digital converter circuit includes: an analog BIST circuit configured to generate a plurality of flag signals indicating whether each of a plurality of monitored voltages of the analog circuit is included within a predetermined range; and a digital BIST circuit configured to apply a test signal to the analog-to-digital converter circuit in a test mode to generate a plurality of alarm signals indicating whether the analog-to-digital converter circuit is operating normally. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above and other features of the inventive concept will be more clearly understood by describing in detail exemplary embodiments of the inventive concept with reference to the accompanying drawings.

[0009] Figure 1 is a diagram showing a temperature measurement circuit according to an exemplary embodiment of the inventive concept.

[0010] Figure 2 is a diagram showing an Figure 1 analog circuit included in the temperature measurement circuit according to an exemplary embodiment of the inventive concept.

[0011] Figure 3 is a diagram showing an Figure 2 bandgap reference circuit included in the analog circuit according to an exemplary embodiment of the inventive concept.

[0012] Figure 4 is a diagram showing an Figure 2 reference voltage generator included in the analog circuit according to an exemplary embodiment of the inventive concept.

[0013] Figure 5 is a diagram showing an Figure 2 sensing circuit included in the analog circuit according to an exemplary embodiment of the inventive concept.

[0014] Figure 6 is a diagram showing a bandgap reference voltage monitor included in the analog BIST circuit according to an exemplary embodiment of the inventive concept.

[0015] Figure 7 is a diagram for describing the operation of a bandgap reference voltage monitor according to an exemplary embodiment of the inventive concept. Figure 6 of the bandgap reference voltage monitor.

[0016] Figure 8 is a circuit diagram showing a measurement reference voltage monitor included in an analog BIST circuit according to an exemplary embodiment of the inventive concept.

[0017] Figure 9 is for describing an exemplary embodiment according to the inventive concept Figure 8 operation of the measurement reference voltage monitor.

[0018] Figure 10 is a circuit diagram showing a bias voltage monitor included in an analog BIST circuit according to an exemplary embodiment of the inventive concept.

[0019] Figure 11 is for describing an exemplary embodiment according to the inventive concept Figure 10 operation of the bias voltage monitor.

[0020] Figure 12 is a block diagram showing an analog BIST circuit according to an exemplary embodiment of the inventive concept.

[0021] Figure 13 is a circuit diagram for describing the bias current and bias voltage of an analog BIST circuit according to an exemplary embodiment of the inventive concept.

[0022] Figure 14 is a block diagram showing a digital BIST circuit according to an exemplary embodiment of the inventive concept.

[0023] Figure 15 and Figure 16 is for describing an exemplary operation of a digital BIST circuit according to an exemplary embodiment of the inventive concept Figure 14 of the digital BIST circuit.

[0024] Figure 17 and Figure 18 is a flowchart showing a method for testing a digital BIST circuit according to an exemplary embodiment of the inventive concept.

[0025] Figure 19 is for describing an exemplary operation of a digital BIST circuit according to an exemplary embodiment of the inventive concept Figure 14 of the digital BIST circuit.

[0026] Figure 20 and Figure 21It is a flowchart showing a method for testing a digital BIST circuit according to an exemplary embodiment of the inventive concept.

[0027] Figure 22 is for describing according to an exemplary embodiment of the inventive concept Figure 14 of an example operation of a digital BIST circuit.

[0028] Figure 23 It is a flowchart showing a method for testing a digital BIST circuit according to an exemplary embodiment of the inventive concept.

[0029] Figure 24 It is a block diagram showing an analog-to-digital converter included in a temperature measurement circuit according to an exemplary embodiment of the inventive concept.

[0030] Figure 25 and Figure 26 is for describing according to an exemplary embodiment of the inventive concept Figure 24 of an example operation of the analog-to-digital converter.

[0031] Figure 27 is a graph for describing the transition time of a ramp voltage according to an exemplary embodiment of the inventive concept.

[0032] Figure 28 It is a flowchart showing a method for testing a digital BIST circuit according to an exemplary embodiment of the inventive concept.

[0033] Figure 29 It is a graph showing an example layout of a temperature measurement circuit according to an exemplary embodiment of the inventive concept.

[0034] Figure 30 is showing according to an exemplary embodiment of the inventive concept Figure 29 of an example configuration of a temperature measurement circuit.

[0035] Figure 31 It is a flowchart showing a method for testing a digital BIST circuit according to an exemplary embodiment of the inventive concept.

[0036] Figure 32 It is a graph showing a semiconductor integrated circuit including a temperature measurement circuit according to an exemplary embodiment of the inventive concept.

[0037] Figure 33 It is a graph showing the operation of a system including a temperature measurement circuit according to an exemplary embodiment of the inventive concept. Detailed Description

[0038] Exemplary embodiments of the inventive concept provide an built-in self-test (BIST) circuit that can effectively monitor a temperature detection circuit and a temperature measurement circuit including the BIST circuit.

[0039] Exemplary embodiments of the inventive concept will be described more fully hereinafter with reference to the accompanying drawings. Throughout this application, like reference numerals may refer to like elements.

[0040] Figure 1 is a diagram illustrating a temperature measurement circuit according to an exemplary embodiment of the inventive concept.

[0041] Referring to Figure 1 , the temperature measurement circuit 1000 may include a temperature detection circuit 10 and an built-in self-test (BIST) circuit 20. As will be described hereinafter with reference to Figure 32 , the temperature detection circuit 10 and the BIST circuit 20 may be integrated in the same semiconductor die, in which case the temperature measurement circuit 1000 may be referred to as an on-chip temperature sensor.

[0042] The temperature detection circuit 10 may include an analog circuit 100 and an analog-to-digital converter ADC 200.

[0043] The analog circuit 100 may generate a fixed measurement reference voltage VREF independent of the operating temperature and a temperature-variable voltage VTEM that varies according to the operating temperature. The analog-to-digital converter 200 may generate a digital code DCD indicating the operating temperature based on the measurement reference voltage VREF and the temperature-variable voltage VTEM. The analog-to-digital converter 200 may be a circuit.

[0044] The BIST circuit 20 may include at least one of an analog BIST circuit ABIST 300 and a digital BIST circuit DBIST 400. In an exemplary embodiment of the inventive concept, the BIST circuit 20 may include only the analog BIST circuit 300 and the digital BIST circuit 400 may be omitted. In an exemplary embodiment of the inventive concept, the BIST circuit 20 may include only the digital BIST circuit 400 and the analog BIST circuit 300 may be omitted. In an exemplary embodiment of the inventive concept, the BIST circuit 20 may include both the analog BIST circuit 300 and the digital BIST circuit 400.

[0045] The analog BIST circuit 300 may generate a plurality of flag signals FG1 to FGk, which indicate whether each of the plurality of monitored voltages VM1 to VMk of the analog circuit 100 is included within a normal range. The normal range may be a predetermined range indicating normal operation of a specific component. The monitored voltage may indicate a voltage used in the analog circuit 100 and / or provided to other components (e.g., the analog-to-digital converter 200) external to the analog circuit 100. For example, the monitored voltages VM1 to VMk may include at least one of a measurement reference voltage VREF, a temperature-varying voltage VTEM, and a bias voltage VBS as will be described below with reference to Figures 6 to 13 the measurement reference voltage VREF, the temperature-varying voltage VTEM, and the bias voltage VBS described below.

[0046] The digital BIST circuit 400 may apply a test signal TS to the analog-to-digital converter 200 in a test mode to generate a plurality of alarm signals ALM1 to ALMs indicating whether the analog-to-digital converter 200 is operating normally. The digital BIST circuit 400 may apply the test signal TS instead of the temperature-varying voltage VTEM in the test mode to receive a digital code DCD for generating the plurality of alarm signals ALM1 to ALMs. The plurality of alarm signals ALM1 to ALMs will be described below with reference to Figures 14 to 31 the plurality of alarm signals ALM1 to ALMs.

[0047] In this way, the BIST circuit and the temperature measurement circuit according to an exemplary embodiment of the inventive concept may effectively diagnose a failure of the temperature measurement circuit by monitoring whether a plurality of voltages are within a normal range using the BIST circuit. In addition, the BIST circuit and the temperature measurement circuit according to an exemplary embodiment of the inventive concept may effectively diagnose the analog-to-digital converter included in the temperature measurement circuit by performing various tests using the digital BIST circuit.

[0048] Figure 2 is a block diagram showing an analog circuit included in a Figure 1 temperature measurement circuit according to an exemplary embodiment of the inventive concept.

[0049] Referring to Figure 2 the analog circuit 100 may include a bandgap reference circuit GBGR 110, a reference voltage generator GREF 120, and a sensing circuit GTEM 130. The reference voltage generator 120 may be a circuit.

[0050] The bandgap reference circuit 110 may generate a fixed bandgap reference voltage VBGR independent of the operating temperature. The reference voltage generator 120 may generate a measurement reference voltage VREF by adjusting the bandgap reference voltage VBGR. Similar to the bandgap reference voltage VBGR, the measurement reference voltage VREF may be fixed and independent of the operating temperature. The sensing circuit 130 may generate a temperature-varying voltage VTEM based on a bias current IBS such that the temperature-varying voltage VTEM may vary according to the operating temperature.

[0051] Figure 2 It is shown that the bias current IBS is provided from the bandgap reference circuit 110, but the inventive concept is not limited thereto. According to an exemplary embodiment of the inventive concept, the bias current IBS may be generated in the sensing circuit 130.

[0052] Hereinafter, exemplary embodiments of the bandgap reference circuit 110, the reference voltage generator 120, and the sensing circuit 130 will be described with reference to Figures 3 to 5 However, the inventive concept is not limited to Figures 3 to 5 the configuration of, and the configuration of the analog circuit 100 may be implemented differently.

[0053] Figure 3 is a circuit diagram showing a bandgap reference circuit included in the Figure 2 analog circuit according to an exemplary embodiment of the inventive concept.

[0054] Referring to Figure 3 , the bandgap reference circuit 110 may include a first p-channel metal oxide semiconductor (PMOS) transistor PM11, a second PMOS transistor PM12, a first resistor R1, a second resistor R2, a third resistor R3, a feedback amplifier AMP, a first sensing unit 111, and a second sensing unit 112, which are connected between a power supply voltage VDD and a ground voltage VSS as Figure 3 shown.

[0055] The first sensing unit 111 may be implemented using a single-signal bipolar junction transistor (BJT), and the second sensing unit 112 may be implemented using a plurality of BJTs. Using such a bandgap reference circuit, a fixed bandgap reference voltage VBGR and / or a bandgap reference current independent of the operating temperature may be provided.

[0056] The emitter voltage of the second sensing unit 112 is inversely proportional to the operating temperature. The voltage across the third resistor R3 and the current flowing through the third resistor R3 are proportional to the operating temperature. As a result, through the proportional and inverse characteristics of the circuit, the bandgap reference voltage VBGR may be fixed regardless of the operating temperature. For example, the bandgap reference voltage VBGR may be provided at the connection node of the second PMOS transistor PM12 and the second resistor R2.

[0057] Figure 4 is a circuit diagram showing a reference voltage generator included in the Figure 2 analog circuit according to an exemplary embodiment of the inventive concept.

[0058] Referring to Figure 4 , the reference voltage generator 120 may include an amplifier AMP, a PMOS transistor PM21, and a plurality of voltage dividing resistors R0 to RN, which are asFigure 4 It is connected between the power supply voltage VDD and the ground voltage VSS as shown. The measurement reference voltage VREF and the plurality of divided voltages VREF1 to VREFN can be determined according to the ratio of the voltage dividing resistors R0 to RN. The amplifier AMP, the PMOS transistor PM21, and the resistor R0 form a feedback loop, so the divided voltage VREF1 can converge to the bandgap reference voltage VBGR. The bandgap reference voltage VBGR can be fixed. Therefore, the measurement reference voltage VREF proportional to the bandgap reference voltage VBGR can be fixed and is independent of the operating temperature.

[0059] Figure 5 is a circuit diagram showing a sensing circuit included in an analog circuit of Figure 2 according to an exemplary embodiment of the inventive concept.

[0060] Referring to Figure 5 , the sensing circuit 130 may include a current-voltage converter 135, a first amplifier AMP1, a second amplifier AMP2, a first resistor R1, and a second resistor R2.

[0061] The current-voltage converter 135 may include a current source CST and a sensing unit SU connected between the power supply voltage VDD and the ground voltage VSS. The sensing unit SU may be implemented using a BJT. The sensing voltage VBE corresponding to the emitter voltage of the BJT may be inversely proportional to the operating temperature. The positive terminal of the first amplifier AMP1 may receive the sensing voltage VBE, and the negative terminal may be connected to the output terminal such that the first amplifier AMP1 may form a unity-gain amplifier. The output terminal of the first amplifier AMP1 may be connected to the negative terminal of the second amplifier AMP2 through the first resistor R1. The second amplifier AMP2 may receive the reference voltage VREFi through the positive terminal. The output terminal of the second amplifier AMP2 may be connected to the negative terminal of the second amplifier AMP2 through the second resistor R2.

[0062] With such a configuration, the sensing voltage VBE inversely proportional to the operating temperature may be inverted and amplified to generate a temperature-varying voltage VTEM that increases as the operating temperature rises.

[0063] As described with reference to Figures 3 to 5 , a fixed measurement reference voltage VREF independent of the operating temperature and a temperature-varying voltage VTEM varying according to the operating temperature may be provided to Figure 1 the analog-to-digital converter 200 in. The analog-to-digital converter 200 may generate a digital code DCD indicating the operating temperature based on the measurement reference voltage VREF and the temperature-varying voltage VTEM.

[0064] Figure 6is a circuit diagram showing a bandgap reference voltage monitor included in an analog BIST circuit according to an exemplary embodiment of the inventive concept, while Figure 7 is a diagram for describing the operation of a bandgap reference voltage monitor according to an exemplary embodiment of the inventive concept Figure 6 of.

[0065] Referring to Figure 6 , the bandgap reference voltage monitor 310 may include a power supply voltage divider 311 and a comparator COM1. The power supply voltage divider 311 and the comparator COM1 may be circuits.

[0066] The power supply voltage divider 311 may generate a power supply divided voltage VD11 corresponding to the lowest limit level of the bandgap reference voltage VBGR by dividing the power supply voltage VDD.

[0067] In an exemplary embodiment of the inventive concept, as Figure 6 shown, the power supply voltage divider 311 may include: a first voltage dividing resistor R11 connected between the power supply voltage VDD and a voltage dividing node N11; and a second voltage dividing resistor R12 connected between the voltage dividing node N11 and the ground voltage VSS. The power supply divided voltage VD11 may be provided at the voltage dividing node N11, and the power supply divided voltage VD11 corresponds to the lowest limit level for setting the normal range of the bandgap reference voltage VBGR. In other words, if the bandgap reference voltage VBGR is excessively reduced, it is determined that the bandgap reference voltage VBGR deviates from the normal range. The lowest limit level of the bandgap reference voltage VBGR or the power supply divided voltage VD11 may be appropriately controlled by adjusting the resistance ratio of the first voltage dividing resistor R11 and the second voltage dividing resistor R12.

[0068] Referring to Figure 6 and Figure 7 , the comparator COM1 may generate a bandgap flag signal FG1 by comparing the bandgap reference voltage VBGR with the power supply divided voltage VD11, so that the bandgap flag signal FG1 may be activated when the bandgap reference voltage VBGR is lower than the lowest limit level of the bandgap reference voltage VBGR.

[0069] For example, when the bandgap reference voltage VBGR is higher than the lowest limit level, the bandgap flag signal FG1 may be deactivated to a first logic level (e.g., logic low level L), and when the bandgap reference voltage VBGR is lower than the lowest limit level, the bandgap flag signal FG1 may be activated to a second logic level (e.g., logic high level H).

[0070] Figure 8 is a circuit diagram showing a measurement reference voltage monitor included in an analog BIST circuit according to an exemplary embodiment of the inventive concept, while Figure 9is a diagram for describing the operation of a measurement reference voltage monitor according to an exemplary embodiment of the inventive concept. Figure 8 of the measurement reference voltage monitor.

[0071] Referring Figure 8 , the measurement reference voltage monitor 320 may include a bandgap reference voltage divider 321, a measurement reference voltage divider 322, and a comparator COM2. The bandgap reference voltage divider 321, the measurement reference voltage divider 322, and the comparator COM2 may be circuits.

[0072] The bandgap reference voltage divider 321 may generate a first bandgap divided voltage VD21 corresponding to the highest limit level of the measurement reference voltage VREF and a second bandgap divided voltage VD22 corresponding to the lowest limit level of the measurement reference voltage VREF by dividing the bandgap reference voltage VBGR.

[0073] In an exemplary embodiment of the inventive concept, as Figure 8 shown, the bandgap reference voltage divider 321 may include: a first voltage dividing resistor R21 connected between the bandgap reference voltage VBGR and a first voltage dividing node N21; a second voltage dividing resistor R22 connected between the first voltage dividing node N21 and a second voltage dividing node N22; and a third voltage dividing resistor R23 connected between the second voltage dividing node N22 and the ground voltage VSS.

[0074] The first bandgap divided voltage VD21 may be provided at the first voltage dividing node N21, and the first bandgap divided voltage V21 may correspond to the highest limit level for setting the normal range of the measurement reference voltage VREF. The second bandgap divided voltage VD22 may be provided at the second voltage dividing node N22, and the second bandgap divided voltage V22 may correspond to the lowest limit level for setting the normal range of the measurement reference voltage VREF. In other words, if the bandgap reference voltage VBGR increases or decreases excessively, it is determined that the measurement reference voltage VREF deviates from the normal range. The highest and lowest limit levels of the measurement reference voltage VREF, or the first bandgap divided voltage VD21 and the second bandgap divided voltage VD22, may be appropriately controlled by adjusting the resistance ratios of the first voltage dividing resistor R21, the second voltage dividing resistor R22, and the third voltage dividing resistor R23.

[0075] The measurement reference voltage divider 322 may generate a measurement divided voltage VD23 by dividing the measurement reference voltage VREF.

[0076] In an exemplary embodiment of the inventive concept, as Figure 8As shown, the measurement reference voltage divider 322 may include: a fourth voltage dividing resistor R24 connected between the measurement reference voltage VREF and the third voltage dividing node N23; and a fifth voltage dividing resistor R25 connected between the third voltage dividing node N23 and the ground voltage VSS. A measurement divided voltage VD23 may be provided at the third voltage dividing node N23. The measurement divided voltage VD23 may be appropriately controlled by adjusting the resistance ratio of the fourth voltage dividing resistor R24 and the fifth voltage dividing resistor R25.

[0077] Reference Figure 8 and Figure 9 , the comparator COM2 may generate a reference voltage flag signal FG2 by comparing the measurement divided voltage VD23 with the first bandgap divided voltage VD21 and the second bandgap divided voltage VD22, so that the reference voltage flag signal FG2 may be activated when the measurement reference voltage VREF is higher than the highest limit level of the measurement reference voltage VREF or lower than the lowest limit level of the measurement reference voltage VREF.

[0078] For example, when the measurement reference voltage VREF is lower than the highest limit level and higher than the lowest limit level, the reference voltage flag signal FG2 may be deactivated to a first logic level (e.g., logic low level L), and when the measurement reference voltage VREF is higher than the highest limit level or lower than the lowest limit level, the reference voltage flag signal FG2 may be activated to a second logic level (e.g., logic high level H).

[0079] Figure 10 is a circuit diagram showing a bias voltage monitor included in an analog BIST circuit according to an exemplary embodiment of the inventive concept, Figure 11 is for describing Figure 10 the operation of the bias voltage monitor according to an exemplary embodiment of the inventive concept.

[0080] Reference Figure 10 , the bias voltage monitor 330 may include a measurement reference voltage divider 331, a current-voltage converter 332, and a comparator COM3. The measurement reference voltage divider 331, the current-voltage converter 332, and the comparator COM3 may be circuits.

[0081] The measurement reference voltage divider 331 may generate a first measurement reference divided voltage VD31 corresponding to the highest limit level of the bias voltage VBS and a second measurement reference divided voltage VD32 corresponding to the lowest limit level of the bias voltage VBS by dividing the measurement reference voltage VREF.

[0082] In an exemplary embodiment of the inventive concept, as Figure 10As shown, the bias voltage divider 331 may include: a first voltage dividing resistor R31 connected between a measurement reference voltage VREF and a first voltage dividing node N31; a second voltage dividing resistor R32 connected between the first voltage dividing node N31 and a second voltage dividing node N32; and a third voltage dividing resistor R33 connected between the second voltage dividing node N32 and a ground voltage VSS.

[0083] A first measurement reference divided voltage VD31 may be provided at the first voltage dividing node N31, and the first measurement reference divided voltage VD31 may correspond to the highest limit level for setting the normal range of the bias voltage VBS. A second measurement reference divided voltage VD32 may be provided at the second voltage dividing node N32, and the second measurement reference divided voltage VD32 may correspond to the lowest limit level for setting the normal range of the bias voltage VBS. In other words, if the bias voltage VBS increases or decreases excessively, it is determined that the bias voltage VBS deviates from the normal range. The highest and lowest limit levels of the bias voltage VBS, or the first measurement reference divided voltage VD31 and the second measurement reference divided voltage VD32, may be appropriately controlled by adjusting the resistance ratios of the first voltage dividing resistor R31, the second voltage dividing resistor R32, and the third voltage dividing resistor R33.

[0084] The current-voltage converter 332 may generate a bias voltage VBS based on a bias current IBS. For example, as Figure 10 shown, the current-voltage converter 332 may include a current source CSM and a resistor R34 connected between a power supply voltage VDD and a ground voltage VSS. In an exemplary embodiment of the inventive concept, the current source CSM may be omitted, and in this case, the bias current IBS may be provided from the Figure 2 bandgap reference circuit 110 therein.

[0085] Refer to Figure 10 and Figure 11 , the comparator COM3 may generate a bias voltage flag signal FG3 by comparing the bias voltage VBS with the first measurement reference divided voltage VD31 and the second measurement reference divided voltage VD32, so that the bias voltage flag signal FG3 may be activated when the bias voltage VBS is higher than the highest limit level of the bias voltage VBS or lower than the lowest limit level of the bias voltage VBS.

[0086] For example, when the bias voltage VBS is lower than the highest limit level and higher than the lowest limit level, the bias voltage flag signal FG3 may be deactivated to a first logic level (e.g., logic low level L), and when the bias voltage VBS is higher than the highest limit level or lower than the lowest limit level, the bias voltage flag signal FG3 may be activated to a second logic level (e.g., logic high level H).

[0087] Figure 12is a block diagram showing a simulated BIST circuit according to an exemplary embodiment of the inventive concept.

[0088] Referring Figure 12 , the simulated BIST circuit 350 may include a bandgap reference voltage monitor VMON1 310, a measurement reference voltage monitor VMON2 320, and a bias voltage monitor VMON3 330. Each of the bandgap reference voltage monitor 310, the measurement reference voltage monitor 320, and the bias voltage monitor 330 may be a circuit. The simulated BIST circuit 350 may receive a bandgap reference voltage VBGR and a measurement reference voltage VREF from the analog circuit 100. Additionally, the simulated BIST circuit 350 may internally generate a bias voltage VBS based on a bias current IBS. According to an exemplary embodiment of the inventive concept, the simulated BIST circuit 350 may receive the bias current IBS from the analog circuit 100 or may internally generate the bias current IBS.

[0089] As referring Figure 6 and Figure 7 described, the bandgap reference voltage monitor 310 may generate a bandgap flag signal FG1 based on the bandgap reference voltage VBGR and the power supply voltage VDD, so that the bandgap flag signal FG1 may be activated when the bandgap reference voltage VBGR deviates from its normal range.

[0090] As referring Figure 8 and Figure 9 described, the measurement reference voltage monitor 320 may generate a reference voltage flag signal FG2 based on the measurement reference voltage VREF and the bandgap reference voltage VBGR, so that the reference voltage flag signal FG2 may be activated when the measurement reference voltage VREF deviates from its normal range.

[0091] As referring Figure 10 and Figure 11 described, the bias voltage monitor 330 may generate a bias voltage flag signal FG3 based on the bias voltage VBS corresponding to the bias current IBS and the measurement reference voltage VREF, so that the bias voltage flag signal FG3 may be activated when the bias voltage VBS deviates from its normal range.

[0092] In other words, each of the monitors 310, 320, and 330 may generate one of the flag signals FG1, FG2, and FG3 by comparing a monitoring voltage with a comparison reference voltage.

[0093] As referring Figure 6 and Figure 7 described, in the case of the bandgap reference voltage monitor 310, the power supply voltage VDD corresponds to the comparison reference voltage, and the bandgap reference voltage VBGR corresponds to the monitoring voltage. As referringFigure 8 and Figure 9 As described, in the case of the measurement reference voltage monitor 320, the bandgap reference voltage VBGR corresponds to the comparison reference voltage, and the measurement reference voltage VREF corresponds to the monitored voltage. As referenced Figure 10 and Figure 11 As described, in the case of the bias voltage monitor 330, the measurement reference voltage VREF corresponds to the comparison reference voltage, and the bias voltage VBS corresponds to the monitored voltage.

[0094] In this way, the monitored voltage of one voltage monitor can be used as the comparison reference voltage of another voltage monitor. As described above, the bandgap reference voltage VBGR corresponding to the monitored voltage of the bandgap reference voltage monitor 310 can be used as the comparison reference voltage of the measurement reference voltage monitor 320, and the measurement reference voltage VREF corresponding to the monitored voltage of the measurement reference voltage monitor 320 can be used as the comparison reference voltage of the bias voltage monitor 330. In this way, the deviation of the monitored voltage of the previous voltage monitor can be propagated to the next voltage monitor, and thus, the last voltage monitor can determine the combined deviation of multiple voltage monitors.

[0095] According to an exemplary embodiment of the inventive concept, the analog BIST circuit may include one or two of the bandgap reference voltage monitor 310, the measurement reference voltage monitor 320, and the bias voltage monitor 330. Additionally, the analog BIST circuit according to an exemplary embodiment of the inventive concept may include four or more voltage monitors for monitoring whether four or more voltages are included within their respective normal ranges.

[0096] Figure 13 is a circuit diagram for describing the bias current and bias voltage of the analog BIST circuit according to an exemplary embodiment of the inventive concept.

[0097] Figure 13 illustrates an exemplary embodiment in which the current-voltage converter 135 included in the sensing circuit 130 as described with reference to Figure 5 and the current-voltage converter 332 included in the bias voltage monitor 330 as described with reference to Figure 10 are implemented as a single entity. The descriptions already provided with reference to Figure 5 and Figure 10 may be omitted.

[0098] Referring to Figure 13 , the current-voltage converter 135 of the sensing circuit 130 may include a first current source CST for generating a bias current IBS, and the current-voltage converter 332 of the bias voltage monitor 330 may include a second current source CSM for generating a bias current IBS.

[0099] The first current source CST and the second current source CSM may include PMOS transistors PM1 and PM2 forming a current mirror. In this case, a standard for normal operation of the analog circuit 100 may be appropriately set by generating a temperature-fixed bias voltage VBS and a temperature-varying sense voltage VBE using the same bias current IBS.

[0100] Figure 14 is a block diagram showing a digital BIST circuit according to an exemplary embodiment of the inventive concept.

[0101] Referring to Figure 14 , the digital BIST circuit 400 may include a counter 410, a memory MEM 420, a test signal generator GTS 430, and a digital logic block DLB 440. The elements of the digital BIST circuit 400 may be circuits.

[0102] The counter 410 may monitor the operation timing of the analog-to-digital converter 200. The counter 410 may generate a count signal CNT corresponding to the operation timing based on a timing signal TIM and a clock signal CLK. For example, as will be described below with reference to Figures 24 to 25 , the timing signal TIM may include a scan start signal SOS, a conversion start signal SOC, a conversion end signal EOC, etc.

[0103] The memory 420 may store information for the operation of the digital BIST circuit 400 and information about test results obtained by the digital BIST circuit 400.

[0104] The test signal generator 430 may generate a test signal TS for each test. In the test mode, the test signal TS instead of the temperature-varying voltage VTEM may be applied to the analog-to-digital converter 200.

[0105] The digital logic block 440 may receive a digital code DCD, control the overall operation of the digital BIST circuit 400, and generate a plurality of alarm signals MONO, LNT, OFF, STC, FLT, FCT, STT, CNV, and PRV based on the test results.

[0106] Figure 15 and Figure 16 is a diagram for describing an example operation of the digital BIST circuit according to an exemplary embodiment of the inventive concept Figure 14 of.

[0107] Referring to Figure 14 and Figure 15, the test signal generator 430 may generate a ramp voltage VRMP having successively increasing or decreasing voltage levels in a test mode, and apply the ramp voltage VRMP as a test signal TS to the analog-to-digital converter 200. Figure 15 An exemplary non-limiting example where the ramp voltage VRMP increases successively is shown.

[0108] The digital logic block 440 may test whether the analog-to-digital converter 200 is operating properly in a test mode based on a plurality of values DL1 to DLp obtained by applying the ramp voltage VRMP instead of the temperature change voltage VTEM to the analog-to-digital converter 200. For example, as Figure 15 shown, the analog-to-digital converter 200 may be implemented such that the values DL1 to DLp may increase as the temperature change voltage VTEM or the ramp voltage VRMP increases. According to an exemplary embodiment of the inventive concept, the analog-to-digital converter 200 may be implemented such that the values DL1 to DLp may decrease as the temperature change voltage VTEM or the ramp voltage VRMP increases.

[0109] Figure 16 The monotonicity and linearity of the exemplary values DL1 to DLp of the digital code DCD are shown. It is required that the analog-to-digital converter 200 generate a digital code DCD having a value that is monotonically linearly proportional to the operating temperature. By testing such monotonicity and linearity, it is determined whether the analog-to-digital converter 200 is operating properly.

[0110] Hereinafter, it is assumed that the alarm signal is activated at a logic high level H and deactivated at a logic low level L, but the inventive concept is not limited thereto.

[0111] Figure 17 and Figure 18 is a flowchart showing a method of testing a digital BIST circuit according to an exemplary embodiment of the inventive concept.

[0112] Referring to Figure 14 , Figure 15 and Figure 17 , when the temperature measurement circuit enters the test mode (S11), the test signal generator 430 may generate a ramp voltage VRMP and apply the ramp voltage VRMP as a test signal TS to the analog-to-digital converter 200 (S12).

[0113] The digital logic block 440 may receive multiple values DL1 to DLp of the digital code DCD generated when applying the ramp voltage VRMP to the analog-to-digital converter 200 (S13). The digital logic block 440 may determine whether the difference DLi+1 - DLi between two adjacent values DLi+1 and DLi among the multiple values DL1 to DLp is less than zero (S14). When the difference DLi+1 - DLi is less than zero (S14: Yes), the digital logic block 440 may activate the monotonic alarm signal MONO to the logic high level H (S15). On the contrary, when the difference DLi+1 - DLi is not less than zero (S14: No), the digital logic block 440 may deactivate the monotonic alarm signal MONO to the logic low level L (S16).

[0114] In this way, the digital BIST circuit 400 may generate the monotonic alarm signal MONO based on the multiple values DL1 to DLp of the digital code DCD, such that the monotonic alarm signal MONO may indicate whether the digital code DCD is monotonically increasing or decreasing.

[0115] Reference Figure 14 、 Figure 15 and Figure 18 When the temperature measurement circuit enters the test mode (S21), the test signal generator 430 may generate the ramp voltage VRMP and apply the ramp voltage VRMP as the test signal TS to the analog-to-digital converter 200 (S22).

[0116] The digital logic block 440 may receive multiple values DL1 to DLp of the digital code DCD generated when applying the ramp voltage VRMP to the analog-to-digital converter 200 (S23). The digital logic block 440 may determine whether the difference DLi+1 - DLi between two adjacent values DLi+1 and DLi among the multiple values DL1 to DLp is greater than the reference value RF1 (S24). When the difference DLi+1 - DLi is greater than the reference value RF1 (S24: Yes), the digital logic block 440 may activate the linear alarm signal LNT to the logic high level H (S25). On the contrary, when the difference DLi+1 - DLi is not greater than the reference value RF1 (S24: No), the digital logic block 440 may deactivate the linear alarm signal LNT to the logic low level L (S26).

[0117] In this way, the digital BIST circuit 400 may generate the linear alarm signal INT based on the multiple values DL1 to DLp of the digital code DCD, such that the linear alarm signal INT may indicate whether the digital code DCD is uniformly increasing or decreasing.

[0118] Figure 19 is a diagram for describing an example operation of the digital BIST circuit according to an exemplary embodiment of the inventive concept Figure 14 of.

[0119] Figure 19 Show a voltage level VMAX corresponding to the maximum value DLMAX of the digital code DCD and a voltage level VMIN corresponding to the minimum value DLMIN of the digital code DCD.

[0120] Figure 14 The test signal generator 430 in can generate a test signal TS having a voltage level VH higher than the voltage level VMAX corresponding to the maximum value DLMAX of the digital code DCD, a voltage level VL lower than the voltage level VMIN corresponding to the minimum value DLMIN of the digital code DCD, or a voltage level VI corresponding to the central value DLI of the digital code DCD.

[0121] The test signal TS can be used to perform tests as will be referred to Figure 20 and Figure 21 described test operations.

[0122] Figure 20 and Figure 21 are flowcharts showing methods of testing a digital BIST circuit according to exemplary embodiments of the inventive concept.

[0123] Referring to Figure 14 , Figure 19 and Figure 20 , when the temperature measurement circuit enters the test mode (S31), the test signal generator 430 can generate a test signal TS having a voltage level VI corresponding to the central value DLI of the digital code DCD to be applied to the analog-to-digital converter 200 (S32).

[0124] The digital logic block 440 can receive the measured value DLI' of the digital code DCD generated when applying the voltage level VI to the analog-to-digital converter 200 (S33). The digital logic block 440 can determine whether the absolute difference |DLI - DLI'| between the measured value DLI' and the central value DLI is greater than a reference value RF2 (S34). When the absolute difference |DLI - DLI'| is greater than the reference value RF2 (S34: Yes), the digital logic block 440 can activate the offset alarm signal OFF to a logic high level H (S35). On the contrary, when the absolute difference |DLI - DLI'| is not greater than the reference value RF2 (S34: No), the digital logic block 440 can deactivate the offset alarm signal OFF to a logic low level L (S35).

[0125] In this way, the digital BIST circuit 400 can generate an offset alarm signal OFF based on the measured value DLI' and the central value DLI, such that the offset alarm signal OFF can indicate whether the offset of the digital code DCD deviates from its normal range represented by the reference value RF2.

[0126] Reference Figure 14 、 Figure 19 and ​ When the temperature measurement circuit enters the test mode (S41), the test signal generator 430 can generate a test signal TS having a voltage level VH higher than the voltage level VMAX corresponding to the maximum value DLMAX of the digital code DCD to be applied to the analog-to-digital converter 200 (S42).

[0127] The digital logic block 440 can receive a first measured value DLH of the digital code DCD generated when applying the voltage level VH to the analog-to-digital converter 200 (S43). The digital logic block 440 can determine whether the first measured value DLH is equal to the maximum value DLMAX (S44). When the first measured value DLH is not equal to the maximum value DLMAX (S44: No), the digital logic block 440 can activate the clipping alarm signal STC to the logic high level H (S45).

[0128] When the first measured value DLH is equal to the maximum value DLMAX (S44: Yes), the test signal generator 430 can generate a test signal TS having a voltage level VL lower than the voltage level VMIN corresponding to the minimum value DLMIN of the digital code DCD to be applied to the analog-to-digital converter 200 (S46).

[0129] The digital logic block 440 can receive a second measured value DLL of the digital code DCD generated when applying the voltage level VL to the analog-to-digital converter 200 (S47). The digital logic block 440 can determine whether the second measured value DLL is equal to the minimum value DLMIN (S48). When the second measured value DLL is not equal to the minimum value DLMIN (S48: No), the digital logic block 440 can activate the clipping alarm signal STC to the logic high level H (S45). When the second measured value DLL is equal to the minimum value DLMIN (S48: Yes), the digital logic block 440 can deactivate the clipping alarm signal STC to the logic low level L (S49).

[0130] In this way, the digital BIST circuit 400 can generate the clipping alarm signal STC based on the first measured value DLH and the second measured value DLL, such that the clipping alarm signal STC can indicate whether each bit of the digital code DCD is fixed regardless of the operating temperature.

[0131] ​ is a diagram for describing an example operation of a digital BIST circuit according to an exemplary embodiment of the inventive concept ​ .

[0132] Reference ​, the digital BIST circuit 400 may further include a pull-up control circuit 450 connected to the output node NO that generates the digital code DCD of the analog-to-digital converter ADC 200. According to an exemplary embodiment of the inventive concept, the pull-up control circuit 450 may be included in the analog-to-digital converter 200.

[0133] The pull-up control circuit 450 of the digital BIST circuit may include: a pull-up resistor RU connected to the power supply voltage VDD; and a pull-up switch SWU configured to control the electrical connection between the pull-up resistor RU and the output node NO of the digital code DCD. Additionally, the pull-up control circuit 450 may include: a pull-down resistor RD connected to the ground voltage VSS; and a pull-down switch SWD configured to control the electrical connection between the pull-down resistor RD and the output node NO of the digital code DCD. The pull-up switch SWU and the pull-down switch SWD may be turned on based on the switch control signals SCU and SCD provided from the ​ digital logic block 440 therein, respectively.

[0134] In other words, in the test mode, the digital BIST circuit applies a test signal TS having a voltage level (VH) higher than the voltage level VMAX corresponding to the maximum value DLMAX of the digital code DCD to the analog-to-digital converter 200 when the pull-down switch SWD is turned on, and applies a test signal TS having a voltage level (VL) lower than the voltage level VMIN corresponding to the minimum value DLMIN of the digital code DCD to the analog-to-digital converter 200 when the pull-up switch SWU is turned on to generate a floating alarm signal FLT. This will be further described with reference to ​ this.

[0135] For ease of explanation, ​ a configuration corresponding to one output node NO is shown. When multiple output nodes are implemented to output multiple bits of the digital code DCD in parallel, multiple pull-up control circuits may be respectively assigned to the multiple output nodes.

[0136] Such a pull-up path and / or pull-down path may be used to perform test operations as will be described with reference to ​ this.

[0137] ​ is a flowchart showing a method of testing a digital BIST circuit according to an exemplary embodiment of the inventive concept.

[0138] Referring to ​ , ​ and ​, when the temperature measurement circuit enters the test mode (S51), the test signal generator 430 can activate the switch control signal SCD and pull down the output node NO by electrically connecting the output node NO to the ground voltage VSS (S52). Additionally, the test signal generator 430 can generate a test signal TS having a voltage level VH higher than the voltage level VMAX corresponding to the maximum value DLMAX of the digital code DCD to be applied to the analog-to-digital converter 200 (S53).

[0139] The digital logic block 440 can receive a first measured value DLH of the digital code DCD generated when the output node NO is pulled down and the voltage level VH is applied to the analog-to-digital converter 200 (S54). The digital logic block 440 can determine whether the first measured value DLH is equal to the maximum value DLMAX (S55). When the first measured value DLH is not equal to the maximum value DLMAX (S55: No), the digital logic block 440 can activate the floating alarm signal FLT to the logic high level H (S56).

[0140] When the first measured value DLH is equal to the maximum value DLMAX (S55: Yes), the test signal generator 430 can activate the switch control signal SCH and pull up the output node NO by electrically connecting the output node NO to the power supply voltage VDD (S57). Additionally, the test signal generator 430 can generate a test signal TS having a voltage level VL lower than the voltage level VMIN corresponding to the minimum value DLMIN of the digital code DCD to be applied to the analog-to-digital converter 200 (S58).

[0141] The digital logic block 440 can receive a second measured value DLL of the digital code DCD generated when the output node NO is pulled up and the voltage level VL is applied to the analog-to-digital converter 200 (S59). The digital logic block 440 can determine whether the second measured value DLL is equal to the minimum value DLMIN (S60). When the second measured value DLL is not equal to the minimum value DLMIN (S60: No), the digital logic block 440 can activate the floating alarm signal FLT to the logic high level H (S56). When the second measured value DLL is equal to the minimum value DLMIN (S60: Yes), the digital logic block 440 can deactivate the floating alarm signal FLT to the logic low level L (S61).

[0142] In this way, the digital BIST circuit 400 can generate the floating alarm signal FLT based on the first measured value DLH and the second measured value DLL, such that the floating alarm signal FLT can indicate whether the output node NO of the digital code DCD is disconnected.

[0143] ​FIG. 0 is a block diagram showing an analog-to-digital converter included in a temperature measurement circuit according to an exemplary embodiment of the inventive concept.

[0144] Referring ​ , the analog-to-digital converter 200 may include a scan voltage generator 210, a comparator COM 220, a converter 230, and a controller CTRL 240. The scan voltage generator 210, the comparator 220, the converter 230, and the controller 240 may be circuits. Additionally, the analog-to-digital converter 200 may further include: an input selector MUX 250 configured to select one of a temperature-varying voltage VTEM and a test signal TS based on a mode signal MD to apply the selected one to the comparator 220. Using the input selector 250, the test signal TS instead of the temperature-varying voltage VTEM may be applied to the analog-to-digital converter 200 in a test mode.

[0145] As will be described below with reference to ​ and ​ , the scan voltage generator 210 may generate a plurality of scan voltages VS0 to VSq having different voltage levels based on a measurement reference voltage VREF and output the plurality of scan voltages VS0 to VSq one by one at a unit scan time tS. The scan voltage generator 210 may include: a voltage divider 211 configured to generate a plurality of scan voltages VS0 to VSq based on the measurement reference voltage VREF; and a selector MUX 212 configured to select and output one of the plurality of scan voltages VSC based on a selection signal SEL.

[0146] The comparator 220 may generate a plurality of comparison result values CMP by comparing the temperature-varying voltage VTEM or the test signal TS with the plurality of scan voltages VS0 to VSq. The converter 230 may generate a digital code DCD based on the plurality of comparison result values CMP.

[0147] The controller 240 may control the scan voltage generator 210, the comparator 220, and the converter 230. The controller 240 may generate a selection signal SEL for controlling the selector 212. The controller 240 may generate a scan start signal SOS and a conversion start signal SOC for controlling the converter 230. The controller may receive a conversion end signal EOC from the converter 230.

[0148] ​ and ​ FIGS. 24 and 25 are diagrams for describing an example operation of the analog-to-digital converter according to an exemplary embodiment of the inventive concept. ​ FIG. 28 shows an example in which the temperature-varying voltage VTEM corresponds to the value “010” of the digital code DCD. ​ ​ ​Another example showing that the temperature-variable voltage VTEM corresponds to the value "110" of the digital code DCD.

[0149] Reference ​ and ​ , during a plurality of unit scan times tS, a plurality of scan voltages VS0 to VSq can be selected by a binary scan scheme, so as to determine the scan voltage for the next unit scan time based on the comparison result of the comparator 220 during the previous unit scan time. However, the inventive concept is not limited to such a binary scan scheme.

[0150] ​ The counter 410 in [[ ]] can generate a stable alarm signal STT based on the scan start signal SOS and the conversion start signal SOC, so that the stable alarm signal STT can indicate whether the total scan time for outputting a plurality of scan voltages VS0 to VSq from the scan voltage generator 210 is shorter than a first reference time. Here, the total scan time corresponds to N*tS, where N is the number of bits of the digital code DCD and tS is the unit scan time. In addition, the counter 410 can generate a conversion alarm signal CNV based on the conversion start signal SOC and the conversion end signal EOC, so that the conversion alarm signal CNV can indicate whether the conversion time tC for generating the digital code DCD by the converter 230 is shorter than a second reference time.

[0151] ​ is a diagram for describing the transition time of the ramp voltage according to an exemplary embodiment of the inventive concept.

[0152] ​ Shows a first case CASE1 and a second case CASE2 where the scan voltage changes from a first scan voltage VSa to a second scan voltage VSb. The first case CASE1 indicates that the transition time of the change is relatively short, and the second case CASE2 indicates that the transition time of the change is relatively long. If the binary scan scheme is performed based on a relatively short first unit scan time tSa, the transition time of the scan voltage may not be ensured. For example, the measured value DLa in the first case CASE1 can indicate the accurate value of the digital code DCD, while the measured value DLa in the second case CASE2 may include errors. In contrast, if the binary scan scheme is performed based on a relatively long second unit scan time tSb, the transition time of the scan voltage can be ensured. For example, the measured value DLb can indicate the accurate value of the digital code DCD in both the first case CASE1 and the second case CASE2.

[0153] This kind of control of the unit scan time can be used to perform a test operation as described in reference [[ ]] ​ as described.

[0154] ​A flowchart showing a method of testing a digital BIST circuit according to an exemplary embodiment of the inventive concept.

[0155] Reference ​ and ​ When the temperature measurement circuit enters the test mode (S71), the digital BIST circuit 400 may control the analog-to-digital converter 200 such that the analog-to-digital converter 200 may perform a binary scan operation based on the first unit scan time tSa (S72), and the digital logic block 440 may receive a first measured value DLa of the digital code DCD corresponding to the first unit scan time tSa (S73). Additionally, the digital BIST circuit 400 may control the analog-to-digital converter 200 such that the analog-to-digital converter 200 may perform a binary scan operation based on the second unit scan time tSb (S74), and the digital logic block 440 may receive a second measured value DLb of the digital code DCD corresponding to the second unit scan time tSb (S75).

[0156] The digital logic block 440 may determine whether the first measured value DLa is equal to the second measured value DLb (S76). When the first measured value DLa is not equal to the second measured value DLb (S76: No), the digital logic block 440 may activate the fluctuation alarm signal FCT to a logic high level H (S77). Conversely, when the first measured value DLa is equal to the second measured value DLb (S76: Yes), the digital logic block 440 may deactivate the fluctuation alarm signal FCT to a logic low level L (S78).

[0157] In this manner, the digital BIST circuit 400 may generate a fluctuation alarm signal FCT based on the first measured value DLa corresponding to the first unit scan time tSa and the second measured value DLb corresponding to the second unit scan time tSb, such that the fluctuation alarm signal FCT may indicate whether the unit scan time is included within a normal range.

[0158] ​ A diagram showing an example layout of a temperature measurement circuit according to an exemplary embodiment of the inventive concept ​ A circuit diagram showing an example configuration of a temperature measurement circuit according to an exemplary embodiment of the inventive concept ​ of

[0159] Reference ​ and ​ The temperature measurement circuit may include a main circuit 1001 and a plurality of local sensing units SUL1 to SUL3, which are integrated in a semiconductor die SDIE. The main circuit 1001 may include a main sensing unit SUM. The main circuit 1001 may also include a temperature detection circuit and a BIST circuit as described above.

[0160] The main sensing unit SUM may be disposed at the main position POSM and generate a main sensing voltage VBEM that varies according to the main operating temperature at the main position POSM.

[0161] A plurality of local sensing units SUL1 to SUL3 may be disposed at a plurality of local positions POSL1 to POSL3 and generate a plurality of local sensing voltages VBEL1 to VBEL3 that vary according to the local operating temperatures at the plurality of local positions POSL1 to POSL3.

[0162] As ​ shown, the main sensing unit SUM and the plurality of local sensing units SUL1 to SUL3 may be selectively connected to a current source that generates a bias current IBS using switches SWM and SWL1 to SWL3. Control signals SSM and SSL1 to SSL3 for respectively controlling the switches SWM and SWL1 to SWL3 may be provided from a digital logic block 440 in the digital BIST circuit 400, respectively.

[0163] Such sensing units may be used to perform a test operation as described in reference ​ .

[0164] ​ is a flowchart showing a method of testing a digital BIST circuit according to an exemplary embodiment of the inventive concept.

[0165] Reference ​ and ​ , when the temperature measurement circuit enters the test mode (S81), the digital BIST circuit 400 may select the main sensing voltage VBEM generated by the main sensing unit SUM (S82) and receive a first measured value DLM of a digital code DCD corresponding to the main sensing voltage VBEM (S83). Additionally, the digital BIST circuit 400 may select the local sensing voltage VBEL1 generated by the local sensing unit SUL1 closest to the main sensing unit SUM (S84) and receive a second measured value DLL1 of the digital code DCD corresponding to the local sensing voltage VBEL1 (S85).

[0166] The digital logic block 440 may determine whether the absolute difference |DLM - DLL1| between the first measurement value DLM and the second measurement value DLL1 is greater than a reference value RF3 (S86). When the absolute difference |DLM - DLL1| is greater than the reference value RF3 (S86: Yes), the digital logic block 440 may activate the probe check alarm signal PRV to a logic high level H (S87). Conversely, when the absolute difference |DLM - DLL1| is not greater than the reference value RF3 (S86: No), the digital logic block 440 may deactivate the probe check alarm signal PRV to a logic low level L (S88).

[0167] In this manner, the digital BIST circuit 400 may generate the probe check alarm signal PRV based on the first measurement value DLM corresponding to the main sense voltage VBEM and the second measurement value DLL1 corresponding to the local sense voltage VBEL1.

[0168] ​ FIG. is a diagram of a semiconductor integrated circuit including a temperature measurement circuit according to an exemplary embodiment of the inventive concept.

[0169] Reference ​ Referring to, the semiconductor integrated circuit 2000 may include an internal circuit 30, a temperature detection circuit 10, a BIST circuit 20, and a control circuit 40, which are integrated in the same semiconductor die SDIE. In an exemplary embodiment of the inventive concept, the control circuit 40 may be disposed in another semiconductor die. The semiconductor die SDIE may include a semiconductor substrate SUP and a dielectric layer DLY over the semiconductor substrate SUB. The temperature detection circuit 10 may detect the operating temperature of the internal circuit 30, and the BIST circuit 20 may monitor whether the temperature detection circuit 10 is operating normally. As described, the BIST circuit 20 may provide a flag signal and / or an alarm signal as a monitoring result to the control circuit 40. The control circuit 40 may control the semiconductor integrated circuit 2000 based on the flag signal and / or the alarm signal.

[0170] ​ FIG. is a diagram of an operation of a system including a temperature measurement circuit according to an exemplary embodiment of the inventive concept.

[0171] Reference ​, when the system is powered on (S100), the temperature measurement circuit can perform a test operation (S200) in response to the power-on signal PWO. When the temperature measurement circuit is operating normally (without faults), the temperature measurement circuit can detect the operating temperature of the system (S300). When the temperature measurement circuit is operating abnormally (faulty), the system can enter the safe mode (S400), and the above-mentioned flag signal FG and / or alarm signal ALM can be provided by the BIST circuit included in the temperature measurement circuit. The system can set the temperature measurement circuit to the off mode based on the flag signal FG and / or alarm signal ALM (S500). The system can power off the temperature measurement circuit (S600) in response to the power-off signal PWD to prevent the output of the temperature measurement circuit or save power consumption.

[0172] As described above, the BIST circuit and the temperature measurement circuit according to the exemplary embodiment of the inventive concept can effectively diagnose faults in the temperature measurement circuit by using the BIST circuit to monitor whether a plurality of voltages are within the normal range.

[0173] In addition, the BIST circuit and the temperature measurement circuit according to the exemplary embodiment of the inventive concept can effectively diagnose the analog-to-digital converter included in the temperature measurement circuit by performing various tests using the digital BIST circuit.

[0174] The inventive concept can be applied to any electronic device and system that requires information about the operating temperature. For example, the inventive concept can be applied to various systems, such as memory cards, solid state drives (SSDs), embedded multimedia cards (eMMCs), universal flash storage (UFSs), mobile phones, smart phones, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, video recorders, personal computers (PCs), servo computers, workstations, laptop computers, digital TVs, set-top boxes, portable game consoles, navigation systems, wearable devices, Internet of Things (IoT) devices, Internet of Everything (IoE) devices, e-books, virtual reality (VR) devices, augmented reality (AR) devices, etc.

[0175] Although the inventive concept has been shown and described with reference to the exemplary embodiments of the inventive concept, it will be apparent to those of ordinary skill in the art that various changes in form and detail can be made therein without departing from the spirit and scope of the inventive concept set forth in the appended claims.

Claims

1. A temperature measurement circuit, comprising: A bandgap reference circuit configured to generate a fixed bandgap reference voltage independent of the operating temperature; A reference voltage generator circuit configured to generate a measurement reference voltage by adjusting the bandgap reference voltage; A sensing circuit configured to generate a temperature-varying voltage based on a bias current, wherein the temperature-varying voltage varies according to the operating temperature; An analog-to-digital converter circuit configured to generate a first digital code indicative of the operating temperature based on the measurement reference voltage and the temperature-varying voltage; and A digital built-in self-test (BIST) circuit configured to: Apply a test signal to the analog-to-digital converter circuit instead of the temperature-varying voltage, Receive a second digital code from the analog-to-digital converter circuit, and Generate a plurality of alarm signals based on the second digital code, wherein the plurality of alarm signals indicate the operating state of the analog-to-digital converter circuit.

2. The temperature measurement circuit according to claim 1, wherein the digital built-in self-test BIST circuit comprises: A test signal generator circuit configured to generate a ramp voltage having sequentially increasing or decreasing voltage levels and apply the ramp voltage as the test signal to the analog-to-digital converter circuit.

3. The temperature measurement circuit according to claim 2, wherein, The digital built-in self-test BIST circuit is configured to generate at least one of a monotonic alarm signal or a linear alarm signal based on a plurality of values of the second digital code, wherein the monotonic alarm signal indicates whether the second digital code monotonically increases or decreases, and wherein the linear alarm signal indicates whether the second digital code changes uniformly.

4. The temperature measurement circuit according to claim 1, wherein, The test signal has a voltage level corresponding to the center value of the second digital code, and wherein the digital built-in self-test BIST circuit is configured to apply the test signal to the analog-to-digital converter circuit to generate an offset alarm signal, the offset alarm signal indicating whether the difference between the measured value of the second digital code and the center value of the second digital code is greater than a reference value.

5. The temperature measurement circuit according to claim 1, wherein, The test signal has a voltage level higher than the voltage level corresponding to the maximum value of the second digital code, and wherein the digital built-in self-test BIST circuit is configured to apply the test signal to the analog-to-digital converter circuit to generate a clipping alarm signal, the clipping alarm signal indicating whether a first measured value of the second digital code is equal to the maximum value of the second digital code.

6. The temperature measurement circuit according to claim 1, wherein the digital built-in self-test BIST circuit comprises: A pull-up resistor connected to a power supply voltage; A pull-up switch configured to control the electrical connection between the pull-up resistor and the output node of the second digital code; A pull-down resistor connected to a ground voltage; And A pull-down switch configured to control the electrical connection between the pull-down resistor and the output node of the second digital code.

7. The temperature measurement circuit according to claim 6, wherein, The digital built-in self-test BIST circuit is configured to: Apply a first test signal having a voltage level higher than the voltage level corresponding to the maximum value of the second digital code to the analog-to-digital converter circuit when the pull-down switch is turned on, When the pull-up switch is turned on, a second test signal having a voltage level lower than the voltage level corresponding to the minimum value of the second digital code is applied to the analog-to-digital converter circuit, and generate a floating alarm signal that indicates at least one of the following: whether a first measured value of the second digital code is equal to the maximum value of the second digital code, or whether a second measured value of the second digital code is equal to the minimum value of the second digital code.

8. The temperature measurement circuit according to claim 1, wherein, The analog-to-digital converter circuit includes: a scan voltage generator circuit configured to generate a plurality of scan voltages having different voltage levels based on the measured reference voltage and output the plurality of scan voltages one by one according to a unit scan time; a comparator circuit configured to generate a plurality of comparison result values by comparing the temperature-varying voltage with the plurality of scan voltages; a converter circuit configured to generate the second digital code based on the plurality of comparison result values; and a controller circuit configured to control the scan voltage generator circuit, the comparator circuit, and the converter circuit.

9. The temperature measurement circuit according to claim 8, wherein, The digital built-in self-test (BIST) circuit is configured to: change the unit scan time between a first unit scan time and a second unit scan time longer than the first unit scan time, and generate a fluctuation alarm signal that indicates whether a first measured value of the second digital code corresponding to the first unit scan time is equal to a second measured value of the second digital code corresponding to the second unit scan time.

10. The temperature measurement circuit according to claim 8, wherein, The digital built-in self-test (BIST) circuit includes a counter configured to monitor the operation timing of the analog-to-digital converter circuit, and wherein the digital built-in self-test (BIST) circuit is configured to generate at least one of a stable alarm signal or a conversion alarm signal using the counter, wherein the stable alarm signal indicates whether a total scan time for outputting the plurality of scan voltages from the scan voltage generator circuit is shorter than a first reference time, and wherein the conversion alarm signal indicates whether a conversion time for generating the second digital code by the converter circuit is shorter than a second reference time.

11. The temperature measurement circuit according to claim 1, comprising: a main sensing unit disposed at a main position and configured to generate a main sensing voltage that varies according to a main operating temperature at the main position; and a plurality of local sensing units disposed at a plurality of local positions and configured to generate a plurality of local sensing voltages that vary according to local operating temperatures at the plurality of local positions.

12. The temperature measurement circuit according to claim 11, wherein, The digital built-in self-test (BIST) circuit is configured to: receive a first measured value of the second digital code corresponding to the main sensing voltage and a second measured value of the second digital code corresponding to a local sensing voltage provided by a local sensing unit closest to the main sensing unit among the plurality of local sensing units, and generate a probe check alarm signal that indicates whether a difference between the first measured value and the second measured value is less than a reference value.

13. The temperature measurement circuit according to claim 11 further includes: An analog built-in self-test (BIST) circuit configured to generate: A first flag signal indicating whether the bandgap reference voltage is within a first predetermined range, A second flag signal indicating whether the measurement reference voltage is within a second predetermined range, and A third flag signal indicating whether the bias voltage corresponding to the bias current is within a third predetermined range.

14. The temperature measurement circuit according to claim 13, wherein, The analog built-in self-test (BIST) circuit includes: A power supply voltage divider circuit configured to generate a power supply voltage division corresponding to the lowest limit level of the bandgap reference voltage by dividing the power supply voltage; and A comparator circuit configured to compare the bandgap reference voltage with the power supply voltage division and activate the first flag signal in response to the bandgap reference voltage being lower than the lowest limit level of the bandgap reference voltage.

15. The temperature measurement circuit according to claim 13, wherein, The analog built-in self-test (BIST) circuit includes: A bandgap reference voltage divider circuit configured to generate a first bandgap voltage division corresponding to the highest limit level of the measurement reference voltage and a second bandgap voltage division corresponding to the lowest limit level of the measurement reference voltage by dividing the bandgap reference voltage; A measurement reference voltage divider circuit configured to generate a measurement voltage division by dividing the measurement reference voltage; and A comparator circuit configured to compare the measurement voltage division with the first bandgap voltage division and the second bandgap voltage division and activate the second flag signal in response to the measurement reference voltage being higher than the highest limit level of the measurement reference voltage or lower than the lowest limit level of the measurement reference voltage.

16. The temperature measurement circuit according to claim 13, wherein, The analog built-in self-test (BIST) circuit includes: A measurement reference voltage divider circuit configured to generate a first measurement reference voltage division corresponding to the highest limit level of the bias voltage and a second measurement reference voltage division corresponding to the lowest limit level of the bias voltage by dividing the measurement reference voltage; A current-voltage converter circuit configured to generate the bias voltage based on the bias current; and A comparator circuit configured to compare the bias voltage with the first measurement reference voltage division and the second measurement reference voltage division and activate the third flag signal in response to the bias voltage being higher than the highest limit level of the bias voltage or lower than the lowest limit level of the bias voltage.

17. The temperature measurement circuit according to claim 16, wherein the sensing circuit includes a first current source configured to generate the bias current, and the current-voltage converter circuit includes a second current source configured to generate the bias current, such that the first current source and the second current source form a current mirror.

18. The temperature measurement circuit according to claim 13, wherein the analog built-in self-test (BIST) circuit includes: A bandgap reference voltage monitoring circuit configured to activate the first flag signal based on the bandgap reference voltage and the power supply voltage in response to the bandgap reference voltage deviating from the first predetermined range; A measurement reference voltage monitoring circuit configured to activate the second flag signal based on the measurement reference voltage and the bandgap reference voltage in response to the measurement reference voltage deviating from the second predetermined range; and a bias voltage monitoring circuit configured to activate the third flag signal based on the bias voltage and the measurement reference voltage in response to the bias voltage deviating from the third predetermined range.

19. A temperature measurement circuit, comprising: A temperature detection circuit, comprising: An analog circuit configured to generate a fixed measurement reference voltage independent of the operating temperature and a temperature-varying voltage that varies according to the operating temperature; and An analog-to-digital converter circuit configured to generate a first digital code indicating the operating temperature based on the measurement reference voltage and the temperature-varying voltage; and A digital built-in self-test (BIST) circuit configured to: Apply a test signal to the analog-to-digital converter circuit instead of the temperature-varying voltage, Receive a second digital code from the analog-to-digital converter circuit, and Generate a plurality of alarm signals based on the second digital code, wherein the plurality of alarm signals indicate the operating state of the analog-to-digital converter circuit.

20. A temperature measurement circuit, comprising: An analog circuit configured to generate a fixed measurement reference voltage independent of the operating temperature and a temperature-varying voltage that varies according to the operating temperature; An analog-to-digital converter circuit configured to generate a first digital code indicating the operating temperature based on the measurement reference voltage and the temperature-varying voltage in a normal mode, and to generate a second digital code based on a test signal in a test mode; An analog built-in self-test (BIST) circuit configured to generate a corresponding flag signal for each of a plurality of monitored voltages of the analog circuit, the flag signal indicating whether the monitored voltage is within a corresponding predetermined range; and A digital built-in self-test (BIST) circuit configured to apply the test signal to the analog-to-digital converter circuit in the test mode and to generate an alarm signal indicating the operating state of the analog-to-digital converter circuit based on the second digital code.

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