Multi-mode scan cell, side scan chain circuit and bidirectional scan chain circuit

Abstract

The application provides a multi-mode scan unit, a side scan chain circuit and a bidirectional scan chain circuit, and relates to the technical field of digital circuits.The application provides a multi-mode scan unit, which realizes the switching of a function mode, a test mode and a diagnosis mode through different voltage levels of a single scan enable signal.The design uses a method of combining a diagnostic device with a double multiplexer, reduces the demand for global signals, simplifies the control logic, reduces the layout and wiring complexity, optimizes the test and diagnosis efficiency, and improves the accuracy of fault diagnosis.The application also provides a side scan chain circuit and a bidirectional scan chain circuit based on the multi-mode scan unit, optimizes the scan chain structure, and reduces the use of global signals.In particular, the side scan chain is used to realize the transmission of scan data to the side, and the bidirectional scan chain supports the bidirectional loading and unloading of scan data, both of which improve the diagnosis efficiency and accuracy, and enhance the circuit stability and test flexibility.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of digital circuit, in particular to the field of integrated circuit testability design and diagnosis. BACKGROUND

[0002] In the process of integrated circuit manufacturing, physical defects may affect the functional completeness of the chip, which must be identified and located by systematic testing means. The traditional method detects faults by applying specific test vectors and analyzing the difference in output response, while in order to improve test efficiency and coverage, testability design is introduced in the design stage, such as replacing the timing unit with a scan unit to form a scan chain structure. However, the scan chain itself has become a major source of chip defects, and the fault phenomenon reflects process deviation or design defects, and accurate positioning of these faults is the key to improving chip yield. The traditional hardware scan chain diagnosis method realizes multi-mode switching by adding multiplexers and global control signals, which improves the diagnosis accuracy, but also introduces new challenges. These methods increase the complexity of layout and wiring, the risk of signal interference, and occupy additional IO resources, making the control logic more complex. SUMMARY

[0003] The present application provides a multi-mode scan unit, a side scan chain circuit and a bidirectional scan chain circuit to solve one or more technical problems existing in the prior art, at least to provide a beneficial choice or create conditions.

[0004] In one aspect, the present application provides a multi-mode scan unit, which comprises a connection component, a first multiplexer, a second multiplexer, a D flip-flop and a diagnostic device.

[0005] The input end of the diagnostic device and the control end of the first multiplexer are connected to the scan enable control end of the scan unit; the scan enable control end is used for receiving a scan enable signal, and generating a control signal according to the voltage level of the scan enable signal to control the scan unit to switch between a functional mode, a test mode and a diagnostic mode;

[0006] The output end of the second multiplexer is connected to the second input end of the first multiplexer;

[0007] The control end of the second multiplexer is connected to the output end of the diagnostic device;

[0008] The output end of the first multiplexer is connected to the data input end of the D flip-flop;

[0009] When the scan enable signal is a first voltage, the scan unit executes a functional mode, and the first multiplexer selects to receive functional logic data through its first input end;

[0010] when the scan enable signal is the second voltage, the scan unit executes a test mode, the first multiplexer selects to receive the scan data from the second input end of the second multiplexer through the second input end thereof;

[0011] when the scan enable signal is the third voltage, the scan unit executes a diagnosis mode, the first multiplexer selects to receive the scan data from the second input end of the second multiplexer through the second input end thereof.

[0012] Further, the first voltage is a ground voltage, the second voltage is a power supply voltage, and the third voltage is a diagnosis enable voltage; the diagnosis enable voltage is higher than the power supply voltage.

[0013] Further, the connection component, the first multiplexer, the second multiplexer, the D flip-flop, and the diagnosis unit are integrated into the scan unit;

[0014] The scan unit comprises a first input end, a second input end, a third input end, a scan enable control end, and an output end;

[0015] The first input end of the first multiplexer serves as the first input end of the scan unit;

[0016] The first input end of the second multiplexer serves as the second input end of the scan unit;

[0017] The second input end of the second multiplexer serves as the third input end of the scan unit;

[0018] The data output end of the D flip-flop serves as the output end of the scan unit, and the clock end of the D flip-flop serves as the clock end of the scan unit;

[0019] when the scan enable signal is the first voltage, the scan unit selects to receive the functional logic data through the first input end thereof and executes a functional mode;

[0020] when the scan enable signal is the second voltage, the scan unit selects to receive the scan data through the second input end thereof and executes a test mode;

[0021] when the scan enable signal is the third voltage, the scan unit selects to receive the scan data through the third input end thereof and executes a diagnosis mode.

[0022] Further, the diagnosis unit comprises a PMOS transistor, a first NMOS transistor, and a second NMOS transistor;

[0023] The gate of the PMOS transistor is fixed to a power supply voltage, the source thereof is connected to the input terminal of the diagnostic device, and the drain thereof is connected to the output terminal of the diagnostic device and the source of the first NMOS transistor;

[0024] The gate of the first NMOS transistor is fixed to a power supply voltage;

[0025] The gate and the source of the second NMOS transistor are interconnected and are commonly connected to the drain of the first NMOS transistor to form a voltage clamping circuit in a diode structure, and the drain of the second NMOS transistor is grounded.

[0026] Further, when the voltage level of the scan enable signal is a ground voltage, the PMOS transistor is turned off, the first NMOS transistor is turned on, and the voltage of the output terminal of the diagnostic device is pulled down to the ground voltage;

[0027] When the voltage level of the scan enable signal is a power supply voltage, the PMOS transistor is turned off, the first NMOS transistor is turned on, and the voltage of the output terminal of the diagnostic device is pulled down to the ground voltage;

[0028] When the voltage level of the scan enable signal is a diagnostic enable voltage, the PMOS transistor is turned on, the first NMOS transistor is turned off, and the voltage of the output terminal of the diagnostic device is raised to the diagnostic enable voltage.

[0029] Further, the diagnostic enable voltage is twice the power supply voltage.

[0030] In another aspect, the present application provides a multi-mode side scan chain circuit, comprising the aforementioned multi-mode scan unit and connection assembly, a plurality of the scan units form at least two parallel side scan chains, and the number of scan units in each side scan chain is consistent;

[0031] The connection mode of the side scan chain circuit is as follows:

[0032] For each scan unit, the first input terminal thereof is connected to a functional logic data input interface, the scan enable control terminal thereof is connected to a scan enable signal input interface, and the output terminal thereof is connected to a functional logic circuit;

[0033] For each side scan chain, the output terminal of each scan unit is further connected to the third input terminal of a scan unit at the same position in the next side scan chain, the output terminal of a scan unit at the first position and the intermediate positions is further connected to the second input terminal of the next scan unit in the same side scan chain, and the output terminal of a scan unit at the last position is connected to a scan data output interface.

[0034] For the first edge scan chain, the second input end of the first scan cell is connected to the scan data input interface; for the second and subsequent edge scan chains, the third input end of each scan cell is connected to the output end of the same-order scan cell in the previous edge scan chain, and the output end of each scan cell of the last edge scan chain is connected to the scan data output interface.

[0035] Further, when the scan enable signal is a ground voltage, the edge scan chain circuit executes a functional mode, and the scan cells in each edge scan chain receive functional logic data through the first input end thereof and output to the functional logic circuit;

[0036] When the scan enable signal is a power supply voltage, the edge scan chain circuit executes a test mode, and the first scan cell of each edge scan chain receives scan data from the scan data input interface and transmits the scan data to the scan data output interface step by step along the same edge scan chain;

[0037] When the scan enable signal is a diagnostic enable voltage, the edge scan chain circuit executes a diagnostic mode, and in the second and subsequent edge scan chains, each scan cell receives the scan data from the output end of the same-order scan cell in the previous edge scan chain through the third input end thereof, transmits the scan data across the chains along the adjacent edge scan chain, and each scan cell of the last edge scan chain transmits the scan data to the scan data output interface through the output end thereof.

[0038] In another aspect, the application provides a multi-mode bidirectional scan chain circuit, comprising the multi-mode scan cell and the connection assembly described above, and a plurality of scan cells constitute a bidirectional scan chain, and in the bidirectional scan chain, the connection mode of each scan cell is as follows:

[0039] The first input end of each scan cell is connected to a functional logic data input interface, the scan enable control end thereof is connected to a scan enable signal input interface, and the output end thereof is connected to a functional logic circuit;

[0040] The output end of each scan cell is further connected to the second input end of the next scan cell to constitute a forward test path.

[0041] The output end of each scan cell is further connected to the third input end of the previous scan cell to constitute a reverse diagnostic path.

[0042] In the bidirectional scan chain, the second input end of the first scan cell is connected to a scan data input interface, the output end of the first scan cell is connected to a scan data output interface, and the output end of the last scan cell is connected to the scan data output interface.

[0043] Further, when the scan enable signal is a ground voltage, the bidirectional scan chain circuit executes a function mode, and a scan cell in the bidirectional scan chain receives function logic data through the first input end thereof and outputs to the function logic circuit;

[0044] When the scan enable signal is a power supply voltage, the bidirectional scan chain circuit executes a test mode, and a first scan cell of the bidirectional scan chain receives scan data from the scan data input interface, transmits the scan data along the forward test path to a last scan cell, and outputs to the scan data output interface through the output end thereof;

[0045] When the scan enable signal is a diagnosis enable voltage, the bidirectional scan chain circuit executes a diagnosis mode, and the last scan cell of the bidirectional scan chain transmits the scan data along the reverse diagnosis path to the first scan cell and outputs to the scan data output interface through the output end thereof.

[0046] The application has the advantages that: the application provides a multi-mode scan cell, and switches between a function mode, a test mode and a diagnosis mode through different voltage levels of a single scan enable signal. The design uses a method of combining a diagnostic instrument with a double multiplexer, reduces the demand for global signals, simplifies the control logic, reduces the layout and wiring complexity, and thus optimizes the test and diagnosis efficiency, improves the accuracy of fault diagnosis, and improves the circuit stability and test flexibility.

[0047] Other features and advantages of the application will be set forth in the following description, and in part will become apparent to those skilled in the art from the description, or can be learned by practice of the application. The objects and other advantages of the application will be realized and attained by the structure particularly pointed out in the written description and claims thereof as well as the appended drawings. BRIEF DESCRIPTION OF DRAWINGS

[0048] The accompanying drawings are included to provide a further understanding of the technical solutions of the application, and constitute a part of the specification, and are used to explain the technical solutions of the application together with the embodiments of the application, and do not constitute a limitation on the technical solutions of the application.

[0049] Figure 1 is an internal structure diagram of the multi-mode scan cell provided by the application;

[0050] Figure 2 is an overall structure diagram of the multi-mode scan cell provided by the application;

[0051] Figure 3 is a structural diagram of a diagnostic device provided by the present application;

[0052] Figure 4 is a structural diagram of a side scan chain circuit provided by the present application;

[0053] Figure 5 is a structural diagram of a bidirectional scan chain circuit provided by the present application. DETAILED DESCRIPTION

[0054] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application is further described in detail below in combination with the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and do not limit the present application.

[0055] The present application is further described below in combination with the drawings and specific embodiments of the present application. The described embodiments should not be considered as limiting the present application, and all other embodiments obtained by those of ordinary skill in the art without making creative efforts fall within the scope of protection of the present application.

[0056] In the following description, "some embodiments" are described, which describe a subset of all possible embodiments, but it can be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments, and can be combined with each other without conflict.

[0057] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present application belongs. The terms used herein are only for the purpose of describing the embodiments of the present application and are not intended to limit the present application.

[0058] Various physical defects can occur in the integrated circuit manufacturing process, and to ensure the completeness of the chip function, systematic testing means must be used to identify and locate faults. The traditional digital integrated circuit testing method detects faults by applying specific test vectors to the circuit under test and analyzing the difference between the output response and the expected value. In order to improve test efficiency and coverage, testability design is introduced at the design stage, such as replacing timing units with scan units and interconnecting them to form a scan chain structure. However, the scan chain itself has become a major source of chip defects, and its fault phenomenon reflects process deviations or design defects, so accurate positioning and diagnosis of scan chain faults have become a key link to improve chip yield.

[0059] The hardware-based scan chain fault diagnosis core process includes loading multiple sets of test vectors, collecting output responses to generate fault logs, and analyzing and positioning fault data. Although scan chain technology is widely used, its fault diagnosis still faces the challenges of accurate positioning and high proportion of defects. Therefore, the industry has proposed innovative solutions such as side scan and bidirectional scan, which optimize the scan chain structure or add diagnosis logic to shorten the diagnosis time and improve the accuracy, thereby effectively improving the chip production yield.

[0060] In the prior art, the main idea of hardware-based scan chain diagnosis is to change the scan chain structure, add additional hardware or modify part of the hardware structure based on the original to obtain better diagnosis results. For example, the side scan and bidirectional scan technologies both add multiplexer hardware modules to the original scan unit module to improve the diagnosis capability, and rely on newly added control signals to realize mode switching. However, these solutions require additional global signals, increasing the layout complexity, signal path length, and power consumption, limiting the chip expansion capability and function implementation. Moreover, in the modern integrated circuit design and test environment, layout complexity, excessive number of global signals, and limited chip IO resources are common problems. These problems not only increase the design difficulty, but also may cause signal interference and conflict, reducing circuit stability.

[0061] To address the problems in the related art, the embodiments of the present application provide a multi-mode scan unit, a side scan chain circuit, and a bidirectional scan chain circuit. First, the embodiments of the present application realize three working modes through voltage level switching of the scan enable signal, without additional global signals, effectively reducing the number of signals and control logic complexity, and reducing the layout difficulty. Second, by integrating the diagnostic device with the multiplexer, the number of transistors and area overhead is reduced, and the power consumption and manufacturing cost are reduced. In addition, the multi-mode scan unit supports the side scan chain circuit and the bidirectional scan chain circuit, supports flexible transmission of test signals and diagnostic signals, and enhances the fault positioning capability.

[0062] First, the multi-mode scan unit provided by the embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0063] Referring to Figure 1 The multi-mode scan unit provided by the embodiments of the present application includes a connection component, a first multiplexer MUX1, a second multiplexer MUX2, a D flip-flop DFF, and a diagnostic device. These components work together to form a comprehensive circuit that can support multiple operating modes. This design enables a single scan unit not only to perform basic data processing functions, but also to effectively operate in test and diagnostic modes, effectively enhancing the functionality and flexibility of integrated circuits.

[0064] The input end D_i of the diagnostic device and the control end of the first multiplexer MUX1 are connected to the scan enable control end SE_i of the scan unit. The scan enable control end is used to receive a scan enable signal and generate a control signal according to the voltage level of the scan enable signal to control the scan unit to switch between the functional mode, the test mode and the diagnostic mode. By connecting the input end D_i of the diagnostic device and the control end of the first multiplexer MUX1 to the scan enable control end SE_i of the scan unit, the working mode of the scan unit is dynamically switched according to different voltage levels of the scan enable signal.

[0065] The output end of the second multiplexer MUX2 is connected to the second input end of the first multiplexer MUX1, and the control end of the second multiplexer MUX2 is connected to the output end D_O of the diagnostic device. The output end of the second multiplexer MUX2 is connected to the second input end of the first multiplexer MUX1, which is to pass the selected data in the test or diagnostic mode to the first multiplexer MUX1. At the same time, the control end of the second multiplexer MUX2 is connected to the output end D_O of the diagnostic device, so that the diagnostic device can determine which input end data the second multiplexer MUX2 should select according to different voltage levels. This design improves the flexibility and response speed of the system.

[0066] The output end of the first multiplexer MUX1 is connected to the data input end DFF_i of the D flip-flop DFF. In this way, the first multiplexer MUX1 can direct the data (such as functional logic data, scan data or diagnostic data) from different sources to the D flip-flop DFF for processing when switching between the functional mode, the test mode and the diagnostic mode, ensuring the consistency and reliability of the data flow, simplifying the circuit design, and improving the working efficiency and stability of the entire scan unit in different operating modes.

[0067] When the scan enable signal is the first voltage, the scan unit executes the functional mode, and the first multiplexer MUX1 selects to receive the functional logic data through the first input end thereof, so that the scan unit can normally execute the predetermined logic function. This setting ensures that when testing or diagnosis is not needed, the system can focus on core task processing and maintain efficient operation.

[0068] When the scan enable signal is the second voltage, the scan unit executes the test mode, and the first multiplexer MUX1 selects to receive the scan data from the first input end of the second multiplexer MUX2 through the second input end thereof, which allows the circuit to be comprehensively detected to identify potential faults or performance bottlenecks and improve the overall quality of the product.

[0069] When the scan enable signal is at the third voltage, the scan unit executes a diagnostic mode, and the first multiplexer MUX1 selects to receive the scan data from the second input of the second multiplexer MUX2 through its second input. The purpose of this is to analyze possible problems in depth, provide accurate fault location and repair suggestions, and effectively improve the efficiency and accuracy of fault diagnosis.

[0070] In some embodiments of the present application, the first voltage is a ground voltage, the second voltage is a power supply voltage, and the third voltage is a diagnostic enable voltage; the diagnostic enable voltage is higher than the power supply voltage.

[0071] In some embodiments of the present application, the first voltage is set to a ground voltage, i.e., a logic low level or 0V. This voltage level is used to indicate that the scan unit enters a functional mode, in which the device performs its predetermined functional operation. Selecting the ground voltage as the trigger condition for the functional mode ensures that the system can operate in the most direct and energy-efficient manner, while simplifying the design of the control logic.

[0072] The second voltage is set to a power supply voltage, which usually corresponds to a logic high level. When the scan enable signal is at this voltage level, the scan unit switches to a test mode and receives scan data from the second input I2 for circuit testing. Using the power supply voltage as the trigger signal for the test mode not only facilitates differentiation from the functional mode, but also achieves standard logic high level, ensuring the reliability and compatibility of the entire system.

[0073] The third voltage is defined as a diagnostic enable voltage, which is set to a specific value higher than the power supply voltage. This higher voltage level is specifically used to activate the diagnostic mode of the scan unit, allowing scan data to be received from the third input I3 for detailed fault analysis and positioning. Using a diagnostic enable voltage higher than the power supply voltage can effectively prevent false triggering, ensuring that the diagnostic mode is only entered when explicit deep diagnosis is required, enhancing the accuracy and reliability of the system. In addition, this design also ensures that the diagnostic mode can be triggered stably even in the case of voltage fluctuations, improving the robustness of the system.

[0074] In some embodiments of the present application, the diagnostic enable voltage is twice the power supply voltage.

[0075] In some embodiments of the present application, the diagnostic enable voltage is set to twice the power supply voltage, which ensures that it can be significantly distinguished from the voltage levels in the conventional operation and test modes, providing a clear and non-confusing high-level signal for triggering the diagnostic mode. By using a specific voltage value higher than the ordinary power supply voltage, false operations caused by voltage fluctuations or noise can be effectively avoided, thereby enhancing the reliability and stability of the system.

[0076] In some embodiments of the present application, the diagnostic enable voltage can be accurately obtained by an automatic test equipment (ATE) machine during testing, or can be introduced from an external pin or port to adapt to different testing environments and requirements. Using the ATE machine can ensure the accuracy and stability of the voltage, which is suitable for complex diagnostic tasks that require high precision control. Introducing the voltage from the external pin increases flexibility, supports on-site debugging or preliminary functional verification in the absence of an ATE machine, reduces dependence on special equipment, and speeds up the testing iteration speed during development. These two methods together improve the testability and maintainability of the system.

[0077] In some embodiments of the present application, with reference to Figure 2 The multi-mode scan unit provided by the embodiments of the present application includes a first input end I1, a second input end I2, a third input end I3, a scan enable control end SE_i, and an output end Sout.

[0078] The first input end of the first multiplexer MUX1 is the first input end I1 of the scan unit, used to receive functional logic data during normal operation. This design ensures that when the functional mode is executed, data can directly enter the first multiplexer MUX1 from the first input end I1 of the scan unit and be further transmitted to subsequent components for processing. Such a configuration ensures the continuity and stability of the system during daily operation.

[0079] The first input end of the second multiplexer MUX2 is the second input end I2 of the scan unit, used to receive scan data in test mode; and the second input end of the second multiplexer MUX2 is the third input end I3 of the scan unit, used to receive scan data in diagnostic mode. In this way, the scan unit can select the correct data flow path according to the current working mode, ensuring the accuracy of data during testing and diagnosis.

[0080] The data output end DFF_O of the D flip-flop DFF is the output end Sout of the scan unit, and the clock end CLK of the D flip-flop DFF is the clock end CLK of the scan unit, connected to the system clock Sys_CLK. The data output end DFF_O of the D flip-flop DFF is the output end Sout of the scan unit, providing an output path for processed data. In addition, the clock end CLK of the D flip-flop DFF is connected to the system clock Sys_CLK, ensuring that all operations are performed under precise time control, maintaining the synchronization and stability of the system.

[0081] The scan enable control end SE_i is used to receive a scan enable signal and generate a control signal according to the voltage level of the scan enable signal to control the scan unit to switch between the functional mode, the test mode, and the diagnostic mode.

[0082] The first input terminal I1 is configured to receive functional logic data; the second input terminal I2 and the third input terminal I3 are configured to receive scan data.

[0083] When the scan enable signal is at the first voltage, the scan unit is configured to receive the functional logic data from the first input terminal I1 and execute a functional mode; when the scan enable signal is at the second voltage, the scan unit is configured to receive the scan data from the second input terminal I2 and execute a test mode; when the scan enable signal is at the third voltage, the scan unit is configured to receive the scan data from the third input terminal I3 and execute a diagnosis mode.

[0084] The multi-mode scan unit provided by the embodiments of the present application first sets the first input terminal I1, the second input terminal I2, the third input terminal I3, the scan enable control terminal SE_i and the output terminal Sout, which provide a hardware basis for implementing multiple operation modes. Each terminal has a specific function: the first input terminal I1 is configured to receive functional logic data required in a normal operation process; the second input terminal I2 and the third input terminal I3 are designed for test and diagnosis processes and are configured to receive corresponding scan data.

[0085] The scan enable control terminal SE_i is the core part of the entire scan unit, which is responsible for receiving a scan enable signal and generating a corresponding control signal according to the voltage level of the signal. This voltage level-based control mechanism enables the scan unit to flexibly switch between different operation modes, including a functional mode, a test mode and a diagnosis mode. Through a single control terminal, effective management of the three modes can be achieved, greatly simplifying the complexity of the system and improving the efficiency.

[0086] When the scan enable signal is at the first voltage, it indicates that the system should execute normal functional operations. At this time, the scan unit automatically selects the data received from the first input terminal I1 for processing, that is, executes the functional mode. This mode ensures the normal operation of the device in daily use and meets the basic needs of users.

[0087] If the scan enable signal is adjusted to the second voltage, it indicates that the system enters the test mode. In this case, the scan unit receives preset scan data from the second input terminal I2 to detect the correctness and performance of the circuit. The test mode is crucial for verifying whether the product meets the specifications after manufacturing is completed and helps to find potential problems early.

[0088] Finally, when the scan enable signal reaches the third voltage, the scan unit enters the diagnosis mode. In this mode, the scan unit receives specially designed scan data through the third input terminal I3 for in-depth analysis and positioning of possible faults in the circuit. The diagnosis mode provides a method for detailed examination of the hardware state, supports more accurate problem solving strategies, and thus improves the reliability and maintenance efficiency of the product.

[0089] In some embodiments of the present application, the structure composed of two multiplexers in the scanning unit and the diagnostic device is equivalent to a three-to-one multiplexer. Unlike ordinary three-to-one multiplexers, this special structure can select according to three different states of a signal.

[0090] In some embodiments of the present application, with reference to Figure 3 , the diagnostic device includes a PMOS transistor M1, a first NMOS transistor M2, and a second NMOS transistor M3 to achieve accurate voltage level detection and control. The gate G1 of the PMOS transistor M1 is fixedly connected to the power supply voltage , the source S1 of which is connected to the input end D_i of the diagnostic device, and the drain D1 of which is connected to the output end D_O of the diagnostic device and the source S2 of the first NMOS transistor M2.

[0091] A PMOS (P-channel Metal-Oxide-Semiconductor) transistor is a type of field-effect transistor whose operation is based on P-type semiconductor material. The gate (Gate), source (Source), and drain (Drain) are the main components of a PMOS transistor. In a PMOS transistor, when the gate voltage is lower than the source voltage, the transistor is turned on, allowing current to flow from the source to the drain; otherwise, when the gate voltage is higher than the source voltage, the transistor is turned off, preventing current flow. In a scan chain diagnostic circuit, PMOS transistors are often used to control the transmission path of signals, especially when a specific voltage signal needs to be passed to the subsequent circuit.

[0092] An NMOS (N-channel Metal-Oxide-Semiconductor) transistor is also a type of field-effect transistor, but its operation is based on N-type semiconductor material. NMOS transistors also have a gate (Gate), source (Source), and drain (Drain). Unlike PMOS transistors, NMOS transistors are turned on when the gate voltage is higher than the source voltage, allowing current to flow from the drain to the source; otherwise, when the gate voltage is lower than the source voltage, the transistor is turned off, preventing current flow. In a scan chain diagnostic circuit, NMOS transistors are often used for grounding operations to ensure that control signals can be pulled down to ground potential, and through the on state to achieve effective transmission and control of signals when needed. In addition, NMOS transistors can also be combined with other elements to form a diode structure to play the role of voltage clamping to protect the circuit from overvoltage or undervoltage.

[0093] In some embodiments of the present application, the gate G1 of the PMOS transistor M1 is fixedly connected to the power supply voltage , ensuring that it is always in an on state, with its source S1 connected to the input D_i of the diagnostic and its drain D1 connected to the output D_O of the diagnostic and the source S2 of the first NMOS transistor M2. This configuration enables the PMOS transistor M1 to effectively pass the input signal to the subsequent circuitry while providing a path to maintain the signal level.

[0094] The gate G2 of the first NMOS transistor M2 is fixed to the power supply voltage , making it normally in an off state unless influenced by other conditions to change its state. This design helps protect the circuit from unnecessary current flow while also laying the foundation for subsequent logic operations. In this way, the first NMOS transistor M2 can be used as a switch, allowing current to flow from the PMOS transistor M1 to ground under certain conditions, thereby affecting the output state of the diagnostic.

[0095] The gate G3 of the second NMOS transistor M3 is interconnected with the source S3 and is commonly connected to the drain D2 of the first NMOS transistor M2 to form a diode structure voltage clamping circuit; the drain D3 of the second NMOS transistor M3 is grounded. This design is mainly used to stabilize the voltage level in the circuit, preventing excessive voltage from damaging sensitive components. The drain D3 of the second NMOS transistor M3 is grounded, which not only provides a necessary reference point for the circuit, but also helps maintain the entire circuit within a safe operating range. This diode structure ensures that even in the case of voltage fluctuations, the voltage at internal nodes of the circuit is maintained within a reasonable range, improving the reliability and stability of the system.

[0096] In some embodiments of the present application, when the voltage level of the scan enable signal is ground voltage, the PMOS transistor M1 is off, the first NMOS transistor M2 is on, and the voltage of the output D_O of the diagnostic is pulled down to ground voltage;

[0097] When the voltage level of the scan enable signal is the power supply voltage, the PMOS transistor M1 is off, the first NMOS transistor M2 is on, and the voltage of the output D_O of the diagnostic is pulled down to ground voltage;

[0098] When the voltage level of the scan enable signal is the diagnostic enable voltage, the PMOS transistor M1 is on, the first NMOS transistor M2 is off, and the voltage of the output D_O of the diagnostic is raised to the diagnostic enable voltage.

[0099] In some embodiments of the present application, the PMOS transistor M1, the first NMOS transistor M2, and the second NMOS transistor M3 are selected from process devices with high threshold voltage.

[0100] In some embodiments of the present application, it is assumed that the threshold voltage of PMOS transistor M1 , the threshold voltage of NMOS transistor M2 , the ground voltage is , the power supply voltage is , the diagnostic enable voltage is .

[0101] When the voltage level of the scan enable signal is the ground voltage (i.e. logic low), the scan enable control end SE_i of the scan cell receives the scan enable signal and transmits it to the input end D_i of the diagnostic and the control end of the first multiplexer MUX1, so that the first multiplexer MUX1 selects its first input end (i.e. the first input end I1 of the scan cell) to receive the functional logic data, and outputs the functional logic data through its output end to the D flip-flop DFF, and finally outputs to the functional logic circuit FLC through the data output end DFF_O (i.e. the output end Sout of the scan cell) of the D flip-flop DFF. At this time, the gate-source voltage of PMOS transistor M1 , i.e. , so PMOS transistor M1 is off; the gate-source voltage of the first NMOS transistor M2 , i.e. , so the first NMOS transistor M2 is on, and the output end D_O of the diagnostic is forced to be pulled low, i.e. , ensuring that the functional logic data path is not disturbed.

[0102] When the voltage level of the scan enable signal is the power supply voltage (i.e. logic high), the scan enable control end SE_i of the scan cell receives the scan enable signal and transmits it to the input end D_i of the diagnostic and the control end of the first multiplexer MUX1, so that the first multiplexer MUX1 selects its second input end to receive scan data from the output end of the second multiplexer MUX2. At this time, the gate-source voltage of PMOS transistor M1 , which does not reach the on condition, and PMOS transistor M1 remains off; the gate-source voltage of the first NMOS transistor M2 Therefore, the first NMOS transistor M2 is turned on, the output terminal D O of the diagnostic device is forced to be pulled low, and the diagnostic device outputs a low logic level to the control terminal of the second multiplexer MUX2, so that the second multiplexer MUX2 selects the first input terminal (i.e., the second input terminal I2 of the scan cell) to receive the scan data and outputs the scan data to the first multiplexer MUX1, and the first multiplexer MUX1 outputs the received scan data to the D flip-flop DFF through the output terminal and finally to the output terminal Sout of the scan cell.

[0103] When the voltage level of the scan enable signal is the diagnostic enable voltage (i.e., twice the logic high level), the control terminal of the scan cell receives the received scan enable signal , and transmits it to the control terminal of the first multiplexer MUX1 and the input terminal D_i of the diagnostic device, so that the first multiplexer MUX1 selects the second input terminal to receive the scan data from the output terminal of the second multiplexer MUX2. At this time, the gate-source voltage of the PMOS transistor M1 is , the PMOS transistor M1 is turned on, the gate-source voltage of the first NMOS transistor M2 is , the first NMOS transistor M2 is cut off, the output terminal D O of the diagnostic device is forced to be pulled up, and the diagnostic device outputs a twice logic high level to the control terminal of the second multiplexer MUX2, so that the second multiplexer MUX2 selects the second input terminal (i.e., the third input terminal I3 of the scan cell) to receive the scan data and outputs the scan data to the first multiplexer MUX1, and the first multiplexer MUX1 outputs the received scan data to the D flip-flop DFF through the output terminal and finally to the output terminal Sout of the scan cell.

[0104] In some embodiments of the present application, when the voltage level of the scan enable signal is the diagnostic enable voltage , a leakage current phenomenon may occur at the moment when the PMOS transistor M1 is turned on and the first NMOS transistor M2 is cut off. At this time, the second NMOS transistor M3 functions as a diode to avoid this situation. The diode can prevent leakage current, mainly due to its unidirectional conduction characteristic and high impedance characteristic when it is reversely biased. When the ground end of the diode is in a forward conduction state, the current is conducted from the drain D2 of the first NMOS transistor M2 to the diode (i.e., the second NMOS transistor M3), at this time the diode is reversely biased and has high impedance, thereby effectively preventing the generation of leakage current.

[0105] Secondly, referring to Figure 4The embodiment of the present application provides a multi-mode side scan chain circuit, which comprises the multi-mode scan unit and the connecting assembly, and a plurality of scan units form at least two parallel side scan chains.

[0106] In some embodiments of the present application, the connection mode of the side scan chain circuit is as follows:

[0107] For each scan unit, the first input end I1 is connected to the functional logic data input interface Data_i, the scan enable control end SE_i is connected to the scan enable signal input interface EN_i, and the output end Sout is connected to the functional logic circuit FLC.

[0108] For each side scan chain, the output end Sout of each scan unit is further connected to the third input end I3 of the same-order scan unit in the next side scan chain, the output end Sout of the first-order and middle-order scan units is further connected to the second input end I2 of the next scan unit in the same side scan chain, and the output end Sout of the last-order scan unit is connected to the scan data output interface.

[0109] For the first side scan chain, the second input end I2 of the first-order scan unit is connected to the scan data input interface Scan_i, for the second and subsequent side scan chains, the third input end I3 of each scan unit is connected to the output end Sout of the same-order scan unit in the previous side scan chain, and the output end Sout of each scan unit of the last side scan chain is connected to the scan data output interface.

[0110] The connection mode of the side scan chain circuit first defines the basic connection of each scan unit. Specifically, the first input end I1 of each scan unit is directly connected to the functional logic data input interface Data_i, so that the functional logic data required in normal operation can accurately enter the scan unit. Meanwhile, the scan enable control end SE_i is connected to the scan enable signal input interface EN_i, so that the scan unit can switch between the functional mode, the test mode and the diagnosis mode according to the received scan enable signal of different voltage levels. In addition, the output end Sout of the scan unit is connected to the functional logic circuit FLC, so that the processed data can continue to be transmitted along the predetermined path.

[0111] For each scan cell in each edge scan chain, its output Sout is not only connected to the third input I3 of the scan cell at the same position in the next edge scan chain, but also further enhances the data flow between scan chains. This design allows data to be smoothly passed from one scan cell to the next, whether within the same edge scan chain or across chains, when performing test or diagnostic modes. In particular, the output Sout of the first and middle position scan cells is also connected to the second input I2 of the next scan cell in the same edge scan chain, ensuring the continuity of data flow within the chain.

[0112] In the first edge scan chain, the second input I2 of the first scan cell is directly connected to the scan data input interface Scan_i, which is intended to initialize the data input process of the entire edge scan chain and ensure that the scan data received from the outside can enter the scan chain correctly. For the second and subsequent edge scan chains, the third input I3 of each scan cell is connected to the output Sout of the scan cell at the same position in the previous edge scan chain. In this way, a complex multi-level data flow network is constructed, supporting more efficient and flexible data processing capabilities.

[0113] Finally, in the entire edge scan chain structure, the output Sout of the last scan cell is connected to the scan data output interface, which is crucial because it is responsible for outputting the final results after a series of processing to the outside of the system for subsequent analysis or verification. In particular, the output Sout of each scan cell in the last edge scan chain is connected to the scan data output interface, ensuring that all necessary test or diagnostic information can be collected and exported completely, providing a solid foundation for the maintenance and optimization of the system.

[0114] In some embodiments of the present application, the scan data output interface and the scan data input interface Scan_i are the same interface. This configuration simplifies the hardware design and reduces the number of physical interfaces required. By sharing the interface, the system can more efficiently manage resources while also reducing complexity and potential failure points due to multiple interfaces. This step not only optimizes circuit layout, but also improves the overall reliability and cost-effectiveness of the system.

[0115] Using a single interface as the input and output port for scan data allows data to enter and exit the system through the same path when performing test or diagnostic operations. Such a design is crucial for reducing signal interference, improving data transmission accuracy and stability. In addition, it also facilitates the implementation of automated test processes, as data can be directly cycled back to the input without the need for manual intervention to complete the continuous data collection and analysis process.

[0116] In some embodiments of the present application, when the scan enable signal is a ground voltage, the side scan chain circuit executes a functional mode, and each scan cell in the side scan chain receives functional logic data through its first input terminal I1 and outputs to the functional logic circuit FLC;

[0117] When the scan enable signal is a power supply voltage, the side scan chain circuit executes a test mode, and the first scan cell of each side scan chain receives scan data from the scan data input interface Scan_i, and transmits the scan data to the scan data output interface along the same side scan chain;

[0118] When the scan enable signal is a diagnostic enable voltage, the side scan chain circuit executes a diagnostic mode, and in the second and subsequent side scan chains, each scan cell receives scan data from the output terminal Sout of the same-order scan cell in the previous side scan chain through its third input terminal I3, and transmits the scan data across the chain along the adjacent side scan chain, and each scan cell in the last side scan chain transmits the scan data to the scan data output interface through its output terminal Sout.

[0119] When the scan enable signal is a ground voltage, the side scan chain circuit enters a functional mode. At this time, each scan cell in the side scan chain receives functional logic data from the functional logic data input interface Data_i through its first input terminal I1, and directly outputs it to the functional logic circuit FLC. This arrangement ensures that in daily operation, the system can normally process and respond to functional requirements without being disturbed by the test or diagnostic process.

[0120] When the scan enable signal becomes a power supply voltage, the side scan chain circuit switches to a test mode. In this mode, the first scan cell of each side scan chain begins to receive predefined scan data from the scan data input interface Scan_i. These data are then transmitted step by step along the same side scan chain until they finally reach the scan data output interface. This way allows a thorough examination of the circuit to verify its correctness and performance, while ensuring the consistency and integrity of the data flow throughout the process.

[0121] Once the scan enable signal rises to the diagnostic enable voltage, the side scan chain circuit enters the diagnostic mode. In this mode, each scan cell in the second and subsequent side scan chains will receive scan data from the output terminal Sout of the same bit scan cell in the previous side scan chain through its third input terminal I3. This mechanism supports cross-chain data transmission, so that complex faults can be accurately located and analyzed. In particular, by transmitting scan data along adjacent side scan chains, the system can achieve more in-depth internal state detection. Finally, each scan cell in the last side scan chain will transmit all the collected scan data to the scan data output interface through its output terminal Sout for further analysis and processing, thereby improving the reliability and maintenance efficiency of the system.

[0122] Further, with reference to Figure 5 The embodiments of the present application provide a multi-mode bidirectional scan chain circuit, which comprises the aforementioned multi-mode scan cell and the connection assembly, and a plurality of scan cells constitute the bidirectional scan chain.

[0123] In some embodiments of the present application, the connection mode of each scan cell in the bidirectional scan chain is as follows:

[0124] The first input terminal I1 of each scan cell is connected to the functional logic data input interface Data_i, the scan enable control terminal SE_i is connected to the scan enable signal input interface EN_i, and the output terminal Sout is connected to the functional logic circuit FLC;

[0125] The output terminal Sout of each scan cell is also connected to the second input terminal I2 of the next scan cell to constitute a forward test path.

[0126] The output terminal Sout of each scan cell is also connected to the third input terminal I3 of the previous scan cell to constitute a reverse diagnostic path.

[0127] In the bidirectional scan chain, the second input terminal I2 of the first scan cell is connected to the scan data input interface Scan_i, the output terminal Sout of the first scan cell is connected to the scan data output interface, and the output terminal Sout of the last scan cell is connected to the scan data output interface.

[0128] In some embodiments of the present application, when the scan enable signal is a ground voltage, the bidirectional scan chain circuit executes the functional mode, and the scan cells in the bidirectional scan chain receive the functional logic data through their first input terminals I1 and output to the functional logic circuit FLC.

[0129] When the scan enable signal is a power voltage, the bidirectional scan chain circuit executes a test mode, and the first scan cell of the bidirectional scan chain receives scan data from the scan data input interface Scan_i, transmits the scan data along a forward test path to the last scan cell, and outputs the scan data to the scan data output interface through the output terminal Sout of the last scan cell.

[0130] When the scan enable signal is a diagnostic enable voltage, the bidirectional scan chain circuit executes a diagnostic mode, and the last scan cell of the bidirectional scan chain transmits scan data along a reverse diagnostic path to the first scan cell, and outputs the scan data to the scan data output interface through the output terminal Sout of the first scan cell.

[0131] In the embodiments of the present application, a multi-mode bidirectional scan chain circuit is provided, which not only includes the aforementioned multi-mode scan cells, but also integrates a connection component, so that multiple scan cells can form a bidirectional scan chain. This design allows the circuit to operate efficiently in different modes, supports bidirectional data transmission, and enhances the flexibility and diagnostic capability of the system.

[0132] The first input terminal I1 of each scan cell is connected to the functional logic data input interface Data_i, ensuring that the required functional logic data can accurately enter each scan cell during normal operation. At the same time, the scan enable control terminal SE_i is connected to the scan enable signal input interface EN_i, so that the scan cell can switch between the functional mode, test mode, and diagnostic mode according to the received scan enable signal of different voltage levels. In addition, the output terminal Sout of the scan cell is connected to the functional logic circuit FLC, ensuring that the processed data can continue to pass along the predetermined path, maintaining the normal operation of the system.

[0133] To realize the forward test path, the output terminal Sout of each scan cell is also connected to the second input terminal I2 of the next scan cell. This connection method constructs a data flow channel from the first to the last, so that in the test mode, scan data can be transmitted step by step along the entire scan chain from the first scan cell to the end. This helps to check the functional correctness and performance indicators of the circuit comprehensively, ensuring the quality of the system.

[0134] To further enhance the diagnostic capability, the output terminal Sout of each scan cell is also connected to the third input terminal I3 of the previous scan cell, thereby forming a reverse diagnostic path. Through this reverse data transmission mechanism, the internal state of the circuit can be analyzed and fault located in detail by starting from the last scan cell and tracing back step by step. This method is particularly suitable for troubleshooting complex faults, as it allows more detailed observation of the working state of each part of the circuit.

[0135] In the bidirectional scan chain structure, the second input end I2 of the first scan cell is directly connected with the scan data input interface Scan_i, serving as an entry point for data entering the entire scan chain. Meanwhile, the output end Sout of the first scan cell and the output end Sout of the last scan cell are both connected to the scan data output interface. Such a design ensures that all processed data can be collected and exported in the process of forward testing or reverse diagnosis, providing complete data support for subsequent verification or fault analysis. This also means that the system can flexibly cope with various situations, whether it is regular operation or in-depth detection in special situations.

[0136] In summary, the multi-mode scan cell, the side scan chain circuit and the bidirectional scan chain circuit provided by the embodiments of the present application have the following technical effects.

[0137] Firstly, the multi-mode scan cell provided by the embodiments of the present application realizes flexible switching between the functional mode, the test mode and the diagnosis mode through different voltage levels (ground voltage, power supply voltage, diagnosis enable voltage) of a single signal, simplifies the control logic, reduces the number of global signals and the complexity and potential interference caused thereby, and optimizes the utilization rate of IO resources of the chip. Such a design not only improves the stability and performance of the circuit, but also enhances the detection and positioning ability of complex faults, effectively improving the overall testability and maintainability of the integrated circuit.

[0138] Secondly, the multi-mode side scan chain circuit provided by the embodiments of the present application realizes efficient data routing and complex test procedures by connecting multiple scan cells into at least two parallel side scan chains and allowing data to be transmitted across the chains between different scan chains. Such a structure not only supports standard functional testing, but also enables detailed fault diagnosis through flexible data path selection, thereby improving the accuracy and efficiency of fault detection without affecting the normal operation of the system, effectively enhancing the reliability and production yield of the circuit.

[0139] Thirdly, the multi-mode bidirectional scan chain circuit provided by the embodiments of the present application uses multi-mode scan cells to build a system that can support forward and reverse data transmission, so that test signals can be transmitted from the first end to the last end or from the last end to the first end, adapting to different test requirements and scenarios. This design is particularly suitable for in-depth fault analysis, as it can accurately locate the problem through the reverse transmission path, providing an efficient and flexible fault detection method that effectively improves the testability and maintenance efficiency of the circuit, ensuring high performance and high reliability of the circuit.

[0140] It should be understood that various parts of the present application can be implemented in hardware, software, firmware or a combination thereof. In the above embodiments, various steps or methods can be implemented in software or firmware that is stored in memory and executed by a suitable

[0141] In the above description of the present application, reference has been made to descriptive terms such as "one embodiment / scheme", "another embodiment / scheme" or "some embodiments / schemes" etc. It is to be understood that such terms are not to be construed as indicating a preferential or advantageous embodiment / scheme. Moreover, the described features, structures, materials or characteristics can be combined in any suitable manner in one or more embodiments / schemes.

[0142] While the embodiments of the present application have been shown and described, it is to be understood that the embodiments can be varied, modified, substituted and changed in many ways without departing from the spirit and scope of the present application, which is defined by the claims and their equivalents.

[0143] The above is a specific description of the preferred embodiments of the present application, but the present application is not limited to the embodiments, and those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the present application, and these equivalent modifications or substitutions are included in the scope defined by the claims of the present application.

Claims

1. A multi-mode scanning unit, characterized by The scan unit comprises a connection component, a first multiplexer, a second multiplexer, a D flip-flop and a diagnostic device; an input terminal of the diagnostic device and a control terminal of the first multiplexer are connected to a scan enable control terminal of the scan unit, the scan enable control terminal is used for receiving a scan enable signal and generating a control signal according to a voltage level of the scan enable signal to control the scan unit to switch among a function mode, a test mode and a diagnostic mode; an output terminal of the second multiplexer is connected to a second input terminal of the first multiplexer; a control terminal of the second multiplexer is connected to an output terminal of the diagnostic device; an output terminal of the first multiplexer is connected to a data input terminal of the D flip-flop; when the scan enable signal is a first voltage, the scan unit executes the function mode, and the first multiplexer selects to receive the function logic data through the first input terminal thereof; when the scan enable signal is a second voltage, the scan unit executes the test mode, and the first multiplexer selects to receive the scan data from the first input terminal of the second multiplexer through the second input terminal thereof; when the scan enable signal is a third voltage, the scan unit executes the diagnostic mode, and the first multiplexer selects to receive the scan data from the second input terminal of the second multiplexer through the second input terminal thereof.

2. The multi-mode scanning unit of claim 1, wherein, The first voltage is a ground voltage, the second voltage is a power supply voltage, and the third voltage is a diagnostic enable voltage; the diagnostic enable voltage is higher than the power supply voltage.

3. The multi-mode scanning unit of claim 1, wherein, The connection component, the first multiplexer, the second multiplexer, the D flip-flop and the diagnostic device are integrated into the scan unit; The scan unit comprises a first input terminal, a second input terminal, a third input terminal, a scan enable control terminal and an output terminal; the first input terminal of the first multiplexer serves as the first input terminal of the scan unit; the first input terminal of the second multiplexer serves as the second input terminal of the scan unit; the second input terminal of the second multiplexer serves as the third input terminal of the scan unit; a data output terminal of the D flip-flop serves as the output terminal of the scan unit, and a clock terminal of the D flip-flop serves as a clock terminal of the scan unit; when the scan enable signal is the first voltage, the scan unit selects to receive the function logic data through the first input terminal thereof to execute the function mode; when the scan enable signal is the second voltage, the scan unit selects to receive the scan data through the second input terminal thereof to execute the test mode; when the scan enable signal is the third voltage, the scan unit selects to receive the scan data through the third input terminal thereof to execute the diagnostic mode.

4. The multi-mode scanning unit of claim 1, wherein, The diagnostic device comprises a PMOS transistor, a first NMOS transistor and a second NMOS transistor; a gate of the PMOS transistor is fixedly connected to a power supply voltage, a source thereof is connected to an input terminal of the diagnostic device, and a drain thereof is connected to an output terminal of the diagnostic device and a source of the first NMOS transistor; a gate of the first NMOS transistor is fixedly connected to the power supply voltage; The gate of the second NMOS transistor is interconnected with the source and is commonly connected to the drain of the first NMOS transistor to form a voltage clamping circuit in a diode structure; and the drain of the second NMOS transistor is grounded.

5. The multi-mode scanning unit of claim 4, wherein, When the voltage level of the scan enable signal is a ground voltage, the PMOS transistor is turned off, the first NMOS transistor is turned on, and the voltage at the output end of the diagnostic device is pulled down to the ground voltage; When the voltage level of the scan enable signal is a power supply voltage, the PMOS transistor is turned off, the first NMOS transistor is turned on, and the voltage at the output end of the diagnostic device is pulled down to the ground voltage; When the voltage level of the scan enable signal is a diagnostic enable voltage, the PMOS transistor is turned on, the first NMOS transistor is turned off, and the voltage at the output end of the diagnostic device is pulled up to the diagnostic enable voltage.

6. The multi-mode scanning unit of claim 5, wherein, The diagnostic enable voltage is twice the power supply voltage.

7. A multi-mode side scan chain circuit, characterized by, The multi-mode scan unit and the connection assembly of any one of claims 1 to 6, a plurality of the scan units form at least two parallel edge scan chains, and the number of scan units in each edge scan chain is consistent; The edge scan chain circuit connection mode is: For each scan unit, the first input end is connected to a functional logic data input interface, the scan enable control end is connected to a scan enable signal input interface, and the output end is connected to a functional logic circuit; For each scan unit, the output end is further connected to the third input end of the same sequence scan unit in the next edge scan chain, the output end of the first and middle position scan units is further connected to the second input end of the next scan unit in the same edge scan chain, and the output end of the last scan unit is connected to a scan data output interface; For the first edge scan chain, the second input end of the first scan unit is connected to a scan data input interface; for the second and subsequent edge scan chains, the third input end of each scan unit is connected to the output end of the same sequence scan unit in the previous edge scan chain, and the output end of each scan unit in the last edge scan chain is connected to the scan data output interface.

8. The multi-mode side scan chain circuit of claim 7, wherein, When the scan enable signal is a ground voltage, the edge scan chain circuit executes a functional mode, and the scan units in each edge scan chain receive functional logic data through the first input end and output to the functional logic circuit; When the scan enable signal is a power supply voltage, the edge scan chain circuit executes a test mode, and the first scan unit of each edge scan chain receives scan data from the scan data input interface and transmits the scan data to the scan data output interface step by step along the same edge scan chain; When the scan enable signal is a diagnostic enable voltage, the edge scan chain circuit executes a diagnostic mode, in the second and subsequent edge scan chains, each scan cell receives the scan data from the output terminal of the same-order scan cell in the previous edge scan chain through the third input terminal, and transmits the scan data across the chain along the adjacent edge scan chain, and each scan cell of the last edge scan chain transmits the scan data to the scan data output interface through the output terminal.

9. A multi-mode bidirectional scan chain circuit, characterized by The multi-mode scan cell and the connection assembly according to any one of claims 1 to 6, a plurality of the scan cells constitute a bidirectional scan chain, and the connection mode of each scan cell in the bidirectional scan chain is: The first input terminal of each scan cell is connected to a functional logic data input interface, the scan enable control terminal is connected to a scan enable signal input interface, and the output terminal is connected to a functional logic circuit; The output terminal of each scan cell is further connected to the second input terminal of the next scan cell to constitute a forward test path; The output terminal of each scan cell is further connected to the third input terminal of the previous scan cell to constitute a reverse diagnostic path; In the bidirectional scan chain, the second input terminal of the first scan cell is connected to a scan data input interface, the output terminal of the first scan cell is connected to a scan data output interface, and the output terminal of the last scan cell is connected to the scan data output interface.

10. The multi-mode bidirectional scan chain circuit of claim 9, wherein, When the scan enable signal is a ground voltage, the bidirectional scan chain circuit executes a functional mode, and each scan cell in the bidirectional scan chain receives functional logic data through the first input terminal and outputs to the functional logic circuit; When the scan enable signal is a power voltage, the bidirectional scan chain circuit executes a test mode, and the first scan cell of the bidirectional scan chain receives scan data from the scan data input interface, transmits the scan data along the forward test path to the last scan cell, and outputs to the scan data output interface through the output terminal; When the scan enable signal is a diagnostic enable voltage, the bidirectional scan chain circuit executes a diagnostic mode, and the last scan cell of the bidirectional scan chain transmits the scan data along the reverse diagnostic path to the first scan cell and outputs to the scan data output interface through the output terminal.

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