Signal selection circuit with feedback and related light sensing distance measurement chip

Abstract

The invention discloses a signal selection circuit with feedback and a related light sensing distance measurement chip. According to the signal selection circuit with feedback, enabling signal feedback is realized by utilizing selection mark units of different levels, so that the address number of the quenching reset unit is output. When the trigger signal of one quenching reset unit is 1, the signal of the signal output end of the selection mark unit connected with the quenching reset unit on the first layer is 1, and the signal is transmitted backwards through the selection mark units on other layers, so that the signal of the signal output end of the selection mark unit on the last layer is 1; in the embodiment of the invention, the selection mark unit of the last layer forwards transmits the first enabling input end signal through the selection mark units of the other layers, and when a plurality of quench units share one TDC unit, the ID of the quench unit can be selectively output, so that the use of an MUX is avoided, and the area utilization rate of a chip is improved.

Description

Technical Field

[0001] This application relates to the technical field of optical ranging, and in particular, to a signal selection circuit with feedback and a related optical sensing ranging chip. Background Art

[0002] For a SPAD (Single Photon Avalanche Diode) ranging chip based on dTOF (direct time of flight), when an avalanche occurs after the SPAD receives photons, the avalanche process will be ended through a quench reset circuit (quench circuit), and an avalanche pulse signal will be generated and sent to a TDC (Time to Digital Convert) circuit. The TDC circuit detects the received avalanche pulse signal within a fixed time, eliminates the interference of noise, and converts the time signal into a digital signal.

[0003] Currently, considering the area and power consumption of the overall chip, usually, multiple SPADs share one TDC circuit to complete the direct time of flight measurement of the SPAD. And a quench reset unit is connected behind each SPAD unit. For simplicity, it can be expressed as multiple quench reset units sharing one TDC unit. To determine which specific SPAD receives photons, the ID of its corresponding quench unit needs to be output during each detection process. Normally, at one sampling moment, even if multiple quench reset units are triggered, the TDC can only process the trigger signal of one of the quench reset units. When multiple quench reset units are triggered simultaneously or the trigger time intervals are short, the output ID becomes very uncertain, that is, it is impossible to determine which quench reset unit is triggered.

[0004] In the prior art, the signal multi-selection method of a MUX (multiplexer) circuit can be used to select one quench reset unit from multiple quench reset units to output its ID; however, each time a multi-selection is made, a MUX circuit equivalent to the number of ID bits is required. If the ID has 5 bits, at least 5 MUX circuits are required for each multi-selection, which occupies a large area of the chip. Summary of the Invention

[0005] In view of this, the embodiments of this application provide a signal selection circuit with feedback and an optical sensing ranging chip, so as to solve the problem of how to perform signal selection without using a MUX circuit when multiple quench reset units share one TDC unit, so that the chip occupies a smaller area.

[0006] In a first aspect, the embodiments of this application provide a signal selection circuit with feedback, and the circuit includes:

[0007] The quenching and reset module includes N quenching and reset units, and each of the quenching and reset units is used to output a trigger signal (trig), where N is an integer greater than 1;

[0008] The DCM (with selection markers) module includes M DCM units. The DCM units are used to perform signal selection on the quenching and reset units, and the DCM units are arranged on different selection layers; when the trigger signal (trig) of a quenching and reset unit is 1, the signal output terminal signal (Q) of the DCM unit connected to the quenching and reset unit on the first layer is 1, and the signal is transmitted backward through the DCM units on other layers, so that the signal output terminal signal (Q) of the DCM unit on the last layer is 1, and the first enable input terminal signal (EN1) of the DCM unit on the last layer is set to 1. The DCM unit on the last layer transmits the first enable input terminal signal forward through the DCM units on other layers, so that the second enable input terminal signal (EN2) of one of the quenching and reset units is 1. M is an integer greater than 1 and M is less than N;

[0009] The quenching and reset unit with the trigger signal (trig) being 1 is further used to output its own (ID) address number after receiving the second enable input signal (EN2) being 1.

[0010] The TDC unit is used to receive the signal output terminal signal (Q) of the DCM unit on the last layer, and is further used to receive the own address number output by the quenching and reset unit with the trigger signal (trig) being 1 after receiving the signal output terminal signal (Q) with the signal being 1, where 1 represents that the signal is valid.

[0011] In the above aspects and any possible implementation manners, a further implementation manner is provided. The ratio of the number of DCM units on the Lth layer to the number of DCM units on the (L + 1)th layer in the selection layer is 2 or 3.

[0012] In the above aspects and any possible implementation manners, a further implementation manner is provided. The DCM unit on the first layer is used to perform a one - in - two selection on the quenching and reset unit connected to it; the DCM unit on the second layer is used to perform a one - in - two selection on the DCM unit on the first layer connected to it; and so on, the DCM unit on the last layer is used to perform a one - in - two selection on the DCM unit on the penultimate layer connected to it.

[0013] For the aspects and any possible implementation manners described above, a further implementation manner is provided. Each DCM unit includes: a first signal input terminal, a second signal input terminal, and one signal output terminal; and further includes: one first enable input terminal and two second enable output terminals; the first signal input terminal and its corresponding second enable output terminal are both connected to a previous-stage module; the second signal input terminal and its corresponding second enable output terminal are both connected to another previous-stage module;

[0014] Wherein, if the signal of one signal input terminal is first 1, then the signal of the signal output terminal is 1; when the signal of the first enable input terminal is 1, for the one whose signal of the signal input terminal is first 1, the signal of its corresponding second enable output terminal is 1.

[0015] For the aspects and any possible implementation manners described above, a further implementation manner is provided. Each DCM unit includes: a first signal input terminal, a second signal input terminal, and one signal output terminal; and further includes: one first enable input terminal and two second enable output terminals; the first signal input terminal and its corresponding second enable output terminal are both connected to a previous-stage module; the second signal input terminal and its corresponding second enable output terminal are both connected to another previous-stage module;

[0016] Wherein, when the signals of the two signal input terminals are both 1 at the same time, then the signal of the signal output terminal is 1; when

[0017] the signal of the first enable input terminal is 1 and the signals of the two signal input terminals are both 1 at the same time, one of the second enable output terminals is automatically selected and its signal is set to 1.

[0018] For the aspects and any possible implementation manners described above, a further implementation manner is provided. The DCM unit includes one OR gate, two NAND gates, and two AND gates;

[0019] For the OR gate, its two inputs are connected to the two signal input terminals, and its output is connected to the signal output terminal;

[0020] For the first NAND gate, one of its inputs is connected to the first signal input terminal, and the other input is connected to the output terminal of the second NAND gate;

[0021] For the second NAND gate, one of its inputs is connected to the second signal input terminal, and the other input is connected to the output terminal of the first NAND gate;

[0022] For the first AND gate, one of its inputs is connected to the output terminal of the first NAND gate, and the other input is connected to the first enable input terminal, and its output is connected to the second enable output terminal corresponding to the second signal input terminal;

[0023] A second AND gate, one input of which is connected to the output terminal of the second NAND gate, and the other input is connected to the first enable input terminal, and the output of which is connected to the second enable output terminal corresponding to the first signal input terminal.

[0024] In the aspects and any possible implementation manners as described above, a further implementation manner is provided. The DCM unit further includes a second OR gate, which is connected in parallel with the first OR gate.

[0025] In the aspects and any possible implementation manners as described above, a further implementation manner is provided. The circuit further includes:

[0026] 4 of the quenching reset units, which are used to output a trigger signal (trig);

[0027] 2 first-stage selection and marking units, which are respectively used to select the 4 connected quenching reset units. When the trigger signal (trig) of one or more of the quenching reset units is 1, the signal (Q) at the signal output terminal of the first-stage DCM unit connected thereto is 1;

[0028] 1 second-stage DCM unit, which is used to select the 2 connected first-stage DCM units. When the signal (Q) at the signal output terminal of the first-stage DCM unit is 1, the signal (Q) at the signal output terminal of the second-stage DCM unit is 1. When the signal (Q) at the signal output terminal is 1, the signal (EN) at the first enable input terminal of the second-stage DCM unit is 1;

[0029] The first-stage DCM unit with the signal at the signal output terminal being 1 is further used to receive the second enable output terminal signal output as 1 by the second-stage DCM unit;

[0030] The quenching reset unit with the trigger signal (trig) being 1 is further used to receive the second enable output terminal signal output as 1 by the first-stage DCM unit and output its own address number;

[0031] A TDC unit, which is used to receive the signal (Q) at the signal output terminal of the second-stage DCM unit, and is further used to receive the own address number output by the quenching reset unit with the trigger signal (trig) being 1 after receiving the signal (Q) at the signal output terminal being 1, where the 1 represents that the signal is valid.

[0032] In the aspects and any possible implementation manners as described above, a further implementation manner is provided. The circuit further includes:

[0033] 8 of the quenching reset units, which are used to output the trigger signal (trig);

[0034] Four first-level DCM units are respectively used to select the eight quenching and reset units connected thereto. When the trigger signal (trig) of one or more of the quenching and reset units is 1, the signal (Q) at the signal output terminal of the first-level DCM unit connected thereto is 1;

[0035] Two second-level DCM units are used to select the four first-level DCM units connected thereto. When the signal (Q) at the signal output terminal of one or more of the first-level DCM units is 1, the signal (Q) at the signal output terminal of one of the second-level DCM units is 1;

[0036] One third-level DCM unit is used to select the two second-level DCM units connected thereto. When the signal (Q) at the signal output terminal of one of the second-level DCM units is 1, the signal (Q) at the signal output terminal of the third-level DCM unit is 1. When the signal (Q) at the signal output terminal is 1, the input signal (EN) of the third-level DCM unit is 1;

[0037] The second-level DCM unit with the signal output terminal signal (Q) being 1 is further used to receive the second enable output signal output as 1 by the third-level DCM unit;

[0038] The first-level DCM unit with the signal output terminal signal (Q) being 1 is further used to receive the second enable output signal output as 1 by the second-level DCM unit;

[0039] The quenching and reset unit that outputs the trigger signal (trig) is further used to receive the second enable output signal output as 1 by the first-level DCM unit and output its own (ID) address number;

[0040] The TDC unit is used to receive the signal (Q) at the signal output terminal of the third-level DCM unit, and is further used to receive the own address number output by the quenching and reset unit with the trigger signal (trig) being 1 after receiving the signal (Q) at the signal output terminal with the signal being 1, where 1 represents a valid signal.

[0041] In a second aspect, an embodiment of the present application provides a light-sensing ranging chip, and the light-sensing ranging chip includes the signal selection circuit with feedback as described in the first aspect.

[0042] In the embodiment of the present application, a signal selection circuit with feedback is adopted. By using DCM units at different levels to implement signal feedback, an address number of a quenching reset unit is output by selecting one quenching reset unit from multiple quenching reset units. Among them, when the trigger signal of a quenching reset unit is 1, the signal output terminal of the DCM unit connected to the quenching reset unit on the first layer is 1, and the signal is transmitted backward through the DCM units of other layers, so that the signal output terminal of the DCM unit on the last layer is 1, and at this time, the first enable input terminal signal of the DCM unit on the last layer is 1; the DCM unit on the last layer transmits the first enable input terminal signal forward through the DCM units of other layers, so that the second enable input terminal signal of one of the quenching reset units is 1. In this way, when multiple quenching reset units share one TDC unit, that is, in a many-to-one situation, an ID of a quenching reset unit can be correctly selected and output, thereby improving the chip area utilization rate without using a MUX. Description of the Drawings

[0043] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0044] Figure 1 It is a schematic diagram of a 4-input circuit with marked feedback in an embodiment of the present application;

[0045] Figure 2 It is a schematic diagram of an 8-input circuit with marked feedback in an embodiment of the present application;

[0046] Figure 3 It is a specific implementation structure diagram of a DCM. Detailed Embodiments

[0047] In order to better understand the technical solutions of the present application, the embodiments of the present application will be described in detail below with reference to the drawings.

[0048] It should be clear that the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present application.

[0049] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms of "a", "the" and "said" used in the embodiments of the present application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0050] It should be understood that the term "and / or" used herein is merely a description of the same fields of associated objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone. Additionally, the character " / " in this text generally indicates that the associated objects before and after are in an "or" relationship.

[0051] It should be understood that although terms such as first, second, third, etc. may be used in the embodiments of this application to describe preset ranges, etc., these preset ranges should not be limited to these terms. These terms are only used to distinguish the preset ranges from each other. For example, without departing from the scope of the embodiments of this application, the first preset range may also be referred to as the second preset range, and similarly, the second preset range may also be referred to as the first preset range.

[0052] Depending on the context, the word "if" as used herein can be interpreted as "when" or "while" or "in response to determining" or "in response to detecting". Similarly, depending on the context, the phrase "if determined" or "if detected (stated condition or event)" can be interpreted as "when determined" or "in response to determining" or "when detected (stated condition or event)" or "in response to detecting (stated condition or event)".

[0053] This application provides a signal selection circuit with feedback. The circuit includes:

[0054] A quench reset module (quench module), including N quench reset units, each quench reset unit is used to output a trigger signal (trig), where N is an integer greater than 1;

[0055] In one embodiment, the quench reset module is a general circuit module, which may specifically include multiple quench reset units. Each quench reset unit uniquely corresponds to an SPAD. That is, the SPAD can also be uniquely determined according to the ID of the quench reset unit. When the SPAD receives photons, the quench reset unit corresponding to the SPAD sets the trigger signal to 1 and can transmit the trigger signal with a value of 1 to subsequent modules / units. It should be noted that in this application, signals with a value of 1 are all considered valid signals.

[0056] The DCM (Decision Mark) module includes M DCM units, which are used to select signals for the quenching reset unit. The DCM units are arranged on different selection layers. When the trigger signal (trig) of a quenching reset unit is 1, the signal output (Q) of the DCM unit connected to the quenching reset unit on the first layer is 1, and the signal is transmitted backward through the DCM units on other layers, so that the signal output (Q) of the DCM unit on the last layer is 1, and the first enable input signal (EN1) of the DCM unit on the last layer is set to 1. The DCM unit on the last layer transmits the first enable input signal forward through the DCM units on other layers, so that the second enable input signal (EN2) of one of the quenching reset units is 1. M is an integer greater than 1 and less than N.

[0057] In an embodiment, the DCM module includes multiple DCM units located on different selection layers. Among them, the ratio of the number of DCM units on the first layer to the number of quenching reset units is 1:2 or 1:3. When the SPAD receives an optical signal, it will set the trigger signal of the corresponding quenching reset unit to 1 and send the trigger signal with a value of 1 to the DCM unit connected to the quenching reset unit.

[0058] After receiving the trigger signal with a value of 1, the DCM unit on the first layer sets the signal output of the DCM unit to 1, and according to the signal output with a value of 1, it is sequentially transmitted to the DCM units on the subsequent layers according to the connection relationship of the DCM units between layers, so that the signal output of the DCM units on the subsequent layers is set to 1. After the DCM unit on the last layer receives the signal 1 transmitted from the DCM unit on the penultimate layer, it will set its own signal output to 1, and according to the signal output set to 1, it will set the first enable input signal of the DCM unit on the last layer to 1.

[0059] The DCM unit on the last layer transmits the first enable input signal forward through the DCM units on other layers and selects a quenching reset unit according to the first enable input signal, and sets the second enable input signal of the quenching reset unit to 1. Among them, the first enable input signal is the judgment node for initiating signal feedback selection. When the first enable input signal is set to 1, the DCM unit will forward the first enable input signal with a value of 1, so that the DCM units on the previous layers can select a quenching reset unit as the ID output object according to the first enable input signal.

[0060] Understandably, the DCM module implements the function of tag feedback. Each time a SPAD is detected, a trigger signal for generating signal 1 is generated in the quenching reset unit, which is equivalent to tagging the quenching reset unit. Using this trigger signal of signal 1, the signal output terminals of the multi-level DCM units are set to 1, and the first enable input terminal signal with the feedback propagation signal of 1 in the last DCM unit is used, so that whenever a trigger signal is generated, through this DCM module, a quenching reset unit will surely be selected as the ID output object by feedback. Among them, the number of bits occupied by the first enable input terminal signal and the trigger signal is both 1. This signal selection circuit with feedback only transmits according to the signal with the number of bits occupied being 1 each time, and only one quenching reset unit will be selected as the ID output object each time.

[0061] The quenching reset unit with the trigger signal (trig) being 1 is also used to output its own (ID) address number after receiving the second enable input signal (EN2) being 1.

[0062] In one embodiment, after the signal transmission of the multi-level DCM units, a quenching reset unit with a trigger signal of 1 is generated, and the signal will finally receive a signal of 1, which can be called the second enable input terminal signal according to its function. The quenching reset unit will output the corresponding ID according to the received second enable input terminal signal.

[0063] It should be understood that the effective signal transmitted by the signal selection circuit with feedback in this application is 1. The signal itself occupies 1 bit, and the signal is only named according to its function implemented in the circuit. There is no essential difference between signals with different names, and the information it transmits is 1.

[0064] The TDC unit is used to receive the signal output terminal signal (Q) of the last DCM unit, and is also used to receive the address number of itself output by the quenching reset unit with the trigger signal (trig) being 1 after receiving the signal output terminal signal (Q) with the signal being 1.

[0065] In one embodiment, the TDC unit can be connected to multiple quenching reset units. After receiving the signal output terminal signal of the last layer, through the feedback of the first enable input terminal signal, the TDC unit will also receive the ID of a selected quenching reset unit.

[0066] Furthermore, the ratio of the number of DCM units in the L-th layer to the number of DCM units in the (L + 1)-th layer in the selection layer is 2 or 3, where L is an integer greater than 0.

[0067] In one embodiment, a DCM unit can be set to connect to two or three quenching and resetting units. Then, the DCM unit in the (L + 1)-th layer is also correspondingly connected to two or three DCM units in the L-th layer. It can be understood that the DCM units are arranged hierarchically. After each additional layer, the number of DCM units decreases proportionally until there is only one DCM unit in the last layer. In this way, when multiple trigger signals are generated simultaneously, the signal channels can be reduced to 1, and the signal of the first enable input terminal can be feedback-transmitted one by one through the DCM unit in the last layer, so that in the case of multiple trigger signals, the ID of the quenching and resetting unit can still be output selectively.

[0068] Further, the DCM unit in the first layer is used to select one of the two quenching and resetting units it is connected to; the DCM unit in the second layer is used to select one of the two DCM units in the first layer it is connected to; and so on. The DCM unit in the last layer is used to select one of the two DCM units in the penultimate layer it is connected to.

[0069] In one embodiment, the signal selection circuit with feedback in the present application can be specifically set as a two-way selection circuit. After each subsequent layer, the number of DCM units is reduced by half. That is, after passing through each DCM selection layer, only one of every two signals enters the next layer. In this way, when the DCM unit in the last layer feedbacks the signal of the first enable input terminal, for the quench with a trigger signal of 1, it is marked during transmission in the DCM unit. Through this mark, the first-triggered quench unit can be found. Therefore, the first-triggered quench unit will output its ID number first. In this way, when the TDC unit is paired with multiple quench units / SPADs, the ID of a triggered quench unit itself can be deterministically output, thereby improving the chip area utilization rate without using a MUX.

[0070] Figure 1 It is a schematic diagram of a 4-input circuit with marked feedback in one embodiment of the present application.

[0071] In the figure, 301, 302, 303, and 304 are quench units. Each quench unit has at least one input terminal ID_EN, two output terminal numbers ID_OUT, and a trigger signal trig. The initial state of trig is 0. Among them, when ID_EN is 1, ID_OUT outputs its ID number. After a photon is detected by the SPAD corresponding to the quench unit, the trig (trigger signal) will be set to 1.

[0072] 305, 306, and 307 are DCM units with marked feedback. Each DCM unit has at least three inputs A, B, and EN, and three output terminals A_EN, B_EN, and Q, and their initial states are all 0. When either A or B becomes 1, Q becomes 1. When EN is 1, A_EN and / or B_EN will output. 308 is a TDC unit that receives the output Q of 307 for photon flight time conversion.

[0073] In one embodiment, as long as one of 301, 302, 303, 304, the SPAD corresponding to the quench unit, detects a photon, for example 301, then the trig of 301 will become 1. After the input A of 305 receives 1, the Q of 305 is also set to 1, and by analogy, the Q of 307 is also correspondingly set to 1.

[0074] When the Q terminal of 307 becomes 1, the EN of 307 can be set to 1 through a preset logic judgment unit, then the A_EN of 307 can output a signal to set the EN of 305 to 1. After the EN of 305 becomes 1, then the output terminal A_EN of 305 outputs 1 to the ID_EN of 301, and then 301 outputs its ID1.

[0075] From Figure 1 it can be seen that after any one of the quench units of 301 - 304 emits a trig signal with a signal of 1, the signal 1 is transmitted layer by layer through a one - of - two selection, and in the DCM unit, the signal 1 is represented by Q. Until after the Q of the DCM unit 307 at the last layer, the EN will be set to 1 according to the Q with a signal of 1, and according to this EN, A_EN or B_EN in 307 is selected, and the signal is fed back to 305 or 306. Similarly, for 301, 302, 303, 304, selection is made in the quench unit using EN, and finally the ID of a quenching reset unit is output.

[0076] Furthermore, if more than two trig signals are continuously triggered within a period of time, the signal path for feedback will be preferentially selected according to the triggering time sequence of the trig signals. For example, if 301 and 302 successively trigger trig signals with a signal of 1 within a short time interval, then 307 will preferentially set the A_EN of 307 to 1 according to the EN with a signal of 1, and in 305, similarly, the A_EN in 305 will be preferentially set to 1, and then the ID_EN in 301 will be preferentially set to 1. Therefore, the quench unit of 301 is selected and its ID number is output.

[0077] Further, if more than two trig signals are continuously triggered within a period of time, the signal path for feedback can be preferentially selected according to the selection logic of the circuit itself. For example, if trig signals with a value of 1 are simultaneously triggered by 301 and 302, since the trig triggers all come from 301 and 302 (belonging to the same selection path), 307 will select A_EN in 307. After the selection, in 305, according to the selection logic of the circuit itself, A_EN or B_EN in 305 will be automatically selected and set to 1, and the corresponding output will be ID1 or ID2. However, in both of the above two methods, when multiple quench units are triggered, it is ensured that only one quench will output the ID number. Therefore, it is clear which quench unit the TDC is connected to at a certain moment.

[0078] Figure 2 It is a schematic circuit diagram of an 8-input circuit with marked feedback in an embodiment of the present application.

[0079] From Figure 2 It can be seen that actually Figure 2 of Figure 1 The difference lies only in the number of inputs of the quench unit. Each quench unit corresponds to two DCM units. Similarly, every two DCM units correspond to one DCM unit at the next level.

[0080] In an embodiment, when the trig of 8 quench units simultaneously becomes 1, the signals of the DCM units at three levels will be selected one by one and then signal feedback will be performed. During the feedback stage, the IDs of the 8 quench units will be sequentially output according to the selection logic of the circuit itself. It can be understood that the present application only focuses on whether the ID of the quench unit can be selectively output. As for the order, in the case of simultaneous trig triggering, the circuit can make its own selection. The present application only needs to ensure that one ID is output each time.

[0081] Figure 3 It is a specific circuit implementation structure diagram of the DCM unit.

[0082] Such as Figure 3As shown in the figure, 101 and 102 are both two-input OR gates. Their two inputs are connected respectively, and the outputs are also connected together. The two inputs come from the output marks A and B of two quenching and reset units respectively. Among them, when one of the two inputs A and B is 1, the output Q is 1; among them, it is also feasible to use one OR gate here. Using two OR gates with cross-connected inputs can achieve the consistency of signal delay at the two input ends. 103 and 104 are both two-input NAND gates, and 105 and 106 are two-input AND gates. One input of 103 comes from the output A of a quenching and reset unit, and the output B of another quenching and reset unit is connected to one input of 104; the signal of another input end of 103 is connected to the signal of the output end of 104, and the signal of the output end of 103 is connected to one input end signal of 104; the signals of one input ends of 105 and 106 are jointly connected to the external signal EN (the first enable input signal), the other input signal of 105 is connected to the output of 103, and the other input signal of 106 is connected to the output of 104; the output of 105 is B_EN, and the output of 106 is A_EN.

[0083] Figure 3 Among them, in the initial state, all input and output signals are reset to 0. According to the logic increment table of the NAND gate, the initial values of 201 and 202 are 1. Specifically, when A becomes 1, it will make Q become 1, 201 is 0, and 202 is 1. When EN becomes 1, the output A_EN becomes 1, and B_EN remains 0. Even when A and B are triggered simultaneously, that is, when the inputs A and B are both 1 at the same time, the output Q becomes 1. 201 and 202 will both become 1. For Figure 3 Regarding the structures of the NAND gates 103 and 104 shown, it can be known that the state where A, B, 201, and 202 are all 1 is an unstable state. After stabilization, only one of 201 and 202 must be 1 and the other is 0. Here, it is assumed that 201 is 1 and 202 is 0; when EN becomes 1, the output B_EN is 1, and A_EN remains 0. In this way, the purpose of only outputting one of the IDs even in the case of simultaneous triggering is achieved.

[0084] In this application, since the number of logic units used is small and no MUX is used, the chip area can be effectively saved while ensuring that data is not wasted and the correct ID is output. The reusability of the DCM unit can also reduce the burden of the design work.

[0085] It should be understood that other deformed circuits of the DCM unit based on Figure 3 have the same logical implementation and different logical units used, and they should all fall within the protection scope of this application.

[0086] In the embodiment of the present application, a signal selection circuit with feedback is adopted. By using DCM units at different levels to implement signal feedback, the address number of the quench reset unit itself is output. Among them, when the trigger signal of a quench reset unit is 1, the signal output terminal of the DCM unit connected to the quench reset unit on the first layer has a signal of 1. The signal is transmitted backward through the DCM units on other layers, so that the signal output terminal of the DCM unit on the last layer has a signal of 1, and at this time, the first enable input terminal of the DCM unit on the last layer has a signal of 1. The DCM unit on the last layer transmits the first enable input terminal signal forward through the DCM units on other layers, so that the second enable input terminal of one of the quench units has a signal of 1. In this way, when multiple quench units correspond to one TDC unit, the ID of the quench unit itself can be selectively output, thus avoiding the use of MUX and improving the chip area utilization rate.

[0087] It should be understood that the sequence numbers of the steps in the above embodiments do not mean the order of execution. The execution order of each process should be determined according to its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.

[0088] The embodiment of the present application also provides a light-sensing ranging chip, which includes the signal selection circuit with feedback in the above embodiment. Compared with the traditional light-sensing ranging chip, the chip area of this light-sensing ranging chip is smaller.

[0089] Those skilled in the art can clearly understand that, for the convenience and simplicity of description, only the above division of each functional unit and module is used as an example. In actual applications, the above functions can be allocated to different functional units and modules according to needs, that is, the internal structure of the device is divided into different functional units or modules to complete all or part of the functions described above.

[0090] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements for some of the technical features; these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A signal selection circuit with feedback, characterized in that, The circuit includes: 4n quenching and resetting units, each of which outputs a trigger signal; n = 1, 2, 4, 8; 4n - 1 identical selection and marking units, where the first 2n selection and marking units have 4n signal input terminals for respectively connecting the trigger signals output by the 4n quenching and resetting units. When the trigger signal of one or more quenching and resetting units is 1, the signal output terminal of the selection and marking unit connected thereto is 1; The subsequent n selection and marking units have 2n signal input terminals for respectively connecting the output terminals of the first 2n selection and marking units. When the signal output terminal of one of the first 2n selection and marking units is 1, the signal output terminal of one of the subsequent n selection and marking units connected thereto is 1; The last selection and marking unit has 2 signal input terminals connected to the output terminals of the previous 2 selection and marking units. Connect the signal output terminal of the last selection and marking unit to its own enable input terminal, then the signal of the enable input terminal of the last selection and marking unit is 1; The 2 enable output terminals of the last selection and marking unit are respectively connected to the enable input terminals of the previous 2 selection and marking units; the subsequent n selection and marking units have 2n enable output terminals for respectively connecting the enable input terminals of the first 2n selection and marking units; the first 2n selection units have 4n enable output terminals for respectively connecting the 4n enable input terminals of the 4n quenching and resetting units; The quenching and resetting unit is further configured to output its own address number according to the received enable signal; The TDC unit is configured to receive the signal of the signal output terminal of the last selection and marking unit, and is further configured to receive the address number output by the quenching and resetting unit with the trigger signal being 1, where the 1 represents that the signal is valid.

2. The circuit according to claim 1, wherein When n = 1, the circuit specifically includes: 4 quenching and resetting units, each of which outputs a trigger signal; 3 identical selection and marking units. The 2 signal input terminals of the first selection and marking unit and the 2 signal input terminals of the second selection and marking unit are respectively connected to the trigger signals output by the 4 quenching and resetting units. When the trigger signal of one or more quenching and resetting units is 1, the signal of the signal output terminal of the first or second selection and marking unit connected thereto is 1; The 2 signal input terminals of the third selection and marking unit are respectively connected to the output terminal of the first selection and marking unit and the output terminal of the second selection and marking unit. When the signal of the signal output terminal of the first or second selection and marking unit is 1, the signal of the signal output terminal of the third selection and marking unit is 1. Connect the signal output terminal of the third selection and marking unit to its own enable input terminal, then the signal of the enable input terminal of the third selection and marking unit is 1; The two enable output terminals of the third selection marking unit are respectively connected to the enable input terminals of the first and second selection marking units; the two enable output terminals of the first selection unit are respectively connected to the enable input terminals of the two quenching reset units, and the two enable output terminals of the second selection unit are respectively connected to the enable input terminals of the other two quenching reset units; The quenching reset unit is further configured to output its own address number according to the received enable signal; The TDC unit is configured to receive the signal output terminal signal of the third selection marking unit, and is further configured to receive the own address number output by the quenching reset unit with the trigger signal being 1, where the 1 represents a valid signal.

3. The circuit according to claim 1, wherein The selection marking unit includes: a first signal input terminal A and a second signal input terminal B, a signal output terminal Q, an enable input terminal EN, a first enable output terminal A_EN, and a second enable output terminal B_EN; a first OR gate, a first NAND gate, and a second NAND gate, a first AND gate, and a second AND gate; For the first OR gate, its two inputs are respectively connected to the two signal input terminals A and B, and its output is connected to the signal output terminal Q; For the first NAND gate 103, one of its inputs is connected to the first signal input terminal A, and the other input is connected to the output terminal of the second NAND gate; For the second NAND gate 104, one of its inputs is connected to the second signal input terminal B, and the other input is connected to the output terminal of the first NAND gate; For the first AND gate 105, one of its inputs is connected to the output terminal of the first NAND gate, and the other input is connected to the enable input terminal, and its output is connected to the second enable output terminal B_EN; For the second AND gate 106, one of its inputs is connected to the output terminal of the second NAND gate, and the other input is connected to the enable input terminal, and its output is connected to the first enable output terminal A_EN.

4. The circuit according to claim 3, characterized in that, The selection marking unit further includes: a second OR gate, which is connected in parallel with the first OR gate.

5. A light-sensing ranging chip, characterized in that, The optical distance measurement chip includes the signal selection circuit with feedback according to any one of claims 1-4.

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