Optical module packaging framework
Through the fan-out line relay layer in the optical module package architecture, the high insertion loss and resistance capacitance delay effect in the prior art is solved, and more efficient signal transmission and larger bandwidth are achieved.
Patent Information
- Application Number
- CN202410189182.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-01-29
- Filing Date
- 2024-02-20
- Publication Date
- 2025-07-29
AI Technical Summary
The existing photonic integrated circuit packaging technology has high insertion loss and obvious resistance and capacitance delay effects, which affect signal transmission efficiency and bandwidth.
It adopts an optical module packaging architecture, including a mold sealing layer, a photonic integrated circuit, a fanout line relay layer and an electronic integrated circuit. The photonic integrated circuit and an electronic integrated circuit are electrically coupled through the fanout line relay layer, shortening the signal transmission path and reducing the resistance and capacitance delay effect.
It improves signal transmission efficiency, reduces insertion loss, expands optical transmission bandwidth, reduces package size, and improves signal transmission rate.
Smart Images
Figure CN120386067A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to an optical module packaging architecture. Background Art
[0002] In response to the high transmission rate requirements of future optical communication systems, smaller, faster, and lower-cost photonic integrated circuits (PICs) can achieve low-cost and high-transmission-rate optical communication. In addition, silicon photon packaging architectures including photonic integrated circuits and electronic integrated circuits (EICs) have attracted much attention due to their advantage of compactness.
[0003] However, the packaging technology of photonic integrated circuits still faces many challenges. For example, there may be signal interference problems in high-frequency transmission applications, such that the compact configuration of photonic integrated circuits and electronic integrated circuits may bring higher insertion loss and obvious resistance-capacitance delay (RC delay) effects. Summary of the Invention
[0004] In view of the above problems, the present invention provides an optical module packaging architecture, which helps to solve the problems of high insertion loss and obvious resistance-capacitance delay effects in the existing packaging architecture.
[0005] The optical module packaging architecture disclosed in an embodiment of the present invention includes a mold encapsulation layer, a photonic integrated circuit, a fan-out type circuit redistribution layer, and an electronic integrated circuit. The photonic integrated circuit is disposed within the mold encapsulation layer. The fan-out type circuit redistribution layer is disposed on the mold encapsulation layer. The electronic integrated circuit is disposed on the fan-out type circuit redistribution layer, and the fan-out type circuit redistribution layer electrically couples the photonic integrated circuit and the electronic integrated circuit.
[0006] According to the optical module packaging architecture disclosed in the present invention, the fan-out type circuit redistribution layer electrically couples the photonic integrated circuit and the electronic integrated circuit. The electrical signals generated by the photonic integrated circuit are fanned out to the electronic integrated circuit, which is beneficial to shortening the signal transmission path, reducing the form factor of the packaging architecture, and reducing the resistance-capacitance delay effect, thereby improving the signal transmission efficiency, reducing the insertion loss, and increasing the optical transmission bandwidth.
[0007] The above description of the content of the present invention and the following description of the embodiments are used to demonstrate and explain the principles of the present invention and provide a further explanation of the scope of the patent application of the present invention. Brief Description of the Drawings
[0008] Figure 1 Schematic diagram of an optical module packaging architecture according to an embodiment of the present invention;
[0009] Figure 2 is Figure 1 Top view schematic diagram of the cross-section of the optical module packaging architecture along line 2-2;
[0010] Figure 3 is Figure 1 a top view schematic diagram of a cross-section along line 3-3 of the optical module packaging architecture;
[0011] Figure 4 is Figure 1 a schematic diagram of the signal transmission path of the optical module packaging architecture;
[0012] Figures 5 to 9 illustrates Figure 1 a schematic diagram of the insertion loss and return loss of the optical module packaging architecture.
[0013] Symbol Explanation
[0014] 1: Optical module packaging architecture
[0015] 10: Mold encapsulation layer
[0016] 2: Optical fiber
[0017] 21: End face
[0018] 3: Substrate
[0019] 20: Photonic integrated circuit
[0020] 210: Active side
[0021] 30: Electronic integrated circuit
[0022] 40: Fan-out line redistribution layer
[0023] 410, 420: Interconnection points
[0024] 41: Line redistribution layer
[0025] 430: Line
[0026] 440: Through-hole array
[0027] 441: Through-hole
[0028] 50: Embedded interposer carrier board
[0029] 510: Silicon substrate
[0030] 521, 522: Through-silicon vias
[0031] 60: Microcontroller unit
[0032] 61: Protective cover
[0033] 70: Memory chip
[0034] 80: Switching element
[0035] 90: Through-mold via array
[0036] 910: Through - molded via hole
[0037] A1: Component area
[0038] A2: Circuit area
[0039] D: Lamination direction
[0040] P1, P2: Signal transmission paths
[0041] S0, S1, S2, S3: Signal transmission paths Detailed implementation manners
[0042] In the following implementation manners, the detailed features and advantages of the present invention are described in detail. The content is sufficient for any person skilled in the relevant art to understand the technical content of the present invention and implement it accordingly. And according to the content disclosed in this specification, the claims and the drawings, any person skilled in the relevant art can easily understand the relevant purposes and advantages of the present invention. The following embodiments further illustrate the viewpoints of the present invention in detail, but do not limit the scope of the present invention in any way.
[0043] Please refer to Figure 1 , which is a schematic diagram of an optical module packaging architecture according to an embodiment of the present invention. In this embodiment, the optical module packaging architecture includes a molded layer 10, a photonic integrated circuit 20, an electronic integrated circuit 30, and a fan - out circuit redistribution layer 40.
[0044] The molded layer 10 is, for example but not limited to, an epoxy resin layer or a solid molded material layer. The photonic integrated circuit 20 is disposed within the molded layer 10. The fan - out circuit redistribution layer 40 is disposed on the molded layer 10, and the electronic integrated circuit 30 is disposed on the fan - out circuit redistribution layer 40. Further, the active side 210 of the photonic integrated circuit 20 may be provided with optical elements (not shown), such as waveguides or optical lenses. The end face 21 of the optical fiber 2 can be optically coupled to the active side 210 of the photonic integrated circuit 20 to allow optical signals to be exchanged between the photonic integrated circuit 20 and the optical fiber 2. The active side 210 of the photonic integrated circuit 20 can receive optical signals and convert them into electrical signals for output. In this embodiment, the photonic integrated circuit 20 further includes a silicon modulator and a waveguide photodetector having a passive photonic circuit.
[0045] The electronic integrated circuit 30 may include an application specific integrated circuit (ASIC), such as a driver or a receiver used in an optical communication system. The electronic integrated circuit 30 may also include any one of transistors, voltage converters, digital signal processors (DSPs), transimpedance amplifiers (TIAs), and clock and data recovery (CDR) circuits. The molding layer 10 and the electronic integrated circuit 30 are respectively located on opposite sides of the fan-out line redistribution layer 40. Further, the fan-out line redistribution layer 40 is formed above the molding layer 10 and exposes the active side 210 of the photonic integrated circuit 20. The molding layer 10 and the electronic integrated circuit 30 are sequentially arranged along the stacking direction D as Figure 1 shown. The electronic integrated circuit 30 partially overlaps with the photonic integrated circuit 20 in the stacking direction D.
[0046] The fan-out line redistribution layer 40 electrically couples the photonic integrated circuit 20 and the electronic integrated circuit 30. Further, the fan-out line redistribution layer 40 may include interconnects 410 connected to the photonic integrated circuit 20, so that each interconnect 410 forms a conduction path. Similarly, the fan-out line redistribution layer 40 may also include interconnects 420 connected to the electronic integrated circuit 30, so that each interconnect 420 forms a conduction path. Each of the interconnects 410 and 420 may include at least one of a line, a via, and a metal pad. The number of conduction paths between the fan-out line redistribution layer 40 and the photonic integrated circuit 20 (i.e., the number of interconnects 410) is less than the number of conduction paths between the fan-out line redistribution layer 40 and the electronic integrated circuit 30 (i.e., the number of interconnects 420).
[0047] The optical module package architecture 1 of this embodiment further includes an embedded interposer carrier 50 disposed in the molding layer 10. The electronic integrated circuit 30 is electrically coupled to the embedded interposer carrier 50. Further, the embedded interposer carrier 50 is electrically coupled to the electronic integrated circuit 30 via the fan-out line redistribution layer 40. The embedded interposer carrier 50 includes a silicon substrate 510 and a plurality of through-silicon vias (TSVs) formed in the silicon substrate 510. The through-silicon vias may include through-silicon vias 521 connected to the electronic integrated circuit 30.
[0048] The optical module packaging architecture 1 of this embodiment further includes a microcontroller unit (MCU) 60. The microcontroller unit 60 is disposed on the fan-out line redistribution layer 40, and the embedded interposer carrier 50 electrically couples the microcontroller unit 60 and the electronic integrated circuit 30. A plurality of through-silicon vias of the embedded interposer carrier 50 include through-silicon vias 522 connected to the microcontroller unit 60. The number of through-silicon vias 522 is greater than the number of through-silicon vias 521. Electrical coupling between the microcontroller unit 60 and the through-silicon vias 522 can be achieved by wire bonding. A protective cover 61 can be additionally provided to cover the microcontroller unit 60 to provide airtightness. The microcontroller unit 60 may include a central processing unit (CPU), a memory (RAM), and an input / output (I / O) interface integrated into a single chip.
[0049] The optical module packaging architecture 1 of this embodiment further includes a memory chip 70, and the memory chip 70 is disposed on the fan-out line redistribution layer 40. The memory chip 70 can be a flash memory.
[0050] The optical module packaging architecture 1 of this embodiment further includes a switching element 80 electrically coupled to the microcontroller unit 60 and the memory chip 70. The switching element 80 is disposed within the encapsulation layer 10, and the switching element 80 is electrically coupled to the embedded interposer carrier 50. Further, the embedded interposer carrier 50 and the switching element 80 are formed on the same layer, that is, both are disposed within the encapsulation layer 10 and at the same horizontal height. The switching element 80 is electrically coupled to the embedded interposer carrier 50 via the fan-out line redistribution layer 40. The switching element 80 can be a single chip including a switching circuit.
[0051] The optical module packaging architecture 1 of this embodiment further includes a through-encapsulation via array 90 disposed within the encapsulation layer 10. Please refer to Figure 2 together. Figure 1 is a top view schematic diagram of the cross-section of the optical module packaging architecture along line 2-2. Figure 2 The cross-section can be understood as the cross-section of the encapsulation layer 10 in Figure 1 . From the top view perspective in Figure 2 , the optical module packaging architecture 1 has an element area A1 and a line area A2 surrounding the element area A1. The embedded interposer carrier 50 and the switching element 80 are located within the element area A1. The through-encapsulation via array 90 is located within the line area A2 and not within the element area A1. The through-encapsulation via array 90 includes a plurality of through-encapsulation vias 910 (Through Molding Via, TMV). Some of the through-encapsulation vias 910 are electrically coupled to the electronic integrated circuit 30, and some other through-encapsulation vias 910 are electrically coupled to the memory chip 70.
[0052] The optical module packaging architecture 1 of this embodiment further includes a redistribution layer 41. Please refer to Figure 3 together, for Figure 1 a top view schematic of the cross-section along line 3-3 of the optical module packaging architecture. Figure 3 The cross-section of Figure 1 can be understood as the cross-section of the redistribution layer 41 in
[0053] The optical module packaging architecture 1 of this embodiment can be disposed on the substrate 3. Further, the substrate 3 is, for example, a printed circuit board. The redistribution layer 41 can be electrically coupled to the circuit of the substrate 3, thereby allowing signal transmission between the electronic integrated circuit 30, the microcontroller unit 60, and the memory chip 70 and the substrate 3.
[0054] According to the optical module packaging architecture 1 of this embodiment, the switching element 80 can regulate the signal transmission path of the embedded interposer carrier 50. Further, the switching element 80 can regulate the number of through-silicon vias 522 of the embedded interposer carrier 50 in the conductive state according to the signal transmission bandwidth requirement. Please refer to Figure 4 together, for Figure 1 a schematic diagram of the signal transmission path of the optical module packaging architecture. The signal transmission path associated with the embedded interposer carrier 50 includes the signal transmission path P1 between the electronic integrated circuit 30 and the microcontroller unit 60 and the signal transmission path P2 between the memory chip 70 and the microcontroller unit 60. The microcontroller unit 60 is used to receive the electrical signal from the electronic integrated circuit 30 to set the operating parameters of the component, and the memory chip 70 is used to store the foregoing operating parameters. According to the signal transmission bandwidth requirement, the switching element 80 can switch at least some of the through-silicon vias 521, 522 between the open state and the conductive state.
[0055] According to the optical module packaging architecture 1 of this embodiment, the fan-out type circuit redistribution layer 40 is electrically coupled to the photonic integrated circuit 20 and the electronic integrated circuit 30. The electrical signals generated by the photonic integrated circuit 20 are fanned out to the electronic integrated circuit 30, which is beneficial to shortening the signal transmission path, reducing the size of the packaging architecture, and reducing the resistance-capacitance delay effect, thereby improving the signal transmission efficiency, reducing the insertion loss, and increasing the optical transmission bandwidth.
[0056] According to the optical module packaging architecture 1 of this embodiment, the embedded interposer carrier board 50 is electrically coupled to the microcontroller unit 60 and the electronic integrated circuit 30. Through the embedded interposer carrier board 50 as a bridging circuit, the through-silicon vias 521 and 522 therein can improve the signal transmission rate, thereby allowing high-speed signal transmission between the electronic integrated circuit 30 and the microcontroller unit 60.
[0057] According to the optical module packaging architecture 1 of this embodiment, the through-mold via array 90, the embedded interposer carrier board 50, and the switching element 80 are arranged in different regions, for example, respectively arranged in Figure 2 the component area A1 and the circuit area A2 in. Thus, space can be reserved in the mold encapsulation layer 10 to embed the photonic integrated circuit 20, the embedded interposer carrier board 50, and the switching element 80, which is beneficial to reducing the parasitic capacitance, that is, reducing the insertion loss, and further optimizing the impedance of the optical module packaging architecture 1. In addition, as Figure 1 and Figure 2 shown, when designing the component configuration of the optical module packaging architecture 1, since the through-mold via array 90 is distributed throughout the circuit area A2, components such as the electronic integrated circuit 30 and the memory chip 70 can be arranged at any position in the circuit area A2, because there are through-mold vias 910 at any position in the circuit area A2 that can be electrically coupled to the electronic integrated circuit 30 or the memory chip 70, which is beneficial to increasing the manufacturing process yield and reducing the manufacturing cost.
[0058] According to the optical module packaging architecture 1 of this embodiment, at least one circuit 430 of the circuit redistribution layer 41 corresponds to a plurality of vias 441. Thus, the circuit 430 is connected to a plurality of vias 441 instead of only a single via 441, which is beneficial to having a high current load capacity.
[0059] Figures 5 to 9 Describe Figure 1 the insertion loss and return loss of the optical module packaging architecture. As Figure 5 shown, the insertion loss and return loss are measured for the signal transmission path S0 between the photonic integrated circuit 20 and the electronic integrated circuit 30 to verify the loss reduction effect provided by the fan-out type circuit redistribution layer 40. As Figure 6As shown, in high-frequency transmission applications where the currently recognized industry frequency ranges from approximately 30 gigahertz (GHz) to 55 GHz, the insertion loss (S21) can be as low as within the range of -0.04 decibels (dB) to -0.14 dB, and the return loss (S11) can be as low as within the range of -16 dB to -21 dB.
[0060] Also, as Figure 7 shown, for the signal transmission path S1 between the electronic integrated circuit 30 and the substrate 3, the signal transmission path S2 between the electronic integrated circuit 30 and the line redistribution layer 41, and the signal transmission path S3 between the electronic integrated circuit 30 and the through-molded via array 90, the insertion loss and the return loss are measured respectively to verify the loss reduction effect provided by the through-molded via array 90.
[0061] As Figure 8 shown, in high-frequency transmission applications where the currently recognized industry frequency ranges from approximately 30 GHz to 55 GHz, the insertion loss (S21) of the signal transmission path S1 can be as low as within the range of -0.64 dB to -1.10 dB, the insertion loss of the signal transmission path S2 can be as low as within the range of -0.49 dB to -0.87 dB, and the insertion loss of the signal transmission path S3 can be as low as within the range of -0.14 dB to -0.24 dB.
[0062] As Figure 9 shown, in high-frequency transmission applications where the currently recognized industry frequency ranges from approximately 30 GHz to 55 GHz, the return loss (S11) of the signal transmission path S1 can be as low as within the range of -20 dB to -27 dB, the return loss of the signal transmission path S2 can be as low as within the range of -18 dB to -29 dB, and the return loss of the signal transmission path S3 can be as low as within the range of -27 dB to -34 dB.
[0063] In summary, according to the optical module packaging architecture disclosed by the present invention, the fan-out type line redistribution layer electrically couples the photonic integrated circuit and the electronic integrated circuit. The electrical signal generated by the photonic integrated circuit is fanned out to the electronic integrated circuit, which is beneficial for shortening the signal transmission path, reducing the size of the packaging architecture, and reducing the resistance-capacitance delay effect, thereby improving the signal transmission efficiency, reducing the insertion loss, and increasing the optical transmission bandwidth.
[0064] In addition, by using the buried interposer carrier board as a bridging circuit, the through-silicon vias therein can improve the signal transmission rate, thereby allowing high-speed signal transmission between the electronic integrated circuit and the microcontroller unit.
Claims
1. An optical module packaging architecture, comprising: A molding encapsulation layer; A photonic integrated circuit disposed within the molding encapsulation layer; A fan-out circuit redistribution layer disposed on the molding encapsulation layer; and An electronic integrated circuit disposed on the fan-out circuit redistribution layer, and the fan-out circuit redistribution layer electrically couples the photonic integrated circuit and the electronic integrated circuit.
2. The optical module packaging architecture according to claim 1, wherein the number of conduction paths between the fan-out circuit redistribution layer and the photonic integrated circuit is less than the number of conduction paths between the fan-out circuit redistribution layer and the electronic integrated circuit.
3. The optical module packaging architecture according to claim 1, further comprising an embedded interposer carrier, wherein the embedded interposer carrier is disposed within the molding encapsulation layer, and the electronic integrated circuit is electrically coupled to the embedded interposer carrier.
4. The optical module packaging architecture according to claim 3, further comprising a microcontroller unit, wherein the microcontroller unit is disposed on the fan-out circuit redistribution layer, and the embedded interposer carrier electrically couples the microcontroller unit and the electronic integrated circuit.
5. The optical module packaging architecture according to claim 4, further comprising a memory chip, wherein the memory chip is disposed on the fan-out circuit redistribution layer.
6. The optical module packaging architecture according to claim 5, further comprising a switching element electrically coupled to the microcontroller unit and the memory chip, wherein the switching element is disposed within the molding encapsulation layer, and the switching element is electrically coupled to the embedded interposer carrier.
7. The optical module packaging architecture according to claim 6, wherein the embedded interposer carrier and the switching element are formed on the same layer.
8. The optical module packaging architecture according to claim 4, wherein the embedded interposer carrier includes a plurality of through-silicon vias, the through-silicon vias include a plurality of first through-silicon vias connected to the microcontroller unit and a plurality of second through-silicon vias connected to the electronic integrated circuit, and the number of the first through-silicon vias is greater than the number of the second through-silicon vias.
9. The optical module packaging architecture according to claim 3, further comprising a through-molding via array disposed within the molding encapsulation layer, wherein the optical module packaging architecture has an element region and a circuit region surrounding the element region in a top view, the embedded interposer carrier is located within the element region, and the through-molding via array is located within the circuit region and not within the element region.
10. The optical module packaging architecture according to claim 9, further comprising a switching element located within the element region, wherein the switching element is disposed within the molding encapsulation layer, and the switching element is electrically coupled to the embedded interposer carrier.
11. The optical module packaging architecture according to claim 1, wherein the molding encapsulation layer and the electronic integrated circuit are sequentially disposed along the stacking direction, and the electronic integrated circuit partially overlaps the photonic integrated circuit in the stacking direction.
12. The optical module packaging architecture according to claim 1, further comprising a circuit redistribution layer, the fan-out circuit redistribution layer and the circuit redistribution layer are respectively located on opposite sides of the molding encapsulation layer, the circuit redistribution layer is electrically coupled to the electronic integrated circuit, the circuit redistribution layer includes a circuit and a via array, and the via array includes at least two vias connected to the circuit.