An on-chip integrated voltage regulator chip power supply circuit with adjustable output amplitude

Abstract

The present invention belongs to the technical field of motorcycle voltage regulator chip circuits, and particularly relates to an on-chip integrated voltage regulator chip power supply circuit with adjustable output amplitude. The circuit comprises a power supply module 1, which receives a battery voltage signal BAT and three-phase electrical signals PH1-PH3 to generate an on-chip power supply VCC; a power supply module 2, whose power supply terminal is connected to the power supply VCC to generate an on-chip reference voltage VREF. The output voltages VP1-VP2 are used to power subsequent digital and analog modules, respectively; an output voltage detection module, which receives the battery voltage signal BAT and detects its voltage, outputting a voltage signal VSEN to an output voltage regulation module; and an output voltage regulation module. By utilizing an on-chip power generation circuit, a voltage detection circuit, and a voltage control circuit, the present invention achieves stable and reliable voltage output, providing a stable charging voltage for the load battery.

Description

Technical Field

[0001] The invention belongs to the technical field of motorcycle voltage regulator chip circuits, and in particular relates to an on-chip integrated voltage regulator chip power supply circuit with adjustable output amplitude. Background Art

[0002] With the continuous miniaturization, integration, and intelligent advancements in electronic devices, on-chip voltage regulator chips are becoming increasingly common in various electronic products. In the motorcycle sector, voltage regulator chips must stably adapt to the complex voltage output of the magneto motor to power the entire vehicle's electrical system. However, existing power supply circuits for on-chip voltage regulator chips present numerous challenges in diverse application scenarios. For example, traditional thyristor (SCR) short-circuit voltage regulators employ a parallel voltage regulation scheme, controlling the SCR to conduct when the output voltage exceeds the regulating voltage. When the magneto motor outputs high power, the voltage regulator's thermal load increases dramatically. To prevent the voltage regulator from overheating, the heat dissipation area must be increased. This not only significantly increases the voltage regulator's size and cost, but also makes it unsuitable for high-power voltage regulation. Existing SCR short-circuit voltage regulators, when operating at high power, require increasing the heat dissipation area to cope with the thermal load, severely impacting the regulator's practicality and cost-effectiveness. The on-chip integrated voltage regulator chip also faces similar thermal management challenges when processing large currents and high powers. The power devices inside the chip generate a large amount of heat during operation. If the heat dissipation design is not good, the chip temperature will be too high, which will affect its performance and reliability.

[0003] Traditional contact-type voltage regulators present numerous challenges in voltage regulation accuracy. For example, when the brushes slide across the coils for voltage regulation, they are affected by factors such as brush position accuracy and contact resistance variations, making voltage regulation accuracy difficult to maintain. For power supply circuits with integrated voltage regulators, their feedback control mechanisms may not be able to adjust the output voltage promptly and accurately when faced with complex load variations. For example, when a motorcycle's electrical equipment switches from low-power indicator lights to high-power headlights, the load current fluctuates dramatically. Some integrated voltage regulators may not be able to quickly stabilize the output voltage at the target value, resulting in large voltage fluctuations that affect the normal operation of the electrical equipment. For example, some early motorcycle voltage regulators could experience output voltage differences of up to several volts between light and heavy loads, which is extremely detrimental to modern motorcycle electronic equipment, such as the fuel injection system's electronic control unit, which requires high voltage stability.

[0004] Electromagnetic compatibility is also a concern for power circuits with integrated voltage regulators. Traditional thyristor voltage regulation methods generate sudden current fluctuations during the thyristor's on- and off-states, causing significant electromagnetic interference. This electromagnetic interference is further exacerbated when inductive loads (such as motors and relays) are present on motorcycles, leading to unstable output voltage and even affecting the normal operation of other surrounding electronic devices. While integrated voltage regulators optimize the circuit structure to a certain extent, they still struggle to completely avoid electromagnetic interference issues due to high-frequency switching and complex electromagnetic environments.

[0005] In summary, the above problems restrict the further improvement of the performance of the motorcycle electrical system, and it is urgent to solve the above problems by developing an on-chip integrated voltage regulator chip power supply circuit with adjustable output amplitude. Summary of the Invention

[0006] The present invention aims to provide an on-chip integrated voltage regulator power supply circuit with adjustable output amplitude. This circuit generates operating power within the voltage regulator chip, eliminating the need for an external power supply. It also generates high-precision analog and digital power for on-chip low-voltage circuits, significantly reducing the impact of power supply interference. Furthermore, it enables precise adjustment of the voltage output range, ensuring stable output voltage.

[0007] To solve the above technical problems, the present invention provides an on-chip integrated voltage regulator chip power supply circuit with adjustable output amplitude, comprising:

[0008] Power module 1, the power module 1 is used to input the battery voltage signal BAT and the three-phase electrical signals PH1-PH3 to generate an on-chip power supply VCC;

[0009] Power module 2, the power supply terminal of the power module 2 is connected to the power supply VCC to generate an on-chip reference voltage VREF, and the output voltages VP1 and VP2 are used to supply power to the subsequent digital module and analog module respectively;

[0010] An output voltage detection module, which is used to input a battery voltage signal BAT and detect its voltage, and output a voltage signal VSEN to the output voltage regulation module;

[0011] An output voltage regulation module is configured to divide the input voltage signal VSEN by resistors and compare them with the voltage signal VCH and the voltage signal VCL to adjust the amplitude of the voltage regulation signal OUT; wherein the voltage signal VCH and the voltage signal VCL are respectively generated by dividing the reference voltage VREF by resistors.

[0012] Preferably, the power module 1 includes: transistors Q1~Q5, PMOS transistors P1~P8, NMOS transistors N1~N8 and resistors R1~R12; the three-phase electrical signals PH1~PH3 are respectively connected to the bases of the transistors Q1~Q3 through the resistor R3, the emitters and collectors of the transistors Q1~Q3 are cascaded in sequence, the emitter of the transistor Q3 is grounded, the collector of the transistor Q1 is connected to the base and collector of the transistor Q4, one end of the resistor R4 and the drain of the NMOS transistor N2 to generate a control signal TP_C; the emitter of the transistor Q4 is connected to the resistors R5~ One end of resistor R6 and the gate of NMOS transistor N3 generate control signal TP_G5, the other end of resistor R6 is grounded, the source of NMOS transistor N2 is grounded, and the gate is connected to control signal TP_G3; the other end of resistor R4 and the source of PMOS transistors P4~P5, one end of resistor R7 and resistor R10, and the drain of NMOS transistor N8 are all connected to battery voltage signal BAT; the gate of PMOS transistor P4 is connected to control signal TP_G2, and the drain is connected to the other end of resistor R5; the other end of resistor R7 is connected to the drain of NMOS transistor N3, and the NMOS The source of transistor N3 is connected to the base and collector of transistor Q5, the emitter of transistor Q5 is connected to one end of resistor R8, the other end of resistor R8 is connected to one end of resistor R9 and the power supply to establish indication signal TD; the other end of resistor R9 is connected to the drain and gate of NMOS transistor N4, and the gates of NMOS transistors N5-N6, the sources of NMOS transistors N4-N6 are grounded; the drain of NMOS transistor N5 is connected to the drain of NMOS transistor N7, the gate and drain of PMOS transistor P7, and the gate of PMOS transistor P8, the gate of NMOS transistor N7 is connected to A control signal TP_G4 is input, the source of the NMOS transistor N7 is connected to the drain of the NMOS transistor N6; the drain and gate of the PMOS transistor P5 are connected to the source of the PMOS transistor P6, and the drain and gate of the PMOS transistor P6 are connected to the source of the PMOS transistor P7; the other end of the resistor R10 is connected to the source of the PMOS transistor P8, the drain of the PMOS transistor P8 is connected to one end of the resistor R11, the other end of the resistor R11 is connected to one end of the resistor R12, the source and gate of the NMOS transistor N8, and the power supply VCC, and the other end of the resistor R12 is grounded.

[0013] Preferably, the power supply module 1 further includes a TP_G2 signal generating circuit, which includes: PMOS tubes P1~P3, an NMOS tube N1 and resistors R1~R2; one end of the resistor R1 and the source of the PMOS tube P1 are connected to the battery voltage signal BAT, and the other end of the resistor R1 is connected to the drain of the NMOS tube N1, the gate and drain of the PMOS tube P3 and outputs the control signal TP_G2; the gate of the NMOS tube N1 is connected to the control signal TP_G1, and the source is connected to one end of the resistor R2, and the other end of the resistor R2 is grounded; the gate and drain of the PMOS tube P1 are connected to the source of the PMOS tube P2, and the gate and drain of the PMOS tube P2 are connected to the source of the PMOS tube P3.

[0014] Preferably, the power establishment indication signal TD further includes a grounded capacitor; the power supply VCC further includes two grounded capacitors connected in parallel, and the other end of one of the capacitors is connected in series with a resistor.

[0015] Preferably, the power supply module 2 includes: a bandgap reference circuit BGR, a VP power supply generating circuit and a VREF power supply generating circuit; the output end of the bandgap reference circuit BGR is respectively connected to the input end of the VP power supply generating circuit and the VREF power supply generating circuit, and the output end of the VP power supply generating circuit and the VREF power supply generating circuit respectively outputs voltages VP1~VP2 and a reference voltage VREF.

[0016] Preferably, the VP power supply generating circuit includes: an operational amplifier OP1, NMOS transistors N9~N11 and resistors R21~R25; the non-inverting input terminal of the operational amplifier OP1 is connected to the output signal BGR_OUT of the bandgap reference circuit BGR, the inverting input terminal is connected to one end of the resistors R22~R23, the other end of the resistor R23 is grounded, and the output terminal of the operational amplifier OP1 is connected to the gate of the NMOS transistor N9; the drain of the NMOS transistor N9 is connected to one end of the resistor R21, and the other end of the resistor R21 is connected to the power supply VCC; the source of the NMOS transistor N9 is connected to the other end of the resistor R22 and one end of the resistors R24~R25 and outputs the voltage VP, the other ends of the resistors R24~R25 are respectively connected to the gates of the NMOS transistors N10~N11 and generate voltages VP1 and VP2 accordingly, and the sources and drains of the NMOS transistors N10~N11 are grounded.

[0017] Preferably, the VREF power supply generating circuit includes: an operational amplifier OP2, PMOS transistors P17~P18, an NMOS transistor N17 and resistors R51~R57; the non-inverting input terminal of the operational amplifier OP2 is connected to the output terminal signal BGR_OUT of the bandgap reference circuit BGR, the inverting input terminal is connected to one end of the resistors R53~R54, the other end of the resistor R54 is grounded, the output terminal of the operational amplifier OP2 is connected to the gate of the PMOS transistor P17; the drain of the PMOS transistor P17 is grounded, the source of the PMOS transistor P17 is connected to the drain of the PMOS transistor P18 and the gate of the NMOS transistor N17, and the PMOS transistor P18 is grounded. The gate of the PMOS transistor P18 is connected to the bias voltage VB2, the source of the PMOS transistor P18 is connected to one end of the resistor R51, and the other end of the resistor R51 is connected to the power supply VCC; the drain of the NMOS transistor N17 is connected to one end of the resistor R52, and the other end of the resistor R52 is connected to the power supply VCC; the source of the NMOS transistor N17 is connected to the other end of the resistor R53 and one end of the resistor R55 and outputs the reference voltage VREF; the other end of the resistor R55 is connected to one end of the resistor R56 and outputs the voltage signal VCH, the other end of the resistor R56 is connected to one end of the resistor R57 and outputs the voltage signal VCL, and the other end of the resistor R57 is grounded.

[0018] Preferably, the output voltage regulation module includes: PMOS tubes P9~P12, comparators COM1~COM2, a digital module, resistors R31~R38 and capacitors C1~C5; one end of the resistor R31 and the source of the PMOS tube P9 and the PMOS tube P12 are connected to the voltage signal VSEN, the other end of the resistor R31 is connected to one end of the resistor R32, and the other end of the resistor R32 is connected to the grounded current source Iref; the gate and drain of the PMOS tube P9 are connected to the source of the PMOS tube P10, the gate and drain of the PMOS tube P10 are connected to the source of the PMOS tube P11, the gate and drain of the PMOS tube P11 are connected to one end of the resistor R32 and the gate of the PMOS tube P12; the drain of the PMOS tube P12 is connected to one end of the resistor R33 The other end of the resistor R33 is connected to the grounded resistor R34, the grounded capacitor C3, and the non-inverting input end of the comparator COM1~COM2; the inverting input end of the comparator COM1 is connected to the grounded capacitor C2 and one end of the resistor R36, the other end of the resistor R36 is connected to the grounded capacitor C1 and one end of the resistor R35, and the other end of the resistor R35 is connected to the voltage signal VCH; the inverting input end of the comparator COM2 is connected to the grounded capacitor C5 and one end of the resistor R38, the other end of the resistor R38 is connected to the grounded capacitor C4 and one end of the resistor R37, and the other end of the resistor R37 is connected to the voltage signal VCL; the output ends of the comparators COM1~COM2 are connected to the input end of the digital module, and the output end of the digital module outputs the voltage regulation signal OUT.

[0019] Preferably, the digital module adopts a phase OR operation, that is, when the voltage signal VSEN is proportionally reduced by the resistor voltage divider, the voltage is compared with the voltage signal VCL and the voltage signal VCH respectively. When the voltage signal VSEN is lower than the voltage signal VCL, the output of the voltage regulation signal OUT is a low voltage, and the three-phase electricity continues to be charged. When the voltage signal VSEN is higher than the voltage signal VCH, the output of the voltage regulation signal OUT is a high voltage.

[0020] Preferably, the bandgap reference circuit BGR includes: PMOS transistors P13 to P16, NMOS transistors N12 to N16, resistors R41 to R49, capacitor C6, transistors Q6 to Q8, and operational amplifier OP3; one end of the resistor R41 is connected to the power supply VCC, and the other end is connected to the source of the PMOS transistor P13 and the PMOS transistors P15 to P16, and one end of the resistor R48; the gate of the PMOS transistor P13 is connected to the bias voltage VB1, and the drain of the PMOS transistor P13 is connected to the source of the PMOS transistor P14. The drain of the PMOS tube P14 is connected to one end of the resistor R42, the other end of the resistor R42 is connected to one end of the resistor R43 and the emitter of the transistor Q6 and outputs the signal BGR_OUT; the other end of the resistor R43 is connected to the resistor R44 and one end of the resistor R45, the other end of the resistor R44 is connected to the inverting input terminal of the operational amplifier OP3 and the emitter of the transistor Q7, the other end of the resistor R45 is connected to the non-inverting input terminal of the operational amplifier OP3 and one end of the resistor R46; the transistors Q7 and Q8 are connected to the inverting input terminal of the operational amplifier OP3 and the emitter of the transistor Q7. The base and collector are grounded, and the emitter of the transistor Q8 is connected to the other end of the resistor R46; the output end of the operational amplifier OP3 is connected to the base of the transistor Q6, and the collector of the transistor Q6 is grounded; the gate of the PMOS transistor P14 is connected to the grounded capacitor C6 and one end of the resistor R47, and a grounded diode; the other end of the resistor R47 is connected to the drain of the PMOS transistor P15, and the gate of the PMOS transistor P15 is connected to the gate and drain of the PMOS transistor P16 and the drain of the NMOS transistor N12 to generate a bias voltage. voltage VB1; the source of the NMOS transistor N12 is connected to the gate of the NMOS transistor N13 and the grounded resistor R49, the gate of the NMOS transistor N12 is connected to the drain of the NMOS transistor N13, the gate and drain of the NMOS transistor N14, and the other end of the resistor R48; the source of the NMOS transistor N13 is grounded, the source of the NMOS transistor N14 is connected to the gate and drain of the NMOS transistor N15, the source of the NMOS transistor N15 is connected to the gate and drain of the NMOS transistor N16, and the source of the NMOS transistor N16 is grounded.

[0021] Preferably, when the battery is supplying power, i.e., the battery voltage signal BAT is at a high level, the control signal TP_G2 is increased to a high level, while the control signal TP_G1 and the control signal TP_G3 are initially both at a low level. The PMOS transistor P4 is cut off, and the voltage of the battery voltage signal BAT is divided by resistors R4 and R6 and input to the gate of the NMOS transistor N3, turning on the NMOS transistor N3, thereby charging the capacitor externally connected to the power supply establishment indication signal TD. When the power supply establishment indication signal TD is charged to a certain voltage value, the NMOS transistors N4 and NMOS transistors N5 are turned on, and the gate voltage of the PMOS transistor P8 is pulled down. At this time, the PMOS transistor P8 is turned on, so that the voltage of the power supply VCC is increased and kept high, thereby establishing the power supply VCC and the digital circuit begins to operate normally.

[0022] Preferably, when in normal working mode, the magneto inputs three-phase electricity, the power supply VCC is increased and kept high, and the power supply establishment indication signal TD is kept high;

[0023] When in low power consumption mode, that is, when the magnetic motor stops rotating, that is, PH1=PH2=PH3=0, the control signal TP_G3 becomes high, turning on the NMOS tube N2, and the control signal TP_C is pulled low, then the control signal TP_G5 becomes low, then the NMOS tube N3 is turned off, and the power establishment indication signal TD is discharged through the NMOS tube N4. The mirror current copied by the NMOS tube N5 also decreases accordingly. After decreasing to a certain extent, the PMOS tube P8 is turned off, and then the NMOS tube N8 is turned off, and the power supply VCC starts to discharge. The chip does not consume battery current at this time. Other modules inside the chip are powered by the energy stored in the capacitor external to the power supply VCC, so that they are all in normal working condition.

[0024] Preferably, when the power supply VCC decreases to a certain level, the digital circuit controls the control signal TP_G3 to a low level, the NMOS transistor N2 is turned off, and the voltage of the battery voltage signal BAT is input to the gate of the NMOS transistor N3 after being divided by the resistors R4 and R6, so that the NMOS transistor N3 is turned on, the power supply establishment indication signal TD is charged, the power supply VCC is established, and the digital circuit starts to work normally again, and the cycle changes in this way.

[0025] Compared with the prior art, the present invention has the following beneficial effects:

[0026] The present invention uses power module 1 to provide a stable and adaptable basic operating power supply VCC for the entire chip, eliminating the need for an additional off-chip operating power supply for the voltage regulator. Power module 2 utilizes its high-precision linear voltage regulator circuit, namely the reference voltage VREF, and the on-chip low-voltage operating power supply VP to significantly reduce on-chip power supply noise. Furthermore, the output voltage is monitored and adjusted in real time using an output voltage regulation module, limiting the output voltage to a certain range and significantly improving output voltage accuracy. This addresses the technical deficiencies of conventional on-chip integrated power supplies in voltage regulators, such as thermal management, voltage regulation accuracy, and voltage range adaptability. By utilizing the on-chip power supply circuit, voltage detection circuit, and voltage regulation circuit, the present invention achieves stable and reliable voltage output, providing a stable charging voltage for the load battery. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 This is a block diagram of the overall structure of the power supply circuit provided by the present invention.

[0028] Figure 2 This is a circuit schematic diagram of the power module provided by the present invention.

[0029] Figure 3 This is a schematic diagram of the TP_G2 signal generating circuit provided by the present invention.

[0030] Figure 4 This is a schematic diagram of the VP power generation circuit in the power module 2 provided by the present invention.

[0031] Figure 5 This is a schematic diagram of the VREF power generation circuit in the power module 2 provided by the present invention.

[0032] Figure 6 This is a circuit schematic diagram of the output voltage regulation module provided by the present invention.

[0033] Figure 7 This is a schematic diagram of a bandgap reference circuit provided by the present invention. DETAILED DESCRIPTION

[0034] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are greatly simplified and not to exact scale, and are only used to facilitate and clearly illustrate the embodiments of the present invention.

[0035] like Figure 1 As shown, an embodiment of the present invention specifically provides an on-chip integrated voltage regulator chip power supply circuit with adjustable output amplitude, comprising:

[0036] Power module 1, the power module 1 is used to input the battery voltage signal BAT and the three-phase electrical signals PH1-PH3 to generate an on-chip power supply VCC;

[0037] Power module 2, the power supply terminal of the power module 2 is connected to the power supply VCC to generate an on-chip reference voltage VREF, and the output voltages VP1 and VP2 are used to supply power to the subsequent digital module and analog module respectively;

[0038] An output voltage detection module, which is used to input a battery voltage signal BAT and detect its voltage, and output a voltage signal VSEN to the output voltage regulation module;

[0039] An output voltage regulation module is configured to compare the input voltage signal VSEN with the voltage signals VCH and VCL after resistor division, to adjust the amplitude of the voltage-regulated signal OUT. The voltage signals VCH and VCL are generated by resistor division of the reference voltage VREF. The output voltage regulation module adjusts the output amplitude while further suppressing fluctuations to ensure output voltage stability.

[0040] like Figure 2As shown, the power module 1 includes: transistors Q1~Q5, PMOS transistors P1~P8, NMOS transistors N1~N8 and resistors R1~R12; the three-phase electrical signals PH1~PH3 are respectively connected to the bases of the transistors Q1~Q3 through the resistor R3, the emitters and collectors of the transistors Q1~Q3 are cascaded in sequence, the emitter of the transistor Q3 is grounded, the collector of the transistor Q1 is connected to the base and collector of the transistor Q4, one end of the resistor R4 and the drain of the NMOS transistor N2 to generate a control signal TP_C; the emitter of the transistor Q4 is connected to the resistors R5~R 6 and the gate of the NMOS transistor N3 to generate a control signal TP_G5, the other end of the resistor R6 is grounded, the source of the NMOS transistor N2 is grounded, and the gate is connected to the control signal TP_G3; the other end of the resistor R4 and the sources of the PMOS transistors P4~P5, one end of the resistor R7 and the resistor R10, and the drain of the NMOS transistor N8 are all connected to the battery voltage signal BAT; the gate of the PMOS transistor P4 is connected to the control signal TP_G2, and the drain is connected to the other end of the resistor R5; the other end of the resistor R7 is connected to the drain of the NMOS transistor N3, and the NMOS The source of transistor N3 is connected to the base and collector of transistor Q5, the emitter of transistor Q5 is connected to one end of resistor R8, the other end of resistor R8 is connected to one end of resistor R9 and the power supply to establish indication signal TD; the other end of resistor R9 is connected to the drain and gate of NMOS transistor N4, and the gates of NMOS transistors N5-N6, the sources of NMOS transistors N4-N6 are grounded; the drain of NMOS transistor N5 is connected to the drain of NMOS transistor N7, the gate and drain of PMOS transistor P7, and the gate of PMOS transistor P8, the gate of NMOS transistor N7 is connected to A control signal TP_G4 is input, the source of the NMOS transistor N7 is connected to the drain of the NMOS transistor N6; the drain and gate of the PMOS transistor P5 are connected to the source of the PMOS transistor P6, and the drain and gate of the PMOS transistor P6 are connected to the source of the PMOS transistor P7; the other end of the resistor R10 is connected to the source of the PMOS transistor P8, the drain of the PMOS transistor P8 is connected to one end of the resistor R11, the other end of the resistor R11 is connected to one end of the resistor R12, the source and gate of the NMOS transistor N8, and the power supply VCC, and the other end of the resistor R12 is grounded.

[0041] like Figure 3As shown, the power module 1 further includes a TP_G2 signal generating circuit, which includes: PMOS transistors P1~P3, NMOS transistor N1 and resistors R1~R2; one end of the resistor R1 and the source of the PMOS transistor P1 are connected to the battery voltage signal BAT, the other end of the resistor R1 is connected to the drain of the NMOS transistor N1, the gate and drain of the PMOS transistor P3, and outputs the control signal TP_G2; the gate of the NMOS transistor N1 is connected to the control signal TP_G1, and the source is connected to one end of the resistor R2, and the other end of the resistor R2 is grounded; the gate and drain of the PMOS transistor P1 are connected to the source of the PMOS transistor P2, and the gate and drain of the PMOS transistor P2 are connected to the source of the PMOS transistor P3.

[0042] The power establishment indication signal TD also includes a grounded capacitor; the power supply VCC also includes two grounded capacitors, and the other end of one of the capacitors is connected in series with a resistor.

[0043] When the power module is operating, the input is the battery signal BAT, and the outputs are VCC and TD. VCC provides power to the chip, and TD is the power supply establishment indicator signal. When the battery is supplying power, BAT is high, the TP_G2 signal is raised to a high level, TP_G1 and TP_G3 are initially low, the P4 control tube is cut off, and the BAT voltage is divided by resistors R4 and R6 before being input to the gate of the N3 control tube. The N3 control tube is turned on, generating a voltage to charge the capacitor connected to the TD. When the TD is charged to a certain voltage value, the N4 and N5 tubes connected to the diode below this point will be turned on. The gate of the P8 tube is pulled low, the P8 tube is turned on, VCC is raised and kept high, VCC is established, and the digital circuit begins normal operation. In normal operation mode, the magneto inputs three-phase power, VCC is raised and kept high, and TD is kept high. In low-power mode, when the magneto stops (i.e., when PH1 = PH2 = PH3 = 0), TP_G3 goes high, turning on N2 and pulling TP_C low. This causes TP_G5 to go low, turning off N3 and discharging TD through N4. The mirror current replicated by N5 also decreases. After decreasing to a certain level, P8 turns off, which in turn turns off N8, causing VCC to discharge. The chip consumes almost no battery current. Other modules within the chip are powered by energy stored in capacitors connected to VCC and operate normally. When VCC drops to 4V, the digital circuit logic controls TP_G3 to go low, turning off N2. The BAT voltage, divided by resistors R4 and R6, is input to the gate of N3, turning on the N3 control transistor and charging TD. This establishes VCC, and the digital circuit resumes normal operation. This cycle repeats.

[0044] like Figure 4 and Figure 5As shown, the power supply module 2 includes: a bandgap reference circuit BGR, a VP power supply generating circuit and a VREF power supply generating circuit;

[0045] The VP power supply generating circuit includes: an operational amplifier OP1, NMOS transistors N9-N11, and resistors R21-R25; the non-inverting input terminal of the operational amplifier OP1 is connected to the output signal BGR_OUT of the bandgap reference circuit BGR, the inverting input terminal is connected to one end of resistors R22-R23, the other end of resistor R23 is grounded, and the output terminal of the operational amplifier OP1 is connected to the gate of the NMOS transistor N9; the drain of the NMOS transistor N9 is connected to one end of the resistor R21, the other end of the resistor R21 is connected to the power supply VCC; the source of the NMOS transistor N9 is connected to the other end of the resistor R22 and one end of the resistors R24-R25 and outputs the voltage VP, the other ends of the resistors R24-R25 are respectively connected to the gates of the NMOS transistors N10-N11 and generate voltages VP1 and VP2 accordingly, and the sources and drains of the NMOS transistors N10-N11 are grounded;

[0046] The VREF power generation circuit includes: an operational amplifier OP2, PMOS transistors P17-P18, an NMOS transistor N17 and resistors R51-R57; the non-inverting input terminal of the operational amplifier OP2 is connected to the output terminal signal BGR_OUT of the bandgap reference circuit BGR, the inverting input terminal is connected to one end of the resistors R53-R54, the other end of the resistor R54 is grounded, the output terminal of the operational amplifier OP2 is connected to the gate of the PMOS transistor P17; the drain of the PMOS transistor P17 is grounded, the source of the PMOS transistor P17 is connected to the drain of the PMOS transistor P18 and the gate of the NMOS transistor N17, and the gate of the PMOS transistor P18 is grounded. The PMOS transistor P18 is connected to a bias voltage VB2. The source of the PMOS transistor P18 is connected to one end of a resistor R51, the other end of which is connected to a power supply VCC. The drain of the NMOS transistor N17 is connected to one end of a resistor R52, the other end of which is connected to a power supply VCC. The source of the NMOS transistor N17 is connected to the other end of a resistor R53 and one end of a resistor R55, and outputs a reference voltage VREF. The other end of the resistor R55 is connected to one end of a resistor R56, and outputs a voltage signal VCH. The other end of the resistor R56 is connected to one end of a resistor R57, and outputs a voltage signal VCL. The other end of the resistor R57 is grounded. The resistance values ​​of the resistors R55, R56, and R57 are 24KΩ, 2KΩ, and 100KΩ, respectively. The reference voltage VREF is divided by the resistors R55, R56, and R57 to generate voltage signals VCH and VCL.

[0047] like Figure 7As shown, the bandgap reference circuit BGR includes: PMOS transistors P13 to P16, NMOS transistors N12 to N16, resistors R41 to R49, capacitor C6, transistors Q6 to Q8, and operational amplifier OP3; one end of the resistor R41 is connected to the power supply VCC, and the other end is connected to the source of the PMOS transistor P13 and PMOS transistors P15 to P16, and one end of the resistor R48; the gate of the PMOS transistor P13 is connected to the bias voltage VB1, and the drain of the PMOS transistor P13 is connected to the source of the PMOS transistor P14. The drain of the PMOS transistor P14 is connected to one end of the resistor R42, the other end of the resistor R42 is connected to one end of the resistor R43 and the emitter of the transistor Q6 and outputs the signal BGR_OUT; the other end of the resistor R43 is connected to the resistor R44 and one end of the resistor R45, the other end of the resistor R44 is connected to the inverting input of the operational amplifier OP3 and the emitter of the transistor Q7, the other end of the resistor R45 is connected to the non-inverting input of the operational amplifier OP3 and one end of the resistor R46; the transistors Q7 and Q8 are connected to the inverting input of the operational amplifier OP3 and the emitter of the transistor Q7. The base and collector are grounded, and the emitter of the transistor Q8 is connected to the other end of the resistor R46; the output end of the operational amplifier OP3 is connected to the base of the transistor Q6, and the collector of the transistor Q6 is grounded; the gate of the PMOS transistor P14 is connected to the grounded capacitor C6 and one end of the resistor R47, and a grounded diode; the other end of the resistor R47 is connected to the drain of the PMOS transistor P15, and the gate of the PMOS transistor P15 is connected to the gate and drain of the PMOS transistor P16 and the drain of the NMOS transistor N12 to generate a bias voltage. voltage VB1; the source of the NMOS transistor N12 is connected to the gate of the NMOS transistor N13 and the grounded resistor R49, the gate of the NMOS transistor N12 is connected to the drain of the NMOS transistor N13, the gate and drain of the NMOS transistor N14, and the other end of the resistor R48; the source of the NMOS transistor N13 is grounded, the source of the NMOS transistor N14 is connected to the gate and drain of the NMOS transistor N15, the source of the NMOS transistor N15 is connected to the gate and drain of the NMOS transistor N16, and the source of the NMOS transistor N16 is grounded.

[0048] When the bandgap reference circuit BGR is working, the bias voltage of NMOS transistor N12 is provided by three diode-connected NMOS transistors N14, N15, and N16. N13 and N12 form a negative feedback structure to stabilize the bias voltage of N12. The branch current is mirrored through P16 to generate a signal to provide bias voltage VB1 to the high-voltage transistor P13 of the bandgap reference circuit BGR. The bias signal of P14 is provided by a grounded voltage regulator diode. Due to the clamping effect of operational amplifier OP3, the voltages at both ends of the input terminal of operational amplifier OP3 are equal, so ,in is the base-emitter voltage difference of transistor Q8; and because the voltage drops of R45 and R44 resistors are equal and their resistance values ​​are equal, the current flowing through both sides is equal, so the output of op amp OP3 ,in is the base-emitter voltage of transistor Q8; then Therefore, a zero-drift voltage output can be achieved by adjusting the resistance values ​​of R43, R46, R45, and R46. The bandgap reference circuit BGR outputs a low-drift, high-stability signal, BGR_OUT. This signal, through the basic op amp circuit OP1, outputs two stable voltages, VP1 and VP2, to power the on-chip digital and analog modules, respectively. Based on virtual short and open circuits, we have:

[0049] , here VP1=VP2≈VP.

[0050] like Figure 6 As shown, the output voltage regulation module includes: PMOS transistors P9~P12, comparators COM1~COM2, a digital module, resistors R31~R38 and capacitors C1~C5; one end of the resistor R31 and the source of the PMOS transistors P9 and P12 are connected to the voltage signal VSEN, the other end of the resistor R31 is connected to one end of the resistor R32, and the other end of the resistor R32 is connected to the grounded current source Iref; the gate and drain of the PMOS transistor P9 are connected to the source of the PMOS transistor P10, the gate and drain of the PMOS transistor P10 are connected to the source of the PMOS transistor P11, the gate and drain of the PMOS transistor P11 are connected to one end of the resistor R32 and the gate of the PMOS transistor P12; the drain of the PMOS transistor P12 is connected to one end of the resistor R33, and the The other end of the resistor R33 is connected to the grounded resistor R34, the grounded capacitor C3, and the non-inverting input of the comparators COM1~COM2; the inverting input of the comparator COM1 is connected to the grounded capacitor C2 and one end of the resistor R36, the other end of the resistor R36 is connected to the grounded capacitor C1 and one end of the resistor R35, and the other end of the resistor R35 is connected to the voltage signal VCH; the inverting input of the comparator COM2 is connected to the grounded capacitor C5 and one end of the resistor R38, the other end of the resistor R38 is connected to the grounded capacitor C4 and one end of the resistor R37, and the other end of the resistor R37 is connected to the voltage signal VCL; the output ends of the comparators COM1~COM2 are connected to the input ends of the digital module, and the digital module outputs the voltage regulation signal OUT after the phase OR operation.

[0051] Resistor R31 has a resistance of 486 kΩ, resistor R32 has a resistance of 10.5 kΩ, the resistance ratio of resistors R33 and R34 is 25:4, resistors R35 and R37 have a resistance of 12.3 kΩ, and resistors R36 and R38 have a resistance of 110.7 kΩ. Capacitor C1 has a capacitance of 1.98 pF, capacitors C2 and C5 have a capacitance of 2.74 pF, capacitor C3 has a capacitance of 1.03 pF, and capacitor C4 has a capacitance of 2.24 pF. VCH and VCL are obtained by resistor-dividing VREF. The VSEN signal is proportionally scaled down by the resistor-divided voltage and compared with VCL and VCH. When the VSEN signal is lower than VCL, the output of the voltage regulation signal OUT is low voltage, keeping the three-phase electricity charging. When the VSEN signal is higher than VCH, the output of the voltage regulation signal OUT is high voltage. At this time, the protection circuit of the integrated voltage regulator chip on the chip directly outputs a high potential to turn on the external NMOS switch tube, directly connecting the input voltage to the ground to disconnect charging, until the sampled battery level is lower than the set level lower limit voltage.

[0052] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A power supply circuit of an on-chip integrated voltage regulator chip with adjustable output amplitude, characterized in that: include: Power module 1, the power module 1 is used to input the battery voltage signal BAT and the three-phase electrical signals PH1-PH3 to generate an on-chip power supply VCC; Power module 2, the power supply terminal of the power module 2 is connected to the power supply VCC to generate an on-chip reference voltage VREF, and the output voltages VP1 and VP2 are used to supply power to the subsequent digital module and analog module respectively; An output voltage detection module, which is used to input a battery voltage signal BAT and detect its voltage, and output a voltage signal VSEN to the output voltage regulation module; an output voltage regulation module, configured to compare the input voltage signal VSEN with the voltage signal VCH and the voltage signal VCL after voltage division by resistors, so as to adjust the amplitude of the voltage regulation signal OUT; wherein the voltage signal VCH and the voltage signal VCL are respectively generated by voltage division by resistors of the reference voltage VREF; The power module 1 includes: transistors Q1~Q5, PMOS transistors P1~P8, NMOS transistors N1~N8 and resistors R1~R12; the three-phase electrical signals PH1~PH3 are respectively connected to the bases of the transistors Q1~Q3 through the resistor R3, the emitters and collectors of the transistors Q1~Q3 are cascaded in sequence, the emitter of the transistor Q3 is grounded, the collector of the transistor Q1 is connected to the base and collector of the transistor Q4, one end of the resistor R4 and the drain of the NMOS transistor N2 to generate a control signal TP_C; the emitter of the transistor Q4 is connected to the base and collector of the transistor Q4, one end of the resistor R4 and the drain of the NMOS transistor N2 to generate a control signal TP_C; the emitter of the transistor Q4 is connected to the base of the resistors R5~R6 One end of the resistor R6 is connected to the gate of the NMOS transistor N3 and generates a control signal TP_G5. The other end of the resistor R6 is grounded. The source of the NMOS transistor N2 is grounded and the gate is connected to the control signal TP_G3. The other end of the resistor R4 and the sources of the PMOS transistors P4 and P5, one end of the resistor R7 and the resistor R10, and the drain of the NMOS transistor N8 are all connected to the battery voltage signal BAT. The gate of the PMOS transistor P4 is connected to the control signal TP_G2, and the drain is connected to the other end of the resistor R5. The other end of the resistor R7 is connected to the drain of the NMOS transistor N3. The source of transistor Q3 is connected to the base and collector of transistor Q5, the emitter of transistor Q5 is connected to one end of resistor R8, the other end of resistor R8 is connected to one end of resistor R9 and the power supply establishes indication signal TD; the other end of resistor R9 is connected to the drain and gate of NMOS transistor N4, and the gates of NMOS transistors N5~N6, and the sources of NMOS transistors N4~N6 are grounded; the drain of NMOS transistor N5 is connected to the drain of NMOS transistor N7, the gate and drain of PMOS transistor P7, and the gate of PMOS transistor P8, and the gate of NMOS transistor N7 is connected to Control signal TP_G4: the source of the NMOS transistor N7 is connected to the drain of the NMOS transistor N6; the drain and gate of the PMOS transistor P5 are connected to the source of the PMOS transistor P6, and the drain and gate of the PMOS transistor P6 are connected to the source of the PMOS transistor P7; the other end of the resistor R10 is connected to the source of the PMOS transistor P8, the drain of the PMOS transistor P8 is connected to one end of the resistor R11, the other end of the resistor R11 is connected to one end of the resistor R12, the source and gate of the NMOS transistor N8, and the power supply VCC, and the other end of the resistor R12 is grounded; The power module 1 further includes a TP_G2 signal generating circuit, which includes: PMOS transistors P1-P3, an NMOS transistor N1, and resistors R1-R2; one end of the resistor R1 and the source of the PMOS transistor P1 are connected to the battery voltage signal BAT, the other end of the resistor R1 is connected to the drain of the NMOS transistor N1, the gate and drain of the PMOS transistor P3, and outputs a control signal TP_G2; the gate of the NMOS transistor N1 is connected to the control signal TP_G1, and the source is connected to one end of the resistor R2, and the other end of the resistor R2 is grounded; the gate and drain of the PMOS transistor P1 are connected to the source of the PMOS transistor P2, and the gate and drain of the PMOS transistor P2 are connected to the source of the PMOS transistor P3; The power establishment indication signal TD also includes a grounded capacitor; the power supply VCC also includes two grounded capacitors, and the other end of one of the capacitors is connected in series with a resistor.

2. The on-chip integrated voltage regulator chip power supply circuit with adjustable output amplitude according to claim 1, characterized in that: The power supply module 2 includes: a bandgap reference circuit BGR, a VP power supply generating circuit and a VREF power supply generating circuit; the output end of the bandgap reference circuit BGR is respectively connected to the input end of the VP power supply generating circuit and the VREF power supply generating circuit, and the output ends of the VP power supply generating circuit and the VREF power supply generating circuit respectively output voltages VP1~VP2 and a reference voltage VREF.

3. The on-chip integrated voltage regulator chip power supply circuit with adjustable output amplitude as claimed in claim 2, characterized in that: The VP power supply generating circuit includes: an operational amplifier OP1, NMOS transistors N9-N11, and resistors R21-R25; the non-inverting input terminal of the operational amplifier OP1 is connected to the output signal BGR_OUT of the bandgap reference circuit BGR, the inverting input terminal is connected to one end of resistors R22-R23, the other end of resistor R23 is grounded, and the output terminal of the operational amplifier OP1 is connected to the gate of the NMOS transistor N9; the drain of the NMOS transistor N9 is connected to one end of the resistor R21, the other end of the resistor R21 is connected to the power supply VCC; the source of the NMOS transistor N9 is connected to the other end of the resistor R22 and one end of the resistors R24-R25 and outputs the voltage VP, the other ends of the resistors R24-R25 are respectively connected to the gates of the NMOS transistors N10-N11 and generate voltages VP1 and VP2 accordingly, and the sources and drains of the NMOS transistors N10-N11 are grounded.

4. The on-chip integrated voltage regulator chip power supply circuit with adjustable output amplitude as claimed in claim 2, characterized in that: The VREF power generation circuit includes: an operational amplifier OP2, PMOS transistors P17-P18, an NMOS transistor N17 and resistors R51-R57; the non-inverting input terminal of the operational amplifier OP2 is connected to the output terminal signal BGR_OUT of the bandgap reference circuit BGR, the inverting input terminal is connected to one end of the resistors R53-R54, the other end of the resistor R54 is grounded, the output terminal of the operational amplifier OP2 is connected to the gate of the PMOS transistor P17; the drain of the PMOS transistor P17 is grounded, the source of the PMOS transistor P17 is connected to the drain of the PMOS transistor P18 and the gate of the NMOS transistor N17, and the gate of the PMOS transistor P18 is grounded. The bias voltage VB2 is connected to the electrode of the PMOS transistor P18, the source of the PMOS transistor P18 is connected to one end of the resistor R51, and the other end of the resistor R51 is connected to the power supply VCC; the drain of the NMOS transistor N17 is connected to one end of the resistor R52, and the other end of the resistor R52 is connected to the power supply VCC; the source of the NMOS transistor N17 is connected to the other end of the resistor R53 and one end of the resistor R55 and outputs a reference voltage VREF; the other end of the resistor R55 is connected to one end of the resistor R56 and outputs a voltage signal VCH, the other end of the resistor R56 is connected to one end of the resistor R57 and outputs a voltage signal VCL, and the other end of the resistor R57 is grounded.

5. The on-chip integrated voltage regulator chip power supply circuit with adjustable output amplitude as claimed in claim 1, characterized in that: The output voltage regulation module includes: PMOS transistors P9~P12, comparators COM1~COM2, a digital module, resistors R31~R38 and capacitors C1~C5; one end of the resistor R31 and the source of the PMOS transistors P9 and P12 are connected to the voltage signal VSEN, the other end of the resistor R31 is connected to one end of the resistor R32, and the other end of the resistor R32 is connected to the grounded current source Iref; the gate and drain of the PMOS transistor P9 are connected to the source of the PMOS transistor P10, the gate and drain of the PMOS transistor P10 are connected to the source of the PMOS transistor P11, the gate and drain of the PMOS transistor P11 are connected to one end of the resistor R32 and the gate of the PMOS transistor P12; the drain of the PMOS transistor P12 is connected to one end of the resistor R33, The other end of the resistor R33 is connected to the grounded resistor R34, the grounded capacitor C3, and the non-inverting input end of the comparator COM1~COM2; the inverting input end of the comparator COM1 is connected to the grounded capacitor C2 and one end of the resistor R36, the other end of the resistor R36 is connected to the grounded capacitor C1 and one end of the resistor R35, and the other end of the resistor R35 is connected to the voltage signal VCH; the inverting input end of the comparator COM2 is connected to the grounded capacitor C5 and one end of the resistor R38, the other end of the resistor R38 is connected to the grounded capacitor C4 and one end of the resistor R37, and the other end of the resistor R37 is connected to the voltage signal VCL; the output ends of the comparators COM1~COM2 are connected to the input end of the digital module, and the output end of the digital module outputs the voltage regulation signal OUT.

6. The on-chip integrated voltage regulator chip power supply circuit with adjustable output amplitude as claimed in claim 5, characterized in that: The digital module adopts a phase OR operation, that is, when the voltage signal VSEN is proportionally reduced by the resistor voltage divider, the voltage is compared with the voltage signal VCL and the voltage signal VCH respectively. When the voltage signal VSEN is lower than the voltage signal VCL, the output of the voltage regulation signal OUT is a low voltage, and the three-phase electricity continues to be charged. When the voltage signal VSEN is higher than the voltage signal VCH, the output of the voltage regulation signal OUT is a high voltage.

7. The on-chip integrated voltage regulator chip power supply circuit with adjustable output amplitude as claimed in claim 2, characterized in that: The bandgap reference circuit BGR includes: PMOS transistors P13-P16, NMOS transistors N12-N16, resistors R41-R49, capacitor C6, transistors Q6-Q8 and operational amplifier OP3; one end of the resistor R41 is connected to the power supply VCC, and the other end is connected to the source of the PMOS transistor P13 and PMOS transistors P15-P16, and one end of the resistor R48; the gate of the PMOS transistor P13 is connected to the bias voltage VB1, and the drain of the PMOS transistor P13 is connected to the source of the PMOS transistor P14. The drain of the PMOS transistor P14 is connected to one end of the resistor R42, the other end of the resistor R42 is connected to one end of the resistor R43 and the emitter of the transistor Q6 and outputs the signal BGR_OUT; the other end of the resistor R43 is connected to the resistor R44 and one end of the resistor R45, the other end of the resistor R44 is connected to the inverting input of the operational amplifier OP3 and the emitter of the transistor Q7, the other end of the resistor R45 is connected to the non-inverting input of the operational amplifier OP3 and one end of the resistor R46; the bases of the transistors Q7 and Q8 are connected. The collector is grounded, the emitter of the transistor Q8 is connected to the other end of the resistor R46; the output end of the operational amplifier OP3 is connected to the base of the transistor Q6, and the collector of the transistor Q6 is grounded; the gate of the PMOS transistor P14 is connected to the grounded capacitor C6 and one end of the resistor R47, and a grounded diode; the other end of the resistor R47 is connected to the drain of the PMOS transistor P15, and the gate of the PMOS transistor P15 is connected to the gate and drain of the PMOS transistor P16 and the drain of the NMOS transistor N12 to generate a bias voltage VB1; the source of the NMOS transistor N12 is connected to the gate of the NMOS transistor N13 and the grounded resistor R49, the gate of the NMOS transistor N12 is connected to the drain of the NMOS transistor N13, the gate and drain of the NMOS transistor N14, and the other end of the resistor R48; the source of the NMOS transistor N13 is grounded, the source of the NMOS transistor N14 is connected to the gate and drain of the NMOS transistor N15, the source of the NMOS transistor N15 is connected to the gate and drain of the NMOS transistor N16, and the source of the NMOS transistor N16 is grounded.

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