Chip data acquisition method and system and storage medium

Abstract

The invention relates to the technical field of data acquisition, in particular to a chip data acquisition method and system and a storage medium. The method comprises the following steps: acquiring working parameters of a chip in real time by using an intelligent sensor, and recording initial performance data of the chip; establishing an initial test data set of the working state of the chip by using data analysis software according to the initial performance data; performing data cleaning based on the initial test data set, and performing chip key feature vector extraction on the initial test preprocessing data to obtain a chip data feature data set; therefore, by dynamically adjusting the data acquisition strategy and enhancing the sensor configuration, the problems of inaccurate traditional data acquisition and improper redundant data processing are solved, and the accuracy of chip performance diagnosis and the production efficiency are improved.

Description

Technical Field

[0001] The present invention relates to the technical field of data acquisition, and particularly to a method, a system and a storage medium for obtaining chip data. Background Art

[0002] Traditional static sampling strategies lack flexibility and cannot dynamically adjust the acquisition frequency and range according to the changes of the chip in different working states, resulting in the omission of redundant or critical data. Secondly, the existing technologies usually rely on offline verification and cannot verify the data validity in real time, affecting the reliability and timeliness of the data. In addition, the existing methods have limitations in detecting and responding to new abnormal patterns, and it is difficult to identify and adjust the acquisition strategy in time to capture new fault signals, affecting the accuracy of fault diagnosis. Finally, the data processing process is complex and inefficient, especially in the real-time analysis of high-dimensional or multi-modal data, the processing speed and adaptability are insufficient, and the requirements of high-frequency acquisition cannot be met. Summary of the Invention

[0003] Based on this, it is necessary to provide a method for obtaining chip data to solve at least one of the above technical problems.

[0004] To achieve the above object, a method, a system and a storage medium for obtaining chip data, the method includes the following steps:

[0005] Step S1: Use an intelligent sensor to collect the working parameters of the chip in real time and record the initial performance data of the chip; according to the initial performance data, use data analysis software to establish an initial test data set of the chip working state;

[0006] Step S2: Perform data cleaning based on the initial test data set, and extract the key feature vectors of the chip from the initial test preprocessed data to obtain a chip data feature data set;

[0007] Step S3: Establish an association model according to the chip data feature data set, and use the obtained association model in the chip test stage to construct a dynamic data acquisition optimization engine to obtain a chip data acquisition optimization engine;

[0008] Step S4: Optimize the data acquisition of the chip data acquisition optimization engine, and use the generated optimized chip acquisition data as input to the defect mode library for knowledge transfer in the test stage, verify the data validity through the actual yield, and if a new abnormal pattern is detected during the acquisition process, automatically trigger a specific enhanced sensor for enhanced acquisition, and finally generate a chip data optimized acquisition report.

[0009] The beneficial effects of the present invention are as follows: By using intelligent sensors to collect the chip working state parameters in real time and constructing an initial test data set based on the initial performance data, high-quality basic data is provided for subsequent analysis. This preliminary working state data set provides an accurate reference basis for subsequent data cleaning and feature extraction. Data cleaning and key feature vector extraction ensure the effectiveness and reliability of the chip data by removing noise, redundant information and extracting key data features. Feature vector extraction can not only remove redundant data, but also uncover potential performance change information of the chip, which is crucial for subsequent dynamic data acquisition optimization and fault mode recognition. By establishing an association model, the chip data features are effectively associated with its working state, and this model provides theoretical support for the construction of the dynamic data acquisition optimization engine. Based on this model, the system can adjust the acquisition strategy according to the actual working state, thereby ensuring the efficient acquisition of key data and effectively avoiding unnecessary redundant data acquisition. By optimizing the data acquisition process, the collected data is input into the defect mode library for knowledge transfer and verified in combination with the actual yield rate to further ensure the actual effectiveness and diagnostic accuracy of the collected data. At the same time, when a new abnormal mode is detected, the system can automatically trigger an enhanced sensor for enhanced acquisition, thereby obtaining more key data in real time. This process effectively improves the flexibility and pertinence of data acquisition, improves the accuracy of chip fault prediction, and reduces manual intervention and misdiagnosis. Through the generation of the data optimization acquisition report, not only a scientific basis is provided for the chip production process, but also a more solid data foundation is provided for future data analysis. Therefore, the present invention solves the problems of inaccurate traditional data acquisition and improper redundant data processing by dynamically adjusting the data acquisition strategy and enhancing the sensor configuration, and improves the accuracy of chip performance diagnosis and production efficiency.

[0010] Preferably, step S1 includes the following steps:

[0011] Step S11: Use a high-precision current sensor to detect the contact impedance of the chip to obtain high-precision current sampling rate data;

[0012] Step S12: Apply dot matrix near-field electromagnetic induction to the chip signal during the signal application stage using an electromagnetic field distribution sensor array to obtain dot matrix near-field electromagnetic induction data;

[0013] Step S13: Use a digital signal oscilloscope to collect the parameters of the synchronous bandwidth greater than or equal to the preset value during the chip function test stage to obtain digital signal test bandwidth data;

[0014] Step S14: Align the high-precision current sampling rate data, dot matrix near-field electromagnetic induction data, and digital signal test bandwidth data in the time domain through time error synchronization technology, and analyze the chip working state using data analysis software to obtain an initial test data set.

[0015] In the present invention, a high-precision current sensor is used to detect the contact impedance of the chip, and the collected current data can accurately reflect the change of the current characteristics of the chip, which provides key electrical characteristic data for subsequent analysis of the working state of the chip. The data with a high sampling rate can capture the details of the chip current change, especially the current fluctuations in the high-frequency and transient states, which is of great significance for identifying potential electrical problems of the chip. Through the dot matrix near-field electromagnetic induction acquisition by the electromagnetic field distribution sensor array, the obtained electromagnetic induction data provides multi-angle spatial distribution information of the electromagnetic behavior of the chip, which helps to discover the electromagnetic characteristic changes of the chip in different working states, and then identify the interference sources or performance anomalies. Using a digital signal oscilloscope to collect synchronous signals with a bandwidth greater than or equal to a preset value can start from the bandwidth characteristics of the digital signal and conduct a detailed analysis of aspects such as the signal stability and frequency response of the chip. The data of this step helps to evaluate the performance of the chip in a specific working frequency band, especially the waveform distortion or delay that occurs during high-speed signal transmission. Through the time misalignment synchronization technology, the above data is aligned in the time domain, ensuring the consistency and synchronization of the data collected by different sensors in time, and providing unified timing data for subsequent analysis. Using data analysis software to comprehensively analyze these aligned data can accurately identify the working state of the chip and provide a reliable data basis for the generation of the initial test data set. By this way of multi-sensor collaborative work and data time-domain alignment, not only the comprehensiveness and accuracy of data collection are improved, but also the influence caused by data distortion or sampling error of a single sensor is effectively reduced, thus providing a scientific and comprehensive basis for the efficient test and performance evaluation of the chip.

[0016] Preferably, step S2 includes the following steps:

[0017] Step S21: Perform chip data cleaning based on the initial test data set, and use the abnormal waveform detection algorithm to perform wavelet transform denoising on the generated initial test chip cleaning data to generate initial test preprocessing data;

[0018] Step S22: Use the preset chip impedance-contact force mapping model to perform contact point impedance correction on the initial test preprocessing data to obtain initial chip test correction data;

[0019] Step S23: Use the initial chip test correction data to extract the key feature vectors of the chip to obtain the chip data feature data set.

[0020] The present invention effectively removes the noise and abnormal waveforms in the initial test data by using an abnormal waveform detection algorithm for wavelet transform denoising. As a time-frequency analysis tool, wavelet transform can decompose signals at multiple scales, accurately remove high-frequency noise, and retain the important features in the signals. This processing step ensures the elimination of potential noise in the original data and enhances the effectiveness of the data, providing a clear signal basis for subsequent analysis. The preset chip impedance-contact force mapping model is used to correct the contact point impedance of the initial test preprocessed data, thereby correcting the impedance deviation caused by poor contact or physical property changes. By accurately correcting the data, the measurement errors caused by different test conditions or external environment changes can be eliminated, ensuring the accuracy and consistency of the data. This process is particularly important because the impedance data of the chip will be distorted due to poor contact or mechanical changes during operation, and impedance correction helps to restore the true working state. By using the initial chip test corrected data for key feature vector extraction, the corrected data is converted into a feature data set suitable for further analysis. The feature vectors extracted in this process can accurately reflect the performance of the chip under different working states, such as various key performance indicators such as current, impedance, and power consumption. Through this feature extraction step, features with high recognition and prediction ability can be extracted from a large amount of original data, providing data support for subsequent chip status monitoring, fault diagnosis, and performance optimization. Generally speaking, this method ensures the high quality of the chip performance data through a series of precise data processing steps, thereby improving the accuracy and reliability of chip testing, avoiding diagnostic deviations caused by noise, errors, or data distortion, and laying a solid data foundation for subsequent performance analysis and fault identification.

[0021] Preferably, the extraction of the key feature vectors of the chip described in step S2 includes the following:

[0022] Extract transient current waveform data, chip electromagnetic radiation data, and chip load thermal distribution images;

[0023] Use the short-time Fourier transform to dynamically convert the transient current waveform data into chip frequency-time domain information. The dynamic conversion includes that if the transient current waveform data is greater than or equal to the severe fluctuation threshold, the window length is shortened so that the chip frequency-time domain information captures more high-frequency information. If the transient current waveform data is less than the severe fluctuation threshold, the window length is increased to obtain chip frequency-time domain information containing more stable low-frequency components;

[0024] Perform a time-frequency matrix conversion on the chip frequency-time domain information to obtain a chip time-frequency joint feature matrix;

[0025] Construct a singular value matrix for the chip electromagnetic radiation data to obtain a chip electromagnetic radiation singular value matrix;

[0026] Calculate the left and right singular value vectors of the chip electromagnetic radiation singular value matrix, and retain the first 20 contributions through the generated left and right singular value vectors to obtain the chip electromagnetic radiation contribution data;

[0027] Use the image pixel block technology to divide the chip load thermal distribution image into blocks with 36×36 - 256×256 pixels, and calculate the gradient of the blocks to obtain the chip load gradient data; draw a gradient histogram of the edge temperature information based on the chip load gradient data to obtain the chip load temperature histogram data;

[0028] Perform multi-modal feature fusion on the chip time-frequency joint feature matrix, the chip electromagnetic radiation contribution data, and the chip load temperature histogram data to generate a chip data feature dataset.

[0029] The present invention converts the dynamic current characteristics of the chip into frequency-time domain information through the short-time Fourier transform (STFT), realizing the time-frequency analysis of the chip's dynamic current characteristics. By dynamically adjusting the STFT window length, the details of data capture can be flexibly adjusted according to the severity of the transient current waveform fluctuations. When the current waveform fluctuates violently, shortening the window length helps capture more high-frequency information, while when the fluctuations are small, extending the window length can capture more stable low-frequency information. This dynamic adjustment mechanism ensures a comprehensive capture of the chip's frequency-time domain information and can more accurately reflect its current characteristics under different working conditions. Secondly, the chip electromagnetic radiation data is decomposed by singular value decomposition (SVD) to obtain the singular value matrix of electromagnetic radiation, and then the left and right singular value vectors are calculated and the first 20 principal components with larger contributions are retained, effectively extracting the key features in the chip electromagnetic radiation. The SVD method provides accurate data support for the electromagnetic compatibility analysis of the chip by removing redundant information while retaining the most representative electromagnetic radiation features through dimensionality reduction and feature extraction. Furthermore, the chip load thermal distribution image undergoes pixel block processing and gradient calculation to further extract the spatial distribution features of the temperature information, and the change of the chip thermal distribution is effectively quantified through the temperature gradient histogram. This process helps accurately identify the thermal stress state of the chip under different loads, providing an effective basis for the thermal management and fault diagnosis of the chip. Finally, performing multi-modal feature fusion on the time-frequency joint feature matrix, the electromagnetic radiation contribution data, and the thermal distribution data can comprehensively consider the features of current, radiation, and heat, providing a comprehensive description of the chip's working state. This multi-modal feature fusion not only improves the data expression ability but also enhances the accuracy and reliability of chip performance evaluation through multi-angle analysis. Through these processing steps, the finally generated chip data feature dataset can provide rich data support for the fault detection, performance evaluation, and optimization of the chip, significantly improving the multi-dimensionality and depth of chip state analysis.

[0030] Preferably, step S3 includes the following steps:

[0031] Step S31: Establish an association model for the chip data feature dataset based on the DTW algorithm for feature similarity analysis to obtain the association model in the chip test stage;

[0032] Step S32: Calculate the feature dimension weight matrix in real time according to the update frequency of 10 Hz for the association model in the chip test stage to obtain the chip feature dimension weight matrix;

[0033] Step S33: Construct a dynamic data acquisition optimization engine based on the chip feature dimension weight matrix to obtain the chip data acquisition optimization engine.

[0034] In the present invention, by using the dynamic time warping (DTW) algorithm to perform feature similarity analysis on the chip data feature dataset and constructing an association model, the timing relationship between features in different test stages of the chip can be accurately captured. The DTW algorithm can effectively measure the similarity between two data sequences, which is especially suitable for the comparison of time series data, thus providing an accurate association description for the performance changes of the chip in each test stage. Through the establishment of this association model, it is possible to accurately identify the performance change trend and potential failure modes based on the feature performance of the chip under different working conditions. In step S32, by calculating the feature dimension weight matrix at a real-time update frequency of 10 Hz, different weights can be assigned to each feature dimension of the chip, so as to better reflect the importance of each feature in actual tests. This process can quickly respond to the changes in chip performance and data acquisition requirements by dynamically adjusting the weight matrix in real time, so as to preferentially collect important features during data processing, improving the efficiency and accuracy of data acquisition. The feature dimension weight matrix not only helps to determine which features are more critical, but also avoids the collection of irrelevant data and reduces data redundancy through this dynamic adjustment mechanism. Step S33 constructs a dynamic data acquisition optimization engine based on the feature dimension weight matrix, which can efficiently collect feature data with different weights according to their priorities. This optimization engine not only improves the real-time performance and accuracy of data acquisition, but also reduces unnecessary data acquisition through an intelligent acquisition strategy, effectively saving storage space and computing resources, and further improving the overall efficiency of chip performance testing. Through these innovative steps, the system can more intelligently adjust the data acquisition strategy, obtain key data of the chip in a real-time and accurate manner, ensure the high quality and efficient processing of data, and thus provide solid data support for subsequent chip performance evaluation and fault diagnosis.

[0035] Preferably, the construction of the dynamic data acquisition optimization engine described in step S3 includes the following steps:

[0036] Calculate the feature coefficient of variation for the chip feature dimension weight matrix, and sample 30% of the reference value according to the coefficient of variation of each generated chip feature being less than 5% to obtain the chip low-dimensional feature sampling data;

[0037] Detect abnormal fluctuations or extreme events in the chip feature dimension weight matrix. If the kurtosis is greater than 5, perform 300% sampling of the reference value through the entropy method to obtain the chip high-dimensional feature sampling data;

[0038] Generate an adaptive acquisition strategy table through the chip low-dimensional feature sampling data and the chip high-dimensional feature sampling data, and perform hardware-level dynamic configuration using a field-programmable gate array to obtain the chip data acquisition optimization engine.

[0039] In the present invention, by calculating the feature coefficient of variation of the chip feature dimension weight matrix, the degree of change of each feature in the dataset can be quantified. The calculation of the coefficient of variation can reflect the stability of data fluctuations of different features during the acquisition process. For features with low variation, their data fluctuations are small and have high stability. Therefore, by setting features with a coefficient of variation less than 5% as 30% of the reference value for sampling, the sampling frequency of features with high stability can be reduced, saving sampling resources and improving data processing efficiency. This strategy makes the data acquisition of low-dimensional features more efficient, avoids the unnecessary acquisition of redundant information, and improves the pertinence and economy of data acquisition. Secondly, by detecting abnormal fluctuations or extreme events in the chip feature dimension weight matrix, if an abnormal fluctuation with a kurtosis greater than 5 is detected, 300% sampling of the reference value is performed through the entropy method, which can strengthen the sampling frequency when key features show abnormal fluctuations, so as to more accurately capture the performance changes of the chip in extreme situations. As an index to measure the sharpness of a signal, kurtosis can help identify sudden fluctuations or extreme events in the data, thereby enhancing the monitoring ability for abnormal situations. Through this targeted data sampling strategy, the system can enhance data acquisition in real time when potential faults or abnormal fluctuations occur in the chip, providing a more accurate basis for fault diagnosis and performance optimization. Finally, combining the low-dimensional feature sampling data and the high-dimensional feature sampling data to generate an adaptive acquisition strategy table, and performing hardware-level dynamic configuration through a field-programmable gate array (FPGA) to ensure that the data acquisition optimization engine can adapt to different working states and environmental changes of the chip in real time. This method not only improves the flexibility and real-time performance of data acquisition, but also can intelligently adjust the sampling frequency according to actual acquisition requirements, maximizing the accuracy and efficiency of data acquisition.

[0040] Preferably, step S4 includes the following steps:

[0041] Step S41: Optimize data acquisition for the chip data acquisition optimization engine to obtain chip acquisition optimization data;

[0042] Step S42: Use the optimized data collected by the chip as input to the defect mode library for knowledge transfer in the testing phase, and generate a new sampling mode for chip data, where the defect mode library includes 1.2×10 6 known defect features;

[0043] Step S43: Verify the effectiveness of the new sampling mode of chip data through the actual yield. If a new abnormal mode is detected during the collection process, automatically trigger a specific enhanced sensor for enhanced collection, and finally generate an optimized acquisition report for chip data.

[0044] Through the optimized data collection of the chip data collection optimization engine, the present invention can dynamically adjust the collection strategy according to different working states and testing requirements of the chip, ensuring the efficiency and accuracy of data collection. This optimization process ensures that the collected data can accurately reflect the true performance of the chip in different testing phases or working conditions, and provides high-quality raw data support for subsequent data processing and analysis. The optimized data collected is input into the defect mode library for knowledge transfer in the testing phase. Using the known 1.2×10 6 defect features, a new sampling mode for chip data is generated. By combining historical data with the existing mode library and using knowledge transfer technology, this process can not only effectively identify potential defect modes of the chip, but also generate a new sampling mode for the newly collected chip data based on the analysis results of historical data, thus ensuring the real-time identification and response to defect modes during the data collection process. This knowledge transfer technology based on the defect mode library provides strong data support and technical guarantee for chip fault detection. Immediately afterwards, verify the effectiveness of the new sampling mode through the actual yield data, which can verify the accuracy of the collection mode during the actual production or testing process, and further ensure the authenticity and reliability of the data. When the system detects a new abnormal mode, automatically trigger a specific enhanced sensor for enhanced collection, effectively enhancing the capture ability of the abnormal mode and ensuring that no potential abnormalities affecting the chip performance are missed during the data collection process. This automatic trigger mechanism enables the defect detection and performance evaluation of the chip to respond in real time to changes in the external environment or internal faults, thus identifying problems more quickly and making feedback. Finally, the generated optimized acquisition report for chip data not only provides a detailed basis for chip fault diagnosis, but also provides valuable data support for subsequent optimization and improvement.

[0045] Preferably, step S43 includes the following steps:

[0046] Step S431: Verify the effectiveness of the new sampling mode of chip data through the actual yield, and use the production line MES system to verify the real-time collected data to obtain chip collection information feedback data;

[0047] Step S432: If the confidence level detected during the acquisition process is <85%, it is classified as a new abnormal mode, and a specific enhanced sensor is automatically triggered for enhanced acquisition. At the same time, abnormal feedback data of the chip acquisition information is obtained;

[0048] Step S433: Construct a chip data acquisition report from the chip acquisition information feedback data and the abnormal feedback data of the chip acquisition information to obtain a chip data optimized acquisition report.

[0049] In the present invention, by combining the new sampling mode of chip data with the actual yield verification data and using the production line MES (Manufacturing Execution System) to verify the real-time acquired data, it can effectively ensure that the acquired data is consistent with the actual performance in the production environment. This process verifies the effectiveness of the acquired data through real-time yield data, making the data acquisition more in line with the actual working state and production conditions of the chip. Through the auxiliary verification of the MES system, the quality of the data can be monitored in real time during the chip testing stage, providing a reliable data source for subsequent data analysis and timely discovering problems in the data acquisition process. If the confidence level is detected to be less than 85% during data acquisition, it is automatically marked as a new abnormal mode, and a specific enhanced sensor is triggered for enhanced acquisition. This mechanism ensures the timely capture of abnormal data and conducts more detailed and in-depth data acquisition on the fault modes that occur through enhanced acquisition technology, thereby improving the accuracy and comprehensiveness of chip data acquisition. The enhanced sensor can provide more sampling information at critical moments to ensure that abnormal modes are not missed, greatly improving the sensitivity and reliability of fault diagnosis and performance evaluation. The system combines the chip acquisition information feedback data with the abnormal feedback data to construct a chip data acquisition report. This report integrates normal and abnormal acquisition data, providing a detailed basis for subsequent chip performance analysis, fault diagnosis, and optimization strategies. By combining the two types of feedback data, the generated chip data optimized acquisition report not only reflects the overall quality of data acquisition but also can timely point out potential abnormal problems and provide an operable improvement plan for production optimization.

[0050] In this specification, a chip data acquisition system is provided for implementing the above chip data acquisition method. The chip data acquisition system includes:

[0051] Real-time acquisition and initial data recording, for using intelligent sensors to real-time acquire the working parameters of the chip and record the initial performance data of the chip; according to the initial performance data, using data analysis software to establish an initial test data set of the chip working state;

[0052] Data cleaning and feature vector extraction, for performing data cleaning based on the initial test data set and extracting the key feature vectors of the chip from the initially preprocessed test data to obtain a chip data feature data set;

[0053] Establishing a correlation model and a collection optimization engine, which is used to establish a correlation model based on the chip data feature data set, and use the obtained chip test phase correlation model to build a dynamic data collection optimization engine to obtain a chip data collection optimization engine;

[0054] Optimize data collection and defect pattern library testing to optimize data collection for the chip data collection optimization engine, and use the generated chip collection optimization data as input to the defect pattern library for knowledge transfer in the testing phase. The data validity is verified through actual yield. If a new abnormal pattern is detected during the collection process, a specific enhanced sensor is automatically triggered for enhanced collection, and finally a chip data optimization acquisition report is generated.

[0055] The present invention achieves the beneficial effect of collecting chip operating parameters in real time through intelligent sensors and constructing an initial test dataset based on initial performance data, providing high-quality basic data for subsequent analysis. This preliminary operating status dataset provides an accurate reference for subsequent data cleaning and feature extraction. Data cleaning and key feature vector extraction ensure the validity and reliability of chip data by removing noise and redundant information and extracting key data features. Feature vector extraction not only removes redundant data but also uncovers potential performance variations in the chip, which is crucial for subsequent dynamic data acquisition optimization and fault pattern identification. By establishing a correlation model that effectively correlates chip data features with their operating status, this model provides theoretical support for the construction of a dynamic data acquisition optimization engine. Based on this model, the system can adjust the acquisition strategy based on actual operating conditions, ensuring efficient acquisition of key data and effectively avoiding unnecessary redundant data acquisition. By optimizing the data acquisition process, the collected data is input into a defect pattern library for knowledge transfer, and verified against actual yield, further ensuring the actual validity and diagnostic accuracy of the collected data. Furthermore, when new abnormal patterns are detected, the system can automatically trigger enhanced sensor acquisition for enhanced acquisition, thereby acquiring more key data in real time. This process effectively improves the flexibility and pertinence of data collection, increases the accuracy of chip fault prediction, and reduces the risk of manual intervention and misdiagnosis. The generation of data optimization acquisition reports not only provides a scientific basis for the chip production process, but also provides a more solid data foundation for future data analysis. Therefore, the present invention solves the problems of inaccurate traditional data collection and improper processing of redundant data by dynamically adjusting data collection strategies and enhancing sensor configuration, thereby improving the accuracy and production efficiency of chip performance diagnosis.

[0056] A chip data acquisition storage medium stores a computer program, wherein the computer program is used to execute the chip data acquisition method. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] Figure 1 It is a schematic diagram of the step flow of a chip data acquisition method;

[0058] Figure 2 It is Figure 1 a detailed implementation step flow diagram of step S2 in

[0059] Figure 3 It is Figure 1 a detailed implementation step flow diagram of step S3 in

[0060] Figure 4 It is Figure 1 a detailed implementation step flow diagram of step S4 in

[0061] The realization of the purpose, functional characteristics and advantages of the present invention will be further described with reference to the embodiments and the accompanying drawings. Specific embodiments

[0062] The technical method of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts fall within the scope of the present invention.

[0063] In addition, the accompanying drawings are only schematic diagrams of the present invention and are not necessarily drawn to scale. The same reference numerals in the drawings represent the same or similar parts, and thus their repeated description will be omitted. Some of the block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. The functional entities can be implemented in software form, or in one or more hardware modules or integrated circuits, or in different networks and / or processor methods and / or microcontroller methods.

[0064] It should be understood that although the terms "first", "second", etc. may be used here to describe various units, these units should not be limited by these terms. These terms are only used to distinguish one unit from another. For example, without departing from the scope of the exemplary embodiments, the first unit can be called the second unit, and similarly the second unit can be called the first unit. The term "and / or" used here includes any and all combinations of one or more of the listed related items.

[0065] To achieve the above object, please refer to Figures 1 to 4 , a chip data acquisition method, the method includes the following steps:

[0066] Step S1: Use intelligent sensors to collect the working parameters of the chip in real time and record the initial performance data of the chip; according to the initial performance data, use data analysis software to establish an initial test data set for the chip working state;

[0067] Step S2: Perform data cleaning based on the initial test data set, and extract the key feature vectors of the chip from the preprocessed initial test data to obtain the chip data feature data set;

[0068] Step S3: Establish an association model according to the chip data feature data set, and use the obtained association model in the chip test stage to construct a dynamic data acquisition optimization engine to obtain the chip data acquisition optimization engine;

[0069] Step S4: Optimize data acquisition for the chip data acquisition optimization engine, and use the generated optimized chip acquisition data as input to the defect mode library for knowledge transfer in the test stage. Verify the data effectiveness through the actual yield. If a new abnormal mode is detected during the acquisition process, automatically trigger a specific enhanced sensor for enhanced acquisition, and finally generate a chip data optimization acquisition report.

[0070] The present invention achieves the beneficial effect of collecting chip operating parameters in real time through intelligent sensors and constructing an initial test dataset based on initial performance data, providing high-quality basic data for subsequent analysis. This preliminary operating status dataset provides an accurate reference for subsequent data cleaning and feature extraction. Data cleaning and key feature vector extraction ensure the validity and reliability of chip data by removing noise and redundant information and extracting key data features. Feature vector extraction not only removes redundant data but also uncovers potential performance variations in the chip, which is crucial for subsequent dynamic data acquisition optimization and fault pattern identification. By establishing a correlation model that effectively correlates chip data features with their operating status, this model provides theoretical support for the construction of a dynamic data acquisition optimization engine. Based on this model, the system can adjust the acquisition strategy based on actual operating conditions, ensuring efficient acquisition of key data and effectively avoiding unnecessary redundant data acquisition. By optimizing the data acquisition process, the collected data is input into a defect pattern library for knowledge transfer, and verified against actual yield, further ensuring the actual validity and diagnostic accuracy of the collected data. Furthermore, when new abnormal patterns are detected, the system can automatically trigger enhanced sensor acquisition for enhanced acquisition, thereby acquiring more key data in real time. This process effectively improves the flexibility and pertinence of data collection, increases the accuracy of chip fault prediction, and reduces the risk of manual intervention and misdiagnosis. The generation of data optimization acquisition reports not only provides a scientific basis for the chip production process, but also provides a more solid data foundation for future data analysis. Therefore, the present invention solves the problems of inaccurate traditional data collection and improper processing of redundant data by dynamically adjusting data collection strategies and enhancing sensor configuration, thereby improving the accuracy and production efficiency of chip performance diagnosis.

[0071] In the embodiment of the present invention, reference Figure 1 FIG. 1 is a flow chart of the steps of the chip data acquisition method of the present invention. In this example, the chip data acquisition method includes the following steps:

[0072] Step S1: Using smart sensors to collect chip operating parameters in real time and record initial chip performance data; based on the initial performance data, using data analysis software to establish an initial test data set for the chip's operating status;

[0073] In the embodiments of the present invention, the working parameters of the chip are collected in real time by using intelligent sensors. In this process, a variety of high-precision sensors are jointly used, such as temperature sensors, current sensors, pressure sensors, etc. These sensors can capture the key physical and electrical characteristic data of the chip during operation in real time. Through high-frequency data acquisition technology, the sensors provide multi-dimensional data including current, voltage, temperature, power consumption, etc., which can comprehensively reflect the dynamic working state of the chip. Secondly, the initially collected chip performance data is transmitted and stored in real time through a data acquisition system. Usually, high-speed data interfaces (such as SPI, I2C, CAN, etc.) are used to transmit the data to local storage devices or cloud platforms. The data is accurately time-synchronized and calibrated during the acquisition process to ensure the accuracy and consistency of the collected data. To further ensure the data quality, the system uses calibration algorithms to perform necessary compensation and correction on the output of the sensors, eliminating the influence of environmental changes or hardware errors on the data, thereby improving the reliability of the data. Then, data analysis software is used to process the initial performance data. Through preprocessing steps such as data cleaning, denoising, and interpolation, interference factors such as outliers and missing values are eliminated to ensure the purity and integrity of the data set. The preprocessed data is then processed by feature extraction algorithms, such as principal component analysis (PCA), time-frequency analysis, etc., to extract the characteristic indicators that have a key impact on the working state of the chip. Finally, through these processing means, an initial test data set of the chip working state is generated. This data set not only contains the key performance parameters of the chip in the initial operation stage, but also provides reliable basic data support for subsequent fault prediction, performance optimization, and data analysis.

[0074] Step S2: Perform data cleaning based on the initial test data set, and extract the key feature vectors of the chip from the initially preprocessed test data to obtain the chip data feature data set;

[0075] In the embodiments of the present invention, data cleaning is performed on the initial test data set to ensure the quality and reliability of the data. The data cleaning process includes, but is not limited to, removing noise, handling missing values and outliers. To remove noise, filtering techniques such as mean filtering, wavelet transform, etc. are usually adopted to smooth the data and suppress high-frequency noise. Especially in signals such as current and voltage, noise has a great interference on subsequent feature extraction. For missing values, interpolation methods (such as linear interpolation, spline interpolation, etc.) are used to fill in the missing data points to ensure the continuity and integrity of the data. In addition, outlier detection methods (such as Z-score, box plot analysis, etc.) are used to screen the data and remove abnormal data points that do not conform to physical or logical laws, thereby further improving the credibility of the data set. After the data cleaning is completed, key feature vectors of the chip are extracted. The goal of feature extraction is to identify key features from the cleaned and processed data that can comprehensively reflect the working state of the chip, usually including time-domain and frequency-domain features of physical quantities such as current waveforms, temperature changes, power consumption, etc. To extract these features, time-frequency analysis techniques such as short-time Fourier transform (STFT), wavelet transform, etc. are often adopted. These methods can capture the key changes of the signal in the time domain and frequency domain and extract representative feature vectors. During the processing, if the signal has periodic or transient fluctuation characteristics, the feature extraction can be further refined through periodic feature extraction algorithms, transient analysis algorithms, etc. to enhance the description ability of the features. Through these technical means, the finally obtained chip data feature data set can not only reflect the working performance of the chip, but also effectively characterize the behavior of the chip under different working conditions, providing reliable feature information for subsequent fault diagnosis, performance evaluation and optimization.

[0076] Step S3: Establish an association model according to the chip data feature data set, and use the obtained chip test stage association model to construct a dynamic data acquisition optimization engine to obtain a chip data acquisition optimization engine;

[0077] In the embodiments of the present invention, an association model is established based on the chip data feature dataset, aiming to identify the internal correlation between the features in different working states of the chip. This process is usually achieved through a variety of statistical and machine learning techniques. Common methods include regression analysis, support vector machine (SVM), random forest, etc. These techniques can extract the non-linear relationships or trend patterns between different features according to the historical working data and feature information of the chip. To enhance the accuracy and generalization ability of the model, cross-validation techniques are usually used to verify and optimize the training data to ensure the accuracy and robustness of the model. In the process of model construction, data preprocessing and feature selection are very crucial steps. Only by selecting the most representative feature variables can the stability and effectiveness of the model be ensured. In addition, to further improve the prediction accuracy of the model, neural network models in deep learning techniques are often combined, especially convolutional neural network (CNN) and recurrent neural network (RNN), etc., which can better capture the complex temporal and spatial features in the chip data. Subsequently, the obtained association model in the chip test stage is used to construct a dynamic data acquisition optimization engine, with the goal of flexibly adjusting the frequency and content of data acquisition according to different working states and actual requirements. Specifically, based on the output of the association model, the working mode or configuration of the sensor can be dynamically adjusted to selectively enhance the acquisition of specific data. At this time, the optimization engine makes real-time adjustments according to the feedback of the model. For example, it increases the acquisition frequency or depth of the key features in the abnormal state and reduces the acquisition intensity of the non-key features in the stable state. In this way, while maintaining the data acquisition efficiency, the important information related to the chip performance or failure can be obtained to the maximum extent. Finally, the chip data acquisition optimization engine can provide an efficient and targeted chip data acquisition solution through effective resource scheduling and configuration, providing rich and accurate data support for subsequent analysis and diagnosis.

[0078] Step S4: Optimize the data acquisition of the chip data acquisition optimization engine, and use the generated optimized chip acquisition data as input to the defect mode library for knowledge transfer in the test stage. Verify the data effectiveness through the actual yield. If a new abnormal mode is detected during the acquisition process, automatically trigger a specific enhanced sensor for enhanced acquisition, and finally generate a chip data optimization acquisition report.

[0079] In the embodiments of the present invention, based on the optimization engine constructed in the foregoing steps, by evaluating the real-time dynamic data acquisition requirements in different working states, the data acquisition frequency, range, and timing are flexibly adjusted. Using an adaptive data acquisition strategy, through real-time feedback adjustment, it is ensured that more key data related to chip performance, faults, etc. can be obtained. Especially during the peak period of chip workload or when abnormalities occur, the acquisition depth and accuracy of relevant features are enhanced. This process usually relies on algorithm models with high-frequency real-time computing, such as Kalman Filter, etc., to achieve real-time optimization and adjustment of acquisition parameters, ensuring that the acquisition process will not affect the accuracy of subsequent analysis due to too much or too little data inflow. Then, the optimized data collected by the chip is input into the defect mode library for knowledge transfer during the testing phase. The defect mode library contains a large number of known chip defect modes and their corresponding feature data. Through machine learning or deep learning algorithms, the defect mode library can automatically identify potential abnormalities in chip data and compare these abnormal modes with the known defect modes in historical data, thereby realizing the prediction and identification of new defect modes. The defect mode library usually adopts methods such as reinforcement learning to continuously match and learn the newly collected abnormal modes with the known modes, gradually expanding its defect recognition ability. At the same time, the actual yield verification data serves as a feedback link to further verify the effectiveness of the collected data. By comparing the yield data in actual production with the data collected during the testing phase, the impact of the collected data on chip performance evaluation is evaluated, thereby ensuring that the collected data can accurately reflect the true performance of the chip. If a new abnormal mode is detected during the acquisition process, the system will automatically trigger specific enhanced sensors for enhanced acquisition based on real-time monitoring and data analysis. The enhanced sensors will add more sensing information to the acquisition mode, especially for the detected abnormal areas, increasing the refined acquisition of relevant signals. This process is based on anomaly detection algorithms, such as anomaly detection based on clustering analysis, which can quickly identify potential new anomalies in actual data, thereby improving the accuracy of chip fault prediction.

[0080] Preferably, step S1 includes the following steps:

[0081] Step S11: Use a high-precision current sensor to detect the contact impedance of the chip to obtain high-precision current sampling rate data;

[0082] Step S12: Apply dot-matrix near-field electromagnetic induction to the chip signal using an electromagnetic field distribution sensor array to obtain dot-matrix near-field electromagnetic induction data;

[0083] Step S13: Use a digital signal oscilloscope to collect parameters with a synchronous bandwidth greater than or equal to a preset value during the chip function test phase to obtain digital signal test bandwidth data;

[0084] Step S14: Align the high-precision current sampling rate data, dot-matrix near-field electromagnetic induction data, and digital signal test bandwidth data in the time domain through time-delay synchronization technology, and analyze the chip working state using data analysis software to obtain an initial test data set.

[0085] In the embodiment of the present invention, a high-precision current sensor is used for contact impedance detection, and the purpose is to accurately capture the current fluctuation when the chip contacts the external circuit. Through the high-precision current sampling rate, the change of the instantaneous current during the chip operation can be accurately recorded, thereby reflecting the current characteristics of the chip in different working states. The high sampling rate can ensure the capture of small current fluctuations and provide high-quality data support for subsequent fault diagnosis. The electromagnetic field distribution sensor array is used to apply dot-matrix near-field electromagnetic induction to the chip signal, and the electromagnetic radiation of the chip can be accurately measured. Through this sensor array, the electromagnetic field distribution data of the chip in different working states can be obtained, further revealing the electromagnetic radiation characteristics of the chip during operation, especially the electromagnetic signal changes under high-frequency or extreme working conditions. The dot-matrix near-field electromagnetic induction technology can accurately capture the small changes in the electromagnetic field on the surface and around the chip, and these changes are closely related to the performance, load, and potential faults of the chip. The digital signal oscilloscope is used to collect the synchronous bandwidth data of the chip in the functional test stage. By setting the threshold of the synchronous bandwidth, the response signals of the chip within a specific working frequency range can be captured, and these signals provide the dynamic response characteristics of the chip within its working frequency range, providing high-dimensional frequency domain information for subsequent analysis. The above three types of data are aligned in the time domain through time-delay synchronization technology. The key technical means of this step is to perform time-domain synchronization on the data collected by different sensors, so that the data from different sensors can be accurately aligned and fused. The time-delay synchronization technology adjusts the sampling time difference to ensure that the acquisition time of each data point is consistent, thereby improving the comparability and consistency of the data. The data analysis software comprehensively analyzes these aligned data to obtain the analysis result of the chip working state and finally forms an initial test data set. This data set will provide a data basis for subsequent performance evaluation, fault diagnosis, and optimization solutions.

[0086] As an example of the present invention, refer to Figure 2 shown, in this example, step S2 includes:

[0087] Step S21: Clean the chip data based on the initial test data set, and use the abnormal waveform detection algorithm to perform wavelet transform denoising on the generated initial test chip cleaning data to generate initial test preprocessing data;

[0088] Step S22: Perform contact point impedance correction on the initial test preprocessing data using a preset chip impedance-contact force mapping model to obtain initial chip test correction data;

[0089] Step S23: Use the initial chip test correction data to extract the key feature vectors of the chip, and obtain the chip data feature dataset.

[0090] In the embodiment of the present invention, an abnormal waveform detection algorithm is used. This algorithm ensures the authenticity and accuracy of the analyzed data by identifying and filtering abnormal waveforms in the data and eliminating invalid data caused by noise or external interference. On this basis, wavelet transform denoising technology is used to denoise the initial test chip data. Wavelet transform can effectively decompose the signal at multiple scales, remove different frequency components, and significantly improve the signal quality and retain the core feature information, especially when dealing with non-stationary signals containing noise. The denoised data forms the initial test preprocessed data, which provides a clean and stable input dataset for subsequent analysis. A preset chip impedance-contact force mapping model is applied to correct the contact point impedance of the preprocessed data. This process aims to compare the experimental data with the theoretical model and correct the errors caused by poor contact or measurement deviation to obtain more accurate test data. Through this correction, the errors caused by unstable contact force or resistance can be eliminated, thereby improving the reliability and effectiveness of the data. Then, extract the key feature vectors of the chip based on the corrected data. This process identifies the important parameters or indicators of the chip in different working states through feature extraction technology, usually using principal component analysis (PCA) or other dimensionality reduction methods to convert high-dimensional data into a low-dimensional key feature dataset. These feature vectors represent the core performance indicators of the chip and can effectively reflect the working state, health status, and potential failure risks of the chip.

[0091] Preferably, the extraction of the key feature vectors of the chip described in step S2 includes the following:

[0092] Extract transient current waveform data, chip electromagnetic radiation data, and chip load thermal distribution images;

[0093] Use the short-time Fourier transform to dynamically convert the transient current waveform data into chip frequency-time domain information. The dynamic conversion includes shortening the window length when the transient current waveform data is greater than or equal to the severe fluctuation threshold, so that the chip frequency-time domain information captures more high-frequency information, and increasing the window length when the transient current waveform data is less than the severe fluctuation threshold to obtain chip frequency-time domain information containing more stable low-frequency components;

[0094] Perform a time-frequency matrix conversion on the chip frequency-time domain information to obtain a chip time-frequency joint feature matrix;

[0095] Construct a singular value matrix for the chip electromagnetic radiation data to obtain a chip electromagnetic radiation singular value matrix;

[0096] Calculate the left and right singular value vectors of the chip electromagnetic radiation singular value matrix, and retain the first 20 contributions through the generated left and right singular value vectors to obtain the chip electromagnetic radiation contribution data;

[0097] Use the image pixel block technology to block the chip load thermal distribution image into blocks of 36×36 - 256×256 pixels, and calculate the gradient of the blocks to obtain the chip load gradient data; draw the gradient histogram of the edge temperature information based on the chip load gradient data to obtain the chip load temperature histogram data;

[0098] Perform multi-modal feature fusion on the chip time-frequency joint feature matrix, the chip electromagnetic radiation contribution data, and the chip load temperature histogram data to generate a chip data feature dataset.

[0099] In the embodiments of the present invention, transient current waveform data, chip electromagnetic radiation data, and chip load thermal distribution images are extracted, which provide multi-modal data sources for subsequent data processing and respectively reflect the electrical performance, electromagnetic behavior, and thermal characteristics of the chip. Then, the transient current waveform data is dynamically transformed through the short-time Fourier transform (STFT) to convert the time-domain signal into frequency-time domain information. The dynamic adjustment strategy of the window length of the short-time Fourier transform judges according to the violent fluctuation threshold. When the fluctuation is high, the window is shortened to capture more high-frequency information, while when the fluctuation is low, the window is extended to focus on the stable low-frequency components, thereby optimizing the acquisition of frequency-domain information under different working conditions. This dynamic window adjustment method can adapt to the changes in signal characteristics and improve the timeliness and accuracy of frequency-domain information. Next, the chip frequency-time domain information is converted into a time-frequency matrix to generate a time-frequency joint feature matrix. This conversion helps to comprehensively capture the time-frequency characteristics of the chip under different working states through the joint representation of the time domain and the frequency domain, providing richer data information for subsequent analysis. For the electromagnetic radiation data, the singular value decomposition (SVD) is used to construct the singular value matrix, and by calculating its left and right singular value vectors, the first 20 features with the largest contributions are selected, which can extract the main components of the chip electromagnetic radiation, reduce the redundancy of the data, and retain the key features. The chip load thermal distribution image is processed through the image pixel block technology, and the image is divided into blocks of 36×36 to 256×256 pixels, and the gradient of each block is calculated to extract the detailed information of the chip thermal distribution. Through the drawing of the gradient histogram of the edge temperature information, the temperature distribution characteristics of the chip load can be further obtained. After being processed, these data from different sources and forms are finally combined through the multi-modal feature fusion technology, combining the time-frequency joint feature matrix, the electromagnetic radiation contribution data, and the load temperature histogram data to form a comprehensive chip data feature dataset.

[0100] As an example of the present invention, refer to Figure 3As shown, in this example, step S3 includes:

[0101] Step S31: Establish an association model for the chip data feature dataset based on the DTW algorithm for feature similarity analysis to obtain the association model in the chip test stage;

[0102] Step S32: Calculate the feature dimension weight matrix in real time for the association model in the chip test stage according to the update frequency of 10 Hz to obtain the chip feature dimension weight matrix;

[0103] Step S33: Construct a dynamic data acquisition optimization engine according to the chip feature dimension weight matrix to obtain the chip data acquisition optimization engine.

[0104] In the embodiment of the present invention, the DTW algorithm based on feature similarity analysis is used to establish an association model for the chip data feature dataset. As a classic time series comparison method, the DTW algorithm can non-linearly align data on the time axis by calculating the similarity between different feature data sequences. This is crucial for the association modeling of data in the chip test stage, and can accurately capture the similarity of feature data changes between different time points, thereby revealing the working rules and behavior patterns of the chip in different states, and thus generating the association model in the chip test stage. The calculation of the feature dimension weight matrix is achieved by real-time updating the feature weights in the association model. The feature dimension weight matrix is dynamically calculated based on the association model of chip data features, and it reflects the importance of different features for chip performance in different test stages. By calculating these weights in real time, the data acquisition strategy can be adjusted and optimized in a timely manner to ensure that the most critical feature dimensions are concerned and the acquisition of redundant features is reduced. The core technical means at the data level in this process is the real-time weighting and dynamic update of feature dimensions, which is crucial for improving the efficiency and accuracy of data acquisition. The construction of the dynamic data acquisition optimization engine is optimized according to the calculated feature dimension weight matrix. This optimization engine can adjust the acquisition strategy in real time and optimize the efficiency and quality of data acquisition. Specifically, the acquisition engine determines which feature data to collect preferentially based on the weight information of the feature dimensions, and ensures that the most valuable data can be obtained under different test conditions by dynamically adjusting parameters such as the acquisition frequency and sampling time.

[0105] Preferably, the construction of the dynamic data acquisition optimization engine described in step S3 includes the following steps:

[0106] Calculate the feature coefficient of variation for the chip feature dimension weight matrix, and sample 30% of the benchmark value according to the coefficient of variation of each chip feature being lower than 5% to obtain the chip low-dimensional feature sampling data;

[0107] Detect abnormal fluctuations or extreme events in the chip feature dimension weight matrix. If the kurtosis is greater than 5, perform 300% sampling of the reference value through the entropy method to obtain chip high-dimensional feature sampling data;

[0108] Generate an adaptive acquisition strategy table using the chip low-dimensional feature sampling data and the chip high-dimensional feature sampling data, and perform hardware-level dynamic configuration using a field-programmable gate array to obtain a chip data acquisition optimization engine.

[0109] In the embodiment of the present invention, calculating the feature coefficient of variation for the chip feature dimension weight matrix is to measure the stability and volatility of each feature in different test stages by statistically analyzing the variation degree of each feature in the dataset. The coefficient of variation (CV) is the ratio of the standard deviation to the mean, which can reflect the relative change degree of different features. By calculating the coefficient of variation of each feature, it can be revealed which features have high variability and which features are relatively stable. Sampling 30% of the reference value based on the features with a coefficient of variation lower than 5% aims to extract low-dimensional feature sampling data from these stable features. This process helps avoid unnecessary data redundancy and improve sampling efficiency. Next, detect abnormal fluctuations or extreme events. If the kurtosis is greater than 5, it indicates that there are spikes or abnormal fluctuations in the data. At this time, use the entropy method to perform 300% sampling of the reference value. The entropy method can quantify the uncertainty of the data. By introducing this method, higher-frequency sampling can be performed for abnormal fluctuations and extreme events during data acquisition, so as to obtain more high-dimensional feature data and ensure that key changes in the chip working state can be comprehensively captured. Finally, generate an adaptive acquisition strategy table using the low-dimensional and high-dimensional feature sampling data. This strategy table assigns different priorities and sampling frequencies to each feature during the acquisition process according to the variability of the sampling data and the abnormal detection results, so as to dynamically adjust the data acquisition process. Through hardware-level dynamic configuration using a field-programmable gate array (FPGA), the acquisition strategy can be adjusted in real time and optimized at the hardware level. FPGA has flexible hardware configuration capabilities, can quickly respond to changes in acquisition requirements, and provide more accurate and efficient data acquisition control.

[0110] As an example of the present invention, refer to Figure 4 As shown, in this example, step S4 includes:

[0111] Step S41: Optimize data acquisition for the chip data acquisition optimization engine to obtain chip acquisition optimization data;

[0112] Step S42: Use the optimized data collected by the chip as input to the defect pattern library for knowledge transfer in the testing phase, and generate a new sampling pattern for chip data, where the defect pattern library includes 1.2×10 6 known defect features;

[0113] Step S43: Verify the effectiveness of the new sampling pattern of chip data through the actual yield. If a new abnormal pattern is detected during the collection process, automatically trigger a specific enhanced sensor for enhanced collection, and finally generate an optimized acquisition report for chip data.

[0114] In the embodiment of the present invention, the optimized data acquisition step of the chip data acquisition optimization engine improves the quality and effectiveness of data by adjusting the parameters of data acquisition in real time. This process usually relies on algorithms and models to dynamically adjust the acquisition strategy to ensure that useful feature data can be collected as efficiently as possible during the testing process and redundant or irrelevant data can be filtered out. The optimized chip acquisition data is sent to the defect pattern library for knowledge transfer. The defect pattern library contains a dataset of known defect features, which are obtained through the analysis and induction of various chip failure modes in the early stage. In the testing phase, by matching the newly collected data with the defect features in the library and using pattern recognition and machine learning methods for knowledge transfer, a "new sampling pattern" for the chip is generated. The generation of this pattern not only considers historical data but also includes the response ability of real-time data to new features, thereby continuously updating and optimizing the data sampling strategy. In the verification phase, the effectiveness of the new sampling pattern of chip data is verified through the actual yield verification data. The actual yield verification data determines whether the collected data pattern is representative and effective by comparing the collected samples with the product yield verified in the actual production process. If a new abnormal pattern is detected during the data collection process, that is, a new abnormal fluctuation or an unknown failure feature is identified, the system will automatically trigger a specific enhanced sensor for enhanced collection. The enhanced sensor automatically adjusts the sampling frequency or sampling pattern according to the real-time feedback signal to deeply capture abnormal data and improve the sampling accuracy. Finally, by integrating the optimized acquisition data and the enhanced acquisition data, an optimized acquisition report for chip data is generated, providing accurate and effective data support for subsequent chip design, improvement, or fault analysis.

[0115] Preferably, step S43 includes the following steps:

[0116] Step S431: Verify the effectiveness of the new sampling pattern of chip data through the actual yield, and verify the real-time collected data using the production line MES system to obtain chip acquisition information feedback data;

[0117] Step S432: If the confidence level detected during the acquisition process is <85%, it is listed as a new abnormal mode, and a specific enhanced sensor is automatically triggered for enhanced acquisition. Meanwhile, abnormal feedback data of chip acquisition information is obtained.

[0118] Step S433: Construct a chip data acquisition report from the chip acquisition information feedback data and the abnormal feedback data of chip acquisition information, and obtain a chip data optimized acquisition report.

[0119] In the embodiment of the present invention, verifying the data validity through the actual yield is a quality control measure, and the real-time acquired data is verified using the production line MES (Manufacturing Execution System) system. This process uses the MES system to obtain real-time data on the production line, such as the yield rate, failure rate, etc., and compares it with the data of the new sampling mode. Through comparative analysis, the reliability and validity of the acquired data are evaluated, and chip acquisition information feedback data is obtained. Through this data verification mechanism, the acquisition strategy can be quickly calibrated in the production environment, thereby ensuring that the acquired data can accurately reflect the performance and state of the chip. The data quality during the acquisition process is monitored using confidence level analysis. When the confidence level of the real-time acquired data is lower than 85%, the data is automatically identified as a new abnormal mode. At this time, the system triggers a specific enhanced sensor for enhanced acquisition, that is, by activating a higher-precision or different type of sensor to improve the quality and accuracy of the acquired data. The enhanced acquisition is not limited to the sampling frequency and precision of the data, but also includes the adjustment of the working mode of the sensor to ensure that when an abnormal mode appears, more abnormal features or detailed information can be captured, thereby generating abnormal feedback data of chip acquisition information. Finally, the chip data acquisition report is constructed based on the above-mentioned data. The chip acquisition information feedback data and the abnormal feedback data are integrated, and through data analysis and report generation algorithms, the final chip data optimized acquisition report is formed. This report summarizes the key data characteristics, abnormal modes, the effects of the enhanced acquisition process, and the implementation effects of the optimized acquisition strategy during the acquisition process, providing detailed and accurate basis for subsequent chip detection, quality control, and optimized design.

[0120] In this specification, a chip data acquisition system is provided for executing the above-mentioned chip data acquisition method. The chip data acquisition system includes:

[0121] Real-time acquisition and initial data recording, for using intelligent sensors to real-time acquire the working parameters of the chip and record the initial performance data of the chip; according to the initial performance data, using data analysis software to establish an initial test data set of the chip working state;

[0122] Data cleaning and feature vector extraction, for performing data cleaning based on the initial test data set, and extracting key feature vectors of the chip from the preprocessed initial test data to obtain a chip data feature data set;

[0123] Establishing a correlation model and a collection optimization engine, which is used to establish a correlation model based on the chip data feature data set, and use the obtained chip test phase correlation model to build a dynamic data collection optimization engine to obtain a chip data collection optimization engine;

[0124] Optimize data collection and defect pattern library testing to optimize data collection for the chip data collection optimization engine, and use the generated chip collection optimization data as input to the defect pattern library for knowledge transfer in the testing phase. The data validity is verified through actual yield. If a new abnormal pattern is detected during the collection process, a specific enhanced sensor is automatically triggered for enhanced collection, and finally a chip data optimization acquisition report is generated.

[0125] A chip data acquisition storage medium stores a computer program, which implements the above-mentioned method for generating a three-dimensional model of a breathing mask when executed.

[0126] The present invention achieves the beneficial effect of collecting chip operating parameters in real time through intelligent sensors and constructing an initial test dataset based on initial performance data, providing high-quality basic data for subsequent analysis. This preliminary operating status dataset provides an accurate reference for subsequent data cleaning and feature extraction. Data cleaning and key feature vector extraction ensure the validity and reliability of chip data by removing noise and redundant information and extracting key data features. Feature vector extraction not only removes redundant data but also uncovers potential performance variations in the chip, which is crucial for subsequent dynamic data acquisition optimization and fault pattern identification. By establishing a correlation model that effectively correlates chip data features with their operating status, this model provides theoretical support for the construction of a dynamic data acquisition optimization engine. Based on this model, the system can adjust the acquisition strategy based on actual operating conditions, ensuring efficient acquisition of key data and effectively avoiding unnecessary redundant data acquisition. By optimizing the data acquisition process, the collected data is input into a defect pattern library for knowledge transfer, and verified against actual yield, further ensuring the actual validity and diagnostic accuracy of the collected data. Furthermore, when new abnormal patterns are detected, the system can automatically trigger enhanced sensor acquisition for enhanced acquisition, thereby acquiring more key data in real time. This process effectively improves the flexibility and pertinence of data collection, increases the accuracy of chip fault prediction, and reduces the risk of manual intervention and misdiagnosis. The generation of data optimization acquisition reports not only provides a scientific basis for the chip production process, but also provides a more solid data foundation for future data analysis. Therefore, the present invention solves the problems of inaccurate traditional data collection and improper processing of redundant data by dynamically adjusting data collection strategies and enhancing sensor configuration, thereby improving the accuracy and production efficiency of chip performance diagnosis.

[0127] Therefore, in any case, the embodiments should be regarded as exemplary and non-limiting. The scope of the present invention is defined by the appended claims rather than the above description. Therefore, all changes falling within the meaning and scope of the equivalent elements of the application documents are intended to be encompassed within the present invention.

[0128] The above description is only a specific implementation manner of the present invention, enabling those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be obvious to those skilled in the art. The general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to these embodiments shown herein, but rather to the broadest scope consistent with the principles and novel features invented herein.

Claims

1. A method for obtaining chip data, characterized in that, Applied to a chip data acquisition device, the chip data acquisition device is equipped with intelligent sensors and an adaptive data acquisition control unit, including the following steps: Step S1: Use intelligent sensors to collect the working parameters of the chip in real time and record the initial performance data of the chip; according to the initial performance data, use data analysis software to establish an initial test data set of the chip working state; Step S2: Perform data cleaning based on the initial test data set, and extract the key feature vectors of the chip from the initial test preprocessed data to obtain a chip data feature data set; Step S3: Establish an association model according to the chip data feature data set, and use the obtained chip test phase association model to construct a dynamic data acquisition optimization engine to obtain a chip data acquisition optimization engine; Step S4: Optimize data acquisition for the chip data acquisition optimization engine, and use the generated chip acquisition optimization data as input to the defect mode library for knowledge transfer in the test phase. Verify the data validity through the actual yield. If a new abnormal mode is detected during the acquisition process, automatically trigger a specific enhanced sensor for enhanced acquisition, and finally generate a chip data optimization acquisition report.

2. The chip data acquisition method according to claim 1, wherein The intelligent sensors include a high-precision current sensor, an electromagnetic field distribution sensor array, and a digital signal oscilloscope. Step S1 includes the following steps: Step S11: Use the high-precision current sensor to detect the contact impedance of the chip to obtain high-precision current sampling rate data; Step S12: Use the electromagnetic field distribution sensor array to apply dot-matrix near-field electromagnetic induction during the chip signal application stage to obtain dot-matrix near-field electromagnetic induction data; Step S13: Use the digital signal oscilloscope to collect parameters with a synchronous bandwidth greater than or equal to a preset value during the chip function test stage to obtain digital signal test bandwidth data; Step S14: Align the high-precision current sampling rate data, dot-matrix near-field electromagnetic induction data, and digital signal test bandwidth data in the time domain through time error synchronization technology, and use data analysis software to analyze the chip working state to obtain an initial test data set.

3. The chip data acquisition method according to claim 2, wherein Step S2 includes the following steps: Step S21: Perform chip data cleaning based on the initial test data set, and use the abnormal waveform detection algorithm to perform wavelet transform denoising on the generated initial test chip cleaning data to generate initial test preprocessed data; Step S22: Use the preset chip impedance-contact force mapping model to perform contact point impedance correction on the initial test preprocessed data to obtain initial chip test correction data; Step S23: Use the initial chip test correction data to extract the key feature vectors of the chip to obtain a chip data feature data set.

4. The chip data acquisition method according to claim 1, wherein The extraction of the key feature vectors of the chip in Step S2 includes the following: Extract transient current waveform data, chip electromagnetic radiation data, and chip load thermal distribution images; Use the short-time Fourier transform to dynamically convert the transient current waveform data into chip frequency-time domain information. The dynamic conversion includes shortening the window length when the transient current waveform data is greater than or equal to the severe fluctuation threshold, so that the chip frequency-time domain information captures more high-frequency information. When the transient current waveform data is less than the severe fluctuation threshold, increase the window length to obtain chip frequency-time domain information containing more stable low-frequency components; Perform a time-frequency matrix conversion on the chip frequency-time domain information to obtain a chip time-frequency joint feature matrix; Construct a singular value matrix for the chip electromagnetic radiation data to obtain a chip electromagnetic radiation singular value matrix; Calculate the left and right singular value vectors of the chip electromagnetic radiation singular value matrix, and retain the first 20 contribution degrees through the generated left and right singular value vectors to obtain chip electromagnetic radiation contribution degree data; Use the image pixel block technology to block the chip load thermal distribution image from 36×36 to 256×256 pixels, and calculate the gradient of the block to obtain chip load gradient data; draw a gradient histogram of the edge temperature information based on the chip load gradient data to obtain chip load temperature histogram data; Perform multi-modal feature fusion on the chip time-frequency joint feature matrix, chip electromagnetic radiation contribution degree data, and chip load temperature histogram data to generate a chip data feature dataset.

5. The chip data acquisition method according to claim 1, characterized in that, Step S3 includes the following steps: Step S31: Establish an association model for the chip data feature dataset based on the DTW algorithm of feature similarity analysis to obtain a chip test phase association model; Step S32: Calculate the feature dimension weight matrix for the chip test phase association model in real time according to the update frequency of 10Hz to obtain a chip feature dimension weight matrix; Step S33: Construct a dynamic data acquisition optimization engine based on the chip feature dimension weight matrix to obtain a chip data acquisition optimization engine.

6. The chip data acquisition method according to claim 1, wherein The construction of the dynamic data acquisition optimization engine described in step S3 includes the following steps: Calculate the feature coefficient of variation of the chip feature dimension weight matrix, and sample 30% of the reference value according to the chip feature coefficient of variation with a coefficient of variation lower than 5% to obtain chip low-dimensional feature sampling data; Detect abnormal fluctuations or extreme events in the chip feature dimension weight matrix. If the kurtosis is greater than 5, sample 300% of the reference value through the entropy value method to obtain chip high-dimensional feature sampling data; Generate an adaptive acquisition strategy table through the chip low-dimensional feature sampling data and chip high-dimensional feature sampling data, and perform hardware-level dynamic configuration using a field programmable gate array to obtain a chip data acquisition optimization engine.

7. The chip data acquisition method according to claim 1, wherein Step S4 includes the following steps: Step S41: Perform optimized data acquisition on the chip data acquisition optimization engine to obtain chip acquisition optimized data; Step S42: Use the chip-collected optimized data as input to perform knowledge transfer in the testing phase in the defect mode library, generating a new sampling mode for chip data, where the defect mode library includes 1.2×10 6 known defect features; Step S43: Verify the data validity of the chip data new sampling mode through the actual yield. If a new abnormal mode is detected during the acquisition process, automatically trigger a specific enhanced sensor for enhanced acquisition, and finally generate a chip data optimization acquisition report.

8. The chip data acquisition method according to claim 7, wherein Step S43 includes the following steps: Step S431: Verify the effectiveness of the new sampling mode of chip data through actual yield verification data, and verify the real-time collected data using the production line MES system to obtain the chip collection information feedback data; Step S432: If the confidence level detected during the collection process is <85%, it is listed as a new abnormal mode, and a specific enhanced sensor is automatically triggered for enhanced collection. At the same time, the chip collection information abnormal feedback data is obtained; Step S433: Construct a chip data collection report from the chip collection information feedback data and the chip collection information abnormal feedback data to obtain a chip data optimized acquisition report.

9. A chip data acquisition system, characterized in that, For implementing the chip data acquisition method as described in claim 1, the chip data acquisition system includes: Real-time collection and initial data recording, for using intelligent sensors to collect the working parameters of the chip in real time and record the initial performance data of the chip; according to the initial performance data, use data analysis software to establish an initial test data set of the chip working state; Data cleaning and feature vector extraction, for performing data cleaning based on the initial test data set, and extracting the key feature vectors of the chip from the initial test preprocessed data to obtain the chip data feature data set; Establishing an association model and constructing an acquisition optimization engine, for establishing an association model according to the chip data feature data set, and constructing a dynamic data acquisition optimization engine using the obtained chip test phase association model to obtain the chip data acquisition optimization engine; Optimizing data collection and testing the defect mode library, for performing optimized data collection on the chip data acquisition optimization engine, and using the generated chip acquisition optimized data as input to the defect mode library for knowledge transfer in the testing phase. Verify the data effectiveness through actual yield. If a new abnormal mode is detected during the collection process, automatically trigger a specific enhanced sensor for enhanced collection, and finally generate a chip data optimized acquisition report.

10. A chip data acquisition storage medium stores a computer program, characterized in that, When the computer program is executed, it implements the chip data acquisition method as described in any one of claims 1 to 8.

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