Data transmission system and method based on dual-channel DMA controller and mixed interrupt mode

Abstract

The invention discloses a data transmission system and method based on dual-channel DMA controllers and a mixed interrupt mode. An FPGA chip integrates a dual-DMA controller group, a PCIe interface module, a data buffer module, a mixed interrupt control module and a CRC verification module through hardware logic. According to the invention, through the division cooperation of the double DMA controller groups, the efficient multiplexing of the circular address queues and the dynamic adaptation of the mixed interruption, the system realizes high-reliability transmission at the rate of 10Gbps.

Description

Technical Field

[0001] The present invention relates to the technical field of high-speed data transmission, and particularly to a data transmission system and method based on a dual-channel DMA controller and a hybrid interrupt mode. Background Art

[0002] In the computer architecture, the high-speed data transmission technology based on the PCIe bus is widely applied to servers, storage devices and embedded systems. Most existing systems use a single DMA controller to manage two-way data streams, which causes the upstream (CPU to peripheral) and downstream (peripheral to CPU) transmissions to compete for the same channel resources. Especially in the two-way high-load scenario, such a design is prone to channel congestion, and the measured data shows that the effective bandwidth utilization rate is less than 60%. In addition, the single-channel architecture is difficult to support the physical isolation between the sender and the receiver, increasing the risk of data transmission delay and error diffusion. In addition, the traditional interrupt mode usually adopts a fixed trigger strategy and cannot be dynamically adjusted according to the data transmission scenario. For example, in the case of bulk data transmission, frequent packet-by-packet interrupts will cause an "interrupt storm", resulting in a sharp increase in CPU load; while in the scenario with high real-time requirements, merged interrupts may introduce uncontrollable delays and it is difficult to meet the requirements of high-real-time applications. Summary of the Invention

[0003] The purpose of the present invention is to overcome the above existing technical problems, and through the innovation of the hardware architecture and the optimization of the interrupt mechanism, provide a data transmission system based on a dual-channel DMA controller and a hybrid interrupt mode, so as to achieve efficient and reliable two-way data transmission.

[0004] To achieve the above purpose, the present invention adopts the following technical solutions: Dual-CPU architecture: The sending-end CPU and the receiving-end CPU are respectively connected to the FPGA chip through independent PCIe physical interfaces for data sending and receiving; The FPGA chip integrates the following functional modules through hardware logic: Dual DMA controller group: including a sending-end DMA controller group and a receiving-end DMA controller group, which are respectively controlled by the sending-end CPU and the receiving-end CPU for managing two-way data streams; where: The sending-end DMA controller group is responsible for the two-way data stream between the sending-end CPU and the FPGA chip; the receiving-end DMA controller group is responsible for the two-way data stream between the receiving-end CPU and the FPGA chip; PCIe interface module: Communicatively connected to the PCIe physical interface for realizing data interaction and interrupt signal transmission between the FPGA chip and the CPU; Data buffer module: contains a circular address queue, which is used to temporarily store the address and length of the transmitted data and cyclically reuse address resources during data transmission; Hybrid interrupt control module: Dynamically selects the interrupt mode by configuring the interrupt control register and works in conjunction with the interrupt mechanism of the PCIe interface module; CRC check module: A check value is added during data transmission, and the receiving end verifies the data integrity. If the check fails, an error interrupt is triggered and fed back to the corresponding CPU.

[0005] Furthermore, the interruption mode includes: Step-by-step operation interrupt: trigger interrupt by writing length and address step by step; Merge operation interrupt: Merge length and address into a single operation to trigger an interrupt; Count clear interrupt: Clear interrupt queues in batches by reading message counts.

[0006] Furthermore, the address resources of the circular address queue are initialized by pre-configuration and are cyclically reused in the writing order during the transmission process to form a circular buffer with a depth of 1024 items. Each address interval is 2048 bytes, which constitutes the basic unit of the circular buffer.

[0007] Furthermore, the hybrid interrupt control module adopts the MSI-X mechanism to allocate independent interrupt information addresses and data registers to the read and write ends of each DMA controller, and feeds back the interrupt suspension status in real time through the status register.

[0008] Furthermore, the DMA controller group is implemented through hardware logic, and its control register is mapped to the address space of the FPGA chip, supporting dynamic configuration of data transmission parameters, including message length, address offset and interrupt trigger threshold.

[0009] Furthermore, the check value of the CRC check module covers the message header, length field and message body. When the receiving end fails to check, the data is discarded and a bus error interrupt is triggered. The bus error interrupt is fed back to the corresponding CPU through the hybrid interrupt control module.

[0010] The present invention also provides a data transmission method based on a dual-channel DMA controller and a mixed interrupt mode, comprising the following steps: S1: Initial configuration Configure the control registers of the transmitter DMA controller group and the receiver DMA controller group to dynamically set the message length, address offset and interrupt trigger threshold; Preconfigure a circular address queue and initialize address resources at certain byte intervals to form a ring buffer; Configure the interrupt mode of the hybrid interrupt control module, and based on the MSI-X mechanism, allocate independent MSI-X interrupt information addresses and data registers for the read and write ends of each DMA controller; S2: Data transfer from the sender to the receiver (1) The sender CPU writes data into the sender address space of the FPGA chip through the PCIe interface module; (2) The downstream controller of the sender DMA controller group reads data according to the addresses and lengths in the circular address queue, appends the CRC check value, and stores it in the queue; (3) The upstream controller of the receiver DMA controller group reads data from the queue and checks it. After successful verification, it sends the data to the receiver CPU through the PCIe interface module; S3: Data transfer from the receiver to the sender (1) The receiver CPU writes data into the receiver address space of the FPGA chip through the PCIe interface module; (2) The downstream controller of the receiver DMA controller group reads data according to the addresses and lengths in the circular address queue, appends the CRC check value, and stores it in the queue; (3) The upstream controller of the sender DMA controller group reads data from the queue and checks it. After successful verification, it sends the data to the sender CPU through the PCIe interface module; S4: Interrupt and feedback When the data transfer is completed or the verification fails, the hybrid interrupt control module triggers an interrupt signal according to the configured interrupt mode. The interrupt signal is transmitted to the corresponding CPU through the PCIe interface module. The CPU reads the status register to confirm the interrupt type and clears the interrupt flag.

[0011] Further, the pre-configured circular address queue initializes 1024 address resources at intervals of 2048 bytes to form a circular buffer.

[0012] Further, the address multiplexing of the circular address queue includes that the sender queue and the receiver queue circularly use the pre-configured 1024 addresses in the writing order. After the addresses are exhausted, the first address is automatically multiplexed to form a circular data flow path.

[0013] Further, the MSI-X interrupt mechanism configuration includes: allocating interrupt information addresses and data registers for the read and write ends of the sender DMA controller group; allocating interrupt information addresses and data registers for the read and write ends of the receiver DMA controller group.

[0014] Advantages of the present invention: 1. High-efficiency bidirectional transmission: The dual DMA controller group realizes physically isolated bidirectional data streams, avoids resource competition, and combines the circular buffer to circularly reuse addresses to improve throughput.

[0015] 2. Flexible Interrupt Control: The hybrid interrupt mode dynamically adapts to different scenarios (e.g., the step mode is suitable for low-latency requests, and the merge mode reduces the number of interrupts), and the MSI-X mechanism reduces the interrupt handling overhead; 3. High Reliability: CRC check covers the entire message field, and error data is discarded and fed back in real time to ensure data integrity. Description of the Drawings

[0016] Figure 1 : It is the system architecture block diagram of the present invention. Detailed Implementation Manner

[0017] The present invention will be described in detail below with reference to the drawings and embodiments.

[0018] As Figure 1 shown in the system structure block diagram, the corresponding relationships of each component are as follows: Transmitting-end CPU: CPU0; Receiving-end CPU: CPU1.

[0019] The PCIe physical interfaces are PCIE0 and PCIE1. Among them, PCIE0: Connects the PCIe interface module of the transmitting-end CPU (CPU0) to the FPGA chip. PCIE1: Connects the PCIe interface module of the receiving-end CPU (CPU1) to the FPGA chip.

[0020] The AXI controllers are AXI_ctrl0 and AXI_ctrl1. Among them, AXI_ctrl0: The AXI bus controller controlled by CPU0, managing the transmitting-end DMA controller group (DMA_rd021, DMA_wt120). AXI_ctrl1: The AXI bus controller controlled by CPU1, managing the receiving-end DMA controller group (DMA_rd120, DMA_wt021).

[0021] The DMA controller group includes a transmitting-end DMA controller group and a receiving-end DMA controller group. The transmitting-end DMA controller group is DMA_rd021 and DMA_wt120.

[0022] DMA_rd021: Responsible for the downstream data stream from CPU0 to the FPGA (transmitting end → FPGA); DMA_wt120: Responsible for the upstream data stream from the FPGA to CPU0 (FPGA → transmitting end).

[0023] The receiving-end DMA controller group includes DMA_rd120 and DMA_wt021.

[0024] DMA_rd120: responsible for the downstream data flow from CPU1 to FPGA (receiver → FPGA); DMA_wt021: Responsible for the upstream data flow from FPGA to CPU1 (FPGA → receiving end).

[0025] The data buffer module includes fifo-021 and fifo-120, where: fifo-021: Transmitter circular address queue, storing the data address and length in the direction from CPU0 to FPGA to CPU1; fifo-120: Receiver circular address queue, storing the data address and length in the direction of CPU1→FPGA→CPU0.

[0026] Hybrid interrupt control module: integrated into the FPGA logic and linked to the PCIe interface module through the MSI-X mechanism.

[0027] CRC check module: embedded in the DMA controller data path, checks the transmitted data in real time.

[0028] This embodiment takes the scenario that CPU0 sends 256 bytes of data to CPU1, and CPU1 transmits the data back to CPU0 after processing. Figure 1 The specific method is as follows:

[0029] Step 1.1: Register and queue configuration ① Transmitter configuration (AXI_ctrl0) Set the message length (DN_PKT_LEN=256) and starting address (DN_PKT_ADDR=0x0000_0000) of DMA_rd021; configure the merge operation interrupt (DN_CTRL[9:8]=1), and enable the MSI-X interrupt (Dma0_rd_msi_addr_l=0x8000_0000).

[0030] ②Receiver configuration (AXI_ctrl1) Set the address interval of DMA_wt021 (2048 bytes) and initialize the 1024-item address of the fifo-120 queue (starting from 0x0010_0000).

[0031] Step 1.2: Round Robin Address Queue Provisioning Transmitter queue (fifo-021): pre-configured with 1024 entries (0x0000_0000 to 0x0007_F800) at 2048-byte intervals; Receiver queue (fifo-120): Configured according to the same rules (0x0010_0000 to 0x0017_F800).

[0032] Step 1.3: MSI-X Interrupt Configuration ① Step-by-step operation interrupt (sender) Interrupt information address: Dma0_rd_msi_addr_l = 0x8000_0000 (length write interrupt), Dma0_rd_msi_addr_l = 0x8000_0010 (address write interrupt); Interrupt data: Dma0_rd_msi_data = 0x01 (length), Dma0_rd_msi_data = 0x02 (address).

[0033] ② Merged operation interrupt (receiver) Interrupt information address: Dma1_wt_msi_addr_l = 0x8000_1000; Interrupt data: Dma1_wt_msi_data = 0x03 (transfer complete).

[0034] Step 2: CPU0 → CPU1 Data Transfer Step 2.1: CPU0 Writes the Length Field CPU0 writes 256 bytes of length to the DN_PKT_LEN register through AXI_ctrl0, triggering a length write interrupt (DN_STAT

[13] = 1); CPU0 reads the interrupt status register (DN_STAT) to confirm that the length has been received.

[0035] Step 2.2: CPU0 Writes the Address Field CPU0 writes the address 0x0000_0000 to the DN_PKT_ADDR register, triggering an address write interrupt (DN_STAT

[12] = 1); DMA_rd021 starts data transfer according to the address and length.

[0036] Step 2.3: DMA_rd021 Reads Data and Appends CRC DMA_rd021 reads data from 0x0000_0000, calculates the CRC1021 value and fills it at the end of the message; stores the data in the current address of the fifo-021 queue, and the queue pointer jumps to the next address.

[0037] Step 2.4: Transfer Complete Interrupt After DMA_rd021 completes data transfer, it triggers an interrupt (DN_STAT[0] = 1), and CPU0 reads the DN_PKT_SIGMA register to confirm the count.

[0038] Step 2.5: DMA_wt021 Reads and Verifies Data DMA_wt021 reads data from fifo-021 and sends it to CPU1 through PCIE1 after passing the verification; if the verification fails, a bus error interrupt is triggered (UP_STAT

[14] =1), and an error code is fed back to CPU0 (Dma1_wt_msi_data = 0x04).

[0039] Step 3: Data transfer from CPU1 to CPU0 Step 3.1: CPU1 processes the data and sends it back CPU1 modifies the message body (such as adding a "processed" flag) and writes the data to the AXI_PCIE1 address space (0x0010_0000) through PCIE1.

[0040] Step 3.2: DMA_rd120 reads and appends CRC DMA_rd120 reads data from 0x0010_0000, appends a new CRC value, and stores it in the fifo-120 queue; Merger operation interrupt trigger: The length and address are merged and written (high 16-bit length + low 16-bit address offset), triggering the Dma1_rd_msi_data = 0x05 interrupt.

[0041] Step 3.3: DMA_wt120 reads and verifies DMA_wt120 reads data from fifo-120 and sends it to CPU0 through PCIE0 after passing the verification; If the verification fails, the DN_STAT

[14] interrupt is triggered and fed back to CPU1.

[0042] Step 3.4: Count clear interrupt CPU0 reads the UP_PKT_SIGMA register to obtain the transmitted message count, and writes 1 to clear the interrupt queue (UP_CTRL[3]=1); The queue pointer is reset to the starting address to prepare for the next round of transmission.

[0043] Step 4: Interrupt feedback closed loop Step-by-step interrupt response: CPU0 processes the length write, address write, and transmission completion interrupts in sequence through AXI_ctrl0 to ensure sequential data transmission.

[0044] Merger interrupt response: CPU1 processes the merger operation interrupt through AXI_ctrl1, and completes data transfer and verification in a single operation.

[0045] Error recovery mechanism: When the verification fails, the sending CPU reinitiates the transmission according to the error code (such as 0x04) to ensure data integrity.

[0046] In this embodiment, the DMA groups at the sending end (DMA_rd021, DMA_wt120) and the receiving end (DMA_rd120, DMA_wt021) operate independently to avoid data competition. Fifo-021 and fifo-120 cycle through addresses at 2048-byte intervals and automatically reset after exhaustion to ensure long-term stable transmission and efficient reuse of the circular queue. The merge operation interrupt reduces the number of CPU operations, and the MSI-X mechanism accurately locates the interrupt source to achieve dynamic adaptation of hybrid interrupts. The closed-loop design with addition at the sending end and verification at the receiving end, combined with the bus error interrupt feedback, realizes highly reliable transmission.

[0047] Through testing, in this embodiment, through the division of labor and cooperation of the dual-DMA controller group, the efficient reuse of the circular address queue, and the dynamic adaptation of hybrid interrupts, the system achieves highly reliable transmission at a rate of 10 Gbps.

[0048] Finally, it should be noted that the above embodiments are only used to illustrate the present invention and do not limit the technical solutions described in the present invention; therefore, although this specification has described the present invention in detail with reference to the above embodiments, those of ordinary skill in the art should understand that the present invention can still be modified or equivalently replaced; and all technical solutions and their improvements that do not depart from the spirit and scope of the present invention should be covered by the scope of the claims of the present invention.

Claims

1. A data transmission system based on a dual-channel DMA controller and a hybrid interrupt mode, characterized in that, include: Dual-CPU architecture: The sending CPU and receiving CPU are connected to the FPGA chip through independent PCIe physical interfaces for data transmission and reception. The FPGA chip integrates the following functional modules through hardware logic: Dual DMA controller group: includes a transmitter DMA controller group and a receiver DMA controller group, controlled by the transmitter CPU and the receiver CPU respectively, for managing bidirectional data flow; The transmitting end DMA controller group is responsible for the bidirectional data flow between the transmitting end CPU and the FPGA chip; the receiving end DMA controller group is responsible for the bidirectional data flow between the receiving end CPU and the FPGA chip; PCIe interface module: communicates with the PCIe physical interface and is used to implement data interaction and interrupt signal transmission between the FPGA chip and the CPU; Data buffer module: contains a circular address queue, which is used to temporarily store the address and length of the transmitted data and cyclically reuse address resources during data transmission; Hybrid interrupt control module: Dynamically selects the interrupt mode by configuring the interrupt control register and works in conjunction with the interrupt mechanism of the PCIe interface module; CRC check module: A check value is added during data transmission, and the receiving end verifies the data integrity. If the check fails, an error interrupt is triggered and fed back to the corresponding CPU.

2. The data transmission system according to claim 1, characterized in that The interruption modes include: Step-by-step operation interrupt: trigger interrupt by writing length and address step by step; Merge operation interrupt: Merge length and address into a single operation to trigger an interrupt; Count clear interrupt: Clear interrupt queues in batches by reading message counts.

3. The data transmission system according to claim 1, characterized in that: The address resources of the circular address queue are initialized by pre-configuration and are cyclically reused in the order of writing during the transmission process to form a circular buffer with a depth of 1024 items. Each address interval is 2048 bytes, which constitutes the basic unit of the circular buffer.

4. The data transmission system according to claim 1, wherein: The hybrid interrupt control module adopts the MSI-X mechanism to allocate independent interrupt information addresses and data registers to the read and write ends of each DMA controller, and feeds back the interrupt suspension status in real time through the status register.

5. The data transmission system according to claim 1, characterized in that: The DMA controller group is implemented through hardware logic, and its control register is mapped to the address space of the FPGA chip, supporting dynamic configuration of data transmission parameters, including message length, address offset and interrupt trigger threshold.

6. The data transmission system according to claim 1, wherein: The check value of the CRC check module covers the message header, length field and message body. When the receiving end fails to check, the data is discarded and a bus error interrupt is triggered. The bus error interrupt is fed back to the corresponding CPU through the hybrid interrupt control module.

7. A data transmission method for a data transmission system according to any one of claims 1-6, characterized in that, The following steps are involved: S1: Initial configuration Configure the control registers of the transmitter DMA controller group and the receiver DMA controller group to dynamically set the message length, address offset and interrupt trigger threshold; Preconfigure a circular address queue and initialize address resources at certain byte intervals to form a ring buffer; Configure the interrupt mode of the hybrid interrupt control module, and allocate independent MSI-X interrupt information address and data registers to the read and write ends of each DMA controller based on the MSI-X mechanism; S2: Data transmission from sender to receiver a. The sending - end CPU writes data into the sending - end address space of the FPGA chip through the PCIe interface module; b. The downstream controller of the sending - end DMA controller group reads data according to the address and length in the circular address queue, attaches the CRC check value and stores it in the queue; c. The upstream controller of the receiving - end DMA controller group reads and checks the data from the queue, and after successful verification, sends it to the receiving - end CPU through the PCIe interface module; S3: Data transfer from the receiving end to the sending end a. The receiving - end CPU writes data into the receiving - end address space of the FPGA chip through the PCIe interface module; b. The downstream controller of the receiving - end DMA controller group reads data according to the address and length in the circular address queue, attaches the CRC check value and stores it in the queue; c. The upstream controller of the sending - end DMA controller group reads and checks the data from the queue, and after successful verification, sends it to the sending - end CPU through the PCIe interface module; S4: Interrupt and feedback When the data transfer is completed or the verification fails, the hybrid interrupt control module triggers an interrupt signal according to the configured interrupt mode. The interrupt signal is transmitted to the corresponding CPU through the PCIe interface module. The CPU reads the status register to confirm the interrupt type and clears the interrupt flag.

8. The data transmission method according to claim 7, wherein: The pre - configured circular address queue initializes 1024 address resources at intervals of 2048 bytes to form a circular buffer.

9. The data transmission method according to claim 8, wherein: The address multiplexing of the circular address queue includes that the sending - end queue and the receiving - end queue circularly use the pre - configured 1024 addresses in the writing order. After the addresses are exhausted, the first address is automatically multiplexed to form a circular data - flow path.

10. The data transmission method according to claim 9, characterized in that The MSI - X interrupt mechanism configuration includes: Allocating interrupt information addresses and data registers for the read - write ends of the sending - end DMA controller group; allocating interrupt information addresses and data registers for the read - write ends of the receiving - end DMA controller group.

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