Multi-host system based on IIC bus and control method

Abstract

The invention provides a multi-host system based on an IIC bus and a control method, the system comprises M slave devices and N host devices, the host devices and the slave devices are interconnected and communicated through an IIC bus system, each device has an independent communication address, the N host devices are respectively marked as host devices 1-N, and the M slave devices and the N host devices are mutually communicated through the IIC bus system. Wherein the host device 1 has an IIC cycle timing function and is used for determining an IIC host cycle cycle, the host devices 1-N adopt a relay mode to be sequentially configured as a host mode in each IIC host cycle cycle, and the host device in the host mode is sequentially communicated with each slave device; m and N are both greater than 1. According to the invention, a plurality of host devices can work orderly on the IIC bus without time sequence and data conflict, and the method is suitable for aerospace hot backup IIC bus communication systems with high reliability requirements or IIC bus data interaction systems with working requirements of a plurality of host devices.

Description

Technical Field

[0001] The present invention belongs to the field of embedded system bus communication, and can enable multiple host devices to work orderly on the IIC bus without timing and data conflicts. It can be used in an IIC bus host hot backup system for multi-device redundant design, or an IIC bus data interaction system with the working requirements of multiple host devices. Background Art

[0002] The IIC bus, also known as the integrated circuit bus, is a serial communication bus. The bus includes two hardware control signals, namely the clock signal and the data signal. The IIC bus adopts a multi-master and slave architecture. Each device on the bus can be used as a control source for real-time data transmission, but there can only be one control source at any point in time, and this control source can be called the host device. The host device is responsible for sending the clock signal, and the slave device selects whether to output data according to the clock signal and data signal sent by the host device. At any point in time, there can also be only one slave device communicating with the host device. If multiple host devices work simultaneously on the bus, the shared clock signal will conflict and eventually cause the IIC bus to crash.

[0003] However, with the development of embedded systems and the increasing complexity of embedded product functions, the security and reliability of the system have become key features of the system. Hot backup systems are often used to improve the reliability and security of the system. When a main device in the hot backup fails, the backup device can seamlessly cover all the functional and performance requirements of the system without having a fatal impact on the normal operation of the system. Such hot backup systems are often used in the fields of aviation, aerospace, and weaponry with high reliability and security requirements. Therefore, under such requirements, the IIC bus will have an architecture with multiple host devices, so how to achieve the safe and reliable operation of multiple host devices on the IIC bus is of great significance. Summary of the Invention

[0004] The technical problem solved by the present invention is: overcoming the deficiencies of the prior art, providing a multi-host system and control method based on the IIC bus, and without adding additional control lines, only through the hardware architecture of the traditional IIC communication bus, by a reasonable control method, solving the problem that multiple host devices can operate safely and reliably on the IIC bus.

[0005] The solution of the present invention to solve the technical problem is: a multi-master system based on the IIC bus. The system includes M slave devices and N master devices. The master devices and the slave devices are interconnected and communicate through the IIC bus system. Each device has an independent communication address. The N master devices are respectively denoted as master device 1 to master device N. Among them, master device 1 has the IIC cycle timing function for determining the IIC master cycle. Within each IIC master cycle, master devices 1 to N are configured as the master mode in turn in a relay manner. The master device in the master mode communicates with each slave device in turn; both M and N are greater than 1.

[0006] Preferably, all master devices are initially configured as the slave mode.

[0007] Preferably, the master device is a device including a micro control unit.

[0008] Preferably, the specific method for configuring the N master devices as the master mode in a relay manner is: when the first IIC master cycle arrives, master device 1 autonomously sets itself as the master mode. After the master device in the master mode completes the task of communicating with each slave device, it sends a communication enable instruction to another master through the IIC bus, and then configures itself as the slave mode and exits the control of the IIC bus; the master device that receives the communication enable instruction configures itself as the master mode and then performs data interaction with each slave device in turn.

[0009] Preferably, after all master devices complete the communication with each slave device within each IIC cycle, when waiting for the next IIC cycle to arrive, the next cycle of data communication starts.

[0010] Preferably, the format of the communication enable instruction is:

[0011] [S][host address][W][ACK][enable code][ACK][check code][ACK][P]

[0012] Among them, S, ACK, and P respectively represent the start signal, the acknowledgment signal, and the stop signal; W represents writing data to the slave, which forms an 8-bit data with the host address, and the highest bit is used to distinguish the host and the slave. The highest bit being 0 represents the host device, and the highest bit being 1 represents the slave device; the enable code is the serial number of the host device to be configured as the master mode; the check code is used to check the host address and the communication enable code.

[0013] Preferably, the data interaction format between the host and the slave is:

[0014] [S][slave address][R][ACK][data 1][ACK]…[data L][ACK][check code][NACK][P]

[0015] Among them, S, ACK, and P respectively represent the start signal, acknowledgment signal, and stop signal;

[0016] R represents reading data from the slave device, which forms an 8-bit data with the slave device address. The highest bit is used to distinguish the master device and the slave device. A highest bit of 0 represents the master device, and a highest bit of 1 represents the slave device; the check code is used to check the slave device address and Data 1 to Data L. Data 1 to Data L are the data that the master device needs to read, and L is determined by the data volume requirement.

[0017] Another technical solution of the present invention is: a multi-master control method for an IIC bus system, and the method includes the following steps:

[0018] Step S1: Initialize and configure all master devices as slave modes, and each master device and slave device has a different communication address;

[0019] Step S2: Master device 1 initializes the IIC master cycle period;

[0020] Step S3: When the IIC master cycle period arrives, master device 1 sets itself as the master mode and sequentially performs data interaction with slave devices 1 to slave device M; after the communication of master device 1 is completed, it sends a communication enable instruction to master device 2 through the IIC bus, then master device 1 is configured as the slave mode, exits the control of the IIC bus, and sets the on-duty serial number n of master device 1 to 2;

[0021] Step S3: After receiving the communication enable instruction sent by master device n-1, master device n configures master device n as the master mode, and then sequentially performs data interaction with slave devices 1 to slave device M. After the communication of master device n is completed, it sends a communication enable instruction to master device n+1 through the IIC bus, then master device n is configured as the slave mode, exits the control of the IIC bus, adjusts the on-duty serial number n of master device n to be updated to n+1, and re-executes step S3 until n is N, and enters step S4;

[0022] Step S4: After receiving the communication enable instruction of master device N-1, master device N configures master device N as the master mode, and then sequentially performs data interaction with slave devices 1 to slave device M. After the communication is completed, directly configure master device N as the slave mode, exit the control of the IIC bus, and wait for the next IIC master cycle period to arrive, and re-execute step S2 to start the data communication of the next IIC master cycle.

[0023] Preferably, the format of the communication enable instruction is:

[0024] [S][Host address][W][ACK][Enable code][ACK][Check code][ACK][P]

[0025] Among them, S, ACK, and P respectively represent the start signal, acknowledgment signal, and stop signal; W represents writing data to the slave, which forms an 8-bit data together with the host address. The host and the slave are distinguished by the highest bit. The highest bit being 0 indicates the host device, and the highest bit being 1 indicates the slave device; the enable code is the serial number of the host device intended to be set as the host mode; the check code is used to check the host address and the communication enable code.

[0026] Preferably, the data interaction format between the host and the slave is:

[0027] [S][Slave address][R][ACK][Data 1][ACK]…[Data L][ACK][Check code][NACK][P]

[0028] Among them, S, ACK, and P respectively represent the start signal, acknowledgment signal, and stop signal; R represents reading data from the slave, which forms an 8-bit data together with the slave address. The host and the slave are distinguished by the highest bit. The highest bit being 0 indicates the host device, and the highest bit being 1 indicates the slave device; the check code is used to check the slave address and Data 1 to Data L. Data 1 to Data L are the data that the host needs to read, and L is determined by the data volume requirement.

[0029] The beneficial effects of the present invention compared with the prior art are:

[0030] (1), The present invention does not require additional control lines. Only through the hardware architecture of the traditional IIC communication bus and through a reasonable control method, the safe and reliable operation of multiple host devices on the IIC bus can be realized.

[0031] (2), The present invention can flexibly configure multiple host devices and multiple slave devices according to actual needs. Relying on the continuous host and slave address coding, the control system can realize the automatic sequential access of each host device to all slave devices, simplifying the bus scheduling and identification process of multiple devices.

[0032] (3), The control method of the present invention realizes the time-sharing and orderly operation of multiple host devices, avoiding the ineffective waiting of other host devices during the bus occupation period and bus conflicts, improving the working efficiency of the system, and reducing the unexpected risks that may be caused by bus conflicts. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 It is the IIC multi-host system architecture diagram of the embodiment of the present invention;

[0034] Figure 2 It is the functional state transition diagram of Host 1 in the embodiment of the present invention;

[0035] Figure 3 It is the functional state transition diagram of Hosts 2 to N-1 in the embodiment of the present invention;

[0036] Figure 4 This is the functional state transition diagram of host N in the embodiments of the present invention. Detailed implementation manners

[0037] The following will combine the accompanying Figure 1 ~accompanying Figure 4 to elaborate in detail on the technical solutions, structural features, achieved objectives and effects in the embodiments of the present invention.

[0038] It should be noted that in the present invention, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, such that a process, method, article or device including a series of elements includes not only those elements expressly listed, but also other elements not expressly listed, or elements inherent to such process, method, article or device.

[0039] The present invention provides a multi-host system based on the IIC bus. Different from the traditional IIC system architecture with one host and multiple slaves, this system includes multiple devices as host devices to communicate with slaves for data traffic.

[0040] As Figure 1 shown, this system includes M slave devices and N host devices. The host devices and slave devices are all interconnected and communicate through the IIC bus system. Each device has an independent communication address. The N host devices are respectively denoted as host device 1 to host device N. Among them, host device 1 has the IIC cycle timing function for determining the IIC host cycle. In each IIC host cycle, host devices 1 to N are configured as the host mode in turn in a relay manner. The host devices in the host mode communicate with each slave device in turn; both M and N are greater than 1. In a specific embodiment of the present invention, it does not exceed 64.

[0041] All host devices are initially configured as the slave mode. The host devices can be in a mutually backup relationship.

[0042] The host devices of the multi-host system generally include a micro control unit (MCU). The MCU can, according to the task requirements, configure the IIC bus of the device as the host working mode or the slave working mode through software;

[0043] N host devices are configured in host mode in a relay manner. The specific method is as follows: When the first IIC host cycle arrives, host device 1 autonomously sets itself to host mode. After the host device in host mode completes the task of communicating with each slave device, it sends a communication enable instruction to another host via the IIC bus, and then configures itself as a slave mode and exits the control of the IIC bus. The host device that receives the communication enable instruction configures itself as host mode and then sequentially conducts data interaction with each slave device.

[0044] After all host devices have completed communication with each slave device within each IIC cycle, when waiting for the next IIC cycle to arrive, the next cycle of data communication begins.

[0045] The communication enable instruction is as follows:

[0046] [S][Host address][W][ACK][Enable code][ACK][Check code][ACK][P]

[0047] Among them, S, ACK, and P respectively represent the start signal, acknowledgment signal, and stop signal; W is the direction bit, indicating writing data to the slave, and together with the host address, it forms an 8-bit data. The host and slave are distinguished by the highest bit. The highest bit being 0 represents the host device, and the highest bit being 1 represents the slave device, to avoid address conflicts when the host device works in slave mode. The data direction is distinguished by the lowest bit. W means the host writes data to the slave, and R means the host reads data from the slave. Therefore, the remaining 6 bits of data can be used as the address encoding for the host and slave. Combining with the highest bit, the host address range is 0 to 63, and the slave address is 64 to 127. The host and slave addresses should be encoded in ascending order. The enable code is the serial number of the host device to be set as host mode; the check code is used to verify the host address and communication enable code. In a specific embodiment of the present invention, the host address in the communication enable instruction is the shift number of the host currently sending the communication enable instruction, that is, n. The communication enable code can be custom-configured according to requirements. The check code adopts PEC check (Packet Error Check, PEC). PEC check is a check method that improves the reliability of communication data through cyclic redundancy check (CRC) technology. The calculation method of the check code is the CRC8 check value of the host address and communication enable code. After receiving the above communication enable instruction, the slave device compares and verifies the enable code and check code. After successful verification, it configures itself as host mode and then sequentially conducts data interaction with all slave devices.

[0048] [S][Slave address][R][ACK][Data 1][ACK]…[Data L][ACK][Check code][NACK][P]

[0049] Among them, S, ACK, and P represent the start signal, acknowledgment signal, and stop signal respectively; R is the direction bit, indicating reading data from the slave device. Together with the host address, it forms an 8-bit data. The host and the slave are distinguished by the highest bit. The highest bit being 0 represents the host device, and the highest bit being 1 represents the slave device; the check code is used to check the slave address and Data 1 to Data L. Data 1 to Data L are the data that the host needs to read, and L is determined by the data volume requirement.

[0050] In a specific embodiment of the present invention, the slave address range is 64 to 127. The host compares the PEC check code read and the check code obtained by performing CRC8 calculation on the slave address and Data 1 to L. If they are equal, the read data is retained; otherwise, the packet data is discarded.

[0051] The present invention also provides a multi-host control method based on the above IIC bus system. To prevent bus conflicts, the host devices in the system communicate with the slave devices in turn.

[0052] As Figures 2 to 4 shown, the method includes the following steps:

[0053] Step S1: All host devices are initialized and configured as slave mode, and each host device and slave device has a different communication address;

[0054] Step S2: Host device 1 initializes the IIC host cycle period;

[0055] Step S3: When the IIC host cycle period arrives, host device 1 sets itself to host mode and sequentially performs data interaction with slave devices 1 to slave device M; after host device 1 completes communication, it sends a communication enable instruction to host device 2 through the IIC bus, then host device 1 is configured as slave mode, exits the control of the IIC bus, and sets the on-duty serial number n of host device to 2;

[0056] Step S3: After host device n receives the communication enable instruction from host device n - 1, it configures host device n to host mode, then sequentially performs data interaction with slave devices 1 to slave device M. After host device n completes communication, it sends a communication enable instruction to host device n + 1 through the IIC bus, then host device n is configured as slave mode, exits the control of the IIC bus, adjusts the on-duty serial number n of host device to n + 1, and re-executes step S3 until n is N, and enters step S4;

[0057] Step S4: After the host device N receives the communication enable instruction from the host device N-1, it configures the host device N as the host mode, then sequentially performs data interaction with the slave devices 1 to M. After the communication is completed, it directly configures the host device N as the slave mode, exits the control of the IIC bus, and waits for the next IIC host cycle to arrive, and then re-executes step S2 to start the data communication of the next IIC host cycle.

[0058] Preferably, Host 1 has an additional IIC periodic timing communication function, and the timing period is longer than the IIC communication time of all hosts. The remaining hosts have no timing communication function and only receive the communication enable instruction sent by the previous host and execute the IIC communication process.

[0059] In summary, compared with the prior art, the present invention provides a multi-host system and a control method based on the IIC bus, which have the advantages of no need for additional communication lines, high reliability, and arbitrary expandability, and are applicable to aerospace hot backup IIC bus communication systems with high reliability requirements or IIC bus data interaction systems with the working requirements of multiple host devices.

[0060] Although the content of the present invention has been described in detail through the above preferred embodiments, it should be recognized that the above description should not be considered as a limitation of the present invention. After those skilled in the art have read the above content, various modifications and substitutions of the present invention will be obvious. Therefore, the protection scope of the present invention should be defined by the appended claims.

Claims

1. A multi-master system based on the IIC bus, characterized in that It includes M slave devices and N master devices. Both the master devices and the slave devices are interconnected and communicate through the IIC bus system. Each device has an independent communication address. The N master devices are respectively denoted as master device 1 to master device N. Among them, master device 1 has the IIC cycle timing function for determining the IIC master cycle. Within each IIC master cycle, master devices 1 to N are configured as the master mode in turn by relay. The master device in the master mode communicates with each slave device in turn; both M and N are greater than 1.

2. The multi-master system based on the IIC bus according to claim 1, characterized in that, All master devices are initially configured as the slave mode.

3. A multi-master system based on the IIC bus according to claim 1, characterized in that, The master device is a device containing a micro control unit.

4. A multi-master system based on the IIC bus according to claim 1, characterized in that, The specific method for configuring the N master devices as the master mode by relay is as follows: When the first IIC master cycle arrives, master device 1 autonomously sets itself as the master mode. After the master device in the master mode completes the task of communicating with each slave device, it sends a communication enable instruction to another master through the IIC bus, and then configures itself as the slave mode and exits the control of the IIC bus; The master device that receives the communication enable instruction configures itself as the master mode and then conducts data interaction with each slave device in turn.

5. A multi-master system based on the IIC bus according to claim 1, characterized in that, After all master devices complete the communication with each slave device within each IIC cycle, when waiting for the next IIC cycle to arrive, the next cycle of data communication begins.

6. The multi-host system based on the IIC bus according to claim 4, characterized in that, The format of the communication enable instruction is: [S][Host address][W][ACK][Enable code][ACK][Check code][ACK][P] Among them, S, ACK, and P respectively represent the start signal, the acknowledgment signal, and the stop signal; W indicates writing data to the slave, which forms an 8-bit data with the host address. The host and the slave are distinguished by the highest bit. The highest bit being 0 represents the host device, and the highest bit being 1 represents the slave device; The enable code is the serial number of the host device to be configured as the master mode; The check code is used to check the host address and the communication enable code.

7. A multi-master system based on the IIC bus according to claim 4, characterized in that, The data interaction format between the host and the slave is: [S][Slave address][R][ACK][Data 1][ACK]…[Data L][ACK][Check code][NACK][P] Among them, S, ACK, and P respectively represent the start signal, the acknowledgment signal, and the stop signal; R indicates reading data from the slave, which forms an 8-bit data with the slave address. The host and the slave are distinguished by the highest bit. The highest bit being 0 represents the host device, and the highest bit being 1 represents the slave device; The check code is used to check the slave address and Data 1 to Data L. Data 1 to Data L are the data that the host needs to read, and L is determined by the data volume requirement.

8. The multi-master control method of the IIC bus system according to claim 1, characterized in that It includes the following steps: Step S1, all master devices are initialized and configured as the slave mode, and each master device and slave device has a different communication address; Step S2, master device 1 initializes the IIC master cycle; Step S3: When the IIC host cycle arrives, the host device 1 sets itself to the host mode and sequentially performs data interaction with slave devices 1 to slave device M; after the communication of the host device 1 is completed, it sends a communication enable instruction to the host device 2 through the IIC bus, then the host device 1 is configured as the slave mode, exits the control of the IIC bus, and sets the on-duty serial number n of the host device to 2; Step S4: After receiving the communication enable instruction sent by the host device n-1, the host device n configures the host device n as the host mode, then sequentially performs data interaction with slave devices 1 to slave device M. After the communication of the host device n is completed, it sends a communication enable instruction to the host device n+1 through the IIC bus, then the host device n is configured as the slave mode, exits the control of the IIC bus, adjusts the on-duty serial number n of the host device to be updated to n+1, and re-executes Step S3 until n is N, and then enters Step S5; Step S5: After receiving the communication enable instruction of the host device N-1, the host device N configures the host device N as the host mode, then sequentially performs data interaction with slave devices 1 to slave device M. After the communication is completed, the host device N is directly configured as the slave mode, exits the control of the IIC bus, and waits for the next IIC host cycle to arrive, and re-executes Step S2 to start the data communication of the next IIC host cycle.

9. The multi-master control method of the IIC bus system according to claim 8, characterized in that, The format of the communication enable instruction is: [S][Host address][W][ACK][Enable code][ACK][Check code][ACK][P] Wherein, S, ACK, and P respectively represent the start signal, the acknowledgment signal, and the stop signal; W indicates writing data to the slave, which forms an 8-bit data with the host address, and the host and the slave are distinguished by the highest bit. The highest bit being 0 represents the host device, and the highest bit being 1 represents the slave device; the enable code is the serial number of the host device to be set as the host mode; the check code is used to check the host address and the communication enable code.

10. The multi-master control method of the IIC bus system according to claim 8, characterized in that, The data interaction format between the host and the slave is: [S][Slave address][R][ACK][Data 1][ACK]…[Data L][ACK][Check code][NACK][P] Wherein, S, ACK, and P respectively represent the start signal, the acknowledgment signal, and the stop signal; R indicates reading data from the slave, which forms an 8-bit data with the slave address, and the host and the slave are distinguished by the highest bit. The highest bit being 0 represents the host device, and the highest bit being 1 represents the slave device; the check code is used to check the slave address and Data 1 to Data L. Data 1 to Data L are the data that the host needs to read, and L is determined by the data volume requirement.

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