Data transmission system and method

Abstract

The application discloses a data transmission system and method, relates to the technical field of prototype verification of integrated circuits, and comprises the following steps: a monitoring module is added in a first logic programming device, and a delay processing module is added in a second logic programming device; the monitoring module can monitor the time length during which an interrupt signal is later than data in the first logic programming device; and since data is delayed to arrive after being transmitted across the logic programming devices, the delay processing module can monitor the time length during which the interrupt signal is earlier than the data. First interrupt signals are generated by operating time length indication information and delay time length indication information, the original time sequence of the interrupt signals and the data for indicating the completion of a write operation can be restored, and the first interrupt signals can accurately indicate that a storage module has completed a write operation.

Description

Technical Field

[0001] This application relates to the field of prototype verification technology for integrated circuits, and more particularly to data transmission systems and methods. Background Technology

[0002] In the field of integrated circuit prototyping, logic programming devices are typically used for verification, such as Field-Programmable Gate Arrays (FPGAs). Register-Transfer Level (RTL) can be ported to FPGAs to verify the functionality and performance of application-specific integrated circuits. RTL is a hardware description language abstraction level used to describe the design of digital circuits. However, the resources of a single logic programming device may be insufficient; therefore, multiple logic programming devices are needed to verify integrated circuits, distributing the components of the integrated circuit across different logic programming devices.

[0003] Because data transmission between different logic programming devices requires chip-to-chip (C2C) transmission, and interrupt signals between different logic programming devices are generally implemented through general-purpose input / output interfaces, the transmission delay of interrupt signals is shorter than that of data transmission. This causes the target logic programming device (i.e., the data receiver in the two logic programming devices) to receive the interrupt signal indicating the completion of the write operation earlier than the time when the target logic programming device completes the write operation, resulting in the interrupt signal failing to correctly indicate whether the write operation is complete. Summary of the Invention

[0004] This application provides a data transmission system, method, electronic device, storage solution, and program product to address the problem that interrupt signals cannot correctly indicate whether a write operation is complete.

[0005] This application provides a data transmission system, which includes a first logic programming device and a second logic programming device. The first logic programming device includes a monitoring module and a data writing module, and the second logic programming device includes a delay processing module, a storage module, and a central processing unit.

[0006] The write data module is used to initiate and execute write operations to the storage module;

[0007] The monitoring module is used to obtain the operation duration indication information of the write data module performing write operations; and send the operation duration indication information to the delay processing module.

[0008] The delay processing module is used to generate a first interrupt signal based on the operation duration indication information and the delay duration indication information corresponding to the write operation when it receives the operation duration indication information and obtains the delay duration indication information corresponding to the write operation. The first interrupt signal is used to indicate that the write operation has been completed. The module also sends the first interrupt signal to the central processing unit.

[0009] This application also provides a data transmission method applied to a data transmission system, the data transmission system including a first logic programming device and a second logic programming device, wherein the first logic programming device includes a monitoring module and a data writing module, and the second logic programming device includes a delay processing module, a storage module, and a central processing unit; the method includes:

[0010] The write data module initiates and executes a write operation to the storage module.

[0011] The monitoring module obtains the operation duration indication information of the write data module performing the write operation; and sends the operation duration indication information to the delay processing module.

[0012] When the delay processing module receives the operation duration indication information and obtains the delay duration indication information corresponding to the write operation, it generates a first interrupt signal based on the operation duration indication information and the delay duration indication information. The first interrupt signal is used to indicate that the write operation has been completed. The module then sends the first interrupt signal to the central processing unit.

[0013] This application also provides an electronic device, including: a memory for storing a computer program; and a processor for implementing the steps of any of the above-described data transmission methods when executing the computer program.

[0014] This application also provides a computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the steps of any of the above-described data transmission methods.

[0015] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of any of the above-described data transmission methods.

[0016] This application adds a monitoring module to the first logic programming device and a delay processing module to the second logic programming device. The monitoring module can monitor the duration by which the interrupt signal arrives later than the data in the first logic programming device. Furthermore, since the data arrives later than the interrupt signal after being transmitted across logic programming devices (requiring processing by other modules along the way), the delay processing module can monitor the duration by which the interrupt signal arrives earlier than the data. By generating a first interrupt signal using operation duration indication information and delay duration indication information, the original timing of the interrupt signal and data used to indicate the completion of the write operation can be restored, meaning the first interrupt signal can accurately indicate that the memory module has completed the write operation. Attached Figure Description

[0017] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This application provides a schematic diagram of the architecture of a data transmission system according to an embodiment of the present application.

[0019] Figure 2 This is a schematic diagram of the architecture of another data transmission system provided in an embodiment of this application;

[0020] Figure 3 This is a schematic diagram of the architecture of another data transmission system provided in an embodiment of this application;

[0021] Figure 4 This is a schematic diagram of the architecture of another data transmission system provided in an embodiment of this application;

[0022] Figure 5 A schematic diagram illustrating the processing of interrupt signals via a shift register, provided as an embodiment of this application;

[0023] Figure 6 This is a schematic diagram of the architecture of another data transmission system provided in an embodiment of this application;

[0024] Figure 7 This is a schematic diagram of the architecture of another data transmission system provided in an embodiment of this application;

[0025] Figure 8 This is a schematic diagram of the architecture of another data transmission system provided in an embodiment of this application;

[0026] Figure 9 This is a schematic diagram of the architecture of another data transmission system provided in an embodiment of this application;

[0027] Figure 10 A flowchart illustrating a data transmission method provided in an embodiment of this application;

[0028] Figure 11 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0029] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0030] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0031] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0032] This application provides a data transmission system, such as Figure 1 As shown, the data transmission system includes a first logic programming device 10 and a second logic programming device 20.

[0033] The first logic programming device 100 may include a data writing module 101 and a monitoring module 102. The second logic programming device 20 includes a delay processing module 201, a central processing unit (CPU) 202, and a storage module 203. The monitoring module 102 can be connected to the data writing module 101 and the delay processing module 201. The data writing module 101 can be connected to the storage module 203. The delay processing module 201 can be connected to both the CPU 202 and the data writing module 101. The CPU 202 can be connected to the storage module 203. Both the first logic programming device 100 and the second logic programming device 200 can be field-programmable gate arrays (FPGAs). The storage module 203 can be a storage device and a storage controller; for example, the storage controller can be a double data rate (DDR) controller. The data writing module 101 can be a universal serial bus (USB). The connections between the various modules included in the second logic programming device 20 can be implemented via a bus, which can be an Advanced eXtensible Interface Interconnect (AXI) bus, and the architecture of the central processing unit 202 can be an Advanced Reduced Instruction Set Computer (ARM) architecture.

[0034] The write data module 101 can be used to initiate and execute write operations to the storage module 203. The monitoring module 102 can be used to obtain the operation duration indication information of the write operation performed by the write data module 101. The operation duration indication information is sent to the delay processing module 201. When the operation duration indication information is received and the delay duration indication information corresponding to the transmission write operation is obtained, a first interrupt signal (InterruptRequest, IRQ) is generated according to the operation duration indication information and the delay duration indication information, wherein the first interrupt signal is used to indicate that the write operation has been completed. The first interrupt signal is sent to the central processing unit 202.

[0035] The interrupt signal can exist in two states: a high-level state, used to indicate the occurrence of a special event (e.g., write operation completed), and a low-level state, used to indicate that no processing is required. The first interrupt signal can be used to indicate that the write operation has been completed, i.e., the interrupt signal in the high-level state. The operation duration indication information can be used to indicate the interval between the start of the write operation by the write data module 101 and the issuance of the interrupt signal. The delay duration indication information can be used to indicate the interval between the detection of the interrupt signal by the delay processing module 201 and the arrival of the first data corresponding to the write operation in the storage module 203.

[0036] Specifically, when the write data module 101 completes its configuration operation, it can initiate and execute a write operation to the storage module 203. The monitoring module 102 can monitor the write data module 101 and obtain the operation duration indication information for its write operation. To avoid the problem of asynchronous data transmission between the interrupt signal and the write operation, the monitoring module 102 can send the operation duration indication information to the delay processing module 201 of the second logic programming device 20, so that the delay processing module 201 can understand the synchronization information between the interrupt signal and the first data.

[0037] Furthermore, considering the delay in the transmission of write data signals, the delay processing module 201 can also acquire the delay duration indication information of the write operation. Then, when the delay processing module 201 acquires the delay duration indication information and receives the operation duration indication information transmitted by the monitoring module 102, it generates a first interrupt signal based on the delay duration indication information and the operation duration indication information, and sends it to the central processing unit 202. In this way, the central processing unit 202 receives the first interrupt signal only after the first data write operation is completed.

[0038] The data transmission system of this application adds a monitoring module 102 to the first logic programming device 10 and a delay processing module 201 to the second logic programming device 20. The monitoring module 102 can monitor the duration by which the interrupt signal arrives later than the data in the first logic programming device 10. Furthermore, since the data arrives later than the interrupt signal after being transmitted across programming devices (requiring processing by other modules along the way), the delay processing module 201 can monitor the duration by which the interrupt signal arrives earlier than the data. By generating a first interrupt signal using operation duration indication information and delay duration indication information, the original timing and interval of the interrupt signal and data used to indicate the completion of the write operation in the first logic programming device 10 (i.e., the timing on the first logic programming device side) can be restored. This means that the first interrupt signal can accurately indicate that the storage module 203 has completed the data write operation.

[0039] First, the step of the monitoring module 102 obtaining the operation duration indication information in the above process can include the following two methods:

[0040] Method 1, such as Figure 2 As shown, the monitoring module 102 may include a first timer 102a (Counter, CNT). Accordingly, when the monitoring module 102 detects that the write data module 101 sends a write data enable signal, it starts the first timer 102a to perform a timing operation. When the write data module 101 sends a second interrupt signal, it stops the first timer 102a to stop the timing operation. First timing information is extracted from the first timer 102a as operation duration indication information.

[0041] The second interrupt signal is issued by the write data module 101 when the write operation ends, and the level of the second interrupt signal is high. The first timing information can be the timing duration or the number of clock cycles.

[0042] Specifically, when the monitoring module 102 detects that the write data module 101 is transmitting a write data enable signal, it indicates that the write data module 101 has initiated a write operation to the storage module 203 and started transmitting data. At this time, the monitoring module 102 can start the first timer 102a to begin timing. After all the data has been transmitted, the write data module 101 sends a write data invalid signal and a second interrupt signal. In this way, the monitoring module 102 can monitor the second interrupt signal transmitted by the write data module 101. At this time, the monitoring module 102 ends the timing operation of the first timer 102a and extracts the first timing information from the first timer 102a as the operation duration indication information. Executing the timing operation through a timer is more accurate and more suitable for schemes with high requirements for signal timing.

[0043] Method 2: The monitoring module 102 records the first moment when it detects the write data module 101 issuing a write data enable signal, and the second moment when it detects the write data module 101 issuing a second interrupt signal. Based on the first and second moments, the operation duration indication information is determined.

[0044] Specifically, when the monitoring module 102 detects that the write data module 101 issues a write data enable signal, it can record the first moment when the write data enable signal is issued. Similarly, when the monitoring module 102 detects that the write data module 101 issues a second interrupt signal, it can record the second moment when the second interrupt signal is issued. Finally, operation duration indication information can be determined based on the first and second moments. For example, the difference between the second and first moments can be determined as the first delay duration. This first delay duration is then used as the operation duration indication information. By recording the moments, hardware resources can be saved.

[0045] Second, in the above process, the step of the delay processing module 201 obtaining the delay duration indication information can include the following two methods:

[0046] Method 1, such as Figure 3 As shown, the delay processing module 201 may include a second timer 201a. Accordingly, when a second interrupt signal is received from the write data module 101, the second timer 201a is started to begin timing. When the first data corresponding to the write operation is detected to have arrived at the storage module 203, the second timer 201a is stopped. Second timing information is extracted from the second timer 201a as delay duration indication information.

[0047] The second timing information can be the timing duration or the number of clock cycles.

[0048] Specifically, when the delay processing module 201 receives the second interrupt signal transmitted by the write data module 101, it can start the second timer 201a to begin timing. When it detects that the first data corresponding to the write operation has arrived at the storage module 203, it can turn off the second timer 201a to stop timing. Then, it can extract the second timing information from the second timer 201a as the delay duration indication information. Executing the timing operation through a timer is more accurate and more suitable for solutions with high requirements for signal timing.

[0049] Method 2: The delay processing module 201 records the third moment when the second interrupt signal is detected, and the fourth moment when the first data corresponding to the write operation arrives at the storage module 203. Based on the third and fourth moments, delay duration indication information is determined.

[0050] Specifically, when the delay processing module 201 receives the second interrupt signal, it can record the third moment when the second interrupt signal is received. When the first data corresponding to the write operation is detected to have arrived at the storage module 203, it can record the fourth moment when the first data corresponding to the write operation arrives at the storage module 203. Finally, the operation duration indication information can be determined based on the fourth moment and the third moment. For example, the difference between the fourth moment and the third moment can be determined as the second delay duration. The second delay duration is used as the delay duration indication information. By recording the times, hardware resources can be saved.

[0051] Third, in the above process, generating the first interrupt signal based on the operation duration indication information and the delay duration indication information may specifically include:

[0052] Step 1: Determine the total delay indication information based on the operation duration indication information and the delay duration indication information.

[0053] Step 2: Based on the total delay indication information, obtain the target interrupt indication information corresponding to the total delay indication information.

[0054] Step 3: Generate an interrupt signal corresponding to the target interrupt indication information based on the target interrupt indication information.

[0055] Among them, the interrupt signal corresponding to the target interrupt indication information is the first interrupt signal.

[0056] Specifically, when both the operation duration indication information and the delay duration indication information are the number of clock cycles, the delay processing module 201 can determine the sum of the operation duration indication information and the delay duration indication information as the target bit identifier information, which is the total delay indication information. Alternatively, when both the operation duration indication information and the delay duration indication information are the timing duration, the sum of the operation duration indication information and the delay duration indication information can be calculated first, and then the ratio of this sum to the length of the clock cycle can be determined as the target bit identifier information. Further, the delay processing module 201 can determine the storage location corresponding to the target bit identifier information from multiple preset storage locations based on the target bit identifier information, extract the target interrupt indication information from it, and then generate the corresponding interrupt signal based on this target interrupt indication information.

[0057] In some alternative implementations, the delay processing module 201 described above can also be used to perform a delay operation on the interrupt signal of each clock cycle transmitted by the write data module 101.

[0058] The delay processing module 201 may include multiple storage units (which may be the storage locations described above), and these storage units may be arranged in a preset order. The storage units may be flip-flops in the shift register 201b; for example, the shift register 201b may be a 64-bit register. Correspondingly, the data transmission system may be as follows: Figure 4 As shown.

[0059] Specifically, the steps for the delay processing module 201 to perform the delay operation may include:

[0060] Step 1: In the current clock cycle, identify the first state information of the interrupt signal received in the current clock cycle.

[0061] The clock cycle can be the clock cycle of the data bus domain.

[0062] Step two: Based on the order of each storage unit, perform a shift operation on the state information stored in each storage unit in turn.

[0063] Step 3: After completing the shift operation of each storage unit, store the first state information into the initial storage unit.

[0064] The initial storage unit is the storage unit that is ranked first among multiple storage units.

[0065] Specifically, since the interrupt signal transmitted from the write data module 101 to the delay processing module 201 is uninterrupted, in order to send the interrupt signal indicating that the write operation has been completed to the central processing unit 202 after the storage module 203 has completed the write operation, the delay processing module 201 can also perform a delay operation on the interrupt signal of each clock cycle transmitted by the write data module 101.

[0066] Taking the flip-flops in shift register 201b as an example, in each clock cycle, the delay processing module 201 can identify and store the status information of the interrupt signal received in that clock cycle. Since the number of storage units in shift register 201b is limited, the status information stored in the last sorted storage unit can be shifted out. For storage units that are not the last sorted unit (taking the first storage unit as an example), the status information stored in the first storage unit can be shifted to the second storage unit after the first storage unit, and the status information stored in the third storage unit before the first storage unit can be shifted to the first storage unit, and so on, completing the shifting operation of the status information stored in each storage unit. In this way, the initial storage unit, which is sorted first, can be emptied, and the first status information of the current clock cycle can be written into the first storage unit.

[0067] Under this mechanism, the delay processing module 201 can record the status information of the second interrupt signal issued by the write data module 101 when it completes the write operation into a certain memory cell of the shift register 201b. By sequentially transmitting the status information of the interrupt signal between different flip-flops in the shift register, the signal delay time can be controlled very precisely according to the required number of clock cycles. This is particularly important for application scenarios requiring precise synchronization under this scheme.

[0068] like Figure 5As shown, at time 0, memory cell 0 stores the status information (IRQ0) of the interrupt signal detected at time 0. At time 1, the status information of the interrupt signal detected at time 0 is shifted to memory cell 1, and the status information (IRQ1) of the interrupt signal detected at time 1 is recorded in memory cell 0. At time 2, the status information of the interrupt signal detected at time 0 is shifted to memory cell 2, the status information of the interrupt signal detected at time 1 is shifted to memory cell 1, and the status information (IRQ2) of the interrupt signal detected at time 2 is recorded in memory cell 0. At time 3, the status information of the interrupt signal detected at time 0 is shifted to memory cell 3, the status information of the interrupt signal detected at time 1 is shifted to memory cell 2, the status information of the interrupt signal detected at time 2 is shifted to memory cell 1, and the status information (IRQ3) of the interrupt signal detected at time 3 is shifted to memory cell 0.

[0069] Under the aforementioned shifting mechanism, when the delay processing module 201 determines the target bit identifier information, it can determine the target storage unit corresponding to the target bit identifier information from multiple storage units based on the target bit identifier information, and extract the second state information from the target storage unit as the target interrupt indication information.

[0070] For example, when the target bit identifier information is 15, the memory cell numbered 15 in the shift register 201b can be identified, and the status information of the first interrupt signal can be extracted from it. The memory cell numbered 15 is... Figure 5 The middle one is the storage unit with the identification information 14.

[0071] In the first logic programming device 10, the second interrupt signal is recorded as arriving 10 clock cycles later than the write data enable signal. Due to the data transmission delay, in the second logic programming device 20, the second interrupt signal arrives 5 clock cycles earlier than the data. Therefore, in order for the second interrupt signal to also arrive 10 clock cycles later than the write data enable signal in the second logic programming device 20 before being transmitted to the central processing unit 202, the received second interrupt signal needs to be delayed by 10 + 5 = 15 clock cycles (i.e., the target bit identifier information is determined to be 15). Correspondingly, the status information indicating the completion of the write operation can be read from the memory cell (i.e., memory cell 14) in the shift register 201b, generating the corresponding interrupt signal (i.e., the first interrupt signal), and then transmitted to the central processing unit 202.

[0072] In the data transmission system of this application embodiment, the interrupt signal used by the first logic programming device 10 to indicate that the write operation is completed arrives later than the write data enable signal. In the second logic programming device 20, the first interrupt signal arrives earlier than the time when the storage module 203 completes the write operation. Therefore, the second logic programming device 20 can use a shift register 201b to record the historical information of the interrupt signal. When it is determined that the storage module 203 has completed the write operation, the status information of the first interrupt signal can be obtained from the historical information, and a second interrupt signal can be issued based on this status information. This can ensure that the interrupt signal used to indicate that the write operation is completed is transmitted to the central processing unit 202 after the data is completely written, so that the central processing unit 202 can obtain accurate write data completion information.

[0073] In some alternative implementations, when the storage module 203 is a storage controller, the data transmission system may further include a memory 30, which may be a DDR memory connected to the storage module 203, such as... Figure 6 As shown, correspondingly, the central processing unit 202 can send a target read request to the storage module 203 when it receives a first interrupt signal. The storage module 203, upon receiving the target read request, can read second data corresponding to the target read request from the memory 30 based on the target read request, and feed the second data back to the central processing unit 202. In this way, the central processing unit 202 can read accurate data from the memory 30 by restoring the timing of the first interrupt signal. Furthermore, this can improve the accuracy of prototype verification for dual-logic programming devices.

[0074] In some optional implementations, the first logic programming device 10 may include a first general-purpose input / output (GPIO) interface, the second logic programming device 20 may include a second GPIO interface, the monitoring module 102 may be connected to the first GPIO interface, the first GPIO interface may be connected to the second GPIO interface, and the second GPIO interface may be connected to the delay processing module 201. Accordingly, the connection channel between the monitoring module 102, the first GPIO interface, the second GPIO interface, and the delay processing module 201 constitutes a target communication link. Specifically, the monitoring module 102 may be used to send operation duration indication information to the delay processing module 201 through the target communication link. This allows for faster transmission of operation duration indication information via the GPIO interface.

[0075] The advantages of the data transmission system provided in this application are illustrated below with a specific example.

[0076] like Figure 7The data transmission system shown includes DDR memory and an FPGA. The FPGA includes a DDR controller, a USB module, an ARM-based CPU 202, and an AXI interconnect bus. That is, when the hardware resources of a single FPGA are sufficient, the ARM CPU and USB module are all housed within a single FPGA. During operation, the ARM CPU and USB module can transfer write data via the FPGA's internal AXI interconnect bus.

[0077] exist Figure 7 In the illustrated architecture, the ARM CPU can configure the USB module via the AXI interconnect bus. After configuration, the USB module can send data to the DDR controller via the AXI interconnect bus, and the DDR controller can store the received data into the DDR memory. When the USB module completes a write operation, it sends an interrupt signal high to the ARM CPU to inform it that the write operation is complete. The high-level interrupt signal can be a 1-bit indication. Upon detecting the high-level interrupt signal, the ARM CPU can access the DDR controller via the AXI interconnect bus, and the DDR controller reads the corresponding data from the DDR memory, thus obtaining the data written to the DDR memory by the USB module.

[0078] When the resources of a single FPGA are insufficient, for example when performing large-scale System-on-Chip (SoC) prototyping, the SoC prototype design can be partitioned, such as... Figure 8 As shown, the USB module is placed on FPGA1 and the ARM architecture CPU is placed on FPGA0. The ARM architecture CPU and the USB module need to transmit data through chip-to-chip (C2C).

[0079] In this architecture, the ARM architecture CPU can transmit configuration information for the USB module to the C2C of FPGA0 via the bus. The C2C of FPGA0 then transmits the configuration information to the C2C of FPGA1. Furthermore, the C2C of FPGA1 can perform configuration operations on the USB module based on the received configuration information. After completing the configuration operation, the USB module initiates and performs a write operation to the DDR controller through its internal Direct Memory Access (DMA) function. Specifically, the write data is transferred to the C2C of FPGA1, which then transfers it to the C2C of FPGA0. The C2C of FPGA0 then transmits the write data to the DDR controller via the AXI interconnect bus, and the DDR controller writes the write data into the DDR memory. After the USB module completes the write operation, it sends an interrupt signal to the ARM architecture CPU through the general purpose input / output interface to indicate that the write operation is complete. Upon detecting this interrupt signal, the ARM architecture CPU can send a target read request to the DDR controller via the AXI interconnect bus, so that the DDR controller can read the data corresponding to the target read request from the DDR memory, such as the write data transferred in by the USB module.

[0080] However, during the process of the USB module writing data to the DDR memory, two C2C mechanisms (i.e., the C2C of FPGA0 and the C2C of FPGA1) are involved, as well as the communication path between the two FPGAs. Therefore, there is a significant delay in the entire process from the USB module sending write data to the DDR controller writing the data. The interrupt signal, on the other hand, is directly transmitted to the ARM architecture CPU through the general-purpose input / output interface, so the delay of the interrupt signal is much smaller than the write data delay. Therefore, when the write data delay is significant, after the ARM architecture CPU responds to the interrupt signal indicating the completion of the write operation and reads data from the DDR memory, the write data transmitted by the USB module has not yet been fully written to the DDR memory, resulting in the ARM architecture CPU being unable to read the accurate data.

[0081] To solve the problems caused by dividing integrated circuit modules into different logic programming devices, the following methods can be adopted: Figure 9 The data transmission system shown. Figure 9 China still maintains Figure 8The integrated circuit is modularly partitioned and laid out. Based on this, cnt1 (i.e., the aforementioned monitoring module 102) is set in FPGA1, and cnt0 (i.e., the aforementioned delay processing module 201) is set in FPGA0. cnt1 is used to calculate the number of clock cycles taken from the USB module on FPGA1 sending write data to DDR memory to the interrupt signal going high. Furthermore, cnt1 operates in the data bus clock domain. The number of clock cycles recorded in cnt1 is transmitted to FPGA0 through the general purpose input / output interface. FPGA0 is equipped with a 64-bit shift register 201b, which shifts the interrupt signal from FPGA1 high. Shift register 201b also operates in the data bus clock domain. On the FPGA0 side, the high-time of the interrupt signal and the arrival time of the data are detected, and the number of clock cycles that the interrupt signal arrives before the data signal is calculated using cnt0. Since shift register 201b has already delayed the early high interrupt signal, the corresponding bit (i.e., the aforementioned storage unit) can be determined in shift register 201b based on the number of clock cycles recorded in cnt1 and cnt0, and a high interrupt signal can be generated based on this and sent to the ARM architecture CPU, that is, the high interrupt signal is delayed and transmitted to the ARM architecture CPU.

[0082] The above comparison shows that by recording the number of clock cycles in cnt0 and cnt1 respectively, the interval and timing between the high interrupt signal and the data can be accurately recovered. This ensures that the high interrupt signal is sent to the ARM architecture CPU only after the data is written to the DDR memory. In other words, the high interrupt signal can accurately indicate that the data has been written, thus enabling the CPU to read the accurate data from the DDR memory.

[0083] Embodiments of this application provide a data transmission method that can be applied to the data transmission system described above, such as... Figure 10 As shown, the specific processing steps of the data transmission method may include:

[0084] Step S1001: The write data module initiates and executes a write operation to the storage module.

[0085] Step S1002: The monitoring module obtains the operation duration indication information of the write data module performing the write operation.

[0086] In step S1003, the monitoring module sends the operation duration indication information to the delay processing module.

[0087] In step S1004, when the delay processing module receives the operation duration indication information and obtains the delay duration indication information corresponding to the write operation, it generates a first interrupt signal based on the operation duration indication information and the delay duration indication information.

[0088] The first interrupt signal is used to indicate that the write operation has been completed.

[0089] In step S1005, the delay processing module sends a first interrupt signal to the central processing unit.

[0090] The specific processing of steps S1001 to S1005 can be referred to the above description of the data transmission system, and will not be repeated here.

[0091] The data transmission method of this application adds a monitoring module to the first logic programming device and a delay processing module to the second logic programming device. The monitoring module can monitor the duration by which the interrupt signal arrives later than the data in the first logic programming device. Furthermore, since the data arrives later than the interrupt signal after being transmitted across programming devices (requiring processing by other modules along the way), the delay processing module can obtain the duration by which the interrupt signal arrives earlier than the data. By generating a first interrupt signal using operation duration indication information and delay duration indication information, the timing of the interrupt signal indicating the completion of the write operation and the data on the first logic programming device side can be restored. That is, the first interrupt signal can accurately indicate that the storage module has completed the data write operation.

[0092] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.

[0093] Embodiments of this application also provide an electronic device, such as... Figure 11 As shown, the device includes a memory 110 and a processor 120. The memory 110 stores a computer program, and the processor 120 is configured to run the computer program to perform the steps in any of the above-described data transmission method embodiments. The electronic device may be either the first logic programming device or the second logic programming device described above.

[0094] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above-described data transmission method embodiments when it is run.

[0095] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0096] Embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the above-described data transmission method embodiments.

[0097] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in any of the above-described data transmission method embodiments.

[0098] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0099] The data transmission system and method provided in this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only for the purpose of helping to understand the method and its core ideas. It should be noted that those skilled in the art can make several improvements and modifications to this application without departing from the principles of this application, and these improvements and modifications also fall within the protection scope of this application.

Claims

1. A data transmission system, characterized by The data transmission system includes a first logic programming device and a second logic programming device, wherein the first logic programming device includes a monitoring module and a data writing module, and the second logic programming device includes a delay processing module, a storage module, and a central processing unit. The write data module is used to initiate and execute write operations to the storage module; The monitoring module is used to obtain the operation duration indication information of the write data module performing the write operation; and send the operation duration indication information to the delay processing module. The delay processing module is configured to, when receiving the operation duration indication information and obtaining the delay duration indication information corresponding to the transmission of the write operation, determine total delay indication information based on the operation duration indication information and the delay duration indication information; obtain target interrupt indication information corresponding to the total delay indication information based on the total delay indication information; generate an interrupt signal corresponding to the target interrupt indication information based on the target interrupt indication information, wherein the interrupt signal corresponding to the target interrupt indication information is a first interrupt signal, the first interrupt signal being used to indicate that the write operation has been completed; and send the first interrupt signal to the central processing unit.

2. The data transmission system of claim 1, wherein, The monitoring module includes a first timer; the monitoring module is specifically used for: When the write data enable signal is detected from the write data module, the first timer is started to perform a timing operation. When the write data module sends a second interrupt signal, the first timer is turned off to stop the timing operation. The first timing information is extracted from the first timer and used as the operation duration indication information.

3. The data transmission system of claim 2, wherein, The delay processing module includes a second timer, and the delay processing module is specifically used for: When the second interrupt signal sent by the write data module is received, the second timer is started to keep track of the time. When the first data corresponding to the write operation is detected to have arrived at the storage module, the second timer is turned off and stopped counting. The second timing information is extracted from the second timer as the delay duration indication information.

4. The data transmission system of claim 1, wherein, The monitoring module is specifically used for: Record the first moment when the write data enable signal issued by the write data module is detected; And, record the second moment when the second interrupt signal is detected by the write data module; The operation duration indication information is determined based on the first time and the second time.

5. The data transmission system of claim 4, wherein, The monitoring module is specifically used for: The difference between the second time point and the first time point is determined as the first delay duration. The first delay duration is used as the operation duration indication information.

6. The data transmission system of claim 4, wherein, The delay processing module is specifically used for: Record the third moment at which the second interrupt signal is detected; And, record the fourth moment when the first data corresponding to the write operation arrives at the storage module; The delay duration indication information is determined based on the third time point and the fourth time point.

7. The data transmission system of claim 6, wherein, The delay processing module is specifically used for: The difference between the fourth time point and the third time point is determined as the second delay duration. The second delay duration is determined as the delay duration indication information.

8. The data transmission system according to any one of claims 1 to 7, characterized in that, The operation duration indication information and the delay duration indication information are both the number of clock cycles, and the total delay indication information is the target bit identification information; the delay processing module is specifically used for: The sum of the operation duration indication information and the delay duration indication information is determined as the target bit identification information.

9. The data transmission system of claim 8, wherein, The delay processing module is also used to perform a delay operation on the interrupt signal of each clock cycle transmitted by the write data module.

10. The data transmission system of claim 9, wherein, The delay processing module further includes multiple storage units, which are arranged in a preset order; the delay processing module is specifically used for: In the current clock cycle, identify the first state information of the interrupt signal received in the current clock cycle; Furthermore, according to the order of each of the storage units, the state information stored in each of the storage units is shifted sequentially; After the shift operation of each of the storage units is completed, the first state information is stored in the initial storage unit, wherein the initial storage unit is the storage unit that is ordered first among the plurality of storage units.

11. The data transmission system of claim 10, wherein, The delay processing module is specifically used for: Based on the target bit identification information, a target storage unit corresponding to the target bit identification information is determined from among the plurality of storage units; The second status information is extracted from the target storage unit as the target interrupt indication information.

12. The data transmission system of any one of claims 1 to 7, wherein, When the storage module is a storage controller, the data transmission system further includes a memory, and the storage controller is connected to the memory; the central processing unit is further configured to: When the first interrupt signal sent by the delay processing module is received, a target read request is sent to the storage module; The storage module is configured to, upon receiving the target read request, read second data corresponding to the target read request from the memory based on the target read request, and feed the second data back to the central processing unit.

13. The data transmission system of any one of claims 1 to 7, wherein, The first logic programming device includes a first general-purpose input / output interface, and the second logic programming device includes a second general-purpose input / output interface. The monitoring module is connected to the first general-purpose input / output interface, the first general-purpose input / output interface is connected to the second general-purpose input / output interface, and the second general-purpose input / output interface is connected to the delay processing module. The connection channel between the monitoring module, the first general-purpose input / output interface, the second general-purpose input / output interface, and the delay processing module constitutes a target communication link. The monitoring module is specifically used for: The operation duration indication information is sent to the delay processing module through the target communication link.

14. A method for initiating an interrupt signal, characterized in that, The method is applied to the data transmission system as described in any one of claims 1 to 13, the data transmission system comprising a first logic programming device and a second logic programming device, wherein the first logic programming device includes a monitoring module and a data writing module, and the second logic programming device includes a delay processing module, a storage module, and a central processing unit; The method includes: The write data module initiates and executes a write operation to the storage module; The monitoring module obtains the operation duration indication information of the write data module executing the write operation; and sends the operation duration indication information to the delay processing module; When the delay processing module receives the operation duration indication information and obtains the delay duration indication information corresponding to the write operation, it determines the total delay indication information based on the operation duration indication information and the delay duration indication information; it obtains the target interrupt indication information corresponding to the total delay indication information based on the total delay indication information; it generates an interrupt signal corresponding to the target interrupt indication information based on the target interrupt indication information, wherein the interrupt signal corresponding to the target interrupt indication information is a first interrupt signal, which is used to indicate that the write operation has been completed; and it sends the first interrupt signal to the central processing unit.

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