Photoelectric sensing signal processing and information fusion calculation system and method

Abstract

The invention discloses a photoelectric sensing signal processing and information fusion computing system and method. The system comprises a CPU unit, an FPGA unit capable of achieving multi-source data fusion, a clock unit, a power supply unit and an interface unit. The CPU unit comprises a first processor and a second processor responsible for communication tasks, the first processor is responsible for management tasks and algorithm tasks, and the second processor can support single-precision and double-precision floating point operation instructions and vector processing instructions; the FPGA unit is connected with the CPU unit through an LBC interface, and the FPGA unit is externally connected with an SPI Flash and a BPI Flash which are used for storing FPGA program codes. The interface unit comprises an A path RS422 communication interface, a B path RS422 synchronization pulse interface, an SRIO interface, an RS232 interface and an SRIO 4 * interface. Wherein A and B are positive integers greater than 1. The invention provides the photoelectric sensing signal processing and information fusion calculation system and method with high reliability, low power consumption and high fusion calculation.

Description

Technical Field

[0001] The present invention relates to the field of optoelectronic technologies, and particularly to an optoelectronic sensing signal processing and information fusion calculation system and method. Background Art

[0002] With the development of information technology, optoelectronic sensing signal processing and information fusion technologies are required in fields such as aviation, aerospace, environmental monitoring, intelligent transportation systems, and medical health monitoring to process and analyze the collected data using information fusion and signal processing technologies to provide more accurate and reliable information. However, existing optoelectronic sensing signal processing and information fusion calculation systems and their methods often have insufficient anti-interference ability in complex environments, limited dynamic range, low multi-module cooperation efficiency, poor real-time performance, and limitations in system stability and reliability technologies. For example, when facing the communication requirements of multiple peripherals simultaneously, the data transmission delay is relatively large, resulting in slow system response. Or when directly fusing raw data during data fusion, a large amount of computational resources are consumed, thus affecting system performance. Summary of the Invention

[0003] The purpose of the present invention is to propose an optoelectronic sensing signal processing and information fusion calculation system and method with high reliability and low power consumption for highly integrated calculation.

[0004] The present invention provides an optoelectronic sensing signal processing and information fusion calculation system, including a CPU unit, an FPGA unit capable of realizing multi-source data fusion, a clock unit, a power supply unit, and an interface unit; The CPU unit includes a first processor and a second processor responsible for communication tasks. The first processor is responsible for management tasks and algorithm tasks, and the second processor can support single-precision and double-precision floating-point operation instructions and vector processing instructions; The FPGA unit is connected to the CPU unit through an LBC interface, and the FPGA unit is externally connected to an SPI Flash and a BPI Flash for storing FPGA program codes; The interface unit includes an A-channel RS422 communication interface, a B-channel RS422 synchronization pulse interface, an SRIO interface, an RS232 interface, and an SRIO 4× interface for realizing fault switching through link redundancy design; where both A and B are positive integers greater than 1; The CPU unit is also provided with a 1553B card. The 1553B card is connected to the CPU unit through a PCIE interface, and the CPU unit communicates with the outside through a VPX connector; the CPU unit is also connected to 4 DDR memories and 1 Ethernet PHY chip through a multi-channel DDR interface and an RGMII interface respectively.

[0005] Further, the optoelectronic sensing signal processing and information fusion computing system of the present invention electrically isolates the communication signals of each module in the optoelectronic sensing signal processing and information fusion computing system through a transformer isolation circuit; The FPGA unit is also connected to the VXP connector through an isolated CAN driver to achieve double isolation of signals and power supply.

[0006] Further, the SRIO 4× interface of the optoelectronic sensing signal processing and information fusion computing system of the present invention supports a rate of 2.5 Gbps, and uses differential pair traces with an impedance of 100Ω ± 5%; the SRIO 4× interface includes a SerDes circuit, and the SerDes circuit is independently powered by a low-noise LDO and tantalum capacitor filtering; and integrates a CRC check and end-to-end retransmission mechanism through a protocol stack, the retransmission counter threshold is set to 3 times, and the timeout threshold is 1 ms.

[0007] Further, the power supply unit of the optoelectronic sensing signal processing and information fusion computing system of the present invention supplies power to the CPU unit, FPGA unit, clock unit, and interface unit through a VPX connector; the VPX connector is also connected to a fan, an aircraft mission system, sensors, an RS422 communication interface, and an RS422 synchronization pulse interface.

[0008] Further, the BPI Flash of the optoelectronic sensing signal processing and information fusion computing system of the present invention is directly connected to the address and data buses of the CPU unit through a 16-bit parallel bus.

[0009] Further, the clock unit of the optoelectronic sensing signal processing and information fusion computing system of the present invention provides a reference clock signal for the phase-locked loop by a 50 MHz crystal oscillator, and then provides a reference clock signal for the CPU unit, FPGA unit, and DDR memory through the phase-locked loop.

[0010] Further, the power supply in the power supply unit of the optoelectronic sensing signal processing and information fusion computing system of the present invention is transmitted to the overcurrent and overvoltage protector through the VPX connector, and then transmitted to the switching power supply and low-dropout linear regulator to be converted into the required voltage for power supply.

[0011] Further, the CPU unit and the FPGA unit in the optoelectronic sensing signal processing and information fusion computing system of the present invention also realize joint debugging of the CPU unit and the FPGA unit through a JTAG interface.

[0012] Further, the CPU unit of the optoelectronic sensing signal processing and information fusion computing system of the present invention runs a domestic Dao partition operating system and the Vxworks operating system; The multi-source data fusion process implemented by the FPGA unit includes the pose data of the synchronous satellite antenna, the primary inertial navigation, and the backup inertial navigation, generates high-precision attitude information through coordinate transformation and error compensation, aligns the I²C data of the temperature and humidity, air pressure, and vibration sensors, and transmits it to the CPU unit through the LBC interface; The multi-source data fusion process specifically includes: 1) Time synchronization: Taking the flight control synchronization pulse as the highest priority, generating a synchronization signal through the PLL inside the FPGA unit, and the time synchronization error ≤ 100 ns; 2) Redundancy switching: When the primary inertial navigation data is abnormal, enabling the backup inertial navigation data stream within 10 ms through the hardware switching logic; 3) Coordinate unification: Converting the longitude and latitude information of the Beidou satellite into the local coordinate system of the inertial navigation, and storing the conversion matrix in the Block RAM of the FPGA unit.

[0013] On the other hand, the present invention also provides an optoelectronic sensing signal processing and information fusion calculation method based on the optoelectronic sensing signal processing and information fusion calculation system described in any one of the above, and the method specifically includes the following steps: S1: Receiving the flight control synchronization signal through the RS422 synchronization pulse interface, and generating a global time reference by the FPGA unit, with the time synchronization error ≤ 100 ns; S2: Collecting the pose data of the satellite antenna, the primary inertial navigation, and the backup inertial navigation through the A-channel RS422 interface, and performing timestamp alignment and coordinate transformation by the FPGA unit; S3: The sensor transmits the collected data to the FPGA unit through the IIC interface, and the FPGA unit analyzes according to the interface protocol, performs multiple checks on the transmitted data, and transmits it to the CPU through the LBC interface after the check is correct; the sensors include a temperature sensor, a humidity sensor, an air pressure sensor, and a vibration sensor; S4: The CPU unit accelerates the floating-point operation through the NEON instruction set, performs the Kalman filter algorithm on the preprocessed data, and compensates for the inertial navigation zero drift, with the scale factor ≤ 0.1%; S5: Outputting the fusion result to the external device through the SRIO 4× interface, with the real-time response delay ≤ 1 ms.

[0014] The optoelectronic sensing signal processing and information fusion calculation method and system described in the present invention have the beneficial effects that: First, this invention significantly improves the system's real-time performance and data processing efficiency through the collaborative design of the CPU unit, FPGA unit, and high-speed interface. The CPU unit adopts a dual-core division of labor strategy, with the first processor dedicated to management tasks and high-complexity algorithms, and the second processor accelerating floating-point operations and vector processing through the NEON instruction set. Combined with the parallel computing capabilities of the FPGA unit (such as coordinate conversion and redundant switching), the end-to-end latency of multi-source data fusion is compressed to ≤1ms, a significant improvement compared to traditional systems. The FPGA integrates internal time synchronization mechanisms and hardware-level redundant switching logic to solve the problems of data asynchrony and single-point failure in complex environments. In addition, the SRIO 4× interface supports 2.5Gbps high-speed transmission. Combined with CRC checking and an end-to-end retransmission mechanism (retransmission threshold 3 times, timeout 1ms), it ensures data integrity while significantly improving bandwidth utilization, meeting the stringent requirements of aviation and aerospace for high-dynamic real-time performance.

[0015] Secondly, the CPU unit of the present invention is equipped with four external DDR3 memory modules and an external 16GB dynamic random access memory (DRAM) to expand CPU capacity and storage space. DDR3 transmits data on both the rising and falling edges of each clock cycle, resulting in a faster transmission rate. This matches the CPU's processing speed, allowing the CPU to execute billions of instructions per second. DDR's high bandwidth reduces CPU latency and latency, ensuring real-time data transmission. Furthermore, the CPU's external Flash memory utilizes parallel transmission, while BPI Flash supports 16-bit data, resulting in a faster data transmission rate over multiple data lines. The CPU can read instructions directly from Flash without a converter, eliminating the need for an additional controller. This simplifies the startup process, enhances system reliability, and further ensures real-time data transmission.

[0016] Furthermore, the present invention also has good anti-interference ability and system reliability. In response to the anti-interference requirements in complex electromagnetic environments, the present invention achieves reliability breakthroughs in three aspects: hardware isolation, power purification, and protocol fault tolerance. The interface unit adopts a transformer isolation circuit and an isolated CAN drive design to block common-mode noise and ground return interference, thereby reducing the communication bit error rate. The power supply unit uses low-noise LDO independent power supply and tantalum capacitor filtering technology to avoid the influence of electromagnetic sensitivity of high-speed signal links. The multi-source data fusion process of FPGA is embedded with multiple verification mechanisms (such as multiple verification of I²C data and BlockRAM solidified storage of coordinate conversion matrix), combined with the link redundancy design of the 1553B bus and VPX connector to achieve seamless fault switching.

[0017] In addition, the present invention also adopts an energy efficiency management strategy that combines software and hardware to significantly optimize power consumption while ensuring high performance. The power supply unit uses a switching power supply and an LDO for hierarchical power supply, dynamically adjusting the voltage according to the load (such as the FPGA core voltage adapting between 0.9V and 1.2V), thereby improving the overall energy efficiency ratio. The CPU unit runs a domestic partitioned operating system and the VxWorks dual-system, reducing the idle power consumption through task priority scheduling (such as the highest priority for flight control synchronization pulses) and dynamic memory allocation. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is a system block diagram of the optoelectronic sensing signal processing and information fusion computing system of the present invention; Figure 2 is a flowchart of the operation of the CPU unit of the present invention; Figure 3 is a synchronization function block diagram of the optoelectronic sensing signal processing and information fusion computing system of the present invention; Figure 4 is a pose function block diagram of the optoelectronic sensing signal processing and information fusion computing system of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0019] In order to more clearly understand the technical features, objectives, and effects of the present invention, the specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings. The described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts fall within the scope of protection of the present invention. Those not specified in the specific embodiments are carried out according to conventional conditions or conditions provided by the manufacturer.

[0020] When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present disclosure. The terms used in the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure. DETAILED DESCRIPTION OF THE EMBODIMENTS I

[0021] An optoelectronic sensing signal processing and information fusion computing system includes a CPU unit, an FPGA unit capable of realizing multi-source data fusion, a clock unit, a power supply unit, and an interface unit; The CPU unit includes a first processor and a second processor responsible for communication tasks. The first processor is responsible for management tasks and algorithm tasks, and the second processor can support single-precision, double-precision floating-point operation instructions, and vector processing instructions; The FPGA unit is connected to the CPU unit through the LBC interface, and the FPGA unit is externally connected to an SPI Flash and a BPI Flash for storing FPGA program codes; The interface unit includes an A-channel RS422 communication interface, a B-channel RS422 synchronization pulse interface, an SRIO interface, an RS232 interface, and an SRIO 4× interface that realizes fault switching through link redundancy design; where both A and B are positive integers greater than 1; The CPU unit is also equipped with a 1553B card. The 1553B card is connected to the CPU unit through a PCIE interface, and the CPU unit communicates with the outside through a VPX connector; the CPU unit is also connected to 4 DDR memories and 1 Ethernet PHY chip through a multi-channel DDR interface and an RGMII interface respectively.

[0022] In other embodiments, an electrical isolation is performed on the communication signals of each module in the optoelectronic sensing signal processing and information fusion computing system through a transformer isolation circuit; The FPGA unit is also connected to the VXP connector through an isolated CAN driver to achieve dual isolation of signals and power.

[0023] In other embodiments, the SRIO 4× interface supports a rate of 2.5 Gbps, and uses differential pair traces with an impedance of 100Ω ± 5%; the SRIO 4× interface includes a SerDes circuit, and the SerDes circuit is independently powered by a low-noise LDO and tantalum capacitor filtering; and a CRC check and end-to-end retransmission mechanism are integrated through a protocol stack, the retransmission counter threshold is set to 3 times, and the timeout threshold is 1 ms.

[0024] In other embodiments, the power supply unit supplies power to the CPU unit, the FPGA unit, the clock unit, and the interface unit through the VPX connector; the VPX connector is also connected to a fan, an aircraft mission system, sensors, an RS422 communication interface, and an RS422 synchronization pulse interface.

[0025] In other embodiments, the BPI Flash is directly connected to the address and data buses of the CPU unit through a 16-bit parallel bus.

[0026] In other embodiments, the clock unit uses a 50 MHz crystal oscillator to provide a reference clock signal for the phase-locked loop, and then provides a reference clock signal for the CPU unit, the FPGA unit, and the DDR memories through the phase-locked loop.

[0027] In other embodiments, the power supply in the power supply unit is transmitted to an overcurrent and overvoltage protector through the VPX connector, and then transmitted to a switching power supply and a low-dropout linear regulator to be converted into the required voltage for power supply.

[0028] In other embodiments, the CPU unit and the FPGA unit are also jointly debugged through a JTAG interface.

[0029] In other embodiments, the CPU unit runs a domestic road partition operating system and the Vxworks operating system; The multi-source data fusion process implemented by the FPGA unit includes the pose data of the synchronous satellite antenna, the primary inertial navigation, and the backup inertial navigation, generating high-precision attitude information through coordinate transformation and error compensation, aligning the I²C data of the temperature and humidity, air pressure, and vibration sensors, and transmitting them to the CPU unit through the LBC interface; The multi-source data fusion process specifically includes: 1) Time synchronization: Taking the flight management synchronization pulse as the highest priority, generating a synchronization signal through the PLL inside the FPGA unit, and the time synchronization error ≤ 100 ns; 2) Redundancy switching: When the primary inertial navigation data is abnormal, enabling the backup inertial navigation data stream within 10 ms through the hardware switching logic; 3) Coordinate unification: Converting the longitude and latitude information of the Beidou satellite into the inertial navigation local coordinate system, and storing the transformation matrix in the Block RAM of the FPGA unit. Specific Embodiment 2

[0030] An optoelectronic sensing signal processing and information fusion calculation method for an optoelectronic sensing signal processing and information fusion calculation system based on any of the above embodiments specifically includes the following steps: S1: Receiving the flight management synchronization signal through the RS422 synchronization pulse interface, and generating a global time reference by the FPGA unit, with the time synchronization error ≤ 100 ns; S2: Collecting the pose data of the satellite antenna, the primary inertial navigation, and the backup inertial navigation through the A-channel RS422 interface, and performing timestamp alignment and coordinate transformation by the FPGA unit; S3: The sensor transmits the collected data to the FPGA unit through the IIC interface. The FPGA unit parses according to the interface protocol, performs multiple checks on the transmitted data, and transmits it to the CPU through the LBC interface after the checks are correct; the sensors include a temperature sensor, a humidity sensor, an air pressure sensor, and a vibration sensor; S4: The CPU unit accelerates the floating-point operation through the NEON instruction set, performs the Kalman filter algorithm on the preprocessed data, and compensates for the inertial navigation zero drift, with the scale factor ≤ 0.1%; S5: Outputting the fusion result to an external device through the SRIO 4× interface, with the real-time response delay ≤ 1 ms. Embodiment 1

[0031] An optoelectronic sensing signal processing and information fusion computing system, as Figure 1 shown, includes a CPU unit, an FPGA unit capable of realizing multi-source data fusion, a clock unit, a power supply unit, and an interface unit.

[0032] In this Embodiment 1, the CPU unit includes a first ARM Cortex processor and a second ARM Cortex processor responsible for communication tasks. The first ARM Cortex processor is responsible for management tasks and algorithm tasks, and the second ARM Cortex processor can support single-precision, double-precision floating-point operation instructions and vector processing instructions. The algorithm tasks include servo control and spot tracking algorithms; the management tasks include system management and sensor management; the communication tasks include data communication and sensor interface management.

[0033] The FPGA unit is connected to the CPU unit through an LBC interface, and the FPGA unit is externally connected to an SPI Flash and a BPI Flash for storing FPGA program codes; the BPI Flash is directly connected to the address and data buses of the CPU unit through a 16-bit parallel bus.

[0034] The interface unit includes an A-channel RS422 communication interface, a B-channel RS422 synchronous pulse interface, an SRIO interface, an RS232 interface, and an SRIO 4× interface that realizes fault switching through link redundancy design; where both A and B are positive integers greater than 1.

[0035] In this Embodiment 1, there are 11 RS422 communication interfaces, including master control intelligent communication, interface board communication, common aperture communication, navigation communication, main inertial navigation backup inertial navigation communication, etc. There are 10 synchronous pulse RS422s, adopting RS422 synchronous pulse interfaces and SRIO interfaces, including servo synchronization, sensor synchronization, infrared synchronization, irradiation synchronization, irradiation discharge synchronization, common aperture synchronization, white light synchronization, navigation synchronization, flight control synchronization, etc.

[0036] The SRIO 4× interface supports a rate of 2.5 Gbps, and adopts differential pair routing with an impedance of 100Ω±5%; the SRIO 4× interface includes a SerDes circuit, and the SerDes circuit is independently powered by a low-noise LDO and tantalum capacitor filtering; and integrates a CRC check and an end-to-end retransmission mechanism through a protocol stack, and the retransmission counter threshold is set to 3 times, and the timeout threshold is 1 ms.

[0037] The CPU unit is also equipped with a 1553B card. The 1553B card is connected to the CPU unit through a PCIE interface, and the CPU unit communicates with the outside through a VPX connector. The CPU unit is also connected to 4 DDR memories and 1 Ethernet PHY chip through a multi-channel DDR interface and an RGMII interface respectively.

[0038] In Embodiment 1, in the hardware design of this system, a hardware isolation technology is adopted, and an independent physical isolation circuit is designed for the communication lines of each module. Specifically, the communication signals of each module in the optoelectronic sensing signal processing and information fusion calculation system are electrically isolated through a transformer isolation circuit; in Embodiment 1, the RS422 transmit / receive ends of the common-aperture communication are transmitted to the system management board through a VPX connector, and then the transmit / receive ends are signal- and power-isolated through an isolated RS422 transceiver and then transmitted to the FPGA unit for processing and communication with the outside.

[0039] The FPGA unit is also connected to the VXP connector through an isolated CAN driver to achieve double isolation of signals and power. In Embodiment 1, the CAN signal transmit / receive ends are transmitted to the system management board through a VPX connector, and then the transmit / receive ends are signal- and power-isolated through an isolated CAN transceiver and then transmitted to the FPGA unit for processing and communication with the outside.

[0040] The power supply unit supplies power to the CPU unit, FPGA unit, clock unit, and interface unit through a VPX connector. The VPX connector is also connected to a fan, an aircraft mission system, sensors, an RS422 communication interface, and an RS422 synchronization pulse interface.

[0041] In Embodiment 1, the clock unit uses a 50MHz crystal oscillator to provide a reference clock signal for the phase-locked loop, and then the phase-locked loop provides a reference clock signal for the CPU unit, FPGA unit, and DDR memories, ensuring that steps such as the CPU fetching instructions, decoding, and executing are advanced sequentially within each clock cycle, ensuring that each task stage is transmitted on time and improving efficiency.

[0042] The power supply in the power supply unit is transmitted to the overcurrent and overvoltage protector through a VPX connector, and then transmitted to the switching power supply and low-dropout linear regulator to be converted into the required voltage for power supply. In Embodiment 1, the external input is a 12V power supply. Through the overcurrent and overvoltage protector and then through 3 multi-output switching power supplies, different voltages and currents are distributed to supply the power required by devices such as the CPU unit, FPGA unit, and DDR, ensuring independent power supply and mutual non-interference among devices.

[0043] The CPU unit and the FPGA unit also achieve joint debugging of the CPU unit and the FPGA unit through a JTAG interface.

[0044] In the first embodiment, the working process of the CPU unit is as follows Figure 2 As shown, after the system is powered on, the FPGA unit reads the program code from the BPI Flash and stores it in the register of the FPGA unit. Then, the CPU unit reads the program code from the register through the LBC interface and loads the operating system application program into the random access memory for execution. The BPI Flash has 16-bit data, and the data line has a faster transmission rate. Especially when a large amount of data needs to be quickly read to start the code at startup, the interface of the BPI Flash is directly connected to the address and data buses of the CPU unit. Therefore, at startup, the CPU unit can directly read instructions from the Flash without passing through a converter and does not require an additional controller, simplifying the startup process and enhancing the system reliability. The access delay of the BPI Flash is lower, and 16 bits can be transmitted at a time, so the delay is lower, ensuring the real-time nature of the data. The BPI Flash has a write protection mechanism to prevent accidental or malicious modification of data.

[0045] In the first embodiment, the 4 DDR3s externally connected to the CPU unit are all 4GB, and 16G of dynamic random access memory is externally connected to expand the capacity and storage space of the CPU unit. The internal cache capacity of the CPU unit is only a few MB and cannot store a large number of running programs and data, thus making up for the shortage of the CPU unit's cache and improving the data transmission rate. With a double data rate design, the DDR3 transmits data on both the rising and falling edges of each clock cycle, doubling the bandwidth compared to traditional SDRAM and having a faster transmission rate. Matching the processing speed of the CPU unit, the CPU unit can execute billions of instructions per second and requires a higher bandwidth memory to quickly supply data. The high bandwidth of the DDR3 reduces the waiting time of the CPU unit and reduces the latency.

[0046] The CPU unit runs a domestic partitioned operating system and the Vxworks operating system; The multi-source data fusion process implemented by the FPGA unit includes the pose data of the synchronous satellite antenna, the primary inertial navigation, and the backup inertial navigation, generating high-precision attitude information through coordinate transformation and error compensation, aligning the I²C data of the temperature and humidity, air pressure, and vibration sensors, and transmitting them to the CPU unit through the LBC interface; The multi-source data fusion process specifically includes: 1) Time synchronization: Taking the flight management synchronization pulse as the highest priority, generating a synchronization signal through the phase-locked loop inside the FPGA unit, and the time synchronization error ≤ 100ns; 2) Redundancy switching: When the primary inertial navigation data is abnormal, enabling the backup inertial navigation data stream within 10ms through the hardware switching logic; 3) Coordinate unification: Convert the longitude and latitude information of Beidou satellites into the inertial navigation local coordinate system, and store the conversion matrix in the Block RAM of the FPGA unit.

[0047] In Embodiment 1 of the present invention, the fusion process in the optoelectronic sensing signal processing and information fusion calculation is as Figure 3 shown, including: (1) Synchronization pulse signal: In the fusion scenario of the fly control synchronization pulse, the navigation synchronization second pulse (PPS), and the pulse locally generated by the FPGA unit, it is necessary to ensure high-precision time synchronization and data consistency. For example: When the fly control synchronization pulse is normal, the synchronization signal is transmitted to the FPGA unit through the RS422 communication interface. After the FPGA unit performs fusion processing, it is transmitted to the CPU unit through the LBC. The CPU unit then transmits it to each component through the RS422 communication interface. FPGA data fusion one: Unify the clock source, priority: "fly control synchronization" takes precedence over "navigation synchronization" takes precedence over "local FPGA". When any pulse source fails, the system can operate in a degraded mode (such as switching to the internal pulse of the FPGA). The fly control synchronization is preferentially used as the global time reference and transmitted to the FPGA unit. The FPGA unit internally generates a high-precision synchronization signal through the PLL and generates pulse logic after the fly control pulse logic to ensure timing constraints. The FPGA unit outputs synchronization pulses to the CPU through multiple IO ports.

[0048] (2) The reliability of the information is improved after the system fusion of the three or two position information of the satellite antenna position, the main inertial navigation position, and the backup inertial navigation position. In Embodiment 1 of the present invention, as Figure 4 shown, for example: When the longitude and latitude information provided by the Beidou satellite is normal, it is transmitted to the navigation module through the RS422 communication interface. The navigation module is transmitted to the FPGA unit through the RS422 communication interface. The FPGA unit performs data preprocessing to align the satellite data with the timestamp of the navigation module itself, converts the Beidou satellite coordinates into the inertial navigation local coordinate system, and then transmits it to the CPU unit through the LBC interface. If the satellite antenna is unavailable or has a delay in some cases, such as in a tunnel, inertial navigation is relied on at this time, and the main inertial navigation is preferentially used. Once data anomalies are detected, switch to the backup inertial navigation, or use the data of both at the same time.

[0049] Data fusion: Data fusion requires processing by the FPGA unit. One: Align the timestamps of the satellite antenna, the main / backup inertial navigation data. Two: Coordinate unification, convert the satellite antenna coordinate system into the local coordinate system of the inertial navigation. Three: Error compensation, calibrate the zero drift of the main and backup inertial navigation and adjust the proportional factor error.

[0050] (3) The temperature and humidity sensor, barometric pressure sensor, and vibration sensor transmit the collected data to the FPGA unit through the IIC interface. The FPGA unit parses according to the interface protocol, performs multiple verifications on the transmitted data, and then transmits it to the CPU unit through the LBC interface after the verification is correct. Embodiment 2

[0051] An optoelectronic sensing signal processing and information fusion calculation method based on the optoelectronic sensing signal processing and information fusion calculation system described in Embodiment 1, specifically including the following steps: S1: Receive the fly tube synchronization signal through the RS422 synchronous pulse interface, and generate a global time reference by the FPGA unit, with a time synchronization error ≤ 100 ns; S2: Collect the pose data of the satellite antenna, main inertial navigation, and backup inertial navigation through the A-channel RS422 interface, and perform timestamp alignment and coordinate conversion by the FPGA unit; S3: The sensor transmits the collected data to the FPGA unit through the IIC interface. The FPGA unit parses according to the interface protocol, performs multiple verifications on the transmitted data, and then transmits it to the CPU through the LBC interface after the verification is correct; the sensor includes a temperature sensor, a humidity sensor, a barometric pressure sensor, and a vibration sensor; S4: The CPU unit accelerates the floating-point operation through the NEON instruction set, executes the Kalman filter algorithm on the preprocessed data, and compensates for the inertial navigation zero drift, with a scale factor ≤ 0.1%; S5: Output the fusion result to the external device through the SRIO 4× interface, with a real-time response delay ≤ 1 ms.

Claims

1. An optoelectronic sensing signal processing and information fusion calculation system, characterized in that, It includes a CPU unit, an FPGA unit capable of realizing multi-source data fusion, a clock unit, a power supply unit, and an interface unit; The CPU unit includes a first processor and a second processor responsible for communication tasks. The first processor is responsible for management tasks and algorithm tasks, and the second processor can support single-precision, double-precision floating-point operation instructions and vector processing instructions; The FPGA unit is connected to the CPU unit through an LBC interface, and the FPGA unit externally connects an SPI Flash and a BPI Flash for storing FPGA program codes; The interface unit includes an A-channel RS422 communication interface, a B-channel RS422 synchronization pulse interface, an SRIO interface, an RS232 interface, and an SRIO 4× interface that realizes fault switching through link redundancy design; where both A and B are positive integers greater than 1; The CPU unit is also provided with a 1553B card. The 1553B card is connected to the CPU unit through a PCIE interface, and the CPU unit communicates with the outside through a VPX connector; the CPU unit is also connected to 4 DDR memories and 1 Ethernet PHY chip through a multi-channel DDR interface and an RGMII interface respectively.

2. The optoelectronic sensing signal processing and information fusion calculation system according to claim 1, wherein: An electrical isolation is performed on the communication signals of each module in the optoelectronic sensing signal processing and information fusion calculation system through a transformer isolation circuit; The FPGA unit is also connected to the VXP connector through an isolated CAN driver to achieve double isolation of signals and power supplies.

3. The optoelectronic sensing signal processing and information fusion calculation system according to claim 1, characterized in that: The SRIO 4× interface supports a rate of 2.5 Gbps, and uses differential pair traces with an impedance of 100Ω ± 5%; the SRIO 4× interface includes a SerDes circuit, and the SerDes circuit is independently powered by a low-noise LDO and tantalum capacitor filtering; and a CRC check and end-to-end retransmission mechanism are integrated through a protocol stack, the retransmission counter threshold is set to 3 times, and the timeout threshold is 1 ms.

4. The optoelectronic sensing signal processing and information fusion calculation system according to claim 1, characterized in that, The power supply unit supplies power to the CPU unit, the FPGA unit, the clock unit, and the interface unit through a VPX connector; the VPX connector is also connected to a fan, an aircraft mission system, sensors, an RS422 communication interface, and an RS422 synchronization pulse interface.

5. The optoelectronic sensing signal processing and information fusion calculation system according to claim 1, wherein: The BPI Flash is directly connected to the address and data buses of the CPU unit through a 16-bit parallel bus.

6. The optoelectronic sensing signal processing and information fusion calculation system according to claim 1, wherein: The clock unit uses a 50 MHz crystal oscillator to provide a reference clock signal for the phase-locked loop, and then the phase-locked loop provides a reference clock signal for the CPU unit, the FPGA unit, and the DDR memories.

7. The optoelectronic sensing signal processing and information fusion calculation system according to claim 1, characterized in that: The power supply in the power supply unit is transmitted to an overcurrent and overvoltage protector through a VPX connector, and then transmitted to a switching power supply and a low-dropout linear regulator to be converted into the required voltage for power supply.

8. The optoelectronic sensing signal processing and information fusion calculation system according to claim 1, wherein: The CPU unit and the FPGA unit also realize joint debugging of the CPU unit and the FPGA unit through a JTAG interface.

9. The optoelectronic sensing signal processing and information fusion calculation system according to claim 1, wherein: The CPU unit runs a domestic road partition operating system and a Vxworks operating system; The multi-source data fusion process implemented by the FPGA unit includes the pose data of the synchronous satellite antenna, the primary inertial navigation, and the backup inertial navigation, generating high-precision attitude information through coordinate transformation and error compensation, aligning the I²C data of the temperature and humidity, air pressure, and vibration sensors, and transmitting it to the CPU unit through the LBC interface; The multi-source data fusion process specifically includes: 1) Time synchronization: Taking the flight management synchronization pulse as the highest priority, generating a synchronization signal through the internal PLL of the FPGA unit, with a time synchronization error ≤ 100 ns; 2) Redundancy switching: When the primary inertial navigation data is abnormal, enabling the backup inertial navigation data stream within 10 ms through the hardware switching logic; 3) Coordinate unification: Converting the longitude and latitude information of the Beidou satellite into the local coordinate system of the inertial navigation, and storing the transformation matrix in the Block RAM of the FPGA unit.

10. An optoelectronic sensing signal processing and information fusion calculation method for the optoelectronic sensing signal processing and information fusion calculation system according to any one of claims 1 to 9, characterized in that: The method specifically includes the following steps: S1: Receiving the flight management synchronization signal through the RS422 synchronization pulse interface, and generating a global time reference by the FPGA unit, with a time synchronization error ≤ 100 ns; S2: Collecting the pose data of the satellite antenna, the primary inertial navigation, and the backup inertial navigation through the A-channel RS422 interface, and performing timestamp alignment and coordinate transformation by the FPGA unit; S3: The sensor transmits the collected data to the FPGA unit through the IIC interface. The FPGA unit parses according to the interface protocol, performs multiple verifications on the transmitted data, and transmits it to the CPU through the LBC interface after verification; The sensors include temperature sensors, humidity sensors, air pressure sensors, and vibration sensors; S4: The CPU unit accelerates floating-point operations through the NEON instruction set, executes the Kalman filter algorithm on the preprocessed data, and compensates for the zero drift of the inertial navigation, with a scale factor ≤ 0.1%; S5: Outputting the fusion result to the external device through the SRIO 4× interface, with a real-time response delay ≤ 1 ms.

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