Low-power-consumption high-flexibility SSD (Solid State Disk) main control chip operation acceleration circuit

Abstract

The invention discloses a low-power-consumption high-flexibility SSD main control chip operation acceleration circuit, which comprises a main control unit, a switch unit and a processing unit, and is characterized in that the main control unit comprises a plurality of triggers, a plurality of calculation chips, a plurality of multiplexing chips and a plurality of diodes, a D pin of a trigger U1 in the plurality of triggers is connected with a Q reverse pin, and a Q reverse pin is connected with a Q reverse pin; a CLK pin is connected with a CLK pin of the computing chip U3, and a CLK pin, a P1 end and a Q pin of the computing chip U4 are connected with a pin A of the multiplexing chip U7 and a CLK pin of the trigger U9; a D pin of the trigger U9 is connected with a Q reverse pin, and a Q pin of the trigger U9 is connected with a B pin of the multiplexing chip U7; a D pin of the trigger U10 is connected with a Q reverse pin, a CLK pin of the trigger U10 is connected with a cathode of a diode D9 and a cathode of a diode D10, and a Q pin of the trigger U10 is connected with an S1 pin and an S2 pin of the multiplexing chip U5 and an S1 pin and an S2 pin of the multiplexing chip U6; a Q4 pin of the computing chip U4 is connected with the anode of the diode D10, and a Q8 pin and an MR pin of the computing chip U4 are connected with the anode of the diode D9.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and particularly to an operation acceleration circuit for a low-power and high-flexibility SSD main control chip. Background Art

[0002] In the field of modern information security, encryption technology is the core means to ensure data security, mainly including three categories: symmetric encryption, asymmetric encryption, and hash algorithms. Symmetric encryption (such as AES, ChaCha20) uses the same key for encryption and decryption, with high speed and efficiency, suitable for encrypting large amounts of data, but key management is a key challenge; Asymmetric encryption (such as RSA, ECC) uses a public key for encryption and a private key for decryption, solving the problem of key distribution, and is widely used in digital signatures and key exchanges, but has a relatively large computational overhead; Hash algorithms (such as SHA-256, BLAKE2) generate irreversible unique digests, commonly used for data integrity verification and password storage (salt value is required to prevent cracking). In addition, hybrid encryption (such as the TLS protocol) combines the advantages of symmetric and asymmetric encryption, taking into account both security and performance, while national cryptographic algorithms (SM4, SM2) and post-quantum cryptography (such as lattice cryptography) meet specific compliance requirements and future anti-quantum attack requirements respectively. When encrypting data, existing SSD hard drives need to integrate one or more encryption algorithms. Since different encryption algorithms have different rules, different control circuits need to be integrated for each encryption algorithm respectively. Therefore, an operation acceleration circuit for a low-power and high-flexibility SSD main control chip that can adaptively control different encryption rules without switching is proposed. Summary of the Invention

[0003] To solve the above technical problems, the object of the present invention is to provide an operation acceleration circuit for a low-power and high-flexibility SSD master control chip, which includes a master control unit, a switching unit, and a processing unit. The master control unit includes several flip-flops, several computing chips, several multiplexing chips, and several diodes. The D pin of flip-flop U1 among the several flip-flops is connected to the Q-bar pin, the CLK pin is connected to the CLK pins of computing chip U3, computing chip U4, and P1 terminal, and the Q pin is connected to the A pin of multiplexing chip U7 and the CLK pin of flip-flop U9; the D pin of flip-flop U9 is connected to the Q-bar pin, and the Q pin is connected to the B pin of multiplexing chip U7; the D pin of flip-flop U10 is connected to the Q-bar pin, the CLK pin is connected to the cathodes of diodes D9 and D10, and the Q pin is connected to the S1 and S2 pins of multiplexing chip U5 and the S1 and S2 pins of multiplexing chip U6; the Q4 pin of computing chip U4 is connected to the anode of diode D10, and the Q8 and MR pins are connected to the anode of diode D9; the A1 pin of multiplexing chip U5 is connected to the 2_1 terminal, and the corresponding pins of Y1 to Y4 are respectively connected to the corresponding pins of 2X0 to 2X3 of multiplexing chip U7; the Y1 pin of multiplexing chip U6 is connected to the 1X0 pin of multiplexing chip U7, and the corresponding pins of Y2 to Y4 are respectively connected to the 1X3 to 1X1 pins of multiplexing chip U7; the Q8 pin of computing chip U3 is connected to the MR pin and the OE-bar pin of computing chip U8; the corresponding pins of Q0 to Q7 of computing chip U3 are respectively connected to the control terminals in the switching unit; the Q0 to Q7 pins of computing chip U8 are respectively connected to the anodes of diodes D1 to D8, and the D0 to D7 pins of computing chip U8 are respectively connected to the cathodes of diodes D1 to D8 and the output terminal of the switching unit; the E pins of computing chip U3 and computing chip U4 are grounded.

[0004] Further, the processing unit includes an exclusive-OR gate. The input terminals of exclusive-OR gate U2 are connected to the 1Y and 2Y pins of multiplexing chip U7, and the output terminal is connected to the input terminal of the switching unit.

[0005] Further, the switching unit includes several triodes. The input terminals of the several triodes are connected in parallel to the output terminal of exclusive-OR gate U2, the control terminals are respectively connected to the Q0 to Q7 pins of computing chip U3, and the output terminals are connected to the cathodes of diodes D1 to D8.

[0006] Further, the master control unit further includes several resistors. One end of resistor R1 among the several resistors is connected to the P1 terminal; one end of resistor R2 is connected to the Q pin of flip-flop U1; one end of resistor R3 is connected to the S1 pin of multiplexing chip U5; one end of resistor R4 is connected to the MR pin of computing chip U3; one end of resistor R5 is connected to the P1 terminal; one end of resistor R6 is connected to the 1E and 2E pins of multiplexing chip U7; one end of resistor R7 is connected to the cathode of diode D9; the other ends of resistors R1 to R7 are grounded.

[0007] Further, it further includes a finite field multiplier. The output end of the multiplexing chip U7 corresponds to the input end of the finite field multiplier, and the output end of the finite field multiplier is fed back to the switching unit.

[0008] Further, the P1 is connected to the clock signal.

[0009] Further, the circuit is powered by 5V.

[0010] The beneficial effects of the present invention compared with the prior art are as follows: The present invention can be adapted to different encryption rules through the encryption control of one byte, and when multiple encryption rules are adopted, the number of control circuits to be integrated can be reduced. Description of the Drawings

[0011] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the prior art and the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0012] Figure 1 It is the circuit structure diagram provided by the present invention. Detailed Embodiments

[0013] In order to make the purpose and advantages of the present invention clearer, the following specifically describes the present invention in conjunction with the embodiments. It should be understood that the following text only describes one or several specific implementation manners of the present invention and does not strictly limit the scope of protection specifically claimed by the present invention.

[0014] The present invention discloses an operation acceleration circuit for a low-power and high-flexibility SSD main control chip, which includes a main control unit, a switching unit, and a processing unit. The main control unit includes a number of flip-flops, a number of computing chips, a number of multiplexing chips, and a number of diodes. The D pin of flip-flop U1 among the number of flip-flops is connected to the Q-bar pin, the CLK pin is connected to the CLK pins of computing chip U3, computing chip U4, and P1 terminal, and the Q pin is connected to the A pin of multiplexing chip U7 and the CLK pin of flip-flop U9; the D pin of flip-flop U9 is connected to the Q-bar pin, and the Q pin is connected to the B pin of multiplexing chip U7; the D pin of flip-flop U10 is connected to the Q-bar pin, the CLK pin is connected to the cathodes of diodes D9 and D10, and the Q pin is connected to the S1 and S2 pins of multiplexing chip U5 and the S1 and S2 pins of multiplexing chip U6; the Q4 pin of computing chip U4 is connected to the anode of diode D10, and the Q8 and MR pins are connected to the anode of diode D9; the A1 pin of multiplexing chip U5 is connected to the 2_1 terminal, and the corresponding pins of Y1 to Y4 are respectively connected to the corresponding pins of 2X0 to 2X3 of multiplexing chip U7; the Y1 pin of multiplexing chip U6 is connected to the 1X0 pin of multiplexing chip U7, and the corresponding pins of Y2 to Y4 are respectively connected to the 1X3 to 1X1 pins of multiplexing chip U7; the Q8 pin of computing chip U3 is connected to the MR pin and the OE-bar pin of computing chip U8; the corresponding pins of Q0 to Q7 of computing chip U3 are respectively connected to the control terminals in the switching unit; the Q0 to Q7 pins of computing chip U8 are respectively connected to the anodes of diodes D1 to D8, and the D0 to D7 pins of computing chip U8 are respectively connected to the cathodes of diodes D1 to D8 and the output terminal of the switching unit; the E pins of computing chip U3 and computing chip U4 are grounded.

[0015] Specifically, the processing unit includes an exclusive-OR gate. The input terminals of exclusive-OR gate U2 are connected to the 1Y and 2Y pins of multiplexing chip U7, and the output terminal is connected to the input terminal of the switching unit.

[0016] Specifically, the switching unit includes a number of triodes. The input terminals of the number of triodes are connected in parallel to the output terminal of exclusive-OR gate U2, the control terminals are respectively connected to the Q0 to Q7 pins of computing chip U3, and the output terminals are connected to the cathodes of diodes D1 to D8.

[0017] Specifically, the main control unit further includes a number of resistors. One end of resistor R1 among the number of resistors is connected to the P1 terminal; one end of resistor R2 is connected to the Q pin of flip-flop U1; one end of resistor R3 is connected to the S1 pin of multiplexing chip U5; one end of resistor R4 is connected to the MR pin of computing chip U3; one end of resistor R5 is connected to the P1 terminal; one end of resistor R6 is connected to the 1E and 2E pins of multiplexing chip U7; one end of resistor R7 is connected to the cathode of diode D9; the other ends of resistors R1 to R7 are grounded.

[0018] Specifically, it further includes a finite field multiplier. The output end of the multiplexing chip U7 corresponds to the input end of the finite field multiplier, and the output end of the finite field multiplier is fed back to the switching unit.

[0019] Specifically, the P1 is connected to the clock signal.

[0020] Specifically, the circuit is powered by 5V.

[0021] In this application, 1_1 is used to input the plaintext bit sequence (the encrypted plaintext and the initial round plaintext data in the round transformation), and 2_1 inputs the key bit sequence (the initial key and the expanded key). When the circuit is loop-unrolled (in the way of multiplexing for each round, for example, each round transformation in AES encryption uses a processing circuit), a master control unit can be adopted. All output pins of the computing chip U8 in each master control unit correspond to one byte (8-bit) data, or 8 units can be used. The same output pins of the computing chip U8 in each master control unit form one byte of data. When fully unrolled, the corresponding quantity is set according to the size of the byte matrix of the key bit number. Among them, P1 inputs the clock signal. Taking the decimal value 97 in ASCII code as an example, the corresponding binary value is 01100001. The initial round key of one byte is 11110000, which is illustrated by XOR processing. The multiplexing chip U6 is used to input the plaintext bit sequence. Its input pins in series of the A series input the first 4 bits, and the pins in series of the B series input the last 4 bits. That is, the data bit corresponding to the A pin is 0110, and the data corresponding to the B pin is 0001. The multiplexing chip U5 is used to input the key bit sequence. Its input pins in series of the A series input the first 4 bits, and the pins in series of the B series input the last 4 bits. That is, the data bit corresponding to the A pin is 1111, and the data corresponding to the B pin is 0000. The output pins of the multiplexing chip U6 and the multiplexing chip U5 are fed back to the multiplexing chip U7. The flip-flops U1 and U9 form a 2-bit four-output decoding circuit and input to the multiplexing chip U7. According to the connection of the multiplexing chip U6, the multiplexing chip U5 input to the multiplexing chip U7 and the flip-flops U1 and U9 input to the multiplexing chip U7 in the attached figure, the corresponding output truth table and sequence are as follows: when the AB pins of the multiplexing chip U7 input 00, the corresponding X0 is input to 1Y and 2Y; when input 11, the corresponding X3 is input to 1Y and 2Y; when input 01, the corresponding X2 is input to 1Y and 2Y; when input 10, the corresponding X1 is input to 1Y and 2Y. Assume that the current key addition program is executed, then the XOR gate U2 performs XOR output, and the output result is fed back to the switch unit composed of transistors Q1 to Q8. The computing chip U8 and the diodes D1 to D8 form a data storage circuit. The control process of one byte is as follows: after the circuit is powered on, the multiplexing chip U6 and the multiplexing chip U5 input the corresponding first several digits of the 1_1 plaintext bit sequence data and the 2_1 key bit sequence data into 1X0 to 1X3 and 2X0 to 2X3 of the multiplexing chip U7. The multiplexing chip U7 inputs 1X0 and 2X0 to the XOR gate U2 through the 1Y and 2Y pins for XOR processing, and the processing result is fed back to the switch unit. At the same time, the Q0 pin of the computing chip U3 outputs to the transistor Q1 in the corresponding switch unit, and the transistor Q1 conducts. The XOR gate U2 outputs the data result of high or low level 1 or 0 to the D0 pin of the computing chip U8. Taking the above example data as an example, the Q0 pin of the computing chip U8 outputs a high level, which is fed back to the D0 of the computing chip U8 through the diode D1 for closed-loop storage. When processing the second bit of data, after a clock signal is input by P1,The corresponding states of the Q pins of flip-flop U1 and flip-flop U9 output 11 to multiplexing chip U7. Multiplexing chip U7 inputs the corresponding data of 1X3 and 2X3 into exclusive-OR gate U2. At the same time, the Q1 pin of computing chip U3 is input into Q2 in the switch unit. The Q1 pin of computing chip U8 outputs a low-level signal. After the above process loops until the first four processed data are obtained. At this time, the corresponding results output by the Q0 to Q3 pins of computing chip U8 are 1001. At the same time, when the P1 input clock signal is also synchronously fed back to computing chip U4. When processing the fifth bit of data, the Q4 pin output of computing chip U4 is fed back to the CLK pin of flip-flop U10 through diode D10. Diodes D10 and D9 are used for signal anti-reversal. The Q pin of flip-flop U10 is set to 1 and fed back to the S series pins of multiplexing chip U6 and multiplexing chip U5. Multiplexing chip U6 and multiplexing chip U5 input the last four plaintext bit sequence data and key bit sequence data corresponding to the B series pins into multiplexing chip U7 until the last four processed data are obtained through the above process. At this time, the output pins of computing chip U8 correspond to 10010001 to complete one processing in the round transformation. For reset, the P1 input clock signal is input again. The Q8 pin output signal of computing chip U4 is fed back to flip-flop U10 through diode D9. The Q pin of flip-flop U10 is set to 0. Multiplexing chip U6 and multiplexing chip U5 are reset to output from the A series pins. At the same time, the Q8 pin of computing chip U4 is also fed back to the MR pin for reset. After P1 is input to computing chip U3 and computing chip U8, the Q8 pin of computing chip U3 is input to the MR pin and the OE inverse pin of computing chip U8. Computing chip U3 is reset and computing chip U8 is erased. When the circuit is multiplexed to the column mixing step, exclusive-OR gate U2 is removed and the output end of multiplexing chip U7 is connected to the restricted domain multiplier. When using one bit, the output end of multiplexing chip U7 corresponds to the input end of the restricted domain multiplier. The output end of the restricted domain multiplier is fed back to the switch unit. It can also use 8 bits. The connection method is that the 1Y pin of the multiplexing chip U7 of each main control unit is input to the first group of input ends of the restricted domain multiplier, and the 2Y pin is input to the second group of input ends of the restricted domain multiplier. When using an 8-bit restricted domain multiplier, 8 main control units are connected in sequence. The output end of the multiplier is directly fed back to the input pins of computing chip U8. The drawings of the restricted domain multiplier are not shown.,

[0022] For those skilled in the art, it is obvious that the present invention is not limited to the details of the above exemplary embodiments, and without departing from the spirit or basic characteristics of the present invention, the present invention can be implemented in other specific forms. Therefore, from any point of view, the embodiments should be regarded as exemplary and non-restrictive. The scope of the present invention is defined by the appended claims rather than the above description. Therefore, it is intended to include all changes falling within the meaning and scope of the equivalent elements of the claims in the present invention. Any reference signs in the claims should not be regarded as limiting the claimed claims.,

Claims

1. An operation acceleration circuit for a low-power and high-flexibility SSD main control chip, characterized in that It includes a main control unit, a switching unit and a processing unit. The main control unit includes several flip-flops, several computing chips, several multiplexing chips, and several diodes. The D pin of flip-flop U1 among the several flip-flops is connected to the Q-bar pin, the CLK pin is connected to the CLK pins of computing chip U3, computing chip U4, and P1 terminal, and the Q pin is connected to the A pin of multiplexing chip U7 and the CLK pin of flip-flop U9; the D pin of flip-flop U9 is connected to the Q-bar pin, and the Q pin is connected to the B pin of multiplexing chip U7; the D pin of flip-flop U10 is connected to the Q-bar pin, the CLK pin is connected to the cathodes of diode D9 and diode D10, and the Q pin is connected to the S1 and S2 pins of multiplexing chip U5 and the S1 and S2 pins of multiplexing chip U6; the Q4 pin of computing chip U4 is connected to the anode of diode D10, and the Q8 and MR pins are connected to the anode of diode D9; the A1 pin of multiplexing chip U5 is connected to the 2_1 terminal, and the corresponding pins of Y1 to Y4 are respectively connected to the corresponding pins of 2X0 to 2X3 of multiplexing chip U7; the Y1 pin of multiplexing chip U6 is connected to the 1X0 pin of multiplexing chip U7, and the corresponding pins of Y2 to Y4 are respectively connected to the 1X3 to 1X1 pins of multiplexing chip U7; the Q8 pin of computing chip U3 is connected to the MR pin and the OE-bar pin of computing chip U8; the corresponding pins of Q0 to Q7 of computing chip U3 are respectively connected to the control terminals in the switching unit; the corresponding pins of Q0 to Q7 of computing chip U8 are respectively connected to the anodes of diodes D1 to D8, and the D0 to D7 pins of computing chip U8 are respectively connected to the cathodes of diodes D1 to D8 and the output terminal of the switching unit; the E pins of computing chip U3 and computing chip U4 are grounded.

2. The operation acceleration circuit of the low-power and high-flexibility SSD main control chip according to claim 1, characterized in that The processing unit includes an exclusive-OR gate. The input terminals of exclusive-OR gate U2 are connected to the 1Y and 2Y pins of multiplexing chip U7, and the output terminal is connected to the input terminal of the switching unit.

3. The low-power high-flexibility SSD master control chip operation acceleration circuit according to claim 1, characterized in that The switching unit includes several triodes. The input terminals of the several triodes are connected in parallel to the output terminal of exclusive-OR gate U2, the control terminals are respectively connected to the Q0 to Q7 pins of computing chip U3, and the output terminals are connected to the cathodes of diodes D1 to D8.

4. The low-power and high-flexibility SSD main control chip operation acceleration circuit according to claim 1, characterized in that The main control unit further includes several resistors. One end of resistor R1 among the several resistors is connected to the P1 terminal; one end of resistor R2 is connected to the Q pin of flip-flop U1; one end of resistor R3 is connected to the S1 pin of multiplexing chip U5; one end of resistor R4 is connected to the MR pin of computing chip U3; one end of resistor R5 is connected to the P1 terminal; one end of resistor R6 is connected to the 1E and 2E pins of multiplexing chip U7; one end of resistor R7 is connected to the cathode of diode D9; the other ends of resistor R1 to resistor R7 are grounded.

5. The operation acceleration circuit of the low-power and high-flexibility SSD main control chip according to claim 2, wherein, It further includes a finite field multiplier. The output terminal of multiplexing chip U7 corresponds to the input terminal of the finite field multiplier, and the output terminal of the finite field multiplier is fed back to the switching unit.

6. The low-power high-flexibility SSD main control chip operation acceleration circuit according to claim 1, characterized in that, The P1 is connected to the clock signal.

7. The operation acceleration circuit of the low-power and high-flexibility SSD main control chip according to claim 1, characterized in that The circuit is powered by 5V.

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