Bitstream verification method, device, equipment, storage medium and program product

Abstract

The present invention relates to the field of electronic design technology, and discloses a bitstream verification method, device, equipment, storage medium and program product. The present invention executes an execution file corresponding to a target test case to obtain a bitstream file and a routing file of the target test case; based on the bitstream file and the routing file, determines the configuration information of the target test case, and based on the configuration information, configures a test file of the target test case; based on the routing file, configures an input signal and a reference model corresponding to the target test case; based on the input signal, tests the test file and the reference model respectively to determine the bitstream verification result of the target test case. In this way, the simulation verification of the bitstream file of the target integrated circuit is deconstructed, and the simulation verification of the bitstream file is performed on each test unit in the target integrated circuit respectively. The simulation verification of the bitstream file is realized through the reference model, which simplifies the simulation of the bitstream file, further improves the simulation efficiency of the bitstream file, and shortens the simulation time.

Description

Technical Field

[0001] The present invention relates to the field of electronic design technology, and in particular to a bitstream verification method, device, equipment, storage medium and program product. Background Art

[0002] In the FPGA (Field Programmable Gate Array) design process, users typically define circuits using hardware description languages ​​such as VHDL and Verilog. Synthesis tools are then used to generate a bitstream file for loading into the FPGA. This bitstream file determines the configuration of the FPGA's internal resources and directly impacts system performance and power consumption. Therefore, verifying the correctness of the bitstream file is crucial to ensure proper circuit functionality. However, due to the complex internal structure of FPGAs, simulating bitstream files can be time-consuming and inefficient. Summary of the Invention

[0003] In view of this, the present invention provides a bitstream verification method, apparatus, device, storage medium and program product to solve the problems of low simulation efficiency and long time required for bitstream files.

[0004] In a first aspect, the present invention provides a bitstream verification method applied to a field programmable gate array circuit, the method comprising:

[0005] Execute the execution file corresponding to the target test case to obtain the bit stream file and routing file of the target test case; the target test case is the test case corresponding to the target test unit in the target integrated circuit;

[0006] Determine configuration information of a target test case based on the bitstream file and the routing file, and configure a test file of the target test case based on the configuration information;

[0007] Based on the routing file, configure the input signal and reference model corresponding to the target test case;

[0008] Based on the input signal, the test file and the reference model are tested respectively to determine the bitstream verification result of the target test case.

[0009] In an optional implementation, determining the configuration information of the target test case based on the bitstream file and the routing file includes:

[0010] Get the first coordinate of the target test case from the routing file;

[0011] Transform the first coordinate to obtain the second coordinate;

[0012] Based on the second coordinate, configuration information is obtained from the bitstream file.

[0013] In an optional implementation, configuring the input signal and reference model corresponding to the target test case based on the routing file includes:

[0014] Search the routing file to obtain the input signal corresponding to the target test case;

[0015] Assigning a value to the input signal based on a signal type of the input signal to configure the input signal;

[0016] A reference model is constructed based on the association between output signals and input signals in the routing file.

[0017] In an optional embodiment, based on the input signal, testing the test file and the reference model respectively to determine the bitstream verification result of the target test case includes:

[0018] Based on the input signal, a simulation test is performed on the test file to obtain a first output signal;

[0019] Inputting the input signal into the reference model to obtain a second output signal;

[0020] The first output signal is compared with the second output signal to obtain a bit stream verification result.

[0021] In an optional embodiment, comparing the first output signal with the second output signal to obtain a bit stream verification result includes:

[0022] If the first output signal is consistent with the second output signal, then determining that the bit stream verification result is that the bit stream configuration is correct;

[0023] If the first output signal is inconsistent with the second output signal, it is determined that the bit stream verification result is a bit stream configuration error.

[0024] In an optional embodiment, the method further includes:

[0025] Splitting the logic unit included in the target integrated circuit to obtain a plurality of target test units;

[0026] Test cases corresponding to the multiple target test units are written respectively to obtain multiple target test cases and execution files corresponding to the multiple target test cases.

[0027] In a second aspect, the present invention provides a bit stream verification device for use in a field programmable gate array circuit, the device comprising:

[0028] A test case execution module is used to execute the execution file corresponding to the target test case to obtain the bit stream file and routing file of the target test case; the target test case is the test case corresponding to the target test unit in the target integrated circuit;

[0029] A test file configuration module, configured to determine configuration information of a target test case based on the bitstream file and the routing file, and configure a test file of the target test case based on the configuration information;

[0030] The reference model configuration module is used to configure the input signal and reference model corresponding to the target test case based on the routing file;

[0031] The verification result determination module is used to test the test file and the reference model based on the input signal and determine the bit stream verification result of the target test case.

[0032] In a third aspect, the present invention provides a computer device comprising: a memory and a processor, the memory and the processor being communicatively connected to each other, computer instructions being stored in the memory, and the processor executing the bitstream verification method of the first aspect or any corresponding embodiment thereof by executing the computer instructions.

[0033] In a fourth aspect, the present invention provides a computer-readable storage medium having computer instructions stored thereon, the computer instructions being used to enable a computer to execute the bitstream verification method of the first aspect or any corresponding embodiment thereof.

[0034] In a fifth aspect, the present invention provides a computer program product comprising computer instructions, wherein the computer instructions are used to enable a computer to execute the bitstream verification method of the first aspect or any corresponding embodiment thereof.

[0035] The bitstream verification method provided by the present invention verifies the bitstream files of each target test unit in the target integrated circuit respectively by executing the test cases corresponding to the target test units in the target integrated circuit, thereby deconstructing the simulation verification of the bitstream files of the target integrated circuit, and performing simulation verification of the bitstream files on each test unit in the target integrated circuit respectively, thereby improving the simulation efficiency of the bitstream files and shortening the simulation time; at the same time, by configuring the test files, input signals and reference models corresponding to the target test cases, the simulation verification of the bitstream files is realized, thereby simplifying the simulation of the bitstream files, further improving the simulation efficiency of the bitstream files and shortening the simulation time. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0037] Figure 1 is a flowchart of a bitstream verification method according to an embodiment of the present invention;

[0038] Figure 2 is a flow chart of another flow verification method according to an embodiment of the present invention;

[0039] Figure 3 is a flowchart of another bitstream verification method according to an embodiment of the present invention;

[0040] Figure 4 is a flow chart of another bitstream verification method according to an embodiment of the present invention;

[0041] Figure 5 is a structural block diagram of a bitstream verification device according to an embodiment of the present invention;

[0042] Figure 6 Schematic diagram of the hardware structure of a computer device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0043] To make the purpose, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative efforts shall fall within the scope of protection of the present invention.

[0044] In the FPGA (Field Programmable Gate Array) design process, users typically define circuits using hardware description languages ​​such as VHDL and Verilog. Synthesis tools are then used to generate a bitstream file for loading into the FPGA. This bitstream file determines the configuration of the FPGA's internal resources and directly impacts system performance and power consumption. Therefore, verifying the correctness of the bitstream file is crucial to ensure proper circuit functionality. However, due to the complex internal structure of FPGAs, simulating bitstream files can be time-consuming and inefficient.

[0045] Based on this, an embodiment of the present invention provides a bitstream verification method, which executes an execution file corresponding to a target test case to obtain a bitstream file and a routing file of the target test case; the target test case is a test case corresponding to a target test unit in a target integrated circuit; based on the bitstream file and the routing file, configuration information of the target test case is determined, and based on the configuration information, a test file of the target test case is configured; based on the routing file, an input signal and a reference model corresponding to the target test case are configured; based on the input signal, the test file and the reference model are tested respectively to determine the bitstream verification result of the target test case. In this way, by executing the test case corresponding to the target test unit in the target integrated circuit, the bitstream file of each target test unit in the target integrated circuit is verified respectively, thereby deconstructing the simulation verification of the bitstream file of the target integrated circuit, and performing simulation verification of the bitstream file on each test unit in the target integrated circuit respectively, thereby improving the simulation efficiency of the bitstream file and shortening the simulation time; at the same time, by configuring the test file, input signal and reference model corresponding to the target test case, simulation verification of the bitstream file is realized, thereby simplifying the simulation of the bitstream file, further improving the simulation efficiency of the bitstream file and shortening the simulation time.

[0046] According to an embodiment of the present invention, an embodiment of a bitstream verification method is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0047] In this embodiment, a bit stream verification method is provided, which can be used in a field programmable gate array circuit. Figure 1 is a flowchart of a bit stream verification method according to an embodiment of the present invention. Figure 1 As shown, the process includes the following steps:

[0048] Step S101: execute the execution file corresponding to the target test case to obtain the bit stream file and routing file of the target test case.

[0049] In an embodiment of the present invention, the target test case is a test case corresponding to a target test unit in a target integrated circuit; the target integrated circuit is an integrated circuit that needs to be simulated and verified by a bitstream file, and the logic units contained in the target integrated circuit are all target test units. That is to say, the simulation of the bitstream file of the target integrated circuit is split according to the logic units contained therein, and the bitstream file of the target integrated circuit is simulated by simulating the bitstream file of the logic units contained therein.

[0050] In an embodiment of the present invention, the executable file corresponding to the target test case is used to execute design and configuration-related processes in EDA software, such as synthesis, mapping, placement, routing, and bitgen, to obtain the bitstream file, routing file, and wiring file corresponding to the target test case. The bitstream file contains all the configuration information of the target integrated circuit, such as logic cell configuration, wiring resources, and I / O configuration; the routing file and wiring file contain the specific wiring information between the logic cells in the target integrated circuit.

[0051] In an optional embodiment, to simulate a bitstream file of a target integrated circuit, the present invention decomposes the logic units included in the target integrated circuit to obtain multiple target test units. Test cases corresponding to the multiple target test units are then written to obtain multiple target test cases and execution files corresponding to the multiple target test cases. The execution files corresponding to the obtained multiple target test cases are then executed to simulate and verify the multiple target test cases, obtain bitstream verification results for the multiple target test cases, and obtain a bitstream verification result for the target integrated circuit based on the bitstream verification results for the multiple target test cases.

[0052] Step S102 : determining configuration information of a target test case based on the bitstream file and the routing file, and configuring a test file of the target test case based on the configuration information.

[0053] In an embodiment of the present invention, the configuration information of the target test case is located based on the bitstream file and the routing file, and the configuration information of the target test case is extracted. The test file of the target test case is configured based on the extracted configuration information, and the bitstream file of the target test case is simulated and tested according to the test file of the target test case.

[0054] Step S103: Based on the routing file, configure the input signal and reference model corresponding to the target test case.

[0055] In this embodiment of the present invention, a routing file is searched to extract the input and output signals corresponding to the target test case. A reference model is then constructed based on the input and output signals. The reference model is used as a comparison reference for simulation verification of the target test case, and the output of the reference model is used as the correct output of the simulation test of the target test case, thereby verifying the correctness of the simulation test results of the target test case.

[0056] Step S104 : Based on the input signal, the test file and the reference model are tested respectively to determine the bitstream verification result of the target test case.

[0057] In an embodiment of the present invention, the configured input signal is input to the test file and the reference model respectively, so that the test file and the reference model are simulated and tested respectively, and the actual simulation output results of the target test case and the simulation results as a reference comparison are obtained. The two are compared to determine the bit stream verification result of the target test case.

[0058] In an optional embodiment, simulation tests are performed on the target test cases corresponding to each target test unit in the target integrated circuit to obtain the bitstream verification results of each target test unit, and the bitstream verification results of the target integrated circuit are determined based on the bitstream verification results of each target test unit.

[0059] The bitstream verification method provided by an embodiment of the present invention verifies the bitstream files of each target test unit in the target integrated circuit by executing the test cases corresponding to the target test units in the target integrated circuit, thereby deconstructing the simulation verification of the bitstream files of the target integrated circuit, and performing simulation verification of the bitstream files on each test unit in the target integrated circuit, thereby improving the simulation efficiency of the bitstream files and shortening the simulation time; at the same time, by configuring the test files, input signals and reference models corresponding to the target test cases, the simulation verification of the bitstream files is realized, thereby simplifying the simulation of the bitstream files, further improving the simulation efficiency of the bitstream files and shortening the simulation time.

[0060] In this embodiment, a bit stream verification method is provided, which can be used in a field programmable gate array circuit. Figure 2 is a flow chart of another flow verification method according to an embodiment of the present invention. Figure 2 As shown, the process includes the following steps:

[0061] Step S201: execute the execution file corresponding to the target test case to obtain the bitstream file and routing file of the target test case. Figure 1 Step S101 of the illustrated embodiment will not be described in detail here.

[0062] Step S202 : determining configuration information of a target test case based on the bitstream file and the routing file, and configuring a test file of the target test case based on the configuration information.

[0063] Specifically, step S202 includes:

[0064] Step S2021: Obtain the first coordinate corresponding to the target test case from the routing file.

[0065] In the embodiment of the present invention, the routing file is searched to find the coordinates corresponding to the target test unit, ie, the first coordinates. The first coordinates are extracted to further determine the coordinates of the configuration information of the target test unit in the bitstream file.

[0066] Step S2022: convert the first coordinate to obtain the second coordinate.

[0067] In the embodiment of the present invention, after the first coordinates are acquired, the first coordinates are converted according to a preset coordinate conversion algorithm to obtain the coordinates of the configuration information of the target test unit in the bitstream file, ie, the second coordinates.

[0068] Step S2023: Obtain configuration information from the bitstream file based on the second coordinate.

[0069] In the embodiment of the present invention, the relevant information at the second coordinate is searched and extracted from the bit stream file to obtain the configuration information of the target test unit.

[0070] Step S203: Based on the routing file, configure the input signal and reference model corresponding to the target test case. Figure 1 Step S103 of the illustrated embodiment will not be described in detail here.

[0071] Step S204: Based on the input signal, the test file and the reference model are tested respectively to determine the bitstream verification result of the target test case. Figure 1 Step S104 of the illustrated embodiment will not be described in detail here.

[0072] In this embodiment, a bit stream verification method is provided, which can be used in a field programmable gate array circuit. Figure 3 FIG. 1 is a flowchart of another bitstream verification method according to an embodiment of the present invention. Figure 3 As shown, the process includes the following steps:

[0073] Step S301: Execute the execution file corresponding to the target test case to obtain the bitstream file and routing file of the target test case. Figure 1 Step S101 of the illustrated embodiment will not be described in detail here.

[0074] Step S302: Determine the configuration information of the target test case based on the bitstream file and the routing file, and configure the test file of the target test case based on the configuration information. Figure 1 Step S102 of the illustrated embodiment will not be described in detail here.

[0075] Step S303: Based on the routing file, configure the input signal and reference model corresponding to the target test case.

[0076] Specifically, step S303 includes:

[0077] Step S3031: search the routing file to obtain the input signal corresponding to the target test case.

[0078] In the embodiment of the present invention, the routing file is searched to determine the target test case, that is, the signal name of the input signal corresponding to the target test unit, thereby determining the input signal corresponding to the target test case.

[0079] Step S3032: assigning a value to the input signal based on the signal type of the input signal to configure the input signal.

[0080] In the embodiment of the present invention, the input signal assignment method varies depending on the signal type of the input signal. The input signal assignment method is determined based on the signal type of the input signal, and the input signal is assigned a value according to the assignment method, thereby completing the configuration of the input signal.

[0081] In an optional implementation, when assigning and configuring input signals, taking into account specific conditions or constraints that the input signals must meet, test boundary conditions and extreme signal values ​​can be set for the input signals, as well as corresponding signal values ​​configured according to different functional modes. This ensures that the configured input signals meet the simulation verification requirements for all functional modes of the target test unit. Furthermore, a random assignment method can be used to generate multiple sets of input signals to cover a variety of test scenarios.

[0082] Step S3033: construct a reference model based on the association relationship between the output signal and the input signal in the routing file.

[0083] In an embodiment of the present invention, the routing file contains the logical function of the corresponding target test unit, which represents the operation that the input signal undergoes after inputting the target test unit to obtain the output signal. Based on the logical function of the target test unit in the routing file, the correlation between the output signal and the input signal is obtained, and a reference model is constructed based on this correlation; that is, the input of the reference model is consistent with the input signal of the target test unit, and the output of the reference model is consistent with the output signal of the target test unit. As a result, the output of the reference model can fully represent the output of the target test unit, making the simulation verification of the bitstream file of the target test unit using the output of the reference model as a reference more reliable and accurate.

[0084] Step S304: Based on the input signal, test the test file and the reference model respectively to determine the bitstream verification result of the target test case. Figure 1 Step S104 of the illustrated embodiment will not be described in detail here.

[0085] In this embodiment, a bit stream verification method is provided, which can be used in a field programmable gate array circuit. Figure 4 FIG. 1 is a flowchart of another bitstream verification method according to an embodiment of the present invention. Figure 4 As shown, the process includes the following steps:

[0086] Step S401: Execute the execution file corresponding to the target test case to obtain the bitstream file and routing file of the target test case. Figure 1 Step S101 of the illustrated embodiment will not be described in detail here.

[0087] Step S402: Determine the configuration information of the target test case based on the bitstream file and the routing file, and configure the test file of the target test case based on the configuration information. Figure 1 Step S102 of the illustrated embodiment will not be described in detail here.

[0088] Step S403: Based on the routing file, configure the input signal and reference model corresponding to the target test case. Figure 1 Step S103 of the illustrated embodiment will not be described in detail here.

[0089] Step S404: Based on the input signal, the test file and the reference model are tested respectively to determine the bitstream verification result of the target test case.

[0090] Specifically, step S404 includes:

[0091] Step S4041: Based on the input signal, perform a simulation test on the test file to obtain a first output signal.

[0092] In an embodiment of the present invention, configuration information of a test file is loaded into a top-level file of a simulation platform of EDA software, and a simulation test is performed on the test file based on an input signal, thereby obtaining a first output signal.

[0093] Step S4042: input the input signal into the reference model to obtain a second output signal.

[0094] In the embodiment of the present invention, the input signal is input into the reference model to obtain the output of the reference model, which is the second output signal.

[0095] Step S4043: Compare the first output signal with the second output signal to obtain a bit stream verification result.

[0096] In the embodiment of the present invention, if the first output signal is consistent with the second output signal, the bitstream verification result is determined to be a correct bitstream configuration; if the first output signal is inconsistent with the second output signal, the bitstream verification result is determined to be an incorrect bitstream configuration.

[0097] In an optional embodiment, if the bitstream verification result of a target test unit in the target integrated circuit is a bitstream configuration error, then the bitstream simulation of the target integrated circuit is determined to have failed. In this case, the target test unit with the bitstream configuration error is the source of the target integrated circuit bitstream simulation failure. Therefore, the problem of the target test unit with the bitstream verification result of the bitstream configuration error can be located, thereby quickly determining the cause of the target integrated circuit bitstream simulation failure. If the bitstream verification results of all target test units in the target integrated circuit are bitstream configuration correct, then it is determined that the target integrated circuit has passed the bitstream simulation.

[0098] In this embodiment, a bitstream verification device is also provided, which is used to implement the above-mentioned embodiments and preferred embodiments. The details that have been described will not be repeated here. As used below, the term "module" can be a combination of software and / or hardware that implements a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, implementation by hardware, or a combination of software and hardware, is also possible and contemplated.

[0099] This embodiment provides a bit stream verification device, which is applied to a field programmable gate array circuit, such as Figure 5 Shown, including:

[0100] The test case execution module 501 is used to execute the execution file corresponding to the target test case to obtain the bit stream file and routing file of the target test case; the target test case is the test case corresponding to the target test unit in the target integrated circuit;

[0101] A test file configuration module 502 is configured to determine configuration information of a target test case based on the bitstream file and the routing file, and configure a test file of the target test case based on the configuration information;

[0102] The reference model configuration module 503 is used to configure the input signal and reference model corresponding to the target test case based on the routing file;

[0103] The verification result determination module 504 is configured to test the test file and the reference model based on the input signal, and determine the bitstream verification result of the target test case.

[0104] In an optional embodiment, the test file configuration module 502 includes:

[0105] A first coordinate obtaining unit, configured to obtain a first coordinate corresponding to a target test case from a routing file;

[0106] A coordinate conversion unit, configured to convert the first coordinate to obtain a second coordinate;

[0107] The configuration information acquiring unit is configured to acquire the configuration information from the bit stream file based on the second coordinate.

[0108] In an optional implementation, the reference model configuration module 503 includes:

[0109] An input signal acquisition unit is used to search the routing file and obtain the input signal corresponding to the target test case;

[0110] an input signal configuration unit, configured to assign a value to the input signal based on a signal type of the input signal to configure the input signal;

[0111] The reference module construction unit is used to construct a reference model based on the association relationship between the output signal and the input signal in the routing file.

[0112] In an optional implementation, the verification result determination module 504 includes:

[0113] A test file simulation unit, configured to perform a simulation test on the test file based on an input signal to obtain a first output signal;

[0114] a reference model simulation unit, configured to input an input signal into the reference model to obtain a second output signal;

[0115] The output signal comparison unit is used to compare the first output signal with the second output signal to obtain a bit stream verification result.

[0116] In an optional embodiment, the output signal comparison unit is configured to:

[0117] If the first output signal is consistent with the second output signal, then determining that the bit stream verification result is that the bit stream configuration is correct;

[0118] If the first output signal is inconsistent with the second output signal, it is determined that the bit stream verification result is a bit stream configuration error.

[0119] In an optional embodiment, the device further includes:

[0120] a logic unit splitting unit, configured to split the logic unit included in the target integrated circuit to obtain a plurality of target test units;

[0121] The test case acquisition unit is used to write test cases corresponding to multiple target test units respectively, and obtain multiple target test cases and execution files corresponding to the multiple target test cases.

[0122] The further functional description of each of the above modules and units is the same as that of the above corresponding embodiments and will not be repeated here.

[0123] The bitstream verification device in this embodiment is presented in the form of a functional unit, where the unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that executes one or more software or fixed programs, and / or other devices that can provide the above functions.

[0124] The embodiment of the present invention also provides a computer device having the above Figure 5 The bitstream verification device shown.

[0125] See also Figure 6 , Figure 6 is a structural diagram of a computer device provided by an optional embodiment of the present invention, such as Figure 6 As shown, the computer device includes: one or more processors 10, memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. Various components utilize different buses to communicate with each other and can be installed on a common mainboard or installed in other ways as needed. The processor can process the instructions executed in the computer device, including instructions stored in the memory or on the memory to display the graphical information of the GUI on an external input / output device (such as, a display device coupled to the interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Equally, multiple computer devices can be connected, and each device provides part of the necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). Figure 6 A processor 10 is taken as an example.

[0126] The processor 10 may be a central processing unit, a network processor, or a combination thereof. The processor 10 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit, a programmable logic device, or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic, or any combination thereof.

[0127] The memory 20 stores instructions that can be executed by at least one processor 10, so that the at least one processor 10 executes the method shown in the above embodiment.

[0128] The memory 20 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and application programs required for at least one function; the data storage area may store data created based on the use of the computer device, etc. In addition, the memory 20 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory 20 may optionally include a memory remotely located relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0129] The memory 20 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid-state drive; the memory 20 may also include a combination of the above types of memory.

[0130] The computer device further includes a communication interface 30 for the computer device to communicate with other devices or a communication network.

[0131] The embodiment of the present invention also provides a computer-readable storage medium. The above-mentioned method according to the embodiment of the present invention can be implemented in hardware, firmware, or implemented as a computer code that can be recorded in a storage medium, or implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and downloaded through a network and will be stored in a local storage medium, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state drive, etc.; further, the storage medium can also include a combination of the above-mentioned types of memory. It can be understood that a computer, a processor, a microprocessor controller or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor or hardware, the method shown in the above embodiment is implemented.

[0132] A portion of the present invention may be applied as a computer program product, such as a computer program instruction, which, when executed by a computer, can call or provide the method and / or technical solution according to the present invention through the operation of the computer. Those skilled in the art should understand that the form in which the computer program instruction exists in a computer-readable medium includes, but is not limited to, a source file, an executable file, an installation package file, etc. Accordingly, the way in which the computer program instruction is executed by the computer includes, but is not limited to: the computer directly executes the instruction, or the computer compiles the instruction and then executes the corresponding compiled program, or the computer reads and executes the instruction, or the computer reads and installs the instruction and then executes the corresponding installed program. Here, the computer-readable medium may be any available computer-readable storage medium or communication medium that can be accessed by the computer.

[0133] Although the embodiments of the present invention have been described with reference to the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention. Such modifications and variations are all within the scope defined by the present invention.

Claims

1. A bit stream verification method, characterized in that: Applied to a field programmable gate array circuit, the method comprises: Executing an execution file corresponding to a target test case to obtain a bitstream file and a routing file of the target test case; the target test case is a test case corresponding to a target test unit in a target integrated circuit; Determining the configuration information of the target test case based on the bitstream file and the routing file, and configuring the test file of the target test case based on the configuration information; determining the configuration information of the target test case based on the bitstream file and the routing file includes: obtaining first coordinates corresponding to the target test case from the routing file, wherein the first coordinates are coordinates corresponding to the target test unit in the routing file; converting the first coordinates according to a preset coordinate conversion algorithm to obtain second coordinates, wherein the second coordinates are coordinates of the configuration information of the target test unit in the bitstream file; and obtaining the configuration information from the bitstream file based on the second coordinates; Configuring the input signal and reference model corresponding to the target test case based on the routing file; configuring the input signal and reference model corresponding to the target test case based on the routing file, including: searching the routing file to obtain the input signal corresponding to the target test case; assigning a value to the input signal based on the signal type of the input signal to configure the input signal; and constructing the reference model based on the association relationship between the output signal and the input signal in the routing file; Based on the input signal, the test file and the reference model are tested respectively to determine a bitstream verification result of the target test case.

2. The method according to claim 1, characterized in that The testing of the test file and the reference model based on the input signal to determine the bitstream verification result of the target test case includes: Based on the input signal, a simulation test is performed on the test file to obtain a first output signal; Inputting the input signal into the reference model to obtain a second output signal; The first output signal is compared with the second output signal to obtain the bit stream verification result.

3. The method according to claim 2, characterized in that The comparing the first output signal with the second output signal to obtain the bit stream verification result includes: If the first output signal is consistent with the second output signal, determining that the bit stream verification result is that the bit stream configuration is correct; If the first output signal is inconsistent with the second output signal, it is determined that the bit stream verification result is a bit stream configuration error.

4. The method according to claim 1, wherein The method further comprises: Splitting the logic unit included in the target integrated circuit to obtain a plurality of target test units; Test cases corresponding to the plurality of target test units are written respectively to obtain the plurality of target test cases and the execution files corresponding to the plurality of target test cases.

5. A bit stream verification device, characterized in that: Applied to a field programmable gate array circuit, the device comprises: A test case execution module is configured to execute an execution file corresponding to a target test case to obtain a bitstream file and a routing file of the target test case; the target test case is a test case corresponding to a target test unit in a target integrated circuit; A test file configuration module, configured to determine the configuration information of the target test case based on the bitstream file and the routing file, and configure the test file of the target test case based on the configuration information; the determining the configuration information of the target test case based on the bitstream file and the routing file includes: obtaining first coordinates corresponding to the target test case from the routing file, wherein the first coordinates are coordinates corresponding to the target test unit in the routing file; converting the first coordinates according to a preset coordinate conversion algorithm to obtain second coordinates, wherein the second coordinates are coordinates of the configuration information of the target test unit in the bitstream file; and obtaining the configuration information from the bitstream file based on the second coordinates; A reference model configuration module is configured to configure the input signal and reference model corresponding to the target test case based on the routing file; configuring the input signal and reference model corresponding to the target test case based on the routing file includes: searching the routing file to obtain the input signal corresponding to the target test case; assigning a value to the input signal based on the signal type of the input signal to configure the input signal; and constructing the reference model based on the association relationship between the output signal and the input signal in the routing file; The verification result determination module is used to test the test file and the reference model respectively based on the input signal to determine the bitstream verification result of the target test case.

6. A computer device, characterized in that: include: A memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the bitstream verification method according to any one of claims 1 to 4 by executing the computer instructions.

7. A computer-readable storage medium, characterized in that The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a computer to execute the bit stream verification method according to any one of claims 1 to 4.

8. A computer program product, characterized in that The method comprises computer instructions for causing a computer to execute the bit stream verification method according to any one of claims 1 to 4.

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