Combination logic clustering optimization method and system based on reinforcement learning

Abstract

The invention discloses a combinational logic clustering optimization method and system based on reinforcement learning. The method comprises the following steps: S1, counting fan-out information of registers and combinational logic units in a circuit netlist; s2, according to the fan-out information, screening out registers and combinational logic units of which the fan-out quantity is greater than a first preset threshold and the worst time sequence path time sequence violation value of the output signal is smaller than a second preset threshold, and generating a target unit list; s3, acquiring fan-out combinational logic information of each unit in the target unit list; s4, on the basis of the fan-out combinatorial logic information, clustering operation is carried out on fan-out logic units on the basis of a reinforcement learning algorithm; s5, after logic clustering is completed, revising the netlist of the circuit; after the revision is completed, carrying out equivalence check; and S6, rearranging and wiring the circuit according to the modified netlist. The method can effectively reduce key path delay, optimizes circuit performance, and is especially suitable for large-scale integrated circuit design.

Description

Technical Field

[0001] The present invention mainly relates to the field of integrated circuit design, and particularly relates to a method and system for optimizing combinational logic clustering based on reinforcement learning. Background Art

[0002] In digital circuit design, the in-depth optimization of critical paths is an important guarantee for improving design frequency and design performance. As the integrated circuit process nodes continue to shrink, the circuit scale and complexity increase sharply, and the high fan-out (HFO) registers or combinational logic on critical paths often become the difficulties in timing optimization. Currently, commercial electronic design automation (EDA) tools widely use inverter or buffer insertion technology to optimize the timing paths of high fan-out registers. However, this traditional method has significant defects in practical applications, which are specifically manifested in the following two aspects: (1) Unreasonable positions and quantities of inverter / buffer insertion Commercial EDA tools usually insert inverters / buffers based on fixed rules or heuristic algorithms. For example, during global optimization, the tool may blindly insert inverters / buffers into non-critical paths, resulting in waste of area and power consumption; while on critical paths, due to the lack of in-depth analysis of the correlation of logic structures and physical layouts, the insertion quantity is insufficient or the position distribution is uneven, and the signal transmission delay cannot be effectively shortened. In addition, the traditional method lacks the ability to dynamically adjust the insertion quantity of inverters / buffers, making it difficult to meet the requirements of high-performance designs, and it is easy to cause wiring congestion and increased delay due to excessive insertion.

[0003] (2) Lack of intelligent optimization ability in the existing technology Traditional methods rely on static rules or empirical formulas and cannot adaptively adjust optimization strategies according to information such as the functional correlation of circuit logic units, physical layout density, and signal timing delay, resulting in phenomena such as routing conflicts and increased timing delay in the multi-objective optimization of inserted inverters / buffers due to factors such as grouping and position.

[0004] In recent years, reinforcement learning (RL) technology has shown significant advantages in complex decision-making problems. Reinforcement learning can effectively solve high-dimensional and multi-constrained optimization problems by interacting with the environment and dynamically adjusting strategies based on feedback rewards. In the field of timing optimization, some studies have tried to apply reinforcement learning to the layout and routing stages, but its application is still limited to local adjustments and has not been deeply combined with the collaborative optimization of logic structure clustering and inverter / buffer insertion. Therefore, there is an urgent need for an intelligent optimization method based on reinforcement learning to solve the inherent defects of traditional inverter / buffer insertion technology and achieve precise optimization of critical path timing. Summary of the Invention

[0005] In view of the technical problems existing in the prior art, the present invention provides a combination logic clustering optimization method and system based on reinforcement learning for realizing efficient optimization of the critical path timing.

[0006] To solve the above technical problems, the technical solution proposed by the present invention is as follows: A combination logic clustering optimization method based on reinforcement learning, comprising the steps of: S1. Stat the fan-out information of the registers and combinational logic units in the circuit netlist; S2. According to the fan-out information in step S1, filter out the registers and combinational logic units whose fan-out quantity is greater than the first preset threshold and the worst timing path timing violation value of the output signal is less than the second preset threshold, and generate a target unit list; S3. Obtain the fan-out combinational logic information of each unit in the target unit list; S4. Based on the fan-out combinational logic information, perform clustering operations on the fan-out logic units respectively based on the reinforcement learning algorithm; S5. After completing the logic clustering, revise the circuit netlist; after the revision is completed, perform equivalence checking; S6. Re-layout and route the circuit according to the modified netlist.

[0007] Preferably, the specific steps of S1 are as follows: S101. Traverse all the registers and combinational logic units in the circuit netlist, and record the output signals of each unit; S102. Analyze the fan-out situation of the output signals of each unit, including buffers, inverters and combinational logic units, add the combinational logic units to the list list1, and add the buffers and inverters to the list list2; S103. Recursively analyze the fan-out situation of the output signals of the buffers and inverters. For each buffer or inverter in the list list2, traverse to find all the directly fan-out combinational logic units and add them to list1, then traverse to find all the directly fan-out buffers and inverters; recursively find all the finally fan-out combinational logic units and add them to list1; S104. Stat the fan-out quantity of each register and combinational logic unit, and generate a fan-out information table.

[0008] Preferably, the specific steps of S3 are as follows: For each cell in the target cell list, obtain all the logic cells son_cells of the output signal fan-out; traverse son_cells, if the cell type is not a buffer or an inverter, add the cell name, the corresponding input pin, and the cell location information to the list f0_list; if the cell type is a buffer or an inverter, recursively search for all the first-occurring non-buffer and non-inverter logic cells, and then add the cell name, the corresponding input pin, and the cell location information to the list f0_list and the list f1_list respectively according to the phase.

[0009] Preferably, the specific steps of S4 include: S401. According to the logic effect and the fan-out constraint, specify the size of the clustering cluster, denoted as Knum; S402. Define the state space and the action space: The state space is the mathematical representation of the clustering cluster, and the action space contains 3 types of actions: changing the clustering cluster belonging of elements, adding a new clustering cluster, and deleting a clustering cluster. S403. Define the reward function based on the timing factor and the distance factor; S404. Initialize the number of clustering clusters and the corresponding center coordinates; S405. Initialize the clustering clusters; S406. Optimize the clustering clusters by reinforcement learning: Use the initial clustering clusters as the initial state space, optimize through reinforcement learning, and stop when the optimization result meets the expectation, and use the final state as the final clustering result; S407. Record the clustering cluster information: Record the final clustering number final_cl_num corresponding to each cell in the target cell list targetr_list, and the element list in each clustering.

[0010] Preferably, the specific steps of S404 are: For each cell in the target cell list target_list, calculate the multiple relationship between the number of elements in the corresponding lists f0_list and f1_list and the size Knum of the clustering cluster, and use the rounded-down value rounddown(size(f0_list) / Knum) as the initial number i0_cl_num of the clustering clusters corresponding to the list f0_list, where rounddown represents the floor function and size represents the function to calculate the number of elements in a set; Randomly select Knum cells from the list f0_list, calculate the mean of their physical positions, and use it as the initial value of the center coordinates of the current clustering cluster. Repeat this process i0_cl_num times to obtain all the initial values of the center coordinates of the clustering clusters.

[0011] Preferably, the specific steps of S405 are: Traverse each cell in list f0_list and list f1_list, and calculate the Manhattan distance between its physical position and the initial coordinates of the center of each clustering cluster in turn. Classify the cell into the clustering cluster with the shortest Manhattan distance, and then recalculate the mean value of the physical positions of the logical cells in each clustering cluster, and use this mean value to update the center coordinates of the clustering cluster.

[0012] Preferably, the specific steps of S5 are as follows: S501. For each cell cell0 in the target cell list target_list and its corresponding clustering cluster, first disconnect the original connections of the input pins pin of the cells within the clustering cluster; S502. For each clustering cluster, judge its phase relationship with the phase output by cell0: If the clustering cluster is in phase with the output of cell0, insert a buffer between the output of cell0 and the clustering cluster, and connect the output of the buffer to the input pins pin of the cells within the clustering cluster; If the clustering cluster is out of phase with the register output, insert an inverter and connect the output of the inverter to the input pins pin of the cells within the clustering cluster; S503. Connect the input of the inserted buffer or inverter to the output of cell0, and delete other inverter or buffer loads on the register output; S504. Save the modified netlist; S505. Perform equivalence checking; if the check passes, end; otherwise, return to S502 to correct the connection relationship.

[0013] The present invention also discloses a combinational logic clustering optimization system based on reinforcement learning, including a memory and a processor connected to each other. A computer program is stored on the memory, and the computer program executes the steps of the above-mentioned method when being run by the processor.

[0014] Compared with the prior art, the advantages of the present invention are as follows: Through steps such as statistically registering and combinational logic fan-out information, generating a target cell list, obtaining target cell fan-out combinational logic information, implementing reinforcement learning-driven combinational logic clustering, revising the netlist and performing equivalence checking, and using the new netlist for placement and routing, the present invention realizes critical path timing optimization and circuit performance improvement. The present invention can effectively reduce the critical path delay and optimize the circuit performance, and is especially suitable for large-scale integrated circuit design.

[0015] The combinational logic clustering optimization method based on reinforcement learning of the present invention can automatically identify critical timing paths by statistically collecting the fan-out information of all units including registers and combinational logic and generating a list of target units, and perform clustering by means of reinforcement learning, and then perform inverter or buffer insertion operations based on the clustering information, effectively avoiding the problem of unreasonable inverter or buffer insertion, thereby improving the critical path delay of large fan-out classes. The present invention implements logic clustering based on reinforcement learning, enabling inverters or buffers to drive nearby in physical layout, effectively reducing the timing path length in critical paths of large fan-out classes, thereby improving the performance of the circuit, and is particularly suitable for large-scale integrated circuit design.

[0016] The present invention introduces reinforcement learning technology to propose a new solution to the two major defects of existing commercial EDA tools in dealing with large fan-out units, namely, unreasonable inverter / buffer insertion positions and insufficient consideration of physical factors. The present invention can accurately locate the list of large fan-out units on critical paths, combines reinforcement learning with clustering, effectively considers the influence of physical factors, shortens the critical path distance, reduces the signal propagation delay and the risk of routing congestion. The present invention has high reliability and ensures that the optimized circuit functions are consistent through equivalence checking. The combinational logic clustering optimization method and system based on reinforcement learning support integration with mainstream EDA tools and are applicable to large-scale circuit design. Under a certain sub-20 nanometer process, implementing this method on a certain core module reduces the maximum setup timing violation by 13 ps and the number of timing violations by 12.3%, greatly improving the design performance. The advantage of this method also lies in its scalability to other optimization scenarios. Brief Description of the Drawings

[0017] Figure 1 It is a flowchart of the combinational logic clustering optimization method based on reinforcement learning provided by an embodiment of the present invention.

[0018] Figure 2 It is a flowchart of the combinational logic clustering driven by reinforcement learning provided by an embodiment of the present invention.

[0019] Figure 3 It is a flowchart of the primary combinational logic clustering provided by an embodiment of the present invention.

[0020] Figure 4 It is a flowchart of the netlist modification after clustering provided by an embodiment of the present invention. Detailed Description of the Invention

[0021] The present invention will be further described below in conjunction with the accompanying drawings of the specification and specific embodiments.

[0022] As Figure 1 shown, the combinational logic clustering optimization method based on reinforcement learning provided by an embodiment of the present invention includes the steps: S1. Statistically analyze the fan-out information of registers and combinational logic units in the circuit netlist. In the circuit netlist, registers and combinational logic units account for more than 90% of the total number of units.

[0023] S2. Generate a target cell list: Based on the fan-out information generated in S1 and the results of timing analysis, filter out the registers and combinational logic units that have a greater impact on the timing path to generate a target cell list. Specifically, for each register or combinational logic unit with a fan-out quantity exceeding the first preset threshold, check the timing violation value of the worst timing path of the output signal passing through this register or combinational logic unit. If it is lower than the second preset threshold, add it to the target cell list target_list.

[0024] S3. Obtain the fan-out combinational logic information of target cells: For each cell in the target cell list target_list, obtain all the logic units son_cells fanned out by the output signal. Traverse son_cells. If the cell type is not a buffer or an inverter, add the cell name, the corresponding input pin, and the cell location information to f0_list. If the cell type is a buffer or an inverter, recursively search for all the first-occurring non-buffer and non-inverter logic units (i.e., combinational logic units and sequential logic other than buffers and inverters) backward, and then add the cell name, the corresponding input pin, and the cell location information to list f0_list and list f1_list respectively according to the phase. S4. Implement reinforcement learning-driven combinational logic clustering: Based on the fan-out combinational logic information obtained in S3, perform clustering operations on the fanned-out logic units respectively based on the reinforcement learning algorithm. The clustering algorithm divides the logic units that are physically adjacent and have no negative impact on timing into the same clustering cluster according to the physical location relationship and timing relationship of the logic units. The clustered logic units can be regarded as a whole, which is convenient for subsequent optimization operations. S5. Revise the netlist and perform equivalence checking: After completing the logic clustering, revise the circuit netlist: associate the clustered logic units together and adjust their connection relationships. Through netlist revision, the physical distance of the timing path can be reduced, thereby optimizing the timing performance of the circuit. After the revision is completed, perform equivalence checking to ensure that the function of the modified circuit is consistent with the original circuit. S6. Use the new netlist for placement and routing: According to the revised netlist, re-perform placement and routing on the module. The re-placement and routing include steps such as placement, clock tree synthesis, global routing, and detailed routing. Among them, during the placement process, corresponding attributes need to be set so that the buffers / inverters inserted in S5 are not optimized, and the other processes remain the same as before.

[0025] In this embodiment, the specific steps of S1 include: S101. Traverse all registers and combinational logic units in the circuit and record the output signals of each unit. S102. Analyze the fan-out situation of the output signals of each unit, including buffers, inverters, and combinational logic units. Add the combinational logic units to the list list1, and add the buffers and inverters to list2. As Figure 2 shown, in this embodiment, for the combinational logic unit C0, add the combinational logic units C1 to C19 whose output signal Z fans out to list1, and then add the buffer Buf1 and the inverter Inv1 to list2. S103. Recursively analyze the fan-out situation of the output signals of the buffers and inverters. For each buffer or inverter in list2, traverse to find all the directly fanned-out combinational logic units and add them to list1. Then traverse to find all the directly fanned-out buffers and inverters, and recursively find all the finally fanned-out combinational logic units and add them to list1. As Figure 2 shown, in this embodiment, for the inverter Inv1, find all the combinational logic units D1 to D27 whose output signal fans out and add them to list1. For the buffer Buf1, its direct fan-out is an inverter Inv2 and combinational logic units E1 to E33. Add E1 to E33 to list1, and then recursively find all the finally fanned-out combinational logic units F1 to F25 and G1 to G23 and add them to list1 as well. S104. Count the fan-out quantity of each register and combinational logic unit and generate a fan-out information table.

[0026] In this embodiment, as Figure 3 shown, the specific steps of S4 include: S401. According to the logic effect and fan-out constraint, specify the size of the clustering cluster, denoted as Knum ; S402. Define the state space and action space: The state space is the mathematical representation of the clustering cluster, and the action space contains three types of actions: changing the clustering cluster belonging of elements, adding a new clustering cluster, and deleting a clustering cluster. S403. Define the reward function based on timing elements, distance elements, etc. S404. Initialize the number of clustering clusters and their corresponding central coordinates: For each unit in the target unit list target_list, calculate the multiple relationship between the number of elements in the corresponding f0_list and f1_list and the clustering cluster size Knum. The rounded-down value rounddown(size(f0_list) / Knum) is used as the initial number of clustering clusters i0_cl_num corresponding to f0_list, where rounddown represents the floor function and size represents the function to calculate the number of elements in a set. Randomly select Knum units from f0_list and calculate the mean of their physical positions as the initial value of the central coordinates of the current clustering cluster. Repeat this process i0_cl_num times to obtain the initial values of all clustering cluster central coordinates. S405. Initialize the clustering clusters: Traverse each unit in f0_list and f1_list, calculate the Manhattan distance between its physical position and the central position of each clustering cluster in turn, and classify the unit into the clustering cluster with the shortest Manhattan distance. Then recalculate the mean of the physical positions of the logical units in each clustering cluster and use this mean to update the central coordinates of the clustering cluster. S406. Optimize the clustering clusters through reinforcement learning: Use the initial clustering clusters as the initial state space and optimize through reinforcement learning. Stop when the optimization result meets the expectation, and use the final state as the final clustering result. S407. Record the clustering cluster information: Record the final number of clustering clusters final_cl_num corresponding to each unit in the target unit list targetr_list, and the element list in each clustering cluster.

[0027] In this embodiment, the specific steps of S5 include: S501. For each unit cell0 in target_list and its corresponding clustering cluster, first disconnect the original connections of the input pins pin of the units within the clustering cluster. S502. For each clustering cluster, judge its phase relationship with the phase output by the unit cell0: If the clustering cluster is in phase with the output of the unit cell0, insert a buffer between the output of the unit cell0 and the clustering cluster, and connect the output of the buffer to the input pins pin of the units within the clustering cluster. If the clustering cluster is out of phase with the register output, insert an inverter and connect the output of the inverter to the input pins pin of the units within the clustering cluster. As Figure 4 shown, the units D24, D25, D26, D27 and the units G20, G21, G22, G23 belong to a clustering cluster and are out of phase with the unit C0. Therefore, an inverter INV_cl1 is inserted, and the output of the inverter is connected to the corresponding input pins pin of D24 to D27 and G20 to G23. S503. Connect the input of the inserted buffer or inverter to the output of cell0, and remove other inverter or buffer loads on the register output; S504. Save the modified netlist; S505. Use a formal verification tool or a simulation tool to perform an equivalence check; if the check passes, end; otherwise, return to S502 or S503 to correct the connection relationship.

[0028] Through steps such as statistically analyzing the fan-out information of registers and combinational logic, generating a target cell list, obtaining the fan-out combinational logic information of target cells, implementing reinforcement learning-driven combinational logic clustering, revising the netlist and performing an equivalence check, and using the new netlist for placement and routing, the present invention realizes the optimization of the critical path timing and the improvement of the circuit performance. The present invention can effectively reduce the critical path delay and optimize the circuit performance, and is particularly suitable for large-scale integrated circuit design.

[0029] The combinational logic clustering optimization method based on reinforcement learning of the present invention can automatically identify the critical timing path by statistically analyzing the fan-out information of all cells including registers and combinational logic and generating a target cell list, and implement clustering by means of reinforcement learning. Then, based on the clustering information, an inverter or buffer insertion operation is performed, effectively avoiding the problem of unreasonable insertion of inverters or buffers, thereby improving the critical path delay of large fan-out classes. The present invention implements logic clustering based on reinforcement learning, enabling the inverter or buffer to drive nearby in the physical layout, effectively reducing the timing path length in the critical path of large fan-out classes, thereby improving the circuit performance, and is particularly suitable for large-scale integrated circuit design.

[0030] The present invention introduces reinforcement learning technology to propose a new solution to the two major defects of existing commercial EDA tools in dealing with large fan-out cells, namely, unreasonable insertion positions of inverters / buffers and insufficient consideration of physical factors. The present invention can accurately locate the list of large fan-out cells on the critical path, combines reinforcement learning with clustering, effectively considers the influence of physical factors, shortens the critical path distance, and reduces the signal propagation delay and the risk of routing congestion. The present invention has high reliability, and ensures that the optimized circuit functions are consistent through an equivalence check. The combinational logic clustering optimization method and system based on reinforcement learning support integration with mainstream EDA tools and are applicable to large-scale circuit design. Under a certain sub-20-nanometer process, when this method is implemented on a certain core module, the maximum setup timing violation is reduced by 13 ps, and the number of timing violations is reduced by 12.3%, greatly improving the design performance. The advantage of this method also lies in its scalability to other optimization scenarios.

[0031] The present invention also discloses a combinatorial logic clustering optimization system based on reinforcement learning, which includes a memory and a processor connected to each other. A computer program is stored on the memory, and when the computer program is run by the processor, it executes the steps of the method described above. The optimization system of the present invention corresponds to the above optimization method and has the same advantages as the above optimization method.

[0032] The present invention can also implement all or part of the processes in the above embodiment methods through hardware related to computer program instructions. The computer program can be stored in a computer-readable storage medium. When the computer program is executed by the processor, the steps of the above method embodiments can be realized. Among them, the computer program includes computer program code, and the computer program code can be in the form of source code, object code, executable file or some intermediate form, etc. The computer-readable storage medium includes: any entity or device capable of carrying computer program code, recording medium, USB flash drive, mobile hard disk, magnetic disk, optical disc, computer memory, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), electrical carrier signal, telecommunication signal, and software distribution medium, etc. The memory is used to store computer programs and / or modules. The processor realizes various functions by running or executing the computer programs and / or modules stored in the memory and calling the data stored in the memory. The memory can include high-speed random access memory, and can also include non-volatile memory, such as hard disk, memory, plug-in hard disk, smart media card (SMC), secure digital (SD) card, flash card, at least one magnetic disk storage device, flash device, or other volatile solid-state storage devices, etc.

[0033] The above is only the preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above embodiments. All technical solutions within the idea of the present invention belong to the protection scope of the present invention. It should be pointed out that for those of ordinary skill in the art, several improvements and refinements made without departing from the principle of the present invention should be regarded as within the protection scope of the present invention.

Claims

1. A combined logic clustering optimization method based on reinforcement learning, characterized in that, Including the steps: S1. Stat the fan-out information of registers and combinational logic units in the circuit netlist; S2. According to the fan-out information in step S1, filter out the registers and combinational logic units whose fan-out quantity is greater than the first preset threshold and the timing violation value of the worst timing path of the output signal is less than the second preset threshold, and generate a target cell list; S3. Obtain the fan-out combinational logic information of each cell in the target cell list; S4. Based on the fan-out combinational logic information, perform clustering operations on the fan-out logic units respectively based on the reinforcement learning algorithm; S5. After completing the logic clustering, revise the circuit netlist; after the revision is completed, perform equivalence checking; S6. Re-layout and route the circuit according to the modified netlist.

2. The combinational logic clustering optimization method based on reinforcement learning according to claim 1, wherein The specific steps of S1 are: S101. Traverse all registers and combinational logic units in the circuit netlist, and record the output signals of each cell; S102. Analyze the fan-out situation of each cell's output signal, including buffers, inverters, and combinational logic units, add the combinational logic units to the list list1, and add the buffers and inverters to the list list2; S103. Recursively analyze the fan-out situation of the output signals of the buffers and inverters. For each buffer or inverter in the list list2, traverse to find all the directly fan-out combinational logic units and add them to list1, then traverse to find all the directly fan-out buffers and inverters; recursively find all the finally fan-out combinational logic units and add them to list1; S104. Stat the fan-out quantity of each register and combinational logic unit, and generate a fan-out information table.

3. The method for optimizing combinational logic clustering based on reinforcement learning according to claim 1 or 2, characterized in that The specific steps of S3 are: For each cell in the target cell list, obtain all the logic units son_cells that the output signal fans out; traverse son_cells, if the cell type is not a buffer and an inverter, add the cell name, the corresponding input pin, and the cell location information to the list f0_list; if the cell type is a buffer or an inverter, recursively search for all the first-occurring non-buffer and non-inverter logic units, and then add the cell name, the corresponding input pin, and the cell location information to the list f0_list and the list f1_list respectively according to the phase.

4. The method for optimizing combinational logic clustering based on reinforcement learning according to claim 3, wherein The specific steps of S4 include: S401. Specify the size of the clustering cluster, denoted as Knum, according to the logic effect and the fan-out constraint; S402. Define the state space and the action space: the state space is the mathematical representation of the clustering cluster, and the action space contains 3 types of actions: changing the clustering cluster belonging, adding a new clustering cluster, and deleting a clustering cluster; S403. Define the reward function based on the timing factor and the distance factor; S404. Initialize the number of clustering clusters and the corresponding center coordinates; S405. Initialize the clustering cluster; S406. Optimize the clustering cluster by reinforcement learning: use the initial clustering cluster as the initial state space, optimize it through reinforcement learning, stop after the optimization result meets the expectation, and use the final state as the final clustering result; S407. Record cluster information: Record the final number of clusters final_cl_num corresponding to each unit in the target unit list targetr_list, and the list of elements in each cluster.

5. The method for optimizing combinational logic clustering based on reinforcement learning according to claim 4, wherein The specific steps of S404 are as follows: For each unit in the target unit list target_list, calculate the multiple relationship between the number of elements in the corresponding lists f0_list and f1_list and the cluster size Knum. The rounded-down value rounddown(size(f0_list) / Knum) is used as the initial number of clusters i0_cl_num corresponding to the list f0_list, where rounddown represents the floor function and size represents the function to calculate the number of elements in a set. Randomly select Knum units from the list f0_list, calculate the mean of their physical positions as the initial value of the center coordinates of the current cluster, and repeat this process i0_cl_num times to obtain the initial values of the center coordinates of all clusters.

6. The method for optimizing combinational logic clustering based on reinforcement learning according to claim 5, wherein The specific steps of S405 are as follows: Traverse each unit in the lists f0_list and f1_list, calculate the Manhattan distance between its physical position and the initial center coordinates of each cluster in turn, classify the unit into the cluster with the shortest Manhattan distance, and then recalculate the mean of the physical positions of the logical units in each cluster and use this mean to update the center coordinates of the cluster.

7. The method for optimizing combinational logic clustering based on reinforcement learning according to claim 1 or 2, characterized in that The specific steps of S5 are as follows: S501. For each unit cell0 in the target unit list target_list and its corresponding cluster, first disconnect the original connections of the input pins pin of the units within the cluster. S502. For each cluster, determine its phase relationship with the phase output by the unit cell0: If the cluster is in phase with the output of the unit cell0, insert a buffer between the output of the unit cell0 and the cluster, and connect the output of the buffer to the input pins pin of the units within the cluster; If the cluster is out of phase with the register output, insert an inverter and connect the output of the inverter to the input pins pin of the units within the cluster. S503. Connect the input of the inserted buffer or inverter to the output of the unit cell0, and remove other inverter or buffer loads on the register output. S504. Save the modified netlist. S505. Perform equivalence checking; if the check passes, end; otherwise, return to S502 to correct the connection relationship.

8. A combinatorial logic clustering optimization system based on reinforcement learning, comprising a memory and a processor connected to each other, wherein a computer program is stored on the memory, and is characterized in that, The computer program, when run by a processor, executes the steps of the method according to any one of claims 1-7.

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