Quantum circuit cutting method and device based on physical hardware

Abstract

The invention provides a quantum circuit cutting method and device based on physical hardware, electronic equipment and a non-instantaneous computer readable storage medium, the cutting method comprises the steps that a logic gate in a quantum algorithm circuit is compiled into a logic circuit, and the logic circuit comprises a native gate; based on physical hardware, the cutting position of the logic circuit is determined, so that after the logic circuit is cut into a plurality of logic sub-circuits, the quantum bit number and depth of each logic sub-circuit are within the range allowed by the physical hardware, and the number of the cut logic sub-circuits is the smallest; and cutting the logic circuit according to the determined cutting position to obtain the plurality of logic sub-circuits. According to the embodiment of the invention, the problem of limited quantum hardware resources is solved, and a quantum algorithm circuit can be operated on an existing quantum computer.

Description

Technical Field

[0001] The present application relates to the field of quantum computing, and in particular, to a method and apparatus for cutting a quantum circuit based on physical hardware, an electronic device, and a non-transitory computer-readable storage medium. Background Art

[0002] At the current stage, the development of quantum computers is in the era of medium-scale noisy quantum computers. However, the quantum resources that can be provided by current hardware devices are limited, specifically manifested in: the number of qubits is small, the coherent operations that can be realized are limited, the depth of the quantum circuits that can be executed is shallow, and the fidelity of quantum gate operations is not high. Therefore, large-scale quantum circuits corresponding to large-scale practical problems cannot be run on current-stage quantum computers.

[0003] Quantum circuit cutting involves complex optimization and calculation problems, and thus usually requires a large amount of computing resources. For example, quantum circuit cutting needs to consider complex factors such as many-body interactions and entanglement relationships between qubits, and the correctness and reliability of the circuit need to be maintained after cutting. Especially for large-scale quantum circuits, the computational complexity of cutting will increase exponentially with the circuit scale. Therefore, cutting large-scale quantum circuits requires sufficient computing resources and efficient optimization algorithms to cope with its computational complexity. Summary of the Invention

[0004] The present application aims to propose a method and apparatus for cutting a quantum circuit based on physical hardware, an electronic device, and a non-transitory computer-readable storage medium to solve the problem of high computational complexity caused by the excessive scale of quantum algorithm circuits in quantum computing.

[0005] According to one aspect of the present application, there is provided a method for cutting a quantum algorithm circuit based on physical hardware, including: compiling logic gates in the quantum algorithm circuit into a logic circuit, where the logic circuit includes native gates; determining a cutting position of the logic circuit based on physical hardware such that after the logic circuit is cut into a plurality of logic sub-circuits, the number of qubits and the depth of each logic sub-circuit are within the range allowed by the physical hardware, and the number of cut logic sub-circuits is the least; cutting the logic circuit according to the determined cutting position to obtain the plurality of logic sub-circuits.

[0006] According to some embodiments, the logic circuit further includes input bits and output bits.

[0007] According to some embodiments, determining the cutting position of the logical circuit based on physical hardware for cutting includes: grouping the input bits and output bits of the logical circuit such that the number of input bits included in each group is the same as the number of output bits; determining at least one dividing polyline with the dividing point of the groups of input bits as the starting point and the dividing point of the groups of output bits as the ending point; and determining a final dividing polyline from the at least one dividing polyline such that the number of qubits and the depth after cutting are within the range allowed by the physical hardware and the number of logical sub - circuits after cutting is minimized.

[0008] According to some embodiments, cutting the logical circuit according to the determined cutting position to obtain the plurality of logical sub - circuits includes: cutting the logical circuit according to the determined cutting position by using horizontal cutting and / or vertical cutting to obtain the plurality of logical sub - circuits.

[0009] According to some embodiments, the cutting method further includes: mapping the plurality of logical sub - circuits into the physical hardware for quantum compilation to obtain a plurality of physical circuits.

[0010] According to some embodiments, mapping the plurality of logical sub - circuits into the physical hardware for quantum compilation includes: determining a set of native gates for mapping based on the physical hardware according to the logical circuit; and mapping the plurality of logical sub - circuits into the set of native gates to obtain a plurality of physical circuits.

[0011] According to some embodiments, mapping the plurality of logical sub - circuits into the physical hardware for quantum compilation further includes: optimizing the obtained physical circuits to reduce the error rate and execution time of the physical circuits.

[0012] According to one aspect of the present application, a cutting device for a quantum circuit based on physical hardware is provided, including: a logical circuit compilation unit configured to compile the logic gates in the quantum algorithm circuit into a logical circuit, where the logical circuit includes native gates; a cutting position determination unit configured to determine the cutting position of the logical circuit based on physical hardware such that after the logical circuit is cut into a plurality of logical sub - circuits, the number of qubits and the depth of each logical sub - circuit are within the range allowed by the physical hardware and the number of logical sub - circuits after cutting is minimized; and a cutting unit configured to cut the logical circuit according to the determined cutting position to obtain the plurality of logical sub - circuits.

[0013] According to one aspect of the present application, an electronic device is provided, including: a processor; and a memory storing a computer program, which when executed by the processor, causes the processor to execute the cutting method as described in any of the previous embodiments.

[0014] According to one aspect of the present application, a non-transitory computer-readable storage medium is provided, on which computer-readable instructions are stored. When the instructions are executed by a processor, the processor is caused to execute the cutting method as described in any of the previous embodiments.

[0015] According to an embodiment of the present application, by converting a quantum algorithm circuit into a quantum logic circuit based on physical hardware and performing circuit cutting, the original large-scale quantum circuit is reduced to a small-scale quantum circuit suitable for the target hardware platform, thereby overcoming the problem of limited quantum hardware resources and enabling the quantum algorithm circuit to run on an existing quantum computer.

[0016] It should be understood that the above general description and the following detailed description are merely exemplary and do not limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] To more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for the description of the embodiments. By referring to the drawings and describing its exemplary embodiments in detail, the above and other objectives, features, and advantages of the present application will become more obvious.

[0018] Figure 1 FIG. shows a flowchart of a method for cutting a quantum algorithm circuit based on physical hardware according to an exemplary embodiment of the present application.

[0019] Figure 2a FIG. shows a schematic diagram of a horizontal cut according to an exemplary embodiment of the present application.

[0020] Figure 2b FIG. shows another schematic diagram of a horizontal cut according to an exemplary embodiment of the present application.

[0021] Figure 3 FIG. shows a flowchart of a method for determining the cutting position of a logic circuit according to an exemplary embodiment of the present application.

[0022] Figure 4 FIG. shows a schematic diagram of a segmented broken line according to an exemplary embodiment of the present application.

[0023] Figure 5 FIG. shows a flowchart of another method for cutting a quantum algorithm circuit based on physical hardware according to an exemplary embodiment of the present application.

[0024] Figure 6 FIG. shows a block diagram of a device for cutting a quantum circuit based on physical hardware according to an exemplary embodiment of the present application.

[0025] Figure 7 FIG. shows an electronic device according to an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0026] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this application will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. Like reference numerals in the figures denote like or similar parts, and thus their repetitive description will be omitted.

[0027] The features, structures, or characteristics described may be combined in one or more embodiments in any suitable manner. In the following description, numerous specific details are provided to give a thorough understanding of the embodiments of the present disclosure. However, those skilled in the art will realize that the technical solutions of the present disclosure may be practiced without one or more of these specific details, or may be implemented in other ways, components, materials, devices, or operations, etc. In these cases, well-known structures, methods, devices, implementations, materials, or operations will not be shown or described in detail.

[0028] The flowcharts shown in the accompanying drawings are merely illustrative and not necessarily inclusive of all contents and operations / steps, nor are they necessarily executed in the order described. For example, some operations / steps may be decomposed, while some operations / steps may be combined or partially combined, so the actual execution order may change according to the actual situation.

[0029] The terms "first", "second", etc. in the specification and claims of this application and the above accompanying drawings are used to distinguish different objects and not to describe a specific order. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but optionally further includes steps or units not listed, or optionally further includes other steps or units inherent to these processes, methods, products, or devices.

[0030] The following will describe in detail specific embodiments according to the present application with reference to the accompanying drawings.

[0031] Figure 1 A flowchart of a method for cutting a quantum algorithm circuit based on physical hardware according to an example embodiment of the present application is shown, as Figure 1 shown. The cutting method includes steps S101, S103, and S105. The following takes Figure 1 as an example to describe in detail a method for cutting a quantum algorithm circuit based on physical hardware according to an example embodiment of the present application.

[0032] As Figure 1 shown, in step S101, the logic gates in the quantum algorithm circuit are compiled into a logic circuit.

[0033] According to an embodiment of the present application, the quantum algorithm circuit is determined according to the specific problem to be solved.

[0034] In some embodiments, the logical circuit includes native gates. In step S101, the logical gates in the quantum algorithm circuit are compiled into native gates that can be implemented by physical hardware. In a specific embodiment, the logical circuit includes native gates, input qubits, and output qubits.

[0035] In step S103, based on the physical hardware, determine the cutting positions of the logical circuit such that after the logical circuit is cut into multiple logical sub-circuits, the number of qubits and the depth of each logical sub-circuit are within the range allowed by the physical hardware, and the number of the cut logical sub-circuits is minimized.

[0036] According to an embodiment of the present application, in step S103, first determine multiple splitting broken lines according to the input qubits and output qubits in the logical circuit, such that the number of qubits and the depth of the trimmed quantum sub-circuits do not exceed the maximum number of qubits and the depth allowed by the hardware device; then, select the splitting broken line with the fewest total cutting positions from them to determine the cutting positions according to the determined splitting broken line. When determining the cutting positions of the logical circuit, it is necessary to determine according to the input qubits and output qubits in the logical circuit, and not exceed the qubit number limit of the quantum hardware, and make the total cutting positions as few as possible, so that the number of the cut logical sub-circuits reaches the minimum.

[0037] In step S105, cut the logical circuit according to the determined cutting positions to obtain multiple logical sub-circuits.

[0038] According to an embodiment of the present application, according to the cutting positions determined in step S103, horizontal cutting and / or vertical cutting can be selected to cut the logical circuit to obtain multiple logical sub-circuits.

[0039] In some embodiments, horizontal cutting can be used to cut multi-bit native gates that intersect the determined splitting broken line. In a specific embodiment, the multi-bit native gates that can be cut can be determined according to the selected cutting method.

[0040] For example, when performing horizontal cutting, the multi-bit control-Z gate is cut by cutting the multi-bit control gate. As Figure 2a shown, by adding H gates before and after the controlled bit, the conversion from the control-Z gate to the control-X gate can be achieved. As Figure 2b shown, by adding X gates before and after the control bits of the multi-bit control-Z gate, the inversion of the control condition can be achieved. It should be noted here that the cutting method for the multi-bit control-Z gate in the embodiments of the present application is also applicable to general multi-bit control gates.

[0041] For another example, a two-bit gate is cut into a single-bit gate through two-bit gate cutting.

[0042] In other embodiments, the lines intersecting the dividing fold lines are cut longitudinally.

[0043] In a specific embodiment, when performing vertical cutting, the tensor network representation of the logic circuit can be written first, then the tensor network can be cut, and finally the cut tensor network can be converted into smaller sub-circuits.

[0044] In other embodiments, longitudinal cutting can be achieved through quasi-probabilistic simulation. For example, by first decomposing the identical channel into a mixture of local channels, large quantum circuits can be simulated on small-scale quantum devices, leveraging local operations and classical communication to reduce the sampling overhead required for simulation. When classical communication is performed between logic subcircuits, the overhead of parallel or arbitrary line cutting can be significantly reduced, demonstrating the potential for optimizing quantum circuits within the constraints of quantum hardware.

[0045] according to Figure 1 The embodiment shown converts quantum algorithm circuits into quantum logic circuits based on physical hardware and performs circuit slicing, thereby reducing the original large-scale quantum circuits to small-scale quantum circuits suitable for the target hardware platform, thereby overcoming the problem of limited quantum hardware resources and enabling quantum algorithm circuits to run on existing quantum computers.

[0046] Furthermore, by combining horizontal and vertical slicing, the number of bits and depth in the resulting logic circuits can be controlled, ensuring that the resulting logic sub-circuits are suitable for actual physical devices. Horizontal slicing is typically used to reduce the number of bits in a quantum circuit by removing irrelevant bits or replacing multi-bit gates with equivalent single-bit gates, thereby reducing the circuit size. Vertical slicing, on the other hand, reduces the depth of the quantum circuit by truncating certain qubits in the original circuit at appropriate locations. By combining horizontal and vertical slicing, the scale and depth of quantum circuits can be flexibly controlled. This approach, combining multiple slicing techniques, broadens the applicability of quantum circuit slicing solutions, enabling them to accommodate quantum computer hardware of varying scales and precisions. This approach can better address the limitations of current quantum computers and improve the feasibility and efficiency of quantum computing.

[0047] Figure 3 A flow chart of a method for determining a logic circuit cutting position according to an exemplary embodiment of the present application is shown. Figure 3 The method shown includes steps S1031 , S1033 and S1035 .

[0048] like Figure 3As shown, when cutting a logical circuit, first in step S1031, the input bits and output bits of the logical circuit are grouped so that each group includes the same number of input bits and output bits, and does not exceed the bit number limit of the physical hardware.

[0049] Then, in step S1033, starting from the group division point of the input bits and ending at the group division point of the output bits, at least one dividing polyline is determined. As Figure 4 shown, multiple dividing polylines can be obtained.

[0050] Finally, in step 1035, the final dividing polyline is determined from at least one dividing polyline so that the number of qubits and the depth after cutting are within the range allowed by the physical hardware, and the number of logical sub - circuits after cutting is the least, thus making the total number of cutting positions as few as possible.

[0051] When performing specific cutting, the intersection of the dividing polyline and the native gate is cut using a horizontal cutting method, and the intersection of the dividing polyline and the logical circuit is cut using a vertical cutting method.

[0052] Figure 5 FIG. shows a flowchart of another method for cutting a quantum algorithm circuit based on physical hardware according to an exemplary embodiment of the present application. Compared with Figure 1 that, as Figure 5 shown, the cutting method includes steps S107 and S109 in addition to steps S101, S103, and S105. For simplicity, only the differences from Figure 1 are described in this embodiment, and the same parts will not be elaborated again.

[0053] As Figure 5 described, in step S107, multiple logical sub - circuits are mapped into the physical hardware for quantum compilation to obtain multiple physical circuits.

[0054] According to an embodiment of the present application, in step S107, first, based on the logical circuit and the physical hardware, a set of physical hardware quantum gates for mapping is determined; then, multiple logical sub - circuits are mapped into the set of physical hardware quantum gates to obtain multiple physical circuits.

[0055] In a specific embodiment, when selecting the native gate set, according to the native gates of the physical hardware and the native gates appearing in the logical circuit, a set of native gates that can make the depth and the number of gates of the physical circuit after compilation both less is selected.

[0056] In some other embodiments, when mapping the logical sub-circuit to physical hardware, based on the specific physical hardware, the high-level logical sub-circuit is compiled into a set of native gates to obtain a physical sub-circuit. In this process, it is necessary to map the logical sub-circuit to the physical hardware based on conditions such as the connectivity limitations of the physical hardware, the measurement methods of the physical hardware, and the noise conditions of the physical hardware.

[0057] In step S109, the obtained physical circuit is optimized to reduce the error rate and execution time of the physical circuit.

[0058] According to the embodiments of the present application, in step S109, based on the limitation conditions of the physical hardware, the circuit is optimized to minimize the error rate on the hardware, shorten the execution time, etc. as much as possible.

[0059] For example, using heuristic algorithms and circuit rewriting rules, the number of gates with higher implementation complexity, such as two-bit gates, is reduced to further improve efficiency.

[0060] For another example, an approximate approximation method is adopted to reduce the gate complexity of the circuit to achieve the best balance between reducing the error rate and shortening the execution time, so as to adapt to the characteristics of quantum hardware and improve the overall performance of quantum computing.

[0061] According to the embodiments of the present application, after step S107 or S109, the obtained multiple physical circuits are post-processed by a classical computer, which is equivalent to running the original quantum algorithm circuit to solve practical problems.

[0062] According to Figure 5 In the shown embodiment, by optimizing the physical circuit and selecting gate operations suitable for the target hardware platform, such as selecting gate operations with higher fidelity, the error rate of the quantum circuit can be reduced, thereby improving the executability of the quantum circuit in the experiment, making the depth of the cut quantum circuit suitable for the target hardware platform, and thus avoiding the problem of error accumulation caused by too deep a quantum circuit depth.

[0063] The above mainly introduced the embodiments of the present application from the perspective of methods. Those skilled in the art should easily realize that, combined with the operations or steps of each example described in the embodiments disclosed herein, the present application can be implemented in the form of hardware or a combination of hardware and computer software. Those skilled in the art can use different methods to implement the described functions for each specific operation or method, and such implementation should not be considered to exceed the scope of the present application.

[0064] The device embodiments of the present application are described below. For details not described in the device embodiments of the present application, reference can be made to the method embodiments of the present application.

[0065] Figure 6The block diagram of a cutting device for a physical-hardware-based quantum circuit according to an exemplary embodiment of the present application is shown. As Figure 6 shown, the cutting device includes a logic circuit compilation unit 601, a cutting position determination unit 603, and a cutting unit 605. Among them, the logic circuit compilation unit 601 is configured to compile the logic gates in the quantum algorithm circuit into a logic circuit, where the logic circuit includes native gates; the cutting position determination unit 603 is configured to determine the cutting position of the logic circuit based on the physical hardware, so that after the logic circuit is cut into multiple logic sub-circuits, the number of qubits and the depth of each logic sub-circuit are within the range allowed by the physical hardware, and the number of the cut logic sub-circuits is the least; the cutting unit 605 is configured to cut the logic circuit according to the determined cutting position to obtain the multiple logic sub-circuits.

[0066] Figure 7 An electronic device according to an exemplary embodiment of the present application is shown. The following will refer to Figure 7 to describe the electronic device 200 according to this embodiment of the present application. Figure 7 The shown electronic device 200 is only an example and should not impose any limitation on the functions and usage scope of the embodiments of the present application.

[0067] As Figure 7 shown, the electronic device 200 is presented in the form of a general-purpose computing device. The components of the electronic device 200 may include, but are not limited to: at least one processing unit 210, at least one storage unit 220, a bus 230 connecting different system components (including the storage unit 220 and the processing unit 210), a display unit 240, etc.

[0068] Among them, the storage unit stores program codes, and the program codes can be executed by the processing unit 210, so that the processing unit 210 executes the methods according to various exemplary embodiments of the present application described in this specification. For example, the processing unit 210 can execute the method as Figure 1 shown.

[0069] The storage unit 220 may include a readable medium in the form of a volatile storage unit, such as a random access storage unit (RAM) 2201 and / or a cache storage unit 2202, and may further include a read-only storage unit (ROM) 2203.

[0070] The storage unit 220 may further include a program / utility 2204 having a set (at least one) of program modules 2205. Such program modules 2205 include, but are not limited to: an operating system, one or more application programs, other program modules, and program data. The implementation of a network environment may be included in each or some combination of these examples.

[0071] The bus 230 may represent one or more of several types of bus structures, including a memory bus or memory controller, a peripheral bus, an Accelerated Graphics Port, a processor, or a local bus using any of a variety of bus structures.

[0072] The electronic device 200 may also communicate with one or more external devices 300 (such as a keyboard, a pointing device, a Bluetooth device, etc.), and may also communicate with one or more devices that enable a user to interact with the electronic device 200, and / or communicate with any device that enables the electronic device 200 to communicate with one or more other computing devices (such as a router, a modem, etc.). Such communication may be through the input / output (I / O) interface 250. Further, the electronic device 200 may also communicate with one or more networks (such as a local area network (LAN), a wide area network (WAN), and / or a public network, such as the Internet) through the network adapter 260. The network adapter 260 may communicate with other modules of the electronic device 200 through the bus 230. It should be understood that, although not shown in the figure, other hardware and / or software modules may be used in conjunction with the electronic device 200, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems, etc.

[0073] Through the description of the above embodiments, those skilled in the art can easily understand that the example embodiments described herein can be implemented by software or by a combination of software and necessary hardware. The technical solutions according to the embodiments of the present application can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which may be a CD-ROM, a USB flash drive, a mobile hard disk, etc.) or on a network, including several instructions to enable a computing device (which may be a personal computer, a server, or a network device, etc.) to execute the above method according to the embodiments of the present application.

[0074] The software product may employ any combination of one or more readable media. The readable media may be a readable signal medium or a readable storage medium. The readable storage medium may, for example, but not be limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the above. More specific examples (a non-exhaustive list) of the readable storage medium include: an electrical connection having one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0075] A computer-readable storage medium may include a data signal propagated in a baseband or as part of a carrier wave, which carries readable program code. Such propagated data signal may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the foregoing. The readable storage medium may also be any readable medium other than the readable storage medium, which can send, propagate, or transmit a program for use by or in conjunction with an instruction execution system, apparatus, or device. The program code contained on the readable storage medium may be transmitted using any appropriate medium, including but not limited to wireless, wired, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

[0076] The program code for performing the operations of the present application may be written in any combination of one or more programming languages. The programming languages include object-oriented programming languages such as Java, C++, etc., and also include conventional procedural programming languages such as the "C" language or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, executed as a stand-alone software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server. In the case of a remote computing device, the remote computing device may be connected to the user computing device through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computing device (e.g., connected through the Internet using an Internet service provider).

[0077] The above computer-readable medium carries one or more programs, and when the one or more programs are executed by a device, the computer-readable medium implements the foregoing functions.

[0078] Those skilled in the art can understand that the above-mentioned modules may be distributed in the device according to the description of the embodiments, or may be correspondingly changed and distributed in one or more devices that are uniquely different from the present embodiment. The modules of the above embodiments may be combined into one module, or may be further split into multiple sub-modules.

[0079] According to an embodiment of the present application, a computer program is provided, including a computer program or instruction, and when the computer program or instruction is executed by a processor, the method described above can be executed.

[0080] The above has introduced the embodiments of the present application in detail. Specific examples are used in this article to expound the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application. At the same time, any changes or deformations made by those skilled in the art based on the idea of the present application, within the specific implementation manner and application scope of the present application, fall within the scope of protection of the present application. In summary, the content of this specification should not be construed as a limitation to the present application.

Claims

1. A cutting method for a quantum algorithm circuit based on physical hardware, characterized in that, Comprising: Compiling the logic gates in the quantum algorithm circuit into a logic circuit, where the logic circuit includes native gates; Based on the physical hardware, determining the cutting positions of the logic circuit such that after the logic circuit is cut into multiple logic sub-circuits, the number of qubits and the depth of each logic sub-circuit are within the range allowed by the physical hardware, and the number of the cut logic sub-circuits is minimized; Cutting the logic circuit according to the determined cutting positions to obtain the multiple logic sub-circuits.

2. The cutting method according to claim 1, wherein The logic circuit further includes input bits and output bits.

3. The cutting method according to claim 2, wherein Based on the physical hardware, determining the cutting positions of the logic circuit for cutting includes: Grouping the input bits and output bits of the logic circuit such that the number of input bits included in each group is the same as the number of output bits; Taking the division points of the groups of input bits as the starting points and the division points of the groups of output bits as the ending points to determine at least one dividing polyline; Determining the final dividing polyline from the at least one dividing polyline such that the number of qubits and the depth after cutting are within the range allowed by the physical hardware, and the number of the cut logic sub-circuits is minimized.

4. The cutting method according to claim 3, wherein cutting the logic circuit according to the determined cutting positions to obtain the multiple logic sub-circuits includes: Cutting the logic circuit according to the determined cutting positions by using horizontal cutting and / or vertical cutting to obtain the multiple logic sub-circuits.

5. The cutting method according to claim 1, wherein Further comprising: Mapping the multiple logic sub-circuits into the physical hardware for quantum compilation to obtain multiple physical circuits.

6. The cutting method according to claim 5, wherein Mapping the multiple logic sub-circuits into the physical hardware for quantum compilation includes: Based on the logic circuit and the physical hardware, determining the set of native gates for mapping; Mapping the multiple logic sub-circuits into the set of native gates to obtain multiple physical circuits.

7. The cutting method according to claim 6, wherein Mapping the multiple logic sub-circuits into the physical hardware for quantum compilation further includes: Optimizing the obtained physical circuits to reduce the error rate and execution time of the physical circuits.

8. A cutting device for a quantum circuit based on physical hardware, characterized in that, Comprising: A logic circuit compilation unit for compiling the logic gates in the quantum algorithm circuit into a logic circuit, where the logic circuit includes native gates; A cutting position determination unit for determining the cutting positions of the logic circuit based on the physical hardware such that after the logic circuit is cut into multiple logic sub-circuits, the number of qubits and the depth of each logic sub-circuit are within the range allowed by the physical hardware, and the number of the cut logic sub-circuits is minimized; A cutting unit for cutting the logic circuit according to the determined cutting positions to obtain the multiple logic sub-circuits.

9. An electronic device, comprising: A processor; And A memory storing a computer program, which when executed by the processor causes the processor to execute the cutting method according to any one of claims 1-7.

10. A non-transitory computer-readable storage medium storing computer-readable instructions that, when executed by a processor, cause the processor to perform the cutting method according to any one of claims 1-7.

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