Semiconductor structure, manufacturing method thereof and semiconductor device

Abstract

The embodiment of the invention provides a semiconductor structure, a manufacturing method thereof and a semiconductor device. The method comprises the following steps: forming a first barrier layer on a first dielectric layer; the first barrier layer comprises barrier sub-layers, and the barrier sub-layers are isolated from one another; forming a second dielectric layer covering the first dielectric layer and the first barrier layer; etching to form a groove penetrating through the second dielectric layer; the bottom of the groove exposes the blocking sub-layer; and forming a second barrier layer covering the side wall of the groove.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of semiconductor technology, and in particular, to a semiconductor structure, a manufacturing method thereof, and a semiconductor device. Background Art

[0002] With the rapid development of semiconductor technology, the application scope of semiconductor devices has also expanded rapidly, and the performance requirements for semiconductor devices are getting higher and higher. As an important part of semiconductor devices, the interconnect structure plays a crucial role in the performance of semiconductor devices. Summary of the Invention

[0003] In view of this, embodiments of the present disclosure provide a semiconductor structure, a manufacturing method thereof, and a semiconductor device.

[0004] To achieve the above object, the technical solution of the present disclosure is realized as follows:

[0005] In a first aspect, embodiments of the present disclosure provide a manufacturing method of a semiconductor structure, the method including: forming a first barrier layer on a first dielectric layer; the first barrier layer includes barrier sub-layers that are isolated from each other; forming a second dielectric layer covering the first dielectric layer and the first barrier layer; etching to form a groove penetrating through the second dielectric layer; the bottom of the groove exposes the barrier sub-layers; forming a second barrier layer covering the sidewalls of the groove.

[0006] In some embodiments, after forming the second barrier layer covering the sidewalls of the groove, the method further includes: filling a conductive material in the groove to form an interconnect structure; wherein the interconnect structures are isolated from each other.

[0007] In some embodiments, etching to form a groove penetrating through the second dielectric layer includes: forming a first mask layer on the second dielectric layer; etching the second dielectric layer using the first mask layer to form a first sub-groove penetrating through the second dielectric layer; the bottom of the first sub-groove exposes the barrier sub-layers.

[0008] In some embodiments, etching to form a groove penetrating through the second dielectric layer further includes: forming a filling layer in the first sub-groove; forming a second mask layer on the filling layer; etching the filling layer and the second dielectric layer using the second mask layer to form a second sub-groove; wherein the size of the second sub-groove in the direction parallel to the first dielectric layer is larger than the size of the first sub-groove in the direction parallel to the first dielectric layer; each second sub-groove communicates with at least one first sub-groove.

[0009] In some embodiments, filling the groove with a conductive material to form an interconnect structure includes: filling the first sub-groove and the second sub-groove with a conductive material to form conductive pillars in the first sub-groove and conductive pads in the second sub-groove; wherein, each of the conductive pads is connected to at least one of the conductive pillars to form an interconnect structure; and the conductive pillars are isolated from each other.

[0010] In some embodiments, forming a first barrier layer on a first dielectric layer includes: providing the first dielectric layer; forming a first barrier material layer covering the first dielectric layer; forming a third mask layer on the first barrier material layer; etching the first barrier material layer using the third mask layer to form the first barrier layer; wherein, the first barrier layer includes the barrier sub-layer; and the contact interface between the first dielectric layer and the barrier sub-layer is substantially planar.

[0011] In some embodiments, the first barrier material layer is formed by a magnetron sputtering process; and the second barrier layer is formed by a magnetron sputtering process.

[0012] In some embodiments, a conductive layer is provided in the first dielectric layer; the conductive layer is connected to the barrier sub-layer and the contact interface between the conductive layer and the barrier sub-layer is substantially planar.

[0013] In some embodiments, the material of the first barrier layer includes tantalum nitride.

[0014] In a second aspect, an embodiment of the present disclosure provides a semiconductor structure, the semiconductor structure includes: a first dielectric layer and a second dielectric layer located on the first dielectric layer; an interconnect structure penetrating the second dielectric layer; a barrier sub-layer located between the interconnect structure and the first dielectric layer; the contact interface between the first dielectric layer and the barrier sub-layer is substantially planar; and a second barrier layer located between the interconnect structure and the second dielectric layer.

[0015] In some embodiments, a conductive layer is provided in the first dielectric layer; the conductive layer is connected to the barrier sub-layer and the contact interface between the conductive layer and the barrier sub-layer is substantially planar.

[0016] In some embodiments, the interconnect structure includes conductive pillars and conductive pads located in the second dielectric layer, and each of the conductive pads is connected to at least one of the conductive pillars.

[0017] In a third aspect, an embodiment of the present disclosure provides a semiconductor device, the semiconductor device includes a semiconductor structure manufactured by the manufacturing method of the semiconductor structure described in the above technical solution.

[0018] In some embodiments, the semiconductor device includes a memory.

[0019] Embodiments of the present disclosure provide a semiconductor structure, a manufacturing method thereof, and a semiconductor device. The method includes: forming a first barrier layer on a first dielectric layer; the first barrier layer includes barrier sub-layers that are isolated from each other; forming a second dielectric layer covering the first dielectric layer and the first barrier layer; etching to form a groove penetrating the second dielectric layer; the bottom of the groove exposes the barrier sub-layers; forming a second barrier layer covering the sidewalls of the groove. In the embodiments of the present disclosure, the first barrier layer (i.e., the barrier sub-layers) formed before etching to form the groove covers the bottom of the groove, and the second barrier layer formed after etching to form the groove covers the sidewalls of the groove. In this way, the continuity of the barrier sub-layers covering the bottom of the groove can be ensured, and the second barrier layer covering the sidewalls of the groove can be prevented from causing the top of the groove to be sealed, thereby expanding the process window for forming the first barrier layer and the second barrier layer, and further improving the quality of the first barrier layer and the second barrier layer to improve the reliability of the semiconductor structure. Description of the Drawings

[0020] Figures 1A to 1D Schematic cross-sectional structure diagram of a semiconductor structure during manufacturing for some examples;

[0021] Figure 2 Electron microscope photograph of a semiconductor structure for some examples;

[0022] Figure 3 Schematic flow chart of the manufacturing method of the semiconductor structure provided by the embodiments of the present disclosure;

[0023] Figures 4A to 4F Schematic cross-sectional structure diagram of the semiconductor structure provided by the embodiments of the present disclosure during manufacturing;

[0024] Figure 5A and Figure 5B Schematic cross-sectional structure diagram of the semiconductor structure provided by the embodiments of the present disclosure. Detailed Embodiments

[0025] Next, the technical solutions in the embodiments of the present disclosure will be clearly and completely described in conjunction with the embodiments of the present disclosure and the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present disclosure.

[0026] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present disclosure. However, it will be apparent to one of ordinary skill in the art that the present disclosure may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the present disclosure; that is, not all features of actual embodiments are described herein, and well-known functions and structures are not described in detail.

[0027] In the drawings, for the sake of clarity, the dimensions of layers, regions, elements, and their relative dimensions may be exaggerated. Throughout the drawings, like reference numerals denote like elements.

[0028] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or section from another element, component, region, layer, or section. Thus, a first element, component, region, layer, or section discussed below may be referred to as a second element, component, region, layer, or section without departing from the teachings of the present disclosure. And when a second element, component, region, layer, or section is discussed, it does not necessarily imply that a first element, component, region, layer, or section exists in the present disclosure.

[0029] Spatial relationship terms such as "under," "below," "beneath," "underneath," "above," "over," etc. are used herein for convenience in describing the relationship of one element or feature to another element or feature shown in the figures. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms are intended to also encompass different orientations of the device during use and operation. For example, if the device in the figures is flipped, then an element or feature described as "under" or "beneath" or "underneath" another element or feature will be oriented "over" the other element or feature. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatial descriptors used herein are to be interpreted accordingly.

[0030] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of the present disclosure. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, specify the presence of the stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups. As used herein, the term "and / or" includes any and all combinations of the related listed items.

[0031] To thoroughly understand the present disclosure, detailed steps and detailed structures will be presented in the following description to illustrate the technical solutions of the present disclosure. The preferred embodiments of the present disclosure are described in detail below. However, in addition to these detailed descriptions, the present disclosure may also have other embodiments.

[0032] Before introducing the embodiments of the present disclosure, various directions for describing semiconductor structures that may be used in the embodiments of the present disclosure are defined first. The thickness direction of the substrate or the first dielectric layer is defined as the Z direction, that is, the direction perpendicular to the substrate or perpendicular to the first dielectric layer is defined as the Z direction. The intersecting X direction and Y direction are defined in the plane perpendicular to the Z direction, that is, both the X direction and the Y direction are parallel to the substrate or both the X direction and the Y direction are parallel to the first dielectric layer. In some embodiments, the X direction and the Y direction may be perpendicular to each other. In other embodiments, the X direction and the Y direction may not be perpendicular. In the following embodiments, the examples in which the X direction, the Y direction, and the Z direction are perpendicular to each other in pairs will be used for illustration.

[0033] Reference Figures 1A to 1D , Figures 1A to 1D is a schematic cross-sectional structure diagram of a semiconductor structure during the manufacturing process for some examples. The manufacturing process of the semiconductor structure will be described below in conjunction with Figures 1A to 1D to illustrate the manufacturing process of the semiconductor structure.

[0034] As Figure 1A shown, an oxide layer 104 is formed on a substrate 102.

[0035] As Figure 1B shown, along the Z direction, the oxide layer 104 is etched to form a groove 106 exposing the substrate 102; wherein, the groove 106 includes a first part and a second part that communicate with each other, the first part and the second part are arranged along the Z direction, the first part is located between the substrate 102 and the second part, and the size of the first part along the direction parallel to the substrate (i.e., the X direction) is smaller than the size of the second part along the direction parallel to the substrate (i.e., the X direction).

[0036] As Figure 1C shown, a barrier layer 108 covering the bottom and side walls of the groove 106 is formed.

[0037] As shown Figure 1D in the figure, the groove 106 is filled with a conductive material to form an interconnect structure 110.

[0038] Here, the conductive material can be, for example, a copper material.

[0039] In the above technical solution, copper materials are widely used in interconnect structures due to their advantages in electrical, mechanical, and thermal aspects. However, copper materials have an extremely high diffusion rate in silicon materials and most dielectric materials, and have poor adhesion with common dielectric materials. In order to ensure the reliable operation of the chip, the barrier layer becomes particularly important. Forming a barrier layer covering the bottom and side walls of the groove can not only increase the adhesion between the conductive material and the substrate and the oxide layer, but also prevent the conductive material from diffusing into the substrate and the oxide layer, thereby improving the reliability of the semiconductor structure.

[0040] Here, a deposition method can be used to form a barrier layer covering the bottom and side walls of the groove. If the deposited barrier material is less, it is difficult to form a continuous and thick enough barrier layer, and a continuous and thick enough barrier layer is crucial for the reliability of the semiconductor structure. If the deposited barrier material is more, due to the overhang effect, the top of the groove may be sealed, which is not conducive to filling the groove with a conductive material to form an interconnect structure later. Therefore, the barrier layer needs to balance the overhang effect and the insufficient thickness, and has extremely high requirements for the process and equipment of depositing the barrier layer.

[0041] Referring to Figure 2 , Figure 2 the electron microscope photographs of semiconductor structures provided for some examples. As Figure 2 shown, during the process of forming a barrier layer covering the bottom and side walls of the groove by deposition, the barrier material particles will hit the bottom of the groove, resulting in the contact interface between the barrier layer finally formed covering the bottom of the groove and the substrate not being planar, that is, the contact interface between the barrier layer and the substrate presents a downward concave shape in the cross-sectional view (as Figure 2 shown by the dashed box in the figure).

[0042] In view of this, the embodiments of the present disclosure provide a semiconductor structure, a manufacturing method thereof, and a semiconductor device.

[0043] Referring to Figure 3 , Figure 3 is a schematic flowchart of the manufacturing method of the semiconductor structure provided by the embodiments of the present disclosure. As Figure 3 shown, the embodiments of the present disclosure provide a manufacturing method of a semiconductor structure, and the method includes:

[0044] Step S301: Form a first barrier layer on the first dielectric layer; the first barrier layer includes barrier sub-layers, and the barrier sub-layers are isolated from each other;

[0045] Step S302: Form a second dielectric layer covering the first dielectric layer and the first barrier layer;

[0046] Step S303: Etch to form a groove penetrating the second dielectric layer; the bottom of the groove exposes the barrier sub-layers;

[0047] Step S304: Form a second barrier layer covering the sidewalls of the groove.

[0048] In the embodiments of the present disclosure, the first barrier layer (i.e., the barrier sub-layers) formed before etching to form the groove covers the bottom of the groove, and the second barrier layer formed after etching to form the groove covers the sidewalls of the groove. In this way, it can not only ensure the continuity of the barrier sub-layers covering the bottom of the groove, but also avoid the second barrier layer covering the sidewalls of the groove from causing the top of the groove to be sealed, so as to balance the overhang effect and the insufficient thickness, thereby expanding the process window for forming the first barrier layer and the second barrier layer, and further improving the quality of the first barrier layer and the second barrier layer to improve the reliability of the semiconductor structure.

[0049] Reference Figures 4A to 4F , Figures 4A to 4F is a schematic cross-sectional structure diagram of the semiconductor structure provided by the embodiments of the present disclosure during the manufacturing process. The manufacturing process of the semiconductor structure provided by the embodiments of the present disclosure will be described in detail below with reference to Figure 3 and Figures 4A to 4F .

[0050] In the embodiments of the present disclosure, in step S301, a first barrier layer 408 is formed on the first dielectric layer 402; the first barrier layer 408 includes barrier sub-layers 410, and the barrier sub-layers 410 are isolated from each other.

[0051] As Figure 4A shown, in some embodiments, step S301 includes: providing a first dielectric layer 402, in which a conductive layer 404 is provided; forming a first barrier material layer 406 covering the first dielectric layer 402. Figure 4A Two isolated conductive layers 404 are schematically shown.

[0052] Here, the material of the first dielectric layer 402 may include an insulating material, and the insulating material may include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

[0053] Here, the process of forming the first dielectric layer 402 may include, but is not limited to, Chemical Vapor Deposition (CVD), Plasma-Enhanced CVD (PECVD), Metal-Organic CVD (MOCVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), or any combination thereof.

[0054] Here, the material of the conductive layer 404 may include, but is not limited to, metal materials such as copper, aluminum, and tungsten.

[0055] Exemplarily, forming the conductive layer 404 may include the following steps: etching a part of the first dielectric layer in the Z direction to form a groove; filling the groove with a conductive material to form a conductive material layer; and planarizing the conductive material layer to form the conductive layer and expose the top surface of the first dielectric layer.

[0056] Here, the planarization process may include, but is not limited to, Chemical Mechanical Polishing (CMP).

[0057] Here, the top surface of the conductive layer 404 and the top surface of the first dielectric layer 402 are substantially flush. Substantially flush can be understood as that after the Chemical Mechanical Polishing process, the top surface of the formed conductive layer 404 and the top surface of the first dielectric layer 402 are flush on the same plane, and in the case where the top surface of the conductive layer 404 and the top surface of the first dielectric layer 402 are not flush on the same plane within the process error range during the Chemical Mechanical Polishing process.

[0058] Here, the material of the first barrier material layer 406 may include, but is not limited to, titanium nitride or tantalum nitride. Here, the material of the first barrier material layer 406 is tantalum nitride. The present disclosure has no special limitation on the material of the first barrier material layer 406, and it can be flexibly selected according to the actual situation. The present disclosure also has no special limitation on the thickness of the first barrier material layer 406, and it can be flexibly selected according to the actual situation.

[0059] In some embodiments, the first barrier material layer 406 is formed by a magnetron sputtering process.

[0060] Here, magnetron sputtering is a form of physical vapor deposition. The working principle of magnetron sputtering means that under the action of an electric field, electrons collide with Ar atoms during their flight towards the substrate (such as the first dielectric layer), causing them to ionize and produce Ar+ ions and new electrons; the new electrons fly towards the substrate, and the Ar ions are accelerated towards the cathode target under the action of the electric field and bombard the target surface with high energy, causing sputtering of the target material. Magnetron sputtering is a collision process between incident particles and the target material. The incident particles undergo a complex scattering process in the target material, collide with target atoms, transfer part of their momentum to the target atoms, and these target atoms then collide with other target atoms, forming a cascade process. In this cascade process, some target atoms near the surface obtain sufficient momentum to move outward, leave the target material, and are sputtered out.

[0061] Here, the top surface of the conductive layer 404 is substantially flush with the top surface of the first dielectric layer 402. A first barrier material layer 406 covering the first dielectric layer 402 and the conductive layer 404 is formed using a magnetron sputtering process on a plane, and the contact interfaces between the first barrier material layer 406 and the first dielectric layer 402 and the conductive layer 404 are substantially planar. Figure 4A In the schematic cross-sectional structure diagram shown, the contact boundary between the first barrier material layer 406 and the first dielectric layer 402 and the conductive layer 404 is substantially a straight line.

[0062] As Figure 4B shown, in some embodiments, step S301 further includes: forming a third mask layer on the first barrier material layer 406; etching the first barrier material layer 406 along the Z direction using the third mask layer to form a first barrier layer 408; wherein, the first barrier layer 408 includes at least one barrier sub-layer 410, and the barrier sub-layers 410 are isolated from each other; the contact interface between the first dielectric layer 402 and the barrier sub-layer 410 is substantially planar, that is, the conductive layer 404 and the barrier sub-layer 410 are connected to each other and the contact interface between the conductive layer 404 and the barrier sub-layer 410 is substantially planar.

[0063] Generally, the mask layer can be a photoresist layer, or the mask layer can include a photoresist layer and a hard mask layer. Here, the hard mask layer can play a conformal role. Exemplarily, forming the first barrier layer 408 can include the following steps: forming a photoresist layer on the first barrier material layer 406, performing exposure and development processes on the photoresist layer, and transferring the pattern on the mask plate to the photoresist layer to form a patterned photoresist layer (i.e., the third mask layer); etching the first barrier material layer 406 using the third mask layer to form the first barrier layer 408.

[0064] Exemplarily, forming the first barrier layer 408 may include the following steps: forming a hard mask layer on the first barrier material layer 406, coating and forming a photoresist layer on the hard mask layer, performing exposure and development processes on the photoresist layer, transferring the pattern on the mask plate to the photoresist layer to form a patterned photoresist layer, thereby transferring the pattern on the mask plate to the photoresist layer; the pattern on the photoresist layer may be continuously transferred to the hard mask layer; wherein, the photoresist layer and the hard mask layer together form a third mask layer; using the third mask layer to etch the first barrier material layer 406 to form the first barrier layer 408.

[0065] It should be noted that the mask plate refers to a photomask that blocks light during exposure and only allows part of the light to pass through. The mask plate can be understood as a film containing the layout information of the semiconductor structure pattern. After exposure, the layout on the mask plate is transferred to the semiconductor structure. The mask layer refers to a patterned shielding layer located above the material layer to be etched in the lithography process. The mask layer can be a photoresist layer, or the mask layer can include a photoresist layer and a hard mask layer.

[0066] Here, the first barrier material layer 406 is etched along the Z direction, and the etching depth is the same as the height of the first barrier material layer 406 along the Z direction. That is, the first barrier material layer 406 is etched along the Z direction to form the first barrier layer 408 (i.e., the barrier sub-layer 410) and expose the top surface of the first dielectric layer 402.

[0067] Here, the process of etching to form the first barrier layer 408 may include wet etching, dry etching, or a combination thereof.

[0068] Here, the first barrier layer 408 formed by etching includes at least one barrier sub-layer 410, and the number of barrier sub-layers 410 is the same as the number of subsequent grooves formed, and each barrier sub-layer 410 is used to cover the bottom of a groove.

[0069] Here, the distribution position of the barrier sub-layer 410 on the first dielectric layer 402 is the same as the distribution position of the subsequent grooves formed by etching. That is, the positive projection of the barrier sub-layer 410 on the XY plane coincides with the positive projection of the bottom of the subsequent grooves formed by etching on the XY plane. For example, if the number of grooves is 4 and the 4 grooves are arranged in a 2-row * 2-column manner, then correspondingly, the number of barrier sub-layers is also 4, and the 4 barrier sub-layers are also arranged in a 2-row * 2-column manner, and each groove bottom corresponds to a barrier sub-layer 410 one by one.

[0070] Here, the size of the blocking sub-layer 410 in the X direction is the same as the size of the bottom of the groove in the X direction, and the size of the blocking sub-layer 410 in the Y direction is the same as the size of the bottom of the groove in the Y direction, that is, the bottom of the groove formed by etching exactly exposes the blocking sub-layer 410 and does not expose the first dielectric layer 402. In other words, the blocking sub-layer 410 exactly covers the bottom of the groove.

[0071] As Figure 4C shown, in the embodiment of the present disclosure, in step S302, a second dielectric layer 412 covering the first dielectric layer 402 and the first blocking layer 408 is formed.

[0072] Here, the material of the second dielectric layer 412 may include an insulating material, and the insulating material may include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

[0073] Here, the materials of the first dielectric layer 402 and the second dielectric layer 412 may be the same or different.

[0074] Here, the process of forming the second dielectric layer 412 may include, but is not limited to, CVD, PECVD, MOCVD, PVD, ALD, or any combination thereof.

[0075] In the embodiment of the present disclosure, in step S303, a groove 414 penetrating the second dielectric layer 412 is etched; the bottom of the groove 414 exposes the blocking sub-layer 410.

[0076] As Figure 4D shown, in some embodiments, step S303 includes: forming a first mask layer on the second dielectric layer 412; etching the second dielectric layer 412 along the Z direction by using the first mask layer to form a first sub-groove 416 penetrating the second dielectric layer 412; the bottom of the first sub-groove 416 exposes the blocking sub-layer 410 and does not expose the first dielectric layer 402 and the conductive layer 404.

[0077] Exemplarily, forming the first sub-groove 416 may include the following steps: forming a hard mask layer on the second dielectric layer 412, coating a photoresist layer on the hard mask layer, performing exposure and development processes on the photoresist layer, transferring the pattern on the mask plate to the photoresist layer to form a patterned photoresist layer, so as to transfer the pattern on the mask plate to the photoresist layer; the pattern on the photoresist layer can be continuously transferred to the hard mask layer; wherein, the photoresist layer and the hard mask layer together form the first mask layer; etching the second dielectric layer 412 by using the first mask layer to form the first sub-groove 416. Of course, the first mask layer can also be a patterned photoresist layer.

[0078] Here, the second dielectric layer 412 is etched along the Z direction, and the etching depth is the same as the height of the second dielectric layer 412 along the Z direction. That is, the second dielectric layer 412 is etched along the Z direction to form a first sub-groove 416 and expose the barrier sub-layer 410.

[0079] Here, the process of etching to form the first sub-groove 416 may include wet etching, dry etching, or a combination thereof.

[0080] As Figure 4D shown, in some embodiments, step S303 further includes: forming a filling layer in the first sub-groove 416; forming a second mask layer on the filling layer; etching the filling layer and the second dielectric layer 412 using the second mask layer to form a second sub-groove 418; wherein, the dimension of the second sub-groove 418 along the direction parallel to the first dielectric layer (i.e., the X direction) is greater than the dimension of the first sub-groove 416 along the direction parallel to the first dielectric layer (i.e., the X direction); each second sub-groove 418 communicates with at least one first sub-groove 416 to form a groove 414. Here, the direction parallel to the first dielectric layer refers to the direction parallel to the top surface of the first dielectric layer, and this direction is perpendicular to the thickness direction of the first dielectric layer.

[0081] Figure 4D Schematically shows that each second sub-groove 418 communicates with one first sub-groove 416 to form a groove 414.

[0082] Exemplarily, forming the second sub-groove 418 may include the following steps: forming a hard mask layer on the second dielectric layer 412 and the filling layer, coating and forming a photoresist layer on the hard mask layer, performing exposure and development processes on the photoresist layer, transferring the pattern on the mask plate to the photoresist layer to form a patterned photoresist layer, thereby transferring the pattern on the mask plate to the photoresist layer; the pattern on the photoresist layer can be continuously transferred to the hard mask layer; wherein, the photoresist layer and the hard mask layer together form the second mask layer; etching the filling layer and the second dielectric layer 412 using the second mask layer to form the second sub-groove 418. Of course, the second mask layer can also be a patterned photoresist layer.

[0083] Here, the filling layer and the second dielectric layer 412 are etched along the Z direction, and the etching depth is less than the height of the second dielectric layer 412 along the Z direction. That is, the filling layer and the second dielectric layer 412 are etched along the Z direction to form the second sub-groove 418.

[0084] Here, the process of etching to form the second sub-groove 418 may include wet etching, dry etching, or a combination thereof.

[0085] As Figure 4E shown, in the embodiments of the present disclosure, in step S304, a second barrier layer 420 covering the sidewalls of the groove 414 is formed.

[0086] Here, the material of the second barrier layer 420 may include, but is not limited to, titanium nitride or tantalum nitride. The present disclosure does not impose any special limitation on the material of the second barrier layer 420, and it can be flexibly selected according to the actual situation. The present disclosure also does not impose any special limitation on the thickness of the second barrier layer 420, and it can be flexibly selected according to the actual situation.

[0087] Here, the materials of the first barrier layer 408 and the second barrier layer 420 are the same.

[0088] In some embodiments, the second barrier layer 420 is formed by a magnetron sputtering process.

[0089] Here, the magnetron sputtering process can be used to bombard the target material with high-energy particles, so that the target atoms obtain sufficient power to move outward, leave the target material and are sputtered out. Since the first barrier layer (i.e., the barrier sub-layer) has been formed before the groove is etched, during the magnetron sputtering process, a re-sputtering process will also occur while the second barrier layer covering the side wall of the groove is deposited. After the target material is sputtered out, it may be deposited on the side wall of the groove or may hit the barrier sub-layer. At this time, the barrier sub-layer can play a protective role to prevent the target material from directly hitting the bottom of the groove and thus forming a concave shape. In this way, the contact interface between the barrier sub-layer and the conductive layer is basically flat.

[0090] In the embodiments of the present disclosure, a first barrier material layer is pre-deposited before the groove is etched, and the first barrier material layer is etched by a photolithography process to form the first barrier layer. Since the first barrier material layer is deposited in a flat manner when it is pre-deposited, the process difficulty is small, and it can ensure the continuity and sufficient thickness of the first barrier layer. Under the condition that the subsequent process remains unchanged, the filling performance of small-size grooves can be optimized, the process window can be enlarged, and the production cost can be greatly reduced.

[0091] In addition, after the groove is etched, a second barrier layer covering the side wall of the groove is formed. Since re-sputtering occurs while the second barrier layer is deposited, the material of the first barrier layer itself can be redistributed as a raw material in the small-size groove, avoiding the sealing of the top of the groove due to obtaining a continuous second barrier layer on the side wall of the groove. Before the groove is etched, the first barrier layer is pre-deposited, which can ensure the continuity of the first barrier layer covering the bottom of the groove and ensure that the first barrier layer covering the bottom of the groove and the second barrier layer covering the side wall of the groove are more likely to reach the expected thickness, which is more conducive to effectively blocking the diffusion of the conductive material and improving the reliability of the semiconductor structure.

[0092] When directly using a magnetron sputtering process to form a barrier layer covering the bottom and sidewalls of a groove with a small size or a high aspect ratio, it is difficult to form a barrier layer that takes into account both continuity and has sufficient thickness. In the embodiments of the present disclosure, before etching to form the groove, a first barrier layer covering the bottom of the groove is pre-formed using a magnetron sputtering process. After etching to form the groove, a second barrier layer covering the sidewalls of the groove is formed using a magnetron sputtering process. By adjusting the process parameters of the magnetron sputtering process, a first barrier layer and a second barrier layer that take into account both continuity and have sufficient thickness can be obtained using the magnetron sputtering process. In this way, the process window can be expanded, the manufacturing cost of the semiconductor structure can be reduced, and the diffusion of conductive materials can be effectively blocked, improving the performance and reliability of the semiconductor structure.

[0093] As Figure 4F shown, in some embodiments, after step S304, the method further includes: filling a conductive material in the groove 414 to form an interconnect structure 422; wherein, the interconnect structures 422 are isolated from each other.

[0094] As Figure 4F shown, in some embodiments, filling a conductive material in the groove 414 to form an interconnect structure 422 includes: filling a conductive material in the first sub-groove 416 and the second sub-groove 418 to form a conductive pillar 424 in the first sub-groove 416 and a conductive pad 426 in the second sub-groove 418; wherein, each conductive pad 426 is connected to at least one conductive pillar 424 to form an interconnect structure 422; the conductive pillars 424 are isolated from each other. Figure 4F Illustrates that each conductive pillar 424 is connected to a conductive pad 426 to form an interconnect structure 422.

[0095] Here, for each interconnect structure 422, the first barrier layer 408 (i.e., the barrier sub-layer 410) is located between the conductive pillar 424 and the conductive layer 404, and the second barrier layer 420 is located between the conductive pillar 424 and the second dielectric layer 412, or the second barrier layer 420 is located between the conductive pad 426 and the second dielectric layer 412. The first barrier layer 408 can block the diffusion of the interconnect structure 422 into the conductive layer 404, and the second barrier layer 420 can block the diffusion of the interconnect structure 422 into the second dielectric layer 412.

[0096] Here, the conductive material may include, but is not limited to, copper, aluminum, tungsten, and the like.

[0097] Exemplarily, filling a conductive material in the groove may include the following steps: forming a copper seed layer covering the bottom and sidewalls of the groove; filling a copper material in the groove.

[0098] Here, the process of forming the copper seed layer may include, but is not limited to, PVD.

[0099] Here, the process of filling the groove with copper material may include, but is not limited to, an electrochemical deposition process (Electrochemical Plating, ECP).

[0100] Exemplarily, the copper material may be planarized to remove the copper material and the second barrier layer material covering the top surface of the second dielectric layer 412, so as to expose the top surface of the second dielectric layer 412.

[0101] Here, the top surface of the interconnect structure 422 and the top surface of the second dielectric layer 412 are substantially flush. Substantially flush can be understood as that after chemical mechanical polishing treatment, the top surface of the formed interconnect structure 422 and the top surface of the second dielectric layer 412 are flush on the same plane, and in the process of chemical mechanical polishing treatment, within the process error range, there is a situation where the top surface of the interconnect structure 422 and the top surface of the second dielectric layer 412 are not flush on the same plane.

[0102] Reference Figure 5A and Figure 5B , Figure 5A and Figure 5B are schematic cross-sectional views of the semiconductor structure provided by the embodiments of the present disclosure. As Figure 5A and Figure 5B shown, the embodiments of the present disclosure provide a semiconductor structure. The semiconductor structure 400 includes: a first dielectric layer 402 and a second dielectric layer 412 located on the first dielectric layer 402; an interconnect structure 422 penetrating the second dielectric layer 412; a barrier sub-layer 410 located between the interconnect structure 422 and the first dielectric layer 402; the contact interface between the first dielectric layer 402 and the barrier sub-layer 410 is substantially planar; a second barrier layer 420 located between the interconnect structure 422 and the second dielectric layer 412.

[0103] In the embodiments of the present disclosure, a barrier sub-layer 410 is pre-formed on the first dielectric layer 402, and the contact interface between the first dielectric layer 402 and the barrier sub-layer 410 is substantially planar.

[0104] In some embodiments, a conductive layer 404 is provided in the first dielectric layer 402; the conductive layer 404 is connected to the barrier sub-layer 410 and the contact interface between the conductive layer 404 and the barrier sub-layer 410 is substantially planar.

[0105] In some embodiments, the interconnect structure 422 includes conductive posts 424 and conductive pads 426 located in the second dielectric layer 412, and each conductive pad 426 is connected to at least one conductive post 424.

[0106] Figure 5AIt is shown that each conductive pad 426 is connected to a conductive post 424 to form an interconnect structure 422, and different interconnect structures 422 are isolated from each other. More specifically, different conductive posts 424 are isolated from each other, and different conductive pads 426 are isolated from each other. Here, different interconnect structures 422 are shown to be isolated from each other in a relative positional relationship, and different interconnect structures 422 are electrically isolated from each other.

[0107] Figure 5B It is shown that a conductive pad 426 is connected to four conductive posts 424 to form an interconnect structure 422, and different interconnect structures 422 are isolated from each other. More specifically, different conductive posts 424 are isolated from each other. It should be noted that in the relative positional relationship, different conductive posts 424 in the same interconnect structure 422 are isolated by a second dielectric layer 412, but different conductive posts 424 in the same interconnect structure 422 are commonly connected to the same conductive pad 426. Here, different interconnect structures 422 are shown to be isolated from each other in a relative positional relationship, and different interconnect structures 422 are electrically isolated from each other. Different conductive posts 424 in the same interconnect structure 422 are electrically connected.

[0108] An embodiment of the present disclosure provides a semiconductor device, which includes a semiconductor structure manufactured by the manufacturing method of the semiconductor structure in the above technical solution.

[0109] Here, the semiconductor device includes a semiconductor structure manufactured by the above method.

[0110] In some embodiments, the above semiconductor structure can be used for bonding between two wafers. For example, a semiconductor structure is manufactured on a first wafer, and a semiconductor structure is also manufactured on a second wafer. Then, the interconnect structures in the semiconductor structure on the first wafer and the interconnect structures in the semiconductor structure on the second wafer are aligned, and the second dielectric layer on the first wafer and the second dielectric layer on the second wafer are aligned, so that the side of the first wafer having the interconnect structure and the side of the second wafer having the interconnect structure are bonded, and the interconnect structures on the first wafer and the interconnect structures on the second wafer are connected, thereby realizing the bonding of the first wafer and the second wafer.

[0111] In some embodiments, the above semiconductor structure can be used for connection between lower metal lines (i.e., lower conductive layers) and upper metal lines (i.e., upper conductive layers) in the same wafer. For example, a semiconductor structure is manufactured, the interconnect structure is connected to the lower conductive layer, and then an upper conductive layer is deposited above the semiconductor structure, thereby realizing the connection between the lower conductive layer and the upper conductive layer.

[0112] In some embodiments, the semiconductor device includes a memory.

[0113] Here, the memory may include a volatile memory and a non-volatile memory. The volatile memory includes a static random-access memory (SRAM) and a dynamic random access memory (DRAM). The non-volatile memory includes a NAND-type memory, a phase-change memory (PCM), and a magnetic random access memory (MRAM). The present disclosure does not have any special limitation on the type of the memory.

[0114] Embodiments of the present disclosure provide a semiconductor structure, a manufacturing method thereof, and a semiconductor device. The method includes: forming a first barrier layer on a first dielectric layer; the first barrier layer includes barrier sub-layers that are isolated from each other; forming a second dielectric layer covering the first dielectric layer and the first barrier layer; etching to form a groove penetrating through the second dielectric layer; the bottom of the groove exposes the barrier sub-layers; forming a second barrier layer covering the sidewalls of the groove. In the embodiments of the present disclosure, the first barrier layer (i.e., the barrier sub-layers) formed before etching to form the groove covers the bottom of the groove, and the second barrier layer formed after etching to form the groove covers the sidewalls of the groove. Thus, it can ensure the continuity of the barrier sub-layers covering the bottom of the groove and avoid the second barrier layer covering the sidewalls of the groove from sealing the top of the groove, thereby expanding the process window for forming the first barrier layer and the second barrier layer, and further improving the quality of the first barrier layer and the second barrier layer to improve the reliability of the semiconductor structure.

[0115] It should be understood that the term "one embodiment" or "an embodiment" mentioned throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of the present disclosure. Therefore, the appearances of "in one embodiment" or "in an embodiment" throughout the specification do not necessarily refer to the same embodiment. In addition, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in various embodiments of the present disclosure, the magnitudes of the serial numbers of the above processes do not mean the order of execution, and the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure above are only for description and do not represent the advantages or disadvantages of the embodiments.

[0116] The above are only the preferred embodiments of the present disclosure, and do not limit the patent scope of the present disclosure. Any equivalent structural transformation made under the inventive concept of the present disclosure by using the content of the specification and drawings of the present disclosure, or any direct / indirect application in other related technical fields is included in the patent protection scope of the present disclosure.

Claims

1. A manufacturing method of a semiconductor structure, characterized in that, The method includes: Forming a first barrier layer on a first dielectric layer; the first barrier layer includes barrier sub-layers that are isolated from each other; Forming a second dielectric layer covering the first dielectric layer and the first barrier layer; Etching to form a groove penetrating through the second dielectric layer; the bottom of the groove exposes the barrier sub-layers; Forming a second barrier layer covering the sidewalls of the groove.

2. The manufacturing method of the semiconductor structure according to claim 1, characterized in that, After forming the second barrier layer covering the sidewalls of the groove, the method further includes: Filling the groove with a conductive material to form an interconnect structure; wherein, the interconnect structures are isolated from each other.

3. The manufacturing method of the semiconductor structure according to claim 2, characterized in that, The etching to form a groove penetrating through the second dielectric layer includes: Forming a first mask layer on the second dielectric layer; Using the first mask layer to etch the second dielectric layer to form a first sub-groove penetrating through the second dielectric layer; the bottom of the first sub-groove exposes the barrier sub-layers.

4. The manufacturing method of the semiconductor structure according to claim 3, characterized in that, The etching to form a groove penetrating through the second dielectric layer further includes: Forming a filling layer in the first sub-groove; Forming a second mask layer on the filling layer; Using the second mask layer to etch the filling layer and the second dielectric layer to form a second sub-groove; wherein, the dimension of the second sub-groove in the direction parallel to the first dielectric layer is larger than the dimension of the first sub-groove in the direction parallel to the first dielectric layer; each second sub-groove communicates with at least one first sub-groove.

5. The manufacturing method of the semiconductor structure according to claim 4, wherein, The filling the groove with a conductive material to form an interconnect structure includes: Filling the first sub-groove and the second sub-groove with a conductive material to form conductive pillars in the first sub-groove and conductive pads in the second sub-groove; wherein, each conductive pad is connected to at least one conductive pillar to form an interconnect structure; the conductive pillars are isolated from each other.

6. The manufacturing method of the semiconductor structure according to claim 1, characterized in that, The forming the first barrier layer on the first dielectric layer includes: Providing the first dielectric layer; Forming a first barrier material layer covering the first dielectric layer; Forming a third mask layer on the first barrier material layer; Using the third mask layer to etch the first barrier material layer to form the first barrier layer; wherein, the first barrier layer includes the barrier sub-layers; the contact interface between the first dielectric layer and the barrier sub-layers is substantially planar.

7. The manufacturing method of the semiconductor structure according to claim 6, wherein, The first barrier material layer is formed by a magnetron sputtering process; The second barrier layer is formed by a magnetron sputtering process.

8. The manufacturing method of the semiconductor structure according to claim 1, characterized in that, A conductive layer is provided in the first dielectric layer; the conductive layer is connected to the barrier sub-layers and the contact interface between the conductive layer and the barrier sub-layers is substantially planar.

9. The manufacturing method of the semiconductor structure according to claim 1, wherein, The material of the first barrier layer includes tantalum nitride.

10. A semiconductor structure, characterized in that, The semiconductor structure includes: A first dielectric layer and a second dielectric layer located on the first dielectric layer; An interconnect structure penetrating through the second dielectric layer; Barrier sub-layers located between the interconnect structure and the first dielectric layer; the contact interface between the first dielectric layer and the barrier sub-layers is substantially planar; A second barrier layer located between the interconnect structure and the second dielectric layer.

11. The semiconductor structure according to claim 10, wherein, A conductive layer is provided in the first dielectric layer; the conductive layer is connected to the barrier layer and the contact interface between the conductive layer and the barrier layer is substantially planar.

12. The semiconductor structure according to claim 10, wherein The interconnect structure includes conductive posts and conductive pads located in the second dielectric layer, and each conductive pad is connected to at least one conductive post.

13. A semiconductor device, characterized in that, The semiconductor device includes a semiconductor structure manufactured by the manufacturing method of the semiconductor structure according to any one of claims 1 to 9.

14. The semiconductor device according to claim 13, wherein The semiconductor device includes a memory.

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