Semiconductor structure and forming method thereof

Abstract

The invention provides a semiconductor structure and a forming method thereof. The semiconductor structure includes a dielectric layer, a conductive layer and at least one support pillar. The conducting layer is arranged in the dielectric layer, and the supporting columns are arranged in the dielectric layer and located on the periphery of the conducting layer.

Description

Technical Field

[0001] The present invention relates to a semiconductor structure and a method for forming the same, and more particularly to a semiconductor structure including support pillars and a method for forming the same. Background Art

[0002] With the development of technology, semiconductor structures have been widely applied to various electronic devices. Due to the recent size and process miniaturization of electronic devices, many challenges are often faced during the manufacturing process of semiconductor structures.

[0003] For example, during the process of manufacturing the conductive layer of a semiconductor structure, chemical mechanical polishing (CMP) is often used to simultaneously remove part of the dielectric material and the conductive material, and stop after removing a certain amount of the dielectric material. However, dishing of the conductive layer often occurs during this process, which may lead to subsequent connection problems (e.g., forming an open circuit).

[0004] Since the result of chemical mechanical polishing is mainly determined by the characteristics of the polishing liquid, and it is difficult to change the properties of the polishing liquid, it may be difficult for existing semiconductor structures and their forming methods to improve the problem of dishing of the conductive layer. Summary of the Invention

[0005] Embodiments of the present invention provide a semiconductor structure including support pillars and a method for forming the same. Based on the polishing selectivity of the polishing liquid for the dielectric layer and the support pillars, the dishing of the conductive layer can be improved, thereby effectively improving subsequent connection problems and further enhancing the overall quality of the semiconductor structure.

[0006] According to some embodiments of the present invention, a semiconductor structure is provided. The semiconductor structure includes a dielectric layer, a conductive layer, and at least one support pillar. The conductive layer is disposed in the dielectric layer, and the support pillar is disposed in the dielectric layer and located around the conductive layer.

[0007] According to some embodiments of the present invention, a method for forming a semiconductor structure is provided. The method for forming a semiconductor structure includes the following steps. Forming a dielectric material. Patterning the dielectric material to form at least one first trench. Forming a support pillar in the first trench. Removing part of the dielectric material to form a dielectric layer having a second trench, wherein the support pillar surrounds the second trench. Forming a conductive layer in the second trench. Description of the Drawings

[0008] Figure 1 is a partial cross-sectional view of a semiconductor structure illustrated according to some embodiments of the present invention.

[0009] Figure 2A is a partial top view of a semiconductor structure illustrated according to some embodiments of the present invention.

[0010] Figure 2B Partial top views of semiconductor structures are shown according to some other embodiments of the present invention.

[0011] Figures 3A to 3G Partial cross-sectional views showing various stages of forming a semiconductor structure are shown according to some embodiments of the present invention.

[0012] Figures 4A to 4B are shown according to some embodiments of the present invention from Figure 3G stage to Figure 1 Partial cross-sectional views of the intermediate stage.

[0013] Figure 5 Partial cross-sectional views of semiconductor structures are shown according to some embodiments of the present invention.

[0014] Reference numerals:

[0015] 100, 102: Semiconductor structures

[0016] 10: Isolation layer

[0017] 12, 12’: Dielectric materials

[0018] 12H1, 12H2, 12H3, 12H4: Trenches

[0019] 14: Support material

[0020] 14A, 14A’, 14B, 14B’, 14C, 14C’, 14D, 14D’, 14E, 14F, 14G, 14H: Support pillars

[0021] 14T: Top surface of the support pillar

[0022] 16: Dielectric layer

[0023] 16H1, 16H2: Trenches

[0024] 18: Surface treatment layer

[0025] 20: Barrier layer

[0026] 22: Conductive layer

[0027] 22A: Lower part

[0028] 22B: Upper part

[0029] 22T: Top surface of the conductive layer

[0030] A - A’, B - B’: Lines

[0031] d14: Depth of the support pillar

[0032] S: Shortest distance DETAILED DESCRIPTION

[0033] Figure 1 FIG. 1 is a partial cross-sectional view of a semiconductor structure 100 according to some embodiments of the present invention. Figure 2A FIG. 1 is a partial top view of a semiconductor structure 100 according to some embodiments of the present invention. Figure 2B FIG. 1 is a partial top view of a semiconductor structure 100 according to some other embodiments of the present invention. For example, Figure 1 The semiconductor structure 100 shown may be along Figure 2A A cross-sectional view taken along the line AA', or a cross-sectional view taken along the line Figure 2B The cross-sectional view is cut along the line BB', but the embodiment of the present invention is not limited thereto. It should be noted that, for the sake of simplicity, Figure 1 , Figure 2A and Figure 2B Some components of the semiconductor structure 100 have been omitted.

[0034] Reference Figure 1 , Figure 2A and Figure 2B The semiconductor structure 100 includes an isolation layer 10 and a dielectric layer 16 disposed on the isolation layer 10. The semiconductor structure 100 also includes a conductive layer 22 and at least one support pillar (e.g., support pillars 14A, 14B, 14C, and / or 14D). The conductive layer 22 is disposed in the dielectric layer 16, and the support pillars 14A, 14B, 14C, and 14D are disposed in the dielectric layer 16 and are located around the conductive layer 22. In some embodiments, the support pillars surround the conductive layer 22.

[0035] The isolation layer 10 may include silicon nitride (Si x N y ), such as silicon nitride (SiN) or silicon carbonitride (SiCN). The dielectric layer 16 may be a high-k dielectric layer, such as tetraethoxysilane (TEOS) or SiH4 oxide.

[0036] The conductive layer 22 may include a conductive material such as a metal, a metal silicide, a similar material, or a combination thereof. For example, the metal includes gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), copper (Cu), a similar material, an alloy thereof, or a combination thereof. The conductive layer 22 may be formed by physical vapor deposition (PVD), chemical vapor deposition, atomic layer deposition, evaporation, sputtering, a similar process, or a combination thereof.

[0037] As Figure 1 shown, in this embodiment, the conductive layer 22 includes a lower portion 22A and an upper portion 22B. The upper portion 22B is connected above the lower portion 22A, and the lower portion 22A and the upper portion 22B have different widths (e.g., different diameters). For example, the lower portion 22A of the conductive layer 22 has a substantially the same width, the upper portion 22B of the conductive layer 22 has a variable width (e.g., getting wider from bottom to top), and the width of the lower portion 22A of the conductive layer 22 is less than the width of the upper portion 22B of the conductive layer 22, but the embodiments of the present invention are not limited thereto.

[0038] The support pillars 14A, 14B, 14C, and 14D may include the same or similar materials as the isolation layer 10. For example, the support pillars 14A, 14B, 14C, and 14D may include silicon nitride or silicon carbonitride.

[0039] In addition, as Figure 1 shown, in this embodiment, the support pillars 14A, 14B, 14C, and 14D are connected to the isolation layer 10. In other words, the support pillars 14A, 14B, 14C, and 14D may penetrate the dielectric layer 16 and be in direct contact with the isolation layer 10, but the embodiments of the present invention are not limited thereto. As Figure 1 shown, in some embodiments, the depth d14 of the support pillars 14A, 14B, 14C, and 14D is between about 100 nm and about 200 nm. It should be particularly noted that although the support pillars 14A, 14B, 14C, and 14D are shown to have the same depth in Figure 1 , the embodiments of the present invention are not limited thereto. In some other embodiments, the support pillars 14A, 14B, 14C, and 14D may also have different or variable depths.

[0040] In some embodiments, the material removal rate (MRR) of the dielectric layer 16 is greater than the material removal rate of the support pillars 14A, 14B, 14C, and 14D. In addition, as Figure 1 shown, in this embodiment, the top surface 22T of the conductive layer 22 is aligned with the top surfaces 14T of the support pillars 14A, 14B, 14C, and 14D, but the embodiments of the present invention are not limited thereto. In some other embodiments, the top surface 22T of the conductive layer 22 is substantially slightly higher than the top surfaces 14T of the support pillars 14A, 14B, 14C, and 14D.

[0041] In some embodiments, the support pillars (e.g., Figure 2A the support pillars 14A, 14B, 14C, and / or 14D shown) are formed into a closed pattern. For example, as Figure 2AAs shown in the top view, the conductive layer 22 can be formed into a circular shape. The support pillars 14A and 14B are substantially the same component and are formed into a closed circle; the support pillars 14C and 14D are substantially the same component and are formed into a closed circle. Furthermore, the support pillars 14A / 14B and the support pillars 14C / 14D can form concentric circles. In other embodiments, the support pillars 14A, 14B, 14C, and / or 14D can also be formed into a closed pattern with other shapes according to the shape of the conductive layer 22, which can be adjusted according to actual needs.

[0042] In some embodiments, the support pillars (e.g., Figure 2B the support pillars 14A, 14B, 14C, 14D, 14E, 14F, 14G, and / or 14H shown) are formed into a discontinuous pattern including multiple segments. For example, as Figure 2B shown in the top view, the conductive layer 22 is formed into a rectangle (e.g., a square). The support pillars 14A, 14B, 14E, and 14F are separated from each other and surround the conductive layer 22. The support pillars 14C, 14D, 14G, and 14H are separated from each other and surround the conductive layer 22 and are located outside the support pillars 14A, 14B, 14E, and 14F. In some other embodiments, the support pillars 14A, 14B, 14C, 14D, 14E, 14F, 14G, and / or 14H can also be formed into a discontinuous pattern with other arrangements according to the shape of the conductive layer 22, which can be adjusted according to actual needs.

[0043] In Figure 2A and Figure 2B the embodiments, the semiconductor structure 100 includes multiple support pillars (e.g., the support pillars 14A, 14B, 14C, 14D, 14E, 14F, 14G, and / or 14H), and these support pillars are arranged sequentially from the inside to the outside with the conductive layer 22 as the center. In some embodiments, in a top view, the shortest distance S between the outermost periphery of the support pillars and the conductive layer 22 is greater than or equal to about 100 nm. For example, as Figure 2A shown, the shortest distance S between the conductive layer 22 and the outermost periphery of the support pillars 14C / 14D is greater than or equal to about 100 nm; as Figure 2B shown, the shortest distance S between the conductive layer 22 and the outermost periphery of the support pillars 14C, 14D, 14G, or 14H is greater than or equal to about 100 nm.

[0044] Referring to Figure 1 , Figure 2A and Figure 2B, the semiconductor structure 100 further includes a surface treatment layer 18 and a barrier layer 20. The surface treatment layer 18 is disposed between the conductive layer 22 and the support pillars 14A / 14B, and the barrier layer 20 is disposed between the conductive layer 22 and the surface treatment layer 18. For example, the surface treatment layer 18 is formed by processing the dielectric layer 16 (e.g., ashing). That is, the surface treatment layer 18 could originally be part of the dielectric layer 16, but the embodiments of the present invention are not limited thereto. In some embodiments, the material removal rate of the surface treatment layer 18 is greater than that of the dielectric layer 16.

[0045] Figures 3A to 3G is a partial cross-sectional view showing various stages of forming the semiconductor structure 100 according to some embodiments of the present invention. Figures 4A to 4B is according to some embodiments of the present invention showing from Figure 3G the stage to Figure 1 the intermediate stage of. Similarly, for the sake of brevity, Figures 3A to 3G and Figures 4A to 4B some components of the semiconductor structure 100 have been omitted in.

[0046] As Figure 3A shown, in some embodiments, a dielectric material 12 is formed over the isolation layer 10. The isolation layer 10 is, for example, silicon nitride or silicon carbonitride. The dielectric material 12 is, for example, tetraethyl orthosilicate (TEOS) or SiH4 oxide. The isolation layer 10 and the dielectric material 12 can be formed by a deposition process, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), similar processes, or a combination of the foregoing.

[0047] Next, as Figure 3B shown, the dielectric material 12 is patterned to form (at least one) trench 12H1, 12H2, 12H3, and 12H4. For example, a mask layer (not shown) can be disposed over the dielectric material 12, and then an etching process is performed using the above mask layer to etch the dielectric material 12 to form the trenches 12H1, 12H2, 12H3, and 12H4. The mask layer can, for example, include a photoresist, such as a positive photoresist or a negative photoresist. The mask layer can include a hard mask and can be formed by silicon dioxide (SiO2), silicon nitride, silicon oxynitride (SiON), silicon carbide (SiC), silicon carbonitride, similar materials, or a combination of the foregoing. The mask layer can be a single-layer or multi-layer structure.

[0048] The mask layer can be formed by a deposition process, a lithography process, other suitable processes, or a combination of the foregoing. Herein, the deposition process includes, for example, spin-on coating, chemical vapor deposition, atomic layer deposition, similar processes, or a combination of the foregoing. The lithography process includes, for example, photoresist coating (e.g., spin-on coating), soft baking, mask aligning, exposure, post-exposure baking (PEB), developing, rinsing, drying (e.g., hard baking), other suitable processes, or a combination of the foregoing.

[0049] The etching process can include a dry etching process. For example, the dry etching process can include reactive ion etch (RIE), inductively-coupled plasma (ICP) etching, neutral beam etch (NBE), electron cyclotron resonance (ERC) etching, similar etching processes, or a combination of the foregoing.

[0050] As Figure 3B shown, the trenches 12H1, 12H2, 12H3, and 12H4 can penetrate the dielectric material 12 and expose a partial surface of the isolation layer 10, but the embodiments of the present invention are not limited thereto.

[0051] Next, as Figure 3C shown, a support material 14 is formed in the trenches 12H1, 12H2, 12H3, and 12H4 (and on the dielectric material 12). For example, the support material 14 can include silicon nitride and can be formed by atomic layer deposition; or, the support material 14 can include silicon carbonitride and can be formed by chemical vapor deposition, but the embodiments of the present invention are not limited thereto.

[0052] Next, as Figure 3DAs shown, a portion of the support material 14 is removed to form support pillars 14A, 14B, 14C, and 14D (in trenches 12H1, 12H2, 12H3, and 12H4). For example, a portion of the support material 14 can be removed by a wet etching process. The wet etching process can use, for example, hydrofluoric acid (HF), ammonium hydroxide (NH4OH), or any suitable etchant. In addition, in this embodiment, the support pillars 14A, 14B, 14C, and 14D can penetrate the dielectric material 12 and be in direct contact with the isolation layer 10, but the embodiments of the present invention are not limited thereto.

[0053] Next, as Figure 3E shown, additional dielectric material 12' is formed over the support pillars 14A, 14B, 14C, and 14D and the dielectric material 12. For example, the dielectric material 12' can include the same or similar material as the dielectric material 12 and can be formed by the same or similar process, but the embodiments of the present invention are not limited thereto. After this step, the overall thickness of the dielectric material (12 or 12') can be substantially increased.

[0054] Next, as Figure 3F shown, a portion of the dielectric materials 12, 12' is removed to form a dielectric layer 16 having trenches 16H1 and 16H2 between the support pillar 14A and the support pillar 14B. In other words, the support pillars 14A and 14B are located on the periphery of the trenches 16H1, 16H2 and surround the trenches 16H1, 16H2. For example, a portion of the dielectric materials 12, 12' can be removed by the same or similar process as that for forming the trenches 12H1, 12H2, 12H3, and 12H4 to form the trenches 16H1, 16H2. Specifically, a dry etching process can be performed first to form the trench 16H1, and then another dry etching process can be performed to form the trench 16H2.

[0055] In addition, as Figure 3F shown, after the trenches 16H1 and 16H2 are formed, the dielectric layer 16 is surface-treated (for example, an ashing process is performed) to form a surface treatment layer 18. In other words, the surface treatment layer 18 can be, for example, formed by converting a portion of the surface of the dielectric layer 16, but the embodiments of the present invention are not limited thereto.

[0056] Next, as Figure 3GAs shown, a barrier layer 20 and a conductive layer 22 are sequentially formed on the surface treatment layer 18. Specifically, the conductive layer 22 is formed in the trenches 16H1 and 16H2 (and on the surface treatment layer 18), such that the support pillars 14A and 14B (and the support pillars 14C and 14D) are located on the periphery of the conductive layer 22 filled in the trenches 16H1 and 16H2 and surround the conductive layer 22. The barrier layer 20 and the conductive layer 22 can be formed by a deposition process, and examples of the deposition process have been described above and will not be repeated here.

[0057] After the stage as shown in Figure 3G , a part of the surface treatment layer 18, a part of the barrier layer 20, and a part of the conductive layer 22 are removed to form a semiconductor structure 100 as shown in Figure 1 . For example, a part of the surface treatment layer 18, a part of the barrier layer 20, and a part of the conductive layer 22 can be removed by a chemical mechanical polishing process.

[0058] As shown in Figure 4A , after removing a part of the conductive layer 22, a part of the barrier layer 20, and exposing the surface treatment layer 18, since the material removal rate of the surface treatment layer 18 is relatively large, it can then be quickly removed, and during this process, the conductive layer 22 can be slightly higher (protruding) than the surface treatment layer 18.

[0059] Next, as shown in Figure 4B , after removing a part of the surface treatment layer 18 and exposing the support pillars 14A, 14C (and the support pillars 14B, 14D), since the material removal rate of the support pillars 14A, 14C (and the support pillars 14B, 14D) is relatively small, they are not easily removed. Based on the polishing selectivity of the polishing liquid for the dielectric layer 16, the support pillars 14A, 14C (and the support pillars 14B, 14D), and the conductive layer 22, at this time, the removal of a part of the conductive layer 22 can be controlled and focused on, so that the conductive layer 22 is finally flush with or slightly higher than the support pillars 14A, 14C (and the support pillars 14B, 14D). Therefore, the depression of the conductive layer 22 can be improved, thereby effectively improving subsequent connection problems and further enhancing the overall quality of the semiconductor structure.

[0060] Figure 5 is a partial cross-sectional view of a semiconductor structure 102 shown according to some embodiments of the present invention. A partial top view of the semiconductor structure 102 can be, for example, the same as or similar to the top view shown in Figure 2A or the top view shown in Figure 2B , but the embodiments of the present invention are not limited thereto. In addition, for the sake of simplicity, Figure 5 some components of the semiconductor structure 102 have been omitted.

[0061] Referring to Figure 5, the semiconductor structure 102 includes an isolation layer 10 and a dielectric layer 16, and the dielectric layer 16 is disposed on the isolation layer 10. The semiconductor structure 102 also includes a conductive layer 22 and at least one support pillar (e.g., support pillars 14A’, 14B’, 14C’ and / or 14D’), the conductive layer 22 is disposed in the dielectric layer 16, and the support pillars 14A’, 14B’, 14C’ and 14D’ are disposed in the dielectric layer 16 and are located around the conductive layer 22. In this embodiment, the support pillars 14A’, 14B’, 14C’ and 14D’ surround the conductive layer 22 and are separated from the isolation layer 10. In other words, the support pillars 14A’, 14B’, 14C’ and 14D’ do not completely penetrate the dielectric layer 16.

[0062] Similarly, in some embodiments, the semiconductor structure 102 further includes a surface treatment layer 18 and a barrier layer 20, the surface treatment layer 18 is disposed between the conductive layer 22 and the support pillar 14A’ / 14B’, and the barrier layer 20 is disposed between the conductive layer 22 and the surface treatment layer 18.

[0063] In summary, the semiconductor structure of the embodiment of the present invention includes support pillars. Based on the polishing selectivity of the polishing liquid for the dielectric layer, the support pillars and the conductive layer, the depression of the conductive layer can be improved, thereby effectively improving subsequent connection problems and further enhancing the overall quality of the semiconductor structure.

[0064] The above outlines the components of multiple embodiments so that those skilled in the art to which the present invention pertains can better understand the viewpoints of the embodiments of the present invention. Those skilled in the art to which the present invention pertains should understand that they can design or modify other processes and structures based on the embodiments of the present invention to achieve the same purposes and / or advantages as the embodiments introduced herein. Those skilled in the art to which the present invention pertains should also understand that such equivalent structures do not depart from the spirit and scope of the present invention, and they can make various changes, substitutions and replacements without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope defined in the appended claims. Additionally, although the present invention has been disclosed above with multiple preferred embodiments, it is not intended to limit the present invention.

Claims

1. A semiconductor structure, characterized in that, Comprising: A dielectric layer; A conductive layer disposed in the dielectric layer; And At least one support pillar disposed in the dielectric layer and located peripherally to the conductive layer.

2. The semiconductor structure according to claim 1, wherein The material removal rate of the dielectric layer is greater than that of the support pillar.

3. The semiconductor structure according to claim 1, wherein, In a top view, the support pillar is formed as a closed pattern.

4. The semiconductor structure according to claim 1, wherein In a top view, the support pillar is formed as a discontinuous pattern including a plurality of sections.

5. The semiconductor structure according to claim 1, wherein, Further comprising a plurality of support pillars, wherein the plurality of support pillars are arranged sequentially from the inside out with the conductive layer as the center.

6. The semiconductor structure according to claim 1, wherein, Further comprising: An isolation layer disposed under the dielectric layer, wherein the support pillar is connected to the isolation layer.

7. The semiconductor structure according to claim 1, wherein Further comprising: An isolation layer disposed under the dielectric layer, wherein the support pillar is separated from the isolation layer.

8. The semiconductor structure according to claim 1, wherein, Further comprising: A surface treatment layer disposed between the conductive layer and the support pillar.

9. The semiconductor structure according to claim 8, wherein The material removal rate of the surface treatment layer is greater than that of the dielectric layer.

10. The semiconductor structure according to claim 8, wherein, Further comprising: A barrier layer disposed between the conductive layer and the surface treatment layer.

11. A method for forming a semiconductor structure, characterized in that, Comprising: Forming a dielectric material; Patterning the dielectric material to form at least one first trench; Forming a support pillar in the first trench; Removing part of the dielectric material to form a dielectric layer having a second trench, wherein the support pillar is disposed peripherally to the second trench; And Forming a conductive layer in the second trench.

12. The method for forming a semiconductor structure according to claim 11, wherein, The material removal rate of the dielectric layer is greater than that of the support pillar.

13. The method for forming a semiconductor structure according to claim 11, wherein Further comprising: After forming the second trench, performing a surface treatment on the dielectric layer to form a surface treatment layer.

14. The method for forming a semiconductor structure according to claim 13, wherein, The surface treatment is an ashing process.

15. The method for forming a semiconductor structure according to claim 11, wherein Further comprising: Sequentially forming a barrier layer and the conductive layer on the surface treatment layer.

16. The method for forming a semiconductor structure according to claim 11, wherein, Further comprising: Forming an isolation layer before forming the dielectric material.

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