Kalman filter hardware accelerator chip applied to multi-target tracking

Abstract

The invention belongs to the technical field of integrated circuits, and particularly relates to a Kalman filter hardware accelerator applied to a multi-target tracking task. The accelerator structure mainly comprises a multiplication matrix, an addition matrix, an inversion matrix, a state controller, a high-speed cache module and a high-speed bus which are used for realizing a Kalman filtering algorithm, wherein the multiplication matrix, the addition matrix and the inversion matrix are special data processing units for Kalman filtering and are designed in an assembly line parallel manner. The accelerator optimizes the matrix operation and prediction updating process in the Kalman filtering algorithm through a specially designed hardware architecture, and the state controller distributes signals to each processing unit through a high-speed bus. According to the method, the operation delay of the Kalman filter in a complex environment is reduced in a hardware acceleration mode, the power consumption of an operation unit is saved, and meanwhile, the dependence on the performance of a processor is reduced.

Description

Technical Field

[0001] The present invention belongs to the field of integrated circuit technology, and particularly relates to a Kalman filter. Background Art

[0002] The Kalman filter is a classic recursive algorithm that is widely used in fields such as signal processing, automatic control, and target tracking. Especially in multi-target tracking tasks, it has attracted much attention due to its high-precision estimation ability of the dynamic system state. However, the calculation process of the Kalman filter involves a large number of complex matrix operations, including matrix multiplication, inversion, transposition, etc. Moreover, in a multi-target scenario, the computational complexity increases exponentially with the increase in the number of targets, which poses a huge challenge to real-time performance and computational resources. Currently, the implementation of the Kalman filter mostly relies on general-purpose processors (CPUs) or digital signal processors (DSPs). Although these processors can flexibly implement the algorithm through software programming, limited by their pipeline structure and instruction scheduling capabilities, it is difficult to efficiently process the large number of parallel matrix operations required by the Kalman filter. While occupying a large amount of processor resources, it also fails to meet the real-time requirements.

[0003] In recent years, to solve the above problems, the academic and industrial communities have begun to explore the hardware-accelerated implementation of the Kalman filter. Some studies have tried to use field-programmable gate arrays (FPGAs) or application-specific integrated circuits (ASICs) to implement some computational modules of the Kalman filter, such as matrix multiplication accelerators. However, most of the existing hardware acceleration schemes only optimize a single computational module, lacking a global optimization design for the complete computational process of the Kalman filter. Although this modular acceleration method can improve the performance of certain operations, the overall performance improvement is still limited.

[0004] Therefore, designing a dedicated hardware accelerator that can comprehensively cover all key steps of the Kalman filter, aiming at the efficient implementation of matrix operations and the reasonable utilization of hardware resources, can not only improve the performance of the Kalman filter, reduce power consumption and resources, but also free up general-purpose processors for other tasks. Summary of the Invention

[0005] The purpose of the present invention is to propose a Kalman filter hardware accelerator applied to multi-target tracking, and the main solutions are as follows:

[0006] A Kalman filter hardware accelerator applied to multi-target tracking proposed by the present invention, its circuit structure includes: a state control unit, a matrix operation module, a matrix processing unit, a cache module, and a data transmission bus. The input signal is distributed to each operation unit by the state control unit through a high-speed bus. The matrix operation module is used to perform matrix operations in the Kalman filter process, and the matrix processing unit is used to process matrix multiplication and matrix addition and subtraction in the algorithm.

[0007] In the present invention, the state controller has a serial pipeline structure, and the Kalman filtering algorithm is split into 11 states according to the sequence of data processing, and each state consists of a set of multiplication operations and addition operations.

[0008] In the present invention, the matrix processing unit is composed of an addition matrix and a multiplication matrix, and works through time-division multiplexing technology. There is only one such processing unit, and the matrix size is the same as the input elements of the Kalman filter, that is, the Kalman filter signal is an N-dimensional element, and the matrix size is N×N.

[0009] In the present invention, the matrix operation module includes matrix inversion and matrix transposition, and the matrix inversion is a diagonal matrix inversion operation module dedicated to the Kalman filter. The inversion and transposition modules work through time-division multiplexing technology. There is only one such module, and the matrix size is the same as the input elements of the Kalman filter, that is, the Kalman filter signal is an N-dimensional element, and the matrix size is N×N. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a schematic diagram of the hardware accelerator structure of the Kalman filter of the present invention.

[0011] Figure 2 is a schematic diagram of state control.

[0012] Figure 3 is a schematic diagram of the matrix processing unit. DETAILED DESCRIPTION OF THE INVENTION

[0013] The present invention will be described in more detail below with reference to the accompanying drawings. In the various drawings, the same elements are denoted by like reference numerals. For clarity, the various parts in the drawings are not drawn to scale. In addition, some well-known parts may not be shown in the figures.

[0014] In the following, many specific details of the present invention are described, such as the structure, type, technology of the hardware, the size, bit width of the data, etc., in order to understand the present invention more clearly. However, as those skilled in the art can understand, the present invention may be implemented without these specific details.

[0015] Figure 1 shows a schematic diagram of the hardware accelerator structure of the Kalman filter of the present invention.

[0016] As Figure 1As shown in the figure, the Kalman filter hardware accelerator 100 in the present invention has a circuit structure including a state control unit 101, a matrix operation module 102, a matrix processing unit 103, a cache module 104, and a data transmission bus 105. The input signal is distributed by the state control unit 101 to each operation unit 102 and 103 through the high-speed bus 105. The matrix operation module 102 is used to perform matrix operations in the Kalman filtering process, and the parallel processing module 103 is used to process matrix multiplication and matrix addition and subtraction in the algorithm.

[0017] Figure 2 Shows the state control schematic diagram of the Kalman filter of the present invention.

[0018] As Figure 2 shown, the state controller in the present invention is a serial pipeline structure. The Kalman filtering algorithm is split into 11 states according to the order of data processing. In essence, it is the splitting and optimization of the Kalman filtering algorithm. The specific algorithm formula is as follows:

[0019]

[0020] Z k = H k X k + V

[0021]

[0022] X ′ k = X k + K ′ (Z k - H k X k )

[0023] P k ′ = P k - K ′ H k P k

[0024] The 11 states executed by the hardware include 1 reset state, 1 division state ( Figure 2 in ÷), and 9 multiplication states ( Figure 2 in ×), and are cyclically executed in a pipeline structure in the direction indicated by the arrow.

[0025] Figure 3 Shows the schematic diagram of the matrix processing unit of the present invention.

[0026] As Figure 3As shown, all hardware computing resources in the present invention are matrix processing networks, including an inverse matrix operation unit 301, a matrix transpose operation unit 302, and a multiplication, addition, and comparator array 303. There is only one set of the above modules, and the matrix size is the same as the input elements of the Kalman filter, that is, the Kalman filter signal is an N-dimensional element, and the matrix size is N×N.

[0027] In this article, the term "including", "comprising", or any other variant thereof is intended to cover non-exclusive inclusion, such that a series of elements (such as processes, methods, articles, or devices) included thereby not only include those elements but also other elements not expressly listed. Without further limitation, an element defined by the statement "including one..." does not exclude the existence of additional identical elements other than the element included.

[0028] In the present invention, the embodiments do not describe all details in detail, nor limit the invention to the specific embodiments described. According to the above description, many changes can be made, such as multipliers and adders with different structures. These embodiments are selected and specifically described in this specification to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and its modifications. The present invention is only limited by the claims and their full scope and equivalents.

Claims

1. A Kalman filter hardware accelerator applied to multi-target tracking, characterized in that The circuit structure includes: a state control unit, a matrix operation module, a matrix processing unit, a cache module, and a data transmission bus. The input signal is distributed by the state control unit to each operation unit through a high-speed bus. The matrix operation module is used to perform matrix operations in the Kalman filtering process, and the matrix processing unit is used to process matrix multiplication and matrix addition and subtraction in the algorithm.

2. The Kalman filter hardware accelerator applied to multi-target tracking according to claim 1, characterized in that, The state controller has a serial pipeline structure, and the Kalman filtering algorithm is split into 11 states according to the order of data processing. Each state consists of a set of multiplication operations and addition operations.

3. The Kalman filter hardware accelerator applied to multi-target tracking according to claim 2, wherein The matrix processing unit is composed of an addition matrix and a multiplication matrix and works through time-division multiplexing technology. There is only one such processing unit, and the matrix size is the same as the input elements of the Kalman filter, that is, the Kalman filter signal is an N-dimensional element, and the matrix size is N×N.

4. The Kalman filter hardware accelerator applied to multi-target tracking according to claim 2, characterized in that The matrix operation module includes matrix inversion and matrix transpose. Among them, the matrix inversion is a dedicated diagonal matrix inversion operation module for the Kalman filter. The inversion and transpose modules work through time-division multiplexing technology. There is only one such module, and the matrix size is the same as the input elements of the Kalman filter, that is, the Kalman filter signal is an N-dimensional element, and the matrix size is N×N.

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