Communication method and communication device based on LDPC (Low Density Parity Check) code

Abstract

According to the communication method and device based on the LDPC code, a matrix B of an LDPC basis matrix used for coding or decoding comprises an xth row and a yth column, the row weight of the xth row is an integer larger than or equal to 3, the column weight of the yth column is an odd number larger than or equal to 3, a matrix located in the xth row and the yth column in a first square matrix is a zero matrix, and the number of the xth row and the yth column in the first square matrix is larger than or equal to 1. The column weight of each column of the first square matrix except the yth column is an integer greater than or equal to 2. In other words, the row with the highest row weight and the column with the highest column weight in the matrix B can be staggered, so that four rings can be prevented from being generated in the basis matrix, the convergence speed is increased, and the coding performance is improved.

Description

Technical Field

[0001] The present application relates to the field of coding, and more particularly, to a communication method and a communication device based on LDPC codes. Background Art

[0002] Low-density parity check (LDPC) codes are one of the most mature and widely used channel coding schemes. Current LDPC codes often suffer from quad-cycles in the LDPC base matrix, hindering fast convergence and affecting encoding and decoding performance. Summary of the Invention

[0003] The embodiments of the present application provide a communication method and a communication device based on LDPC codes, which help to improve encoding or decoding performance.

[0004] In a first aspect, a communication method based on LDPC codes is provided, which can be executed by a transmitting device or a module or unit in the transmitting device (e.g., a chip). The transmitting device can be a terminal device or a network device.

[0005] The method includes: obtaining an information bit sequence; performing LDPC encoding on the information bit sequence according to an LDPC base matrix to obtain an LDPC codeword sequence, wherein the LDPC base matrix includes a first square matrix, the first square matrix is composed of the 1st to wth rows and the rth to r+w-1th columns of the LDPC base matrix, the first square matrix includes the xth row and the yth column, the row weight of the xth row is an integer greater than or equal to 3, the column weight of the yth column is an odd number greater than or equal to 3, the matrix located in the xth row and yth column of the first square matrix is a zero matrix, the column weight of each column of the first square matrix except the yth column is an integer greater than or equal to 2, and w, r, x, and y are positive integers; and outputting the LDPC codeword sequence.

[0006] In the above method, the xth row is the row with the highest row weight in the first matrix, the yth column is the column with the highest column weight in the first matrix, and the matrix located at the xth row and yth column in the first matrix is a zero matrix, that is, the row with the highest row weight and the column with the highest column weight can be staggered, which can avoid the generation of 4 cycles in the basis matrix, accelerate the convergence speed, and improve the coding performance.

[0007] On the other hand, since the rows with the highest row weight and the columns with the highest column weight can be staggered, parallel encoding can be achieved, thereby improving encoding efficiency.

[0008] In a second aspect, a communication method based on LDPC codes is provided, which can be executed by a receiving device or a module or unit in the receiving device (e.g., a chip). The receiving device can be a terminal device or a network device.

[0009] The method includes: obtaining an LDPC codeword sequence; decoding the LDPC codeword sequence according to an LDPC base matrix to obtain an information bit sequence, wherein the LDPC base matrix includes a first square matrix, the first square matrix is composed of the 1st to wth rows and the rth to r+w-1th columns of the LDPC base matrix, the first square matrix includes the xth row and the yth column, the row weight of the xth row is an integer greater than or equal to 3, the column weight of the yth column is an odd number greater than or equal to 3, the matrix located in the xth row and yth column of the first square matrix is a zero matrix, the column weight of each column of the first square matrix except the yth column is an integer greater than or equal to 2, and w, r, x, and y are positive integers.

[0010] In the above method, the xth row is the row with the highest row weight in the first matrix, the yth column is the column with the highest column weight in the first matrix, and the matrix located at the xth row and yth column in the first matrix is a zero matrix, that is, the row with the highest row weight and the column with the highest column weight can be staggered, which can avoid the generation of 4 cycles in the basis matrix, accelerate the convergence speed, and improve the coding performance.

[0011] On the other hand, since the rows with the highest row weight and the columns with the highest column weight can be staggered, parallel encoding can be achieved, thereby improving encoding efficiency.

[0012] In combination with any of the above aspects, in some implementations, each row of the first matrix except the x-th row has a row weight of 2, and each column of the first matrix except the y-th column has a column weight of 2.

[0013] In combination with any of the above aspects, in some implementations, the row weight of the x-th row is 3, and the column weight of the y-th column is 3.

[0014] In combination with any of the foregoing aspects, in some implementations, the first square matrix is a 4×4 matrix, and the base graph of the first square matrix is an M1 matrix, or the base graph of the first square matrix is a matrix obtained by performing at least one of a row transformation or a column transformation on the M1 matrix, wherein the M1 matrix is the following matrix:

[0015]

[0016] Among them, "0" represents a zero matrix of Zc×Zc, "1" represents a non-zero matrix of Zc×Zc, and Zc is a positive integer.

[0017] In combination with any of the above aspects, in some implementations, the base image of the first matrix is an M1 matrix, and the first matrix is an M2 matrix, where the M2 matrix is the following matrix:

[0018]

[0019] Among them, "-1" represents the zero matrix of Zc×Zc, "0" represents the identity matrix in the non-zero matrix of Zc×Zc, "a", "b", and "c" represent the matrices obtained by cyclically shifting the identity matrix of Zc×Zc by a, b, or c positions, respectively. The non-zero matrix of Zc×Zc also includes matrices represented by "a", "b", and "c", where a, b, and c are integers greater than or equal to 0.

[0020] In combination with any of the foregoing aspects, in some implementations, the first square matrix is a 5×5 matrix, and the base graph of the first square matrix is an M1 matrix. Alternatively, the base graph of the first square matrix is a matrix obtained by performing at least one of a row transformation or a column transformation on the M1 matrix, where the M1 matrix is the following matrix:

[0021]

[0022] Among them, "0" represents a zero matrix of Zc×Zc, "1" represents a non-zero matrix of Zc×Zc, and Zc is a positive integer.

[0023] In combination with any of the above aspects, in some implementations, the base image of the first matrix is an M1 matrix, and the first matrix is an M2 matrix, where the M2 matrix is the following matrix:

[0024]

[0025] Among them, "-1" represents the zero matrix of Zc×Zc, "0" represents the identity matrix in the non-zero matrix of Zc×Zc, "a", "b", and "c" represent the matrices obtained by cyclically shifting the identity matrix of Zc×Zc by a, b, or c positions, respectively. The non-zero matrix of Zc×Zc also includes matrices represented by "a", "b", and "c", where a, b, and c are integers greater than or equal to 0.

[0026] In combination with any of the above aspects, in some implementations, the base graph of the first square matrix is a matrix obtained by performing at least one of row transformation or column transformation on the M1 matrix, and the first square matrix is a matrix obtained by performing at least one of row transformation or column transformation on the M2 matrix.

[0027] In combination with any of the above aspects, in some implementations, at least two of a, b, and c are equal.

[0028] In combination with any of the above aspects, in some implementations, the LDPC base matrix includes a core matrix, the core matrix includes a first square matrix and a first matrix, the first matrix is composed of the 1st to wth rows and the 1st to r-1th columns of the LDPC base matrix, and the first matrix is determined based on the first square matrix.

[0029] In combination with any of the above aspects, in some implementations, at least two offset values corresponding to non-zero elements in the y-th column may be the same.

[0030] This can simplify the encoding process.

[0031] In combination with any of the above aspects, in some implementation manners, the offset values corresponding to the non-zero elements in each column except the y-th column are the same.

[0032] In a third aspect, a communication device is provided, and this device is used to execute the method provided by any of the above aspects or its implementation manners. Specifically, this device may include units and / or modules for executing the method provided by any of the above aspects or its implementation manners, such as a processing unit and / or a transceiver unit.

[0033] In one implementation manner, this device is a transmitting-end device or a receiving-end device. When this device is a transmitting-end device or a receiving-end device, the transceiver unit may be a transceiver, or an input / output interface, or a communication interface, or an interface unit; the processing unit may be at least one processor. Optionally, the transceiver is a transceiver circuit. Optionally, the input / output interface is an input / output circuit.

[0034] In another implementation manner, this device is a chip, a chip system or a circuit in a transmitting-end device or a receiving-end device. When this device is a chip, a chip system or a circuit in a transmitting-end device or a receiving-end device, the transceiver unit may be an input / output interface, an interface circuit, an output circuit, an input circuit, a pin or a related circuit, etc. on this chip, chip system or circuit; the processing unit may be at least one processor, a processing circuit or a logic circuit, etc.

[0035] In a fourth aspect, a communication device is provided, and this device includes: at least one processor, this processor is coupled with a memory, this memory is used to store a program, and this processor is used to run the computer program or instruction stored in the memory to execute the method provided by any of the above aspects or its implementation manners.

[0036] In one implementation manner, this device is a transmitting-end device or a receiving-end device.

[0037] In another implementation manner, this device is a chip, a chip system or a circuit in a transmitting-end device or a receiving-end device.

[0038] In a fifth aspect, a communication device is provided, and this device includes: at least one processor and a communication interface, this at least one processor is used to obtain the computer program or instruction stored in the memory through this communication interface to execute the method provided by any of the above aspects or its implementation manners. This communication interface may be implemented by hardware or software.

[0039] In one implementation manner, this device further includes this memory.

[0040] In a sixth aspect, a processor is provided for executing the methods provided in the above aspects.

[0041] For operations such as sending and obtaining / receiving involved in the processor, if there is no special description, or if it does not conflict with its actual role or internal logic in the relevant description, then it can be understood as operations such as the processor outputting and receiving, inputting, etc., and can also be understood as the sending and receiving operations performed by the radio frequency circuit and the antenna. This application does not make any limitations in this regard.

[0042] In a seventh aspect, a computer-readable storage medium is provided, on which a computer program or instruction is stored. When the computer program or instruction runs on a computer, the computer is caused to execute the method provided in any of the above aspects or its implementation.

[0043] In an eighth aspect, a computer program product containing instructions is provided. When the computer program product runs on a computer, the computer is caused to execute the method provided in any of the above aspects or its implementation.

[0044] In a ninth aspect, a chip or a chip system is provided. The chip or the chip system includes a processor, and the processor causes a communication device installed with the chip or the chip system to execute the method provided in any of the above aspects or its implementation by running a computer program or instruction stored in a memory.

[0045] Optionally, the chip or the chip system further includes a communication interface, and the processor can run a computer program or instruction in the memory through the communication interface. Wherein, the communication interface can be implemented by hardware or software.

[0046] Optionally, as an implementation, the chip further includes a memory for storing a computer program or instruction.

[0047] Wherein, when the method provided in this application is executed by a chip, this application does not limit the number of chips for specifically implementing the method of this application. For example, it can be executed by one chip, or can be executed by 2 or more chips. And when the number of chips for implementing the method of this application is 2 or more, the chip manufacturers are not limited, and they can be the same manufacturer or different manufacturers.

[0048] In a tenth aspect, a communication system is provided, including at least one of the sending-end device or the receiving-end device described above.

[0049] In an eleventh aspect, a computer program is provided. When it runs on a computer, the method provided in any of the above aspects or its implementation is caused to be executed. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] Figure 1 It is a schematic diagram of a network architecture to which embodiments of the present application can be applied.

[0051] Figure 2 It is a schematic diagram of a parity-check matrix H of an LDPC.

[0052] Figure 3 It is a Tanner graph of a parity-check matrix H of an LDPC.

[0053] Figure 4 It is a schematic diagram of the structure of the parity-check matrix.

[0054] Figure 5 It is a schematic diagram of the information transmission process.

[0055] Figure 6 It is a schematic diagram of the structure of the base graphs of several B matrices.

[0056] Figure 7 It is a schematic flowchart of a communication method 700 based on LDPC codes provided by the present application.

[0057] Figure 8 and Figure 9 It is a schematic diagram of the encoding process provided by the embodiments of the present application.

[0058] Figure 10 It is a schematic flowchart of a communication method 1000 based on LDPC codes provided by the present application.

[0059] Figure 11 It is a comparison graph of the simulation results of the core matrix corresponding to the bidiagonal structure and the M b matrix of the present application.

[0060] Figure 12 and Figure 13 It is a schematic diagram of a possible communication device provided by the embodiments of the present application.

[0061] Figure 14 It is a schematic diagram of a chip system 30 provided by the embodiments of the present application. Detailed implementation manners

[0062] For ease of understanding the embodiments of the present application, before introducing the embodiments of the present application, the following points are explained first.

[0063] "For indicating" or "indicating" may include direct indication and indirect indication, or in other words, "for indicating" or "indicating" may indicate explicitly and / or implicitly.

[0064] Various numerical numbers such as first, second, etc. are only for the convenience of description and are not used to limit the scope of the embodiments of the present application, for example, to distinguish different messages, different information, etc. "

[0065] "Pre - defined" can be achieved by pre - saving corresponding codes, tables or other means that can be used to indicate relevant information in the device. The present application does not limit its specific implementation manner.

[0066] The "protocol" involved may refer to standard protocols in the communication field. For example, it may include long - term evolution (LTE) protocols, new radio (NR) protocols, and related protocols applied to future communication systems. The present application does not limit this.

[0067] Words such as "exemplary", "for example", "exemplarily", "as (another) example" are used to give examples, illustrations or explanations. Any embodiment or design solution described as "exemplary" in the present application should not be construed as being more preferred or having more advantages than other embodiments or design solutions.

[0068] The terms "comprise", "include", "have" and their variants all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0069] "At least one" means one or more, and "a plurality" means two or more. "And / or" describes the association relationship of associated objects and indicates that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone, where A and B can be singular or plural. The character " / " generally represents an "or" relationship between the associated objects before and after. "At least one (item)" or its similar expression refers to any combination of these items, including any combination of single item (s) or plural items (s). For example, at least one (item) of a, b, and c can represent: a, or, b, or, c, or, a and b, or, a and c, or, b and c, or, a, b, and c. Where a, b, and c can be single or multiple respectively.

[0070] "When", "if", "in the case of", and "if" all mean that in a certain objective situation, the network element will make corresponding processing. It does not limit the time, nor does it require the network element to have a judgment action when implemented, nor does it mean that there are other limitations. In addition, in the present application, the description of the above conditions of "when", "if", "in the case of", and "if" can be understood as a necessary condition, and it is not limited whether the condition is a sufficient condition or a sufficient and necessary condition. For example, "In the case of A, execute B" can be understood as "In the case of at least meeting A, execute B".

[0071] In addition, the network architecture and service scenarios described in the embodiments of this application are used to more clearly illustrate the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided by the embodiments of this application. Those of ordinary skill in the art can understand that with the evolution of the network architecture and the emergence of new service scenarios, the technical solutions provided by the embodiments of this application are equally applicable to similar technical problems.

[0072] Next, a communication system to which the embodiments of this application can be applied will be described.

[0073] The embodiments of this application can be applied to various communication systems, including but not limited to: the fifth generation (5G) system or NR system, LTE system, long term evolution-advanced (LTE-A) system, LTE frequency division duplex (FDD) system, LTE time division duplex (TDD) system, etc. It can also be applied to future communication systems, such as the sixth generation mobile communication system. In addition, it can also be applied to device-to-device (D2D) communication, vehicle-to-everything (V2X) communication, machine-to-machine (M2M) communication, machine type communication (MTC), Internet of Things (IoT) communication system, narrow band-Internet of Things (NB-IoT) or other communication systems. In addition, it can be extended to similar wireless communication systems, such as wireless-fidelity (WiFi), worldwide interoperability for microwave access (WIMAX), and communication systems related to the 3rd generation partnership project (3GPP), etc., without limitation.

[0074] A communication system applicable to the embodiments of this application may include one or more sending end devices, and one or more receiving end devices. Optionally, one of the sending end device and the receiving end device may be a terminal device, and the other may be a network device. Optionally, both the sending end device and the receiving end device may be terminal devices. Optionally, both the sending end device and the receiving end device may be network devices.

[0075] For example, Figure 1 A schematic diagram of a network architecture to which embodiments of the present application may be applied is shown.

[0076] like Figure 1 As shown, the embodiments of the present application can be applied to both uplink data transmission and downlink data transmission. Figure 1 The examples herein only use uplink data transmission or downlink data transmission between a network device and two terminal devices (e.g., terminal device 1 and terminal device 2) as an example. In uplink data transmission, the transmitting device herein is a terminal device, and the receiving device is a network device; conversely, in downlink data transmission, the transmitting device is a network device, and the receiving device is a terminal device. Furthermore, the applicability of the embodiments of the present application to other communication scenarios is not limited; for example, they may also be applied to sidelink communications.

[0077] The terminal device of the present application may also be referred to as user equipment (UE), access terminal, user unit, user station, mobile station, mobile station, mobile terminal (MT), remote station, remote terminal, mobile device, user terminal, terminal, drone, wireless communication device, user agent or user device, etc. The terminal device in the embodiments of the present application may refer to a device that provides voice and / or data connectivity to a user and can be used to connect people, objects and machines, such as a handheld device with wireless connection function, a vehicle-mounted device, etc. The terminal device in the embodiments of the present application can be a mobile phone, a tablet computer, a laptop computer, a PDA, a mobile internet device (MID), a wearable device, a virtual reality (VR) device, an augmented reality (AR) device, a wireless terminal in industrial control, a wireless terminal in self-driving, a wireless terminal in remote medical surgery, a wireless terminal in a smart grid, a wireless terminal in transportation safety, a wireless terminal in a smart city, a wireless terminal in a smart home, etc.

[0078] The network device of the present application may be a device with wireless transceiver functions. The network device may be a device providing wireless communication function services, usually located on the network side, including but not limited to the next-generation base station (gNodeB, gNB) in the 5G system, the base station in the sixth-generation mobile communication system, the base station in the future mobile communication system, or the access node in the wireless fidelity (WiFi) system, the evolved node B (eNB) in the long term evolution (LTE) system, the radio network controller (RNC), the node B (NB), the base station controller (BSC), the home base station (e.g., home evolved NodeB or home Node B, HNB), the base band unit (BBU), the transmission reception point (TRP), the transmitting point (TP), the base transceiver station (BTS), satellites, drones, etc.

[0079] In a network structure, the network device may include a centralized unit (CU) node, or include a distributed unit (DU) node, or be a radio access network (RAN) device including a CU node and a DU node, or be a RAN device including a control plane CU node, a user plane CU node, and a DU node. Alternatively, the network device may also be a wireless controller, a relay station, a vehicle-mounted device, a wearable device, etc. in the cloud radio access network (CRAN) scenario. In addition, the base station may be a macro base station, a micro base station, a relay node, a donor node, or a combination thereof. The base station may also refer to a communication module, a modem, or a chip disposed in the aforementioned device or apparatus. The base station may also be a mobile switching center and a device undertaking the base station function in D2D, V2X, M2M communications, a network-side device in the 6G network, a device undertaking the base station function in future communication systems, etc. The base station may support networks with the same or different access technologies, which is not limited.

[0080] Unless otherwise specified, the device for implementing the functions of the terminal device or the network device in this application may refer to the terminal device or the network device itself, or may refer to a device capable of supporting the terminal device or the network device to implement the functions, such as a chip system or a chip. Specifically, a system on a chip (SoC), a modem. The device may be installed in the terminal device or the network device. In the embodiments of this application, the chip system may be composed of chips, or may include chips and other discrete devices.

[0081] It should also be noted that some embodiments in this article introduce specific solution details taking the 5G system as an example. It can be understood that when this solution is used in other communication systems, for example, the LTE system, or future communication systems, each message, channel, or information in the solution can be replaced with messages, channels, or information that can implement the corresponding functions in other communication systems. This application does not make any limitations in this regard.

[0082] In addition, the embodiments of this application can be applied to various application scenarios, such as high-throughput scenarios, high-reliability scenarios, low-latency scenarios, high-reliability low-latency scenarios, or low-power scenarios. Among them, high-throughput scenarios can be, for example, enhanced mobile broadband (eMBB) scenarios, etc., high-reliability low-latency scenarios can be, for example, ultra reliable low latency communication (URLLC) scenarios, etc., and low-power scenarios can be, for example, M2M scenarios, MTC scenarios, or IoT scenarios, etc.

[0083] To facilitate the understanding of the embodiments of this application, several concepts or terms related to the embodiments of this application are briefly described. The concepts or terms introduced below are described based on the concepts or terms specified in the protocol, but it does not mean that the embodiments of this application can only be applied to existing systems. The concepts or terms involved in the embodiments of this application can be applied to future systems. And the specific names of the concepts or terms (for example, the concepts or terms related to functional descriptions) can be adjusted with the development of future systems.

[0084] 1. LDPC code

[0085] LDPC code is a linear block code, and its parity-check matrix is a sparse matrix. The number of zero elements in the parity-check matrix of LDPC is much larger than the number of non-zero elements. Or rather, the row weight and column weight of the parity-check matrix are very small numbers compared to the code length of LDPC.

[0086] An LDPC code with a length of K for an information bit sequence and a code length of N can be uniquely determined by its parity-check matrix. The dimension of the parity-check matrix H is (N - K) × N, and the corresponding codeword c can be defined by the parity-check matrix H as follows:

[0087] c = {c | Hc T = 0, c ∈ {0, 1} N}

[0088] In the parity-check matrix H, each row corresponds to a parity-check equation of the LDPC code, and each parity-check equation corresponds to a check node (CN). The N - K parity-check equations correspond to the N - K check nodes of the LDPC code; each column corresponds to a code element (or codeword bit) of the LDPC code, and each codeword bit corresponds to a variable node. The N code elements correspond to the N variable nodes (variable node, VN) of the LDPC code. The non-zero element h i,j in the matrix H indicates that the i-th check node is connected to the j-th variable node. The number of non-zero elements in each row of the parity-check matrix is the degree of the check node, and the number of non-zero elements in each column is the degree of the variable node. If the degrees of all check nodes are equal and the degrees of all variable nodes are also equal, the LDPC code corresponding to this matrix is a regular code; otherwise, it is an irregular code. A parity-check matrix H of a regular LDPC code with a code length of 10 and a code rate of 1 / 2 is as Figure 2 shown, where v0, v1, …, v9 represent variable nodes, and c0, c1, …, c4 represent check nodes.

[0089] Figure 2 is a schematic diagram of a parity-check matrix H of an LDPC. Figure 2 In it, there are 10 variable nodes and 5 check nodes. If a codeword bit is included in the corresponding parity-check equation, a connection is used to connect the involved variable node and check node to obtain a Tanner graph.

[0090] LDPC codes can be represented by a graph model. Commonly used graph models include Tanner graphs, factor graphs, and tree graphs, etc. Among them, the Tanner graph is described more simply and intuitively. Tanner represented the codeword of LDPC in the form of a graph in 1981. Now this graph is called a Tanner graph, and the Tanner graph corresponds one-to-one with the parity-check matrix. The Tanner graph consists of two types of vertices. One type of vertex represents the codeword bit and is called a variable node, and the other type of vertex is a check node, representing the parity-check constraint relationship. Each check node represents a parity-check constraint relationship. The following is an explanation in combination with Figure 3 this. Figure 3 Corresponding to the definition of degree in the matrix description, the degree of a node can be defined as the number of edges connected to it.

[0091] Figure 3 It is the Tanner graph of the parity-check matrix H of an LDPC.

[0092] As Figure 3 shown, the Tanner graph represents the parity-check matrix of the LDPC. For example, for a parity-check matrix H of size m rows and n columns, the Tanner graph contains two types of nodes, namely n variable nodes and m check nodes. Among them, the n variable nodes respectively correspond to the n columns of the parity-check matrix H, and the m check nodes respectively correspond to the m rows of the parity-check matrix H. The cycles in the Tanner graph are composed of vertices connected to each other. The cycle takes one of these vertices as both the starting point and the ending point, and only passes through each node once. The length of the cycle is defined as the number of connections it contains, and the girth of the graph, which can also be called the size of the graph, is defined as the minimum cycle length in the graph. As Figure 3 shown, the girth is 4, as Figure 3 shown by the thickened connections in. The variable nodes in the Tanner graph correspond to each column of the parity-check matrix H, that is, to each codeword bit of the LDPC. The check nodes in the Tanner graph respectively correspond to each row of the parity-check matrix H, that is, to the check bits of the LDPC. The connection situation between the two types of nodes corresponds to the value of the elements in the H matrix. If there is a connection relationship between the i-th check node and the j-th variable node, it means that the value of the element (i, j) in the H matrix is 1; if there is no connection, the corresponding element is 0. The connection between the variable node and the check node can also be called an edge. The existence of a connection relationship between the check node and the variable node can also be described as: there is a connection or an edge between the check node and the variable node. The edge relationship between the check node and the variable node can include two situations: there is an edge or there is no edge.

[0093] As described above, LDPC is a linear block code. A linear block code divides the information sequence to be encoded into groups of q bits, and then the encoder performs a linear operation on these q information bits to obtain m check bits. Then, these q information bits and m check bits are combined to obtain a codeword of length n = q + m. The mapping relationship from the q-bit information bits to the n-bit codeword is usually represented by a corresponding parity-check matrix H. According to the parity-check matrix H, a codeword sequence can be generated accordingly to complete the encoding process. After the codeword sequence is transmitted through the channel, the receiving-end device performs corresponding decoding on the received signal to determine the original information bits.

[0094] 2. QC-LDPC code

[0095] Quasi-cyclic low density parity check (QC-LDPC) codes are a type of structured LDPC codes. Due to the unique structure of its parity check matrix, encoding can be implemented using a simple feedback shift register, reducing the coding complexity of LDPC codes. When the code length is long, the parity check matrix H of the LDPC code will be very large. Therefore, H is usually represented in blocks: the complete parity check matrix H is considered to be composed of multiple Z c ×Z c Specifically, the complete check matrix H can be generated by a base matrix H b Indicates that H b Each element in corresponds to a Z c ×Z c Each submatrix can be represented by the number of cyclic shift bits, thus greatly reducing the storage space required for the complete check matrix H. b The elements in can also be called quasi-cyclic (QC) blocks.

[0096] Based on the basis matrix H b And the improvement value Z c (lifting size), the basis matrix H b Expanded to a complete check matrix for encoding or decoding. c It may also be called expansion factor, lifting factor, expansion value, expansion coefficient, or lifting size, etc.

[0097] Specifically, for the (N, K) QC-LDPC code, the number of check bits is M=NK, and the check matrix H can be expressed as:

[0098]

[0099] Where N = n b ×Zc,M=m b ×Zc,Zc≥1,P i,j Represents a Zc×Zc cyclic shift matrix or a Zc×Zc all-zero matrix, which can be represented by the corresponding cyclic shift coefficient p i,j To simplify the representation. The cyclic shift matrix here is defined as a cyclic right shift matrix of a unit matrix. The shift factor is determined by the number of bits of the first element shifted right, and the value range is P i,j ∈[-1, Z max -1], where Z max is the maximum value of Zc, that is, Zc≤Z max Therefore, p i,j =-1 represents an all-zero matrix, p i,j =0 represents the unit matrix, 1≤pi,j ≤Z max -1 means that each element in the unit matrix is cyclically shifted right by p i,j The matrix obtained by bit. The conversion function g(p i,j , Z) usually has the following form:

[0100]

[0101] Here, % represents the modulo operation.

[0102] For example, the basis matrix H of the QC-LDPC code b As shown below:

[0103]

[0104] It can be seen that the basis matrix H b The size of the matrix is 4 rows and 24 columns, and the basis matrix H b Each element in represents a Z c The matrix is a square matrix of order. Among them, the basis matrix H n The "-1" in the matrix represents an all-zero matrix, "0" represents the identity matrix, and values such as "13" and "48" represent the cyclic right shift matrix of the identity matrix, with the number of bits shifted right being 13, 48, etc.

[0105] Optionally, the basis matrix H b In addition to "-1", the zero elements in can also be expressed in other forms, such as using "-" or null values to represent an all-zero matrix.

[0106] 3. Non-zero elements and zero elements

[0107] In the check matrix, a zero element indicates that there is no connection relationship between the variable node and the check node, and a non-zero element indicates that there is a connection relationship between the variable node and the check node.

[0108] In the LDPC basis matrix, the zero element represents Z c An all-zero square matrix of order, with non-zero elements representing Z c The identity matrix of order or based on Z c The cyclic permutation matrix of the identity matrix of order , where the values of the non-zero elements represent the cyclic shift values or offset values (SV) relative to the identity matrix. The cyclic shift can be a right cyclic shift or a left cyclic shift.

[0109] This application does not limit the specific forms of zero elements and non-zero elements. Figure 2 In the check matrix H shown, "0" is used to represent a zero element, and "1" is used to represent a non-zero element. For another example, as described above, the base matrix H b"-1" is used to represent zero elements, and non-negative values (including 0, 1, 13, 48, etc.) are used to represent non-zero elements.

[0110] When the check matrix only indicates whether a connection exists, the matrix can also be called a basegraph (BG). Figure 2 The matrix shown is a base graph.

[0111] 4. Column weight and row weight

[0112] For a column of a matrix, the column weight can refer to the number of nonzero elements contained in the column. Column weight can also be called column degree or column degree.

[0113] For a row of a matrix, the row weight can refer to the number of non-zero elements contained in the row. Row weight can also be called row degree or row degree.

[0114] For example, Figure 2 As shown, the first column of the check matrix H has a column weight of 2 and the first row has a row weight of 4.

[0115] 5. Structure of the check matrix

[0116] Figure 4 It is a schematic diagram of the structure of the check matrix.

[0117] like Figure 4 As shown in (1), the check matrix may include a high rate region, an all-zero region, an incremental redundancy region, and a raptor-like region. Figure 4 As shown in (2), the high code rate area can include part A and part B, where part A corresponds to information bits (or information bits, system bits, etc.), and part B is a square matrix and corresponds to core check bits (or core check bits). The all-zero area can correspond to Figure 4 The C part of (2) is an all-zero matrix. The incremental redundancy region can correspond to Figure 4 Part D of (2). The Laputa-like region can correspond to Figure 4 The E part of (2) can be a unit matrix, corresponding to the parity bits of the low code rate extension.

[0118] Figure 4 The check matrix of the LDPC code shown in the figure adopts a "raptor-like" structure, which can be gradually extended to low code rates through a high code rate core matrix. Figure 4As shown in (1), the first X1 rows and Y1 columns of the check matrix can be truncated. As the code rate decreases from high to low, X1 and Y1 gradually increase, and the area of the matrix used also gradually expands.

[0119] It should be noted that the check matrix can be represented by the LDPC base matrix, so the structure of the LDPC base matrix is similar to that of the check matrix, which will not be described in detail here.

[0120] In the LDPC base matrix, the core rows are the rows corresponding to the core check bits. In other words, the core rows are the rows corresponding to the high code rate region, or the rows corresponding to part A, part B, or part C. The core columns can include all information columns and all core check columns. In other words, the core columns are the columns corresponding to the high code rate region, or the columns corresponding to part A + part B. The kernel matrix is a matrix region composed of all the core rows and all the core columns of the LDPC base matrix. In other words, the kernel matrix is the high code rate region of the LDPC base matrix, or the part composed of part A and part B.

[0121] In this application, the matrix of part A can be referred to as A matrix. Similarly, the matrices of part B, part C, part D, and part E can be referred to as B matrix, C matrix, D matrix, and E matrix, respectively.

[0122] 6. Information transmission process

[0123] Figure 5 It is a schematic diagram of the information transmission process. Figure 5 As shown in Figure 1, information is sent from the source, and after processing such as source coding, channel coding, modulation, air interface transmission, demodulation, channel decoding, and source recovery, it reaches the destination, completing the transmission of information from the source to the destination. Figure 5 The processing shown in the upper layer (including source coding, channel coding and modulation, etc.) is performed at the transmitting end device, and the processing shown in the lower layer (including demodulation, channel decoding, source recovery, etc.) is performed at the receiving end device. Figure 5 Source coding, channel coding, channel decoding and source recovery are shown.

[0124] In current LDPC codes, there are four cycles in the LDPC base matrix, which is not conducive to fast convergence and affects encoding or decoding performance.

[0125] It should be understood that the shortest loop of a variable node refers to the length of the shortest path, which is equivalent to the minimum number of iterations required for information from the node to be transmitted back to the node itself. Common short loops include 4 loops and 6 loops. The longer the shortest loop, the closer the information transmission algorithm is to the optimal algorithm, and the better the decoding performance.

[0126] For example, Figure 2 and Figure 3The dotted line in it represents a 4-cycle.

[0127] Figure 6 It is a schematic diagram of the base graphs of several B matrices applied in current LDPC codes. Figure 6 The shaded part in it represents non-zero elements, the blank part represents zero elements, and the dotted box represents a 4-cycle. Figure 6 The parity-check matrix corresponding to the B matrix in (1) of is called BG1, Figure 6 The parity-check matrix corresponding to the B matrix in (2) of is called BG2.

[0128] Among them, the B matrix of BG1 is as follows:

[0129]

[0130] The B matrix of BG2 is as follows:

[0131]

[0132] Among them, "0" represents the zero matrix of Zc×Zc, "1" represents the non-zero matrix of Zc×Zc, and Zc is a positive integer. It can also be said that "0" represents a zero element and "1" represents a non-zero element.

[0133] Such as Figure 6 As shown in (1) and (2) of, the B matrix adopts a bi-diagonal structure, that is, the B matrix is a bi-diagonal matrix. This kind of LDPC code has the characteristic of easy encoding. However, it can be seen from the figure that there are 4-cycles in the B matrix. Since in the message-passing decoding algorithm of LDPC codes, it is assumed that variable nodes are independent of each other, the existence of 4-cycles destroys the assumption of the independence of variable nodes. During the iterative decoding process, variable nodes will frequently pass messages to themselves, which is not conducive to the convergence of the decoding algorithm and leads to a significant decline in decoding performance.

[0134] Such as Figure 6 As shown in (3) of, in the standard 802.15.3, the B matrix adopts a lower-triangular structure.

[0135] Among them, the B matrix with a lower-triangular structure is as follows:

[0136]

[0137] Among them, "0" represents the zero matrix of Zc×Zc, "1" represents the non-zero matrix of Zc×Zc, and Zc is a positive integer. It can also be said that "0" represents a zero element and "1" represents a non-zero element.

[0138] Since there is no need to accumulate all the parity equations like the double diagonal structure before the lower triangular structure recursive encoding, the lower triangular structure has lower encoding complexity than the double diagonal structure. However, the lower triangular structure has higher row weight and column weight (as shown in (1) and (2) of Figure 6 The maximum row weight in this base graph is 3, as shown in (3) of Figure 6 The maximum row weight in this base graph is 4), and the number of 4-cycles in the lower triangular structure is more than that in the double diagonal structure (as shown in (1) and (2) of Figure 6 There is 1 4-cycle in this base graph respectively, as shown in (3) of Figure 6 There are 2 4-cycles in this base graph), during iterative decoding, when the node information is updated, the lower triangular structure needs to calculate more information from other nodes. Therefore, it has higher decoding complexity.

[0139] To solve the above problems, the present application provides a communication method and a communication device based on LDPC codes, which can eliminate short cycles, thereby achieving fast convergence and improving encoding or decoding performance.

[0140] The method embodiments of the present application will be described below with reference to the accompanying drawings.

[0141] Figure 7 is a schematic flowchart of a communication method 700 based on LDPC codes provided by the present application.

[0142] The method 700 can be executed by a sending end device. Without special instructions, the "sending end device" can refer to the sending end device itself or a device that can support the sending end device to implement its functions. For the convenience of description, the sending end device will be uniformly used to describe below. Among them, the sending end device can be a terminal device or a network device.

[0143] The method 700 may include at least one of the following steps.

[0144] Step 701, the sending end device obtains an information bit sequence.

[0145] That is to say, if the sending end device needs to communicate with the receiving end device, that is, the sending end device needs to send a signal to the receiving end device, the sending end device needs to first obtain the information bit sequence corresponding to the signal to be sent to the receiving end device.

[0146] Among them, the sending end device obtains an information bit sequence, which may mean that the sending end device performs source coding on source symbols to generate an information bit sequence. The sending end device obtains an information bit sequence, which may also mean that the sending end device receives an information bit sequence from other communication devices.

[0147] Step 702, the sending device performs LDPC encoding on the information bit sequence according to the LDPC base matrix to obtain an LDPC codeword sequence.

[0148] Among them, the LDPC base matrix can be a base matrix stored in the device or a base matrix predefined by the protocol, or it can also be a base matrix further obtained according to the stored base matrix or the base matrix predefined by the protocol, without limitation.

[0149] In the embodiments of the present application, the LDPC base matrix includes a first square matrix, and the first square matrix is composed of the first w rows to the w-th row and the r-th column to the (r + w - 1)-th column of the LDPC base matrix, where w and r are positive integers. Exemplarily, when the LDPC base matrix can be divided into five parts A, B, C, D, and E as shown in Figure 4 The first square matrix can be part B among them. The solution of the present application will be described below by taking the first square matrix as part B as an example. The first square matrix can also be referred to as the B matrix.

[0150] Among them, the first square matrix includes a row with a row weight greater than or equal to 3 (for the convenience of description, this row is denoted as the x-th row, where x is an integer and 1 ≤ x ≤ w) and a column with a column weight greater than or equal to 3 and odd (for the convenience of description, this column is denoted as the y-th column, where y is an integer and r ≤ y ≤ r + w - 1). The matrix located at the x-th row and the y-th column in the first square matrix is a zero matrix, and the column weight of each column except the y-th column in the first square matrix is an integer greater than or equal to 2.

[0151] Specifically, the matrix located at the x-th row and the y-th column in the first square matrix is a zero matrix, that is to say, the element located at the x-th row and the y-th column in the first square matrix is a zero element, and this zero element represents a zero matrix. Or rather, the non-zero elements corresponding to the row with the highest row weight and the non-zero elements corresponding to the column with the highest column weight can be staggered and have no overlap.

[0152] It should be understood that in the present application, the zero element in the matrix represents a zero matrix or a square matrix of all zeros. As Figure 2 shown, the "0" in the matrix H represents a zero element, and this zero element represents a square matrix of all zeros. As shown in the base matrix H above b shown, "-1" represents a zero element, and this zero element represents a square matrix of all zeros.

[0153] Specifically, the x-th row can be understood as the row with the highest row weight in the first square matrix, and the y-th column can be understood as the column with the highest column weight in the first square matrix.

[0154] The encoding structure of the first square matrix will be described in detail below in combination with Figures 8 to 9 for details.

[0155] Step 703, the sending device outputs the LDPC codeword sequence.

[0156] Subsequently, the transmitting device can map the LDPC codeword sequence into an air interface signal and send the air interface signal to the receiving device.

[0157] Based on the above solution, the matrix located in the x-th row and y-th column of the first square matrix is a zero matrix, that is, the non-zero elements in the row with the highest row weight and the non-zero elements in the column with the highest column weight are staggered. Since in the row or column with a higher weight, the probability of non-zero elements appearing is higher and it is easier to form a 4-cycle, therefore, staggering the non-zero elements in these rows and columns can, to a certain extent, avoid the generation of 4-cycles in the base matrix, accelerate the convergence speed, and improve the performance of encoding.

[0158] On the other hand, since the non-zero elements in the row with the highest row weight and the non-zero elements in the column with the highest column weight can be staggered, parallel encoding can be achieved, thereby improving the encoding efficiency.

[0159] In this application, the row weight of each row except the x-th row can be the same or different, and this application does not limit it.

[0160] Optionally, the row weight of each row of the first square matrix except the x-th row is equal, for example, all are 2.

[0161] In this application, the column weight of each column except the y-th column can be the same or different, and this application does not limit it.

[0162] Optionally, the column weight of each column of the first square matrix except the y-th column is equal, for example, all are 2.

[0163] Optionally, the row weight of the x-th row is 3, and the column weight of the y-th column is 3.

[0164] The embodiments of this application mainly improve the B part of the LDPC base matrix, that is, improve the encoding structure of the LDPC base matrix.

[0165] The encoding structure of the first square matrix will be described in detail below.

[0166] Optionally, the row weight of the x-th row is 3, the column weight of the y-th column is 3, the row weight of each row except the x-th row is 2, and the column weight of each column except the y-th column is 2.

[0167] As Example 1, the first square matrix is a 4×4 matrix, and the base graph of the first square matrix is the M1 matrix, or a matrix obtained by performing at least one of row transformation or column transformation on the M1 matrix, where the M1 matrix is the following matrix:

[0168]

[0169] Among them, "0" represents the zero matrix of Zc×Zc, "1" represents the non-zero matrix of Zc×Zc, and Zc is a positive integer. In other words, "0" represents the zero element, and "1" represents the non-zero element.

[0170] In this Example 1, matrix M1 is a 4×4 matrix. The row weights of the first to fourth rows are {3, 2, 2, 2} respectively, and the column weights of the first to fourth columns are {3, 2, 2, 2} respectively. That is, this matrix includes a row with a row weight of 3 (i.e., the first row) and a column with a column weight of 3 (i.e., the first column). The first row is the row with the highest row weight, and the first column is the column with the highest column weight. The row weight of each row except the first row is 2, and the column weight of each column except the first column is 2. The element located at the first row and first column in this matrix M1 is "0", which is a zero matrix. The non-zero elements in the first row are located in the second to fourth columns of the first row, and the non-zero elements in the first column are located in the second to fourth rows of the first column. That is, the non-zero elements in the row with the highest row weight and the non-zero elements in the column with the highest column weight can be staggered and have no intersection.

[0171] On the contrary Figure 6 , the element located at the x-th row and y-th column in these matrices is a non-zero element. That is, the non-zero elements in the row with the highest row weight and the non-zero elements in the column with the highest column weight cannot be staggered, that is, there is an intersection. For example, in Figure 6 of (1), the second row is the row with the highest row weight, and the first column is the column with the highest column weight. The element located at the second row and first column in the matrix is a non-zero element. Another example, in Figure 6 of (2), the third row is the row with the highest row weight, and the first column is the column with the highest column weight. The element located at the third row and first column in the matrix is a non-zero element. Another example, in Figure 6 of (3), the fourth row is the row with the highest row weight, and the first column is the column with the highest column weight. The element located at the fourth row and first column in the matrix is a non-zero element.

[0172] Next, the encoding process will be described in conjunction with matrix M1 and Figure 8 .

[0173] Figure 8 are schematic diagrams of several encoding processes provided by the embodiments of the present application.

[0174] According to the structure of the LDPC code as shown in Figure 4 , the matrix in part B is the M1 matrix described above. Assume that the input information bit sequence is s, and the length of s is n A , and A[i] represents the i-th row of matrix A, and the value of i is 1, 2, 3, 4. Assume:

[0175]

[0176] Among them, d1, d2, d3, and d4 represent the calculation results of A[i] and s, which are intermediate results in the encoding process.

[0177] Assuming that the codeword sequence output by the core matrix encoding is c1, then the equation group Established, so:

[0178] [AB]·[sp] T =0 (2)

[0179] Wherein, p represents the parity bit, p={p0, p1, p2, p3}, p0, p1, p2, p3 represent the parity bit values corresponding to the 1st to 4th columns respectively.

[0180] Expanding formula (2) yields:

[0181]

[0182] Where B[i] represents the i-th row of the B matrix.

[0183] like Figure 8 As shown in (1), substitute the values of formula (1) and M1 matrix into formula (3), and the calculation can be obtained:

[0184]

[0185] Solving equation (4) yields:

[0186]

[0187] It should be understood that the above operations are all modulo 2 operations.

[0188] In summary, the encoding process can be divided into two parts:

[0189] In the first part, sum all the equations to get the check bit value p0 corresponding to the first column;

[0190] In the second part, p1 to p3 are calculated based on the obtained check bit value p0 corresponding to the first column. Since the calculation processes of p1 to p3 are not interdependent, the second part can be encoded in parallel, which helps to reduce the encoding delay.

[0191] The following combination Figure 8 (2) and (3) briefly explain parallel coding and serial coding.

[0192] like Figure 8 As shown in (2), substitute the values of the B matrix of BG1 and Equation (1) into Equation (3), and the calculation yields:

[0193]

[0194] Solving the system of equations (5) gives:

[0195]

[0196] It should be understood that the above operations are all modulo 2 operations.

[0197] In summary, the encoding process can include two parts:

[0198] In the first part, summing all the systems of equations gives the check bit value p0 corresponding to the first column.

[0199] In the second part, based on the obtained check bit value p0 corresponding to the first column, p1 is calculated. Further, p2 is calculated based on p0 and p1. Still further, p3 is calculated based on p2. Since the calculation process of p2 depends on p0 and p1, and the calculation process of p3 depends on p2, the second part requires serial encoding and has a relatively large delay.

[0200] As Figure 8 shown in (3) of [], substituting the values of formula (1) and the B matrix with a lower triangular structure into formula (3), the operation gives:

[0201]

[0202] Solving the system of equations (6) gives:

[0203]

[0204] It should be understood that the above operations are all modulo 2 operations.

[0205] In summary, the encoding process can include two parts:

[0206] In the first part, d1 is used as the check bit value p0 corresponding to the first column.

[0207] In the second part, based on the obtained check bit value p0 corresponding to the first column, p1 is calculated. Further, p2 is calculated based on p0 and p1. Still further, p3 is calculated based on p0, p1 and p2. Since the calculation process of p2 depends on p0 and p1, and the calculation process of p3 depends on p0, p1 and p2, the second part requires serial encoding and has a relatively large delay.

[0208] Optionally, in this Example 1, the base graph of the first square matrix is the M1 matrix. Correspondingly, the first square matrix is the M2 matrix, where the M2 matrix is the following matrix:

[0209]

[0210] Here, "-1" represents the zero matrix of Zc×Zc, "0" represents the identity matrix in the non-zero matrix of Zc×Zc, and "a," "b," and "c" represent matrices obtained by cyclically shifting the identity matrix of Zc×Zc by a, b, or c positions, respectively. In addition to the identity matrix represented by "0," the non-zero matrix of Zc×Zc also includes matrices represented by "a," "b," and "c," where a, b, and c are integers greater than or equal to 0. Alternatively, "-1" represents a zero element, "0" represents a non-zero element with an offset of 0, and "a," "b," and "c" represent non-zero elements with offsets of a, b, or c, respectively. That is, a "0" in the M1 matrix is represented by "-1" in the M2 matrix, and a "1" in the M1 matrix is represented by "0," "a," "b," and "c" in the M2 matrix.

[0211] It should be understood that the cyclic shift in the present application may refer to a right cyclic shift or a left cyclic shift, without limitation.

[0212] Optionally, when the base image of the first square matrix is a matrix obtained by performing at least one of row transformation or column transformation on the M1 matrix, the first square matrix is a matrix obtained by performing at least one of row transformation or column transformation on the M2 matrix.

[0213] Exemplarily, Table 1 shows matrices obtained by performing at least one of row transformation or column transformation on the M1 matrix, and each matrix is numbered #1, #2, ..., #24.

[0214] Table 1

[0215]

[0216] It should be understood that Table 1 only lists a portion of matrices obtained by row transformation or column transformation of the M1 matrix, and the remaining matrices are not described in detail.

[0217] Optionally, in the first square matrix, at least two of the offset values corresponding to the non-zero elements in the y-th column may be the same. For example, in the M2 matrix mentioned above, at least two of a, b, and c may be the same.

[0218] It should be understood that Figure 8 In the encoding process shown, when calculating the parity bit of the first column, all rows need to be added together and duplicates eliminated to obtain p0. When at least two offset values are the same, the duplicates corresponding to the same offset value can be eliminated, simplifying the encoding process.

[0219] Optionally, in the first square matrix, the offset values corresponding to the non-zero elements in each column except the yth column are all the same. For example, in the M2 matrix mentioned above, the offset values of the non-zero elements in columns 2-4 are all 0.

[0220] As Example 2, the first square matrix is a 5×5 matrix, and the base graph of the first square matrix is the M3 matrix, or the base graph of the first square matrix is a matrix obtained by performing at least one of a row transformation or a column transformation on the M3 matrix, where the M3 matrix is the following matrix:

[0221]

[0222] Wherein, "0" represents the zero matrix of Zc×Zc, "1" represents the non-zero matrix of Zc×Zc, and Zc is a positive integer. It can also be said that "0" represents the zero element, and "1" represents the non-zero element.

[0223] In this Example 2, the matrix M3 is a 5×5 matrix. The row weights of the first to fifth rows are {3, 2, 2, 2, 2} respectively, and the column weights of the first to fifth columns are {3, 2, 2, 2, 2} respectively. That is, this matrix includes a row with a row weight of 3 (i.e., the first row) and a column with a column weight of 3 (i.e., the first column). The first row is the row with the highest row weight, and the first column is the column with the highest column weight. The row weight of each row except the first row is 2, and the column weight of each column except the first column is 2. The element at the first row and first column in the matrix M3 is "0", which is a zero matrix. The non-zero elements in the first row are located in the second to fourth columns of the first row, and the non-zero elements in the first column are located in the third to fifth rows of the first column. That is, the non-zero elements in the row with the highest row weight and the non-zero elements in the column with the highest column weight can be staggered and have no intersection.

[0224] Optionally, in this Example 2, the base graph of the first square matrix is the M3 matrix. Correspondingly, the first square matrix is the M4 matrix, where the M4 matrix is the following matrix:

[0225]

[0226] Wherein, "-1" represents the zero matrix of Zc×Zc, "0" represents the identity matrix in the non-zero matrix of Zc×Zc, and "a", "b", and "c" respectively represent the matrices obtained by circularly shifting the identity matrix of Zc×Zc by a, b, or c positions. The non-zero matrix of Zc×Zc includes, in addition to the identity matrix represented by "0", the matrices represented by "a", "b", and "c". a, b, and c are integers greater than or equal to 0. It can also be said that "-1" represents the zero element, "0" represents the non-zero element with an offset value of 0, and "a", "b", and "c" respectively represent non-zero elements with offset values of a, b, or c. That is, "0" in the M3 matrix is represented by "-1" in the M4 matrix, and "1" in the M3 matrix is represented by "0", "a", "b", and "c" in the M4 matrix.

[0227] It should be understood that the circular shift in this application can be a right circular shift or a left circular shift, without limitation.

[0228] Optionally, when the base graph of the first square matrix is a matrix obtained by performing at least one of a row transformation or a column transformation on the M3 matrix, the first square matrix is a matrix obtained by performing at least one of a row transformation or a column transformation on the M4 matrix.

[0229] Exemplarily, Table 2 shows matrices obtained by performing at least one of a row transformation or a column transformation on the M3 matrix, and the numbers of each matrix are #1, #2, …, #6 respectively.

[0230] Table 2

[0231]

[0232]

[0233] It should be understood that Table 2 only lists a part of the matrices obtained by performing a row transformation or a column transformation on the M3 matrix, and the remaining matrices will not be elaborated.

[0234] Optionally, in the first square matrix, at least two of the offset values corresponding to the non-zero elements in the y-th column can be the same. For example, in the M4 matrix mentioned above, at least two of a, b, and c are the same, so that the encoding process can be simplified.

[0235] Optionally, in the first square matrix, the offset values corresponding to the non-zero elements in each column except the y-th column are the same. For example, in the M4 matrix mentioned above, the offset values of the non-zero elements in columns 2 - 5 are all 0.

[0236] As Example 3, the first square matrix is an 8×8 matrix. For example, the base graph of the first square matrix is the M5 matrix, and the M5 matrix is as follows:

[0237]

[0238] In this Example 3, the matrix M5 is an 8×8 matrix. The row weights of the 1st to 8th rows are {2, 2, 2, 2, 2, 2, 3, 2}, and the column weights of the 1st to 8th columns are {3, 2, 2, 2, 2, 2, 2, 2}, that is, this matrix includes a row with a row weight of 3 (i.e., the 7th row) and a column with a column weight of 3 (i.e., the 1st column). The 7th row is the row with the highest row weight, and the 1st column is the column with the highest column weight. The row weight of each row except the 7th row is 2, and the column weight of each column except the 1st column is 2. The element located in the 1st column and 7th row of this matrix M5 is “0”, that is, it is a zero matrix. The non-zero elements in the 7th row are located in the 5th, 7th, and 8th columns of the 7th row, and the non-zero elements in the 1st column are located in the 1st, 3rd, and 8th rows of the 1st column, that is, the non-zero elements in the row with the highest row weight and the non-zero elements in the column with the highest column weight can be staggered and have no intersection.

[0239] Optionally, the row weight of the x-th row in the first matrix is an integer greater than 3.

[0240] As Example 4, the first square matrix is an 8×8 matrix. For example, the base image of the first square matrix is an M6 matrix, and the M6 matrix is as follows:

[0241]

[0242] In Example 4, the row weights of rows 1 to 8 are {6, 2, 1, 1, 1, 2, 2, 2}, and the column weights of columns 1 to 8 are {3, 2, 2, 2, 2, 2, 2, 2}. The row weight of row 1 is 6, and the row weights of the remaining rows are 2 or 1, with row 1 having the highest row weight. The column weight of column 1 is 3, and the column weights of the remaining columns are all 2, with column 1 having the highest column weight. The element in row 1 and column 1 of matrix M6 is "0," meaning it is a zero matrix. In other words, the non-zero elements in row 1 and column 1 are staggered and have no intersection.

[0243] Optionally, the column weight of the y-th column in the first square matrix is an odd number greater than 3.

[0244] As Example 5, the first square matrix is a 9×9 matrix, and its base graph is:

[0245]

[0246] In Example 5, the row weights of rows 1 to 9 are {2, 2, 2, 3, 2, 3, 2, 3, 2}, and the column weights of columns 1 to 9 are {5, 2, 2, 2, 2, 2, 2, 2, 2}. The row weights of rows 4, 6, and 8 are 3, and the row weights of the remaining rows are 2. Rows 4, 6, and 8 have the highest row weights. The column weight of column 1 is 5, and the column weights of the remaining columns are all 2, with column 1 having the highest column weight. The elements in rows 4, 6, and 8 and columns 1 of this matrix are all "0," making it a zero matrix. In other words, the non-zero elements in rows 4, 6, and 8 are staggered with the non-zero elements in column 1 and have no intersection.

[0247] Optionally, the row weight of each row in the first matrix except the x-th row is an integer greater than 2.

[0248] As Example 6, the first square matrix is a 9×9 matrix, and its base graph is:

[0249]

[0250] In this Example 6, the row weights of the first to the ninth rows are {3, 3, 4, 3, 3, 3, 4, 5, 3} respectively, the column weights of the first to the ninth columns are {5, 3, 4, 3, 3, 4, 3, 3, 3} respectively, the row weight of the eighth row is 5, the row weights of the remaining rows are 3 or 4, and the eighth row has the highest row weight. The column weight of the first column is 5, the column weights of the remaining columns are 3 or 4, and the first column has the highest column weight. The element at the intersection of the eighth row and the first column in this matrix is "0", which is a zero matrix. In other words, the non-zero elements in the eighth row and the non-zero elements in the first column are staggered and have no intersection.

[0251] Optionally, the column weight of each column in the first square matrix except the y-th column is an integer greater than 2.

[0252] As Example 7, the first square matrix is a 9×9 matrix, and its base graph is:

[0253]

[0254] In this Example 7, the row weights of the first to the ninth rows are {2, 2, 5, 3, 4, 3, 4, 3, 3} respectively, the column weights of the first to the ninth columns are {5, 3, 3, 3, 3, 3, 3, 3, 3} respectively, the row weight of the third row is 5, the row weights of the remaining rows are 2, 3 or 4, and the third row has the highest row weight. The column weight of the first column is 5, the column weights of the remaining columns are 3, and the first column has the highest column weight. The element at the intersection of the third row and the first column in this matrix is "0", which is a zero matrix. In other words, the non-zero elements in the third row and the non-zero elements in the first column are staggered and have no intersection.

[0255] Optionally, the row weights and column weights in the first square matrix satisfy the following characteristics: the column weight of the y-th column is odd, for example, it is N, the column weight of each column except the y-th column is 2, the row weight of the x-th row is 3, the row weights of each row except the x-th row are 3 or 2, and the element at the intersection of the x-th row and the y-th column is a zero element, that is, the column with column weight N is staggered from the row with row weight 3.

[0256] This can eliminate short cycles and improve the performance of encoding or decoding.

[0257] Among them, the number of rows with row weight 3 in the first square matrix is (N - 2), and the number of rows with row weight 2 is (w - N + 2), where w is the dimension of the first square matrix.

[0258] Among them, the relationship between the value of N and the dimension w of the first square matrix satisfies the following:

[0259]

[0260] Among them, represents rounding down.

[0261] As Example 8, the first square matrix is a 9×9 matrix, and its base graph is any matrix shown in Table 3, and each matrix is numbered 1, 2, 3, and 4 respectively.

[0262] Table 3

[0263]

[0264] In Example 8, the first column of matrices 1-4 has a column weight of 5, and the remaining columns have a column weight of 2.

[0265] In Matrix 1, the rows with a row weight of 3 are rows 5, 7, and 8, and the remaining rows have a row weight of 2. The element in row 8 and column 1 of Matrix 1 is "0," making it a zero matrix. In other words, the non-zero elements in row 8 and column 1 are staggered and have no intersection.

[0266] In Matrix 2, the rows with a row weight of 3 are rows 2, 3, and 7, and the remaining rows have a row weight of 2. The element in the second row and first column of Matrix 2 is "0", which means it is a zero matrix. In other words, the non-zero elements in the second row and the non-zero elements in the first column are staggered and have no intersection.

[0267] In Matrix 3, the rows with a row weight of 3 are rows 4, 5, and 7, and the remaining rows have a row weight of 2. The element in the 5th row and 1st column of Matrix 3 is "0", which means it is a zero matrix. In other words, the non-zero elements in the 5th row and the non-zero elements in the 1st column are staggered and have no intersection.

[0268] In Matrix 4, the rows with a row weight of 3 are rows 3, 6, and 7, and the remaining rows have a row weight of 2. The element in the 7th row and 1st column of Matrix 4 is "0", which means it is a zero matrix. In other words, the non-zero elements in the 7th row and the non-zero elements in the 1st column are staggered and have no intersection.

[0269] In the first square matrix given in Example 8, its row degree distribution is more uniform, easier to encode, and more suitable for hardware implementation of the row decoding algorithm, with better performance.

[0270] It should be understood that in Examples 3 to 8 above, "0" represents a zero matrix of Zc×Zc, and "1" represents a non-zero matrix of Zc×Zc, where Zc is a positive integer. In other words, "0" represents a zero element and "1" represents a non-zero element.

[0271] Optionally, in each of the above examples, at least two offset values corresponding to the non-zero elements in the column with the highest column weight may be the same, which can simplify the encoding process.

[0272] For example, when the column weight of the yth column is N (where N is an odd number), there are N-1 offset values in the yth column that are identical to each other, and the column weight of each column except the yth column is an even number. In this way, duplicate items corresponding to the same offset value can be eliminated, thereby simplifying the encoding process.

[0273] It should be understood that due to the basic characteristics of LDPC codes, the equivalent matrices of the matrices listed in the above examples after the rows and / or columns are swapped also fall within the scope of the embodiments of the present application. The equivalent matrices of the matrices listed in the above examples after the values of the non-zero elements of the matrices are added to an integer for the entire row and / or column (such as adding 1 to the entire first row or adding 2 to the entire first row, etc.) also fall within the scope of the embodiments of the present application.

[0274] It should also be understood that the embodiments of the present application do not limit the storage method of the offset value of the non-zero element. For example, the storage rule can be used, and the stored value can be the value before modulo (i.e., remainder), modulo the boost value when used, or the value after modulo the maximum boost value, without limitation.

[0275] In addition, in this application, the values of the same letter in matrices of different orders can be the same or different, without limitation. For example, in Example 1, the first square matrix is a 4×4 matrix, Zc represents the order of the zero matrix or non-zero matrix in the M1 matrix, and "a", "b" and "c" represent the offset values ​​of a, b or c in the M2 matrix respectively. In Example 2, the first square matrix is a 5×5 matrix, Zc represents the order of the zero matrix or non-zero matrix in the M3 matrix, and "a", "b" and "c" represent the offset values ​​of a, b or c in the M4 matrix respectively. However, the values of parameters such as Zc, a, b and c in the 4×4 matrix and the 5×5 matrix are not related, and they can be the same or different.

[0276] Figure 9 This is a schematic diagram of an encoding process provided in an embodiment of the present application.

[0277] Assume that the input information bit sequence of the LDPC encoder is s, the length is K, and the output encoding codeword sequence is d, the length is N, where N = [K / R], R is the code rate. Figure 4 LDPC code check matrix, assuming that the dimension of matrix A is n A ×m A , the dimension of the B matrix is m A ×m A , the dimension of the C matrix is m A ×m D , the dimension of the D matrix is m D ×(n A +m A ), the dimension of the E matrix is m D ×mD ,like Figure 9 As shown, the encoding process includes the following steps:

[0278] Step 901: core matrix encoding.

[0279] Specifically, the transmitting device encodes according to the core matrix [AB] to obtain c1=[s e1], where the length of e1 is m A Zc;

[0280] Step 902: Extended Matrix Coding

[0281] Encode the extended matrix [DE] with c1 as the new information bit sequence, and get c = [c1 e2], where the length of e2 is m D Zc, the final check digit is recorded as e = [e1 e2], then K = n A Zc, the codeword length after extended matrix coding is K+(m A +m D )Zc.

[0282] Step 903: Rate matching

[0283] Punch the check bits according to the code length and code rate required by the system, and discard the last K+(m A +m D )Zc-[K / R]bit, and obtain the LDPC code encoding result of N points.

[0284] In the above encoding process, the LDPC code check matrix starts from the second row, and the lower right corner is a single diagonal form. Therefore, the calculation of the corresponding check bits is independent of each other, and parallel encoding can be performed to reduce the coding delay.

[0285] Figure 10 It is a schematic flowchart of the communication method 1000 based on LDPC code provided in this application.

[0286] Method 1000 may be performed by a receiving device. Unless otherwise specified, "receiving device" may refer to the receiving device itself or to a device that supports the receiving device in implementing its functions. For ease of description, the following description uses the receiving device. The receiving device may be a terminal device or a network device.

[0287] Method 1000 may include at least part of the following.

[0288] Step 1001: A receiving device obtains an LDPC codeword sequence.

[0289] The receiving device obtains an LDPC codeword sequence, which may refer to the receiving device obtaining an LDPC codeword sequence from a memory. The LDPC codeword sequence may be obtained by the receiving device based on an air interface signal from the transmitting device. The receiving device obtains an LDPC codeword sequence, which may refer to the receiving device receiving an air interface signal from the transmitting device and obtaining the LDPC codeword sequence based on the air interface signal.

[0290] Step 1002: The receiving end device decodes the LDPC codeword sequence according to the LDPC base matrix to obtain an information bit sequence.

[0291] It should be noted that since channel noise signals may be introduced during the transmission of air interface signals, the air interface signal output or sent by the transmitting device may be different from the air interface signal received by the receiving device, and the LDPC codeword sequence obtained thereby may also be different from the LDPC codeword sequence output by the transmitting device.

[0292] Similarly, the LDPC base matrix can be a base matrix stored in the receiving device or a base matrix predefined by the protocol, or can be a base matrix further obtained based on the stored base matrix or the base matrix predefined by the protocol, without limitation. The LDPC base matrix in method 1000 can be referred to the relevant description of the transmitting device and will not be described in detail here.

[0293] Optionally, in the present application, the LDPC base matrix includes a core matrix, the core matrix includes a first square matrix and a first matrix, the first matrix is composed of the 1st to wth rows and the 1st to r-1th columns of the LDPC base matrix, and the first matrix is determined based on the first square matrix.

[0294] For example, the LDPC basis matrix can be divided into Figure 4 In the case of the five parts A, B, C, D, and E shown, the first matrix may be part A. The first matrix may be determined based on the first square matrix.

[0295] For example, if the first matrix is the M1 matrix mentioned above, the first matrix can be determined based on the first matrix. For example, the principle of the shortest loop in the basis matrix is the longest can be adopted, and the progressive edge growth (PEG) algorithm can be used to expand the search for the base graph of the core matrix as follows: a As shown:

[0296]

[0297] Here, "0" represents a zero matrix of Zc×Zc, and "1" represents a non-zero matrix of Zc×Zc, where Zc is a positive integer. In other words, "0" represents a zero element and "1" represents a non-zero element.

[0298] It can be seen that the dimension of the core matrix is 4×16. The first square matrix is located in rows 1 to 4 and columns 13 to 16 thereof, and the first matrix is located in rows 1 to 4 and columns 1 to 12 thereof. The first matrix is obtained by searching the first square matrix through the PEG algorithm. The column weight of the core matrix is 3 or 2, among which there are 13 columns with a column weight of 3 and 3 columns with a column weight of 2.

[0299] Furthermore, according to the approximate cycle extrinsic message degree (ACE, where EMD represents the extrinsic message degree) algorithm, the offset values of the corresponding elements of the above core matrix can be searched, as follows M b shown:

[0300]

[0301] Among them, "-1" represents the zero matrix of Zc×Zc, "0" represents the identity matrix of Zc×Zc, and "1163", "1152",... represent the matrices obtained by circularly shifting the identity matrix of Zc×Zc by 1163, 1152,... bits. It can also be said that "-1" represents the zero element, "0" represents the identity matrix, and "1163", "1152",... represent the offset values of 1163, 1152,....

[0302] It can be seen from the core matrix that the maximum value of the offset value is 1519. Since the values supported by the lifting factor include 3, 6, 12, 24, 48, 96, 192, 384, 768, 1536, the maximum value of the lifting factor Z supported by the core matrix is 1536.

[0303] Next, in combination with the simulation results, the performance of the LDPC code of the embodiment of the present application will be described.

[0304] Figure 11 is a comparison chart of the simulation results of the core matrix corresponding to the double diagonal structure and the M b matrix of the present application. Among them, the simulation parameters are shown in Table 4.

[0305] Table 4

[0306] Parameter Value Information bit length 2304、1152、576 Code rate 0.93 Boosting factor 192、96、48 Decoding algorithm Belief propagation (BP) algorithm Number of iterations 50

[0307] Specifically, Figure 11 (1) is the simulation result with the information length of 2304 bits and the lifting factor of 192, Figure 11 (2) is the simulation result with the information length of 1152 bits and the lifting factor of 96, Figure 11(3) is the simulation result of information with a length of 576 bits and a lifting factor of 48. Figure 11 It can be seen from (1), (2) and (3) that at different symbol signal-to-noise ratios (E s N0), M b The block error ratio (BLER) of the matrix is lower than the BLER of the core matrix corresponding to the dual diagonal structure. b The LDPC code constructed by the matrix has a performance gain of about 0.05dB compared to the dual diagonal matrix.

[0308] Combined with the above Figures 7 to 11 , describes in detail the method embodiment provided by this application, and will be combined with Figures 12 to 14 , describing an apparatus embodiment of the present application.

[0309] It is understandable that in order to realize the functions in the above embodiments, Figures 12 to 14 The device includes hardware structures and / or software modules that perform the corresponding functions. It should be readily apparent to those skilled in the art that, in combination with the units and method steps of each example described in the embodiments disclosed in this application, this application can be implemented in the form of hardware or a combination of hardware and computer software.

[0310] Figure 12 and Figure 13 The following is a schematic diagram of the structure of possible communication devices provided by the embodiments of the present application. These devices can be used to implement the functions of the transmitting end device or the receiving end device in the above method embodiments, and thus can also achieve the beneficial effects possessed by the above method embodiments.

[0311] like Figure 12 As shown, the device 10 includes a transceiver unit 11 and a processing unit 12 .

[0312] When apparatus 10 is used to implement the functions of a transmitting device in each of the above method embodiments, transceiver unit 11 is used to execute the transmitting and receiving steps of the transmitting device, such as steps 701 and 703, and processing unit 12 is used to execute the processing step 702 of the transmitting device. When apparatus 10 is used to implement the functions of a receiving device in each of the above method embodiments, transceiver unit 11 is used to execute the transmitting and receiving steps of the receiving device, such as step 1001, and processing unit 12 is used to execute the processing steps of the receiving device, such as step 1002.

[0313] For a more detailed description of the transceiver unit 11 and the processing unit 12 , please refer to the relevant description in the above method embodiment, which will not be described again here.

[0314] like Figure 13As shown, device 20 includes processing circuitry 21. The processing circuitry 21 is coupled to a memory 23 for storing instructions. When the device 20 is used to implement the method described above, the processing circuitry 21 is configured to execute the instructions in the memory 23 to implement the functions of the above-mentioned processing unit 12.

[0315] Optionally, the device 20 further includes a memory 23.

[0316] Optionally, the device 20 further includes a transceiver circuitry 22. The transceiver circuitry may be referred to as a communication interface. The processing circuitry 21 and the transceiver circuitry 22 are coupled to each other. It can be understood that the transceiver circuitry 22 may be a transceiver or an input / output interface. When the device 20 is used to implement the method described above, the processing circuitry 21 is configured to execute instructions to implement the functions of the above-mentioned processing unit 12, and the transceiver circuitry 22 is configured to implement the functions of the above-mentioned transceiver unit 11.

[0317] Optionally, the device 20 may be a transmitting-end device or a receiving-end device, and correspondingly, the transceiver circuitry may be a transceiver.

[0318] Optionally, the device 20 may be a chip applied to a transmitting-end device or a receiving-end device, and correspondingly, the transceiver circuitry may be an input / output interface.

[0319] Exemplarily, when the device 20 is a chip applied to a transmitting-end device or a receiving-end device, the chip implements the functions of the transmitting-end device or the receiving-end device in the above method embodiment. The chip receives information from other modules (such as a radio frequency module or an antenna) in the transmitting-end device or the receiving-end device, and the information is sent by other devices to the transmitting-end device or the receiving-end device; or, the chip sends information to other modules (such as a radio frequency module or an antenna) in the transmitting-end device or the receiving-end device, and the information is sent by the transmitting-end device or the receiving-end device to other devices.

[0320] Figure 14 It is a schematic diagram of a chip system 30 provided by an embodiment of the present application. The chip system 30 (or may also be referred to as a processing system) includes a logic circuit 31 and an input / output interface 32.

[0321] Wherein, the logic circuit 31 may be the processing circuitry in the chip system 30. The logic circuit 31 may be coupled to a storage unit and run the instructions in the storage unit, so that the chip system 30 can implement the methods and functions of the embodiments of the present application. The input / output interface 32 may be the input / output circuitry in the chip system 30, output the information processed by the chip system 30, or input the data or signaling information to be processed into the chip system 30 for processing.

[0322] As a solution, the chip system 30 is used to implement the operations performed by the sending device or the receiving device in the above method embodiments.

[0323] For example, the logic circuit 31 is used to implement the operations related to the processing performed by the sending device or the receiving device in the above method embodiments; the input / output interface 32 is used to implement the operations related to sending and / or receiving performed by the sending device or the receiving device in the above method embodiments.

[0324] The present application also provides a communication device, including a processing circuit, which is coupled to a memory. The memory is used to store computer programs or instructions and / or data. The processing circuit is used to execute the computer programs or instructions stored in the memory, or read the data stored in the memory, so as to execute the methods in the above method embodiments. Optionally, the processing circuit is one or more. Optionally, the communication device includes a memory. Optionally, the memory is one or more. Optionally, the memory is integrated with the processing circuit or is separately provided.

[0325] The present application also provides a chip, including a processing circuit, the processing circuit is coupled to a memory, the memory is used to store computer programs or instructions, and the processing circuit is used to execute the computer programs or instructions stored in the memory to implement the methods performed by the sending device or the receiving device in the above method embodiments. The memory may be located inside the chip or may be independent of the chip and located outside the chip, which is not limited herein.

[0326] The present application also provides a computer-readable storage medium, on which computer instructions for implementing the methods performed by the sending device or the receiving device in the above method embodiments are stored.

[0327] The present application also provides a computer program product, including instructions, which when executed by a computer, implement the methods performed by the sending device or the receiving device in the above method embodiments.

[0328] The present application also provides a communication system, which includes at least one of the sending device or the receiving device in the above embodiments.

[0329] The explanations and beneficial effects of the relevant content in any of the above provided devices can be referred to the corresponding method embodiments provided above, and will not be elaborated here.

[0330] It can be understood that the processing circuit in the embodiments of the present application may be a processor or a circuit in the processor for performing processing operations. The processor may be a central processing unit (CPU), or may also be other general-purpose processors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. The general-purpose processor may be a microprocessor or any conventional processor.

[0331] The method steps in the embodiments of the present application may be implemented in a hardware manner or by a processor executing software instructions. The software instructions may be composed of corresponding software modules, and the software modules may be stored in a random access memory, flash memory, read-only memory, programmable read-only memory, erasable programmable read-only memory, electrically erasable programmable read-only memory, registers, hard disks, removable hard disks, compact disc read-only memories (CD-ROMs), or any other form of storage medium well known in the art. An exemplary storage medium is coupled to the processor so that the processor can read information from the storage medium and write information to the storage medium. Of course, the storage medium may also be a component of the processor. The processor and the storage medium may be located in an ASIC. Additionally, the ASIC may be located in the transmitting end device or the receiving end device. Of course, the processor and the storage medium may also exist as discrete components in the transmitting end device or the receiving end device.

[0332] In the above embodiments, all or part of the embodiments may be implemented using software, hardware, firmware, or any combination thereof. When implemented using software, all or part of the embodiments may be implemented in the form of a computer program product. The computer program product includes one or more computer programs or instructions. When the computer program or instructions are loaded and executed on a computer, the processes or functions described in the embodiments of the present application are performed in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, a network device, a user device, or other programmable device. The computer program or instructions may be stored in a computer-readable storage medium or transferred from one computer-readable storage medium to another. For example, the computer program or instructions may be transferred from one website, computer, server, or data center to another website, computer, server, or data center via wired or wireless means. The computer-readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server or data center that integrates one or more available media. The available medium may be a magnetic medium, such as a floppy disk, hard disk, or magnetic tape; an optical medium, such as a digital video disk; or a semiconductor medium, such as a solid-state drive.

[0333] In the various embodiments of the present application, unless otherwise specified or provided for in any logical conflict, the terms and / or descriptions between the different embodiments are consistent and may be referenced to each other, and the technical features in the different embodiments may be combined to form new embodiments according to their inherent logical relationships.

[0334] Unless otherwise indicated, all technical and scientific terms used in the embodiments of the present application have the same meaning as those generally understood by those skilled in the art of the technical field of the application. The terms used in this application are only for the purpose of describing specific embodiments and are not intended to limit the scope of the application. It should be understood that the above are for illustration, and the examples above are only for helping those skilled in the art to understand the embodiments of the present application, rather than limiting the application embodiments to the specific numerical values or specific scenarios illustrated. Those skilled in the art can obviously carry out various equivalent modifications or changes based on the examples given above, and such modifications and changes also fall within the scope of the embodiments of the present application.

Claims

1. A communication method based on Low-Density Parity-Check (LDPC) codes, characterized in that, The method includes: Obtain an information bit sequence; Perform LDPC encoding on the information bit sequence according to an LDPC base matrix to obtain an LDPC codeword sequence, where the LDPC base matrix includes a first square matrix, the first square matrix is composed of the 1st row to the wth row and the rth column to the (r + w - 1)th column of the LDPC base matrix, the first square matrix includes the xth row and the yth column, the row weight of the xth row is an integer greater than or equal to 3, the column weight of the yth column is an odd number greater than or equal to 3, the matrix at the xth row and the yth column in the first square matrix is a zero matrix, and the column weight of each column in the first square matrix except the yth column is an integer greater than or equal to 2, where w, r, x, and y are positive integers; Output the LDPC codeword sequence.

2. A communication method based on low-density parity-check (LDPC) codes, characterized in that, The method includes: Obtain an LDPC codeword sequence; Perform decoding on the LDPC codeword sequence according to an LDPC base matrix to obtain an information bit sequence, where the LDPC base matrix includes a first square matrix, the first square matrix is composed of the 1st row to the wth row and the rth column to the (r + w - 1)th column of the LDPC base matrix, the first square matrix includes the xth row and the yth column, the row weight of the xth row is an integer greater than or equal to 3, the column weight of the yth column is an odd number greater than or equal to 3, the matrix at the xth row and the yth column in the first square matrix is a zero matrix, and the column weight of each column in the first square matrix except the yth column is an integer greater than or equal to 2, where w, r, x, and y are positive integers.

3. The method according to claim 1 or 2, characterized in that, The row weight of each row in the first square matrix except the xth row is 2, and the column weight of each column in the first square matrix except the yth column is 2.

4. The method according to any one of claims 1 to 3, characterized in that The row weight of the xth row is 3, and the column weight of the yth column is 3.

5. The method according to any one of claims 1 to 4, characterized in that, The first square matrix is a 4×4 matrix, and the base graph of the first square matrix is the M1 matrix, or the base graph of the first square matrix is a matrix obtained by performing at least one of row transformation or column transformation on the M1 matrix, where the M1 matrix is the following matrix: where "0” represents the zero matrix of Zc×Zc, "1” represents the non-zero matrix of Zc×Zc, and Zc is a positive integer.

6. The method according to claim 5, characterized in that, The base graph of the first square matrix is the M1 matrix, and the first square matrix is the M2 matrix, where the M2 matrix is the following matrix: where "-1” represents the zero matrix of Zc×Zc, "0” represents the identity matrix in the non-zero matrix of Zc×Zc, "a”, "b”, and "c” respectively represent the matrices obtained by circularly shifting the identity matrix of Zc×Zc by a, b, or c positions, and the non-zero matrix of Zc×Zc further includes the matrices represented by "a”, "b”, and "c”, and a, b, and c are integers greater than or equal to 0.

7. The method according to any one of claims 1 to 4, characterized in that The first square matrix is a 5×5 matrix, and the base graph of the first square matrix is the M1 matrix, or the base graph of the first square matrix is a matrix obtained by performing at least one of row transformation or column transformation on the M1 matrix, where the M1 matrix is the following matrix: where "0” represents the zero matrix of Zc×Zc, "1” represents the non-zero matrix of Zc×Zc, and Zc is a positive integer.

8. The method according to claim 7, wherein The base graph of the first square matrix is the M1 matrix, and the first square matrix is the M2 matrix, where the M2 matrix is the following matrix: Among them, "-1" represents the zero matrix of Zc×Zc, "0" represents the identity matrix in the non-zero matrix of Zc×Zc, "a", "b", and "c" respectively represent the matrices obtained by circularly shifting the identity matrix of Zc×Zc by a, b, or c positions. The non-zero matrix of Zc×Zc also includes the matrices represented by "a", "b", and "c", and a, b, and c are integers greater than or equal to 0.

9. The method according to claim 6 or 8, characterized in that, The base graph of the first square matrix is a matrix obtained by performing at least one of row transformation or column transformation on the M1 matrix, and the first square matrix is a matrix obtained by performing at least one of the row transformation or column transformation on the M2 matrix.

10. The method according to any one of claims 6, 8 and 9, characterized in that, At least two of a, b, and c are equal.

11. The method according to any one of claims 1 to 10, characterized in that, The LDPC base matrix includes a core matrix, the core matrix includes the first square matrix and the first matrix, the first matrix is composed of the first w rows and the first r-1 columns of the LDPC base matrix, and the first matrix is determined according to the first square matrix.

12. A communication device, characterized in that, The device includes a unit for executing the method according to any one of claims 1, 3 to 11, or includes a unit for executing the method according to any one of claims 2 to 11.

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