Self-adaptive equalization circuit and self-adaptive equalization method

Abstract

The invention provides a self-adaptive equalization circuit and a self-adaptive equalization method, and relates to the technical field of data communication. The adaptive equalization circuit comprises an equalizer, a gain amplifier, a signal acquisition unit and a digital control unit, the signal acquisition unit comprises a low-pass filter, a first power detection module and a first comparator, and the output end of the equalizer is connected with the gain amplifier to form a signal path. The output end of the equalizer, the low-pass filter, the first power detection module and the first input end of the first comparator are sequentially connected, the second input end of the first comparator is used for inputting a reference level, and the digital control unit is respectively connected with the output end of the first comparator and the gain amplifier; the digital control unit is used for adjusting the reference level according to the first comparison result until the first comparison result output by the first comparator conforms to a preset signal mode; and the gain of the gain amplifier is adjusted according to the corresponding reference level in the preset signal mode. The method has the effect of reducing power consumption.

Description

Technical Field

[0001] This application relates to the field of data communication technologies, and in particular, to an adaptive equalization circuit and an adaptive equalization method. Background Art

[0002] In high-speed signal transmission systems, as the signal transmission rate becomes higher and higher, the parasitic distributed parameters of signal transmission media (such as package bonding wires, PCB transmission lines, etc.) will cause serious insertion loss (Insert loss) to high-frequency signals, resulting in severe influence of the signal by ISI (Inter Symbol Interference), poor eye diagram quality, and increased bit error rate. To compensate for the insertion loss caused by the channel, generally, a CTLE (Continuous Time Linear Equalizer) is used at the front end of the receiver to achieve frequency compensation and finally generate a relatively flat frequency response.

[0003] The function of the CTLE is to offset the influence of channel insertion loss, but it is necessary to compensate for the channel insertion loss as much as possible. Usually, when applied, the attenuation of the signal by different channels is different, and it will also be affected by temperature and other influencing factors. The high-pass characteristic of the CTLE itself will also be affected by PVT (Process, Voltage, Temperature). Therefore, it is very necessary to accurately compensate for the channel insertion loss.

[0004] Currently, generally, the CTLE adaptive equalization technology is adopted to achieve accurate compensation of channel insertion loss, that is, on the signal path of the CTLE and the VGA (Voltage Gain Amplifier), a feedback branch is added, and the equalization value of the CTLE is dynamically adjusted through the feedback branch to achieve the adaptive equalization of the CTLE.

[0005] However, in the current CTLE adaptive equalization technology, although the equalization value of the CTLE can be dynamically adjusted, the gain value of the VGA cannot be adjusted. And to meet the gain requirements under different working conditions, generally, the gain value of the VGA is set to the maximum value, resulting in a relatively large power consumption of the entire CTLE circuit.

[0006] In summary, there is a problem of relatively large power consumption in the CTLE circuit in the prior art. Summary of the Invention

[0007] The purpose of this application is to provide an adaptive equalization circuit and an adaptive equalization method to solve the problem of relatively large power consumption in the CTLE circuit in the prior art.

[0008] To achieve the above purpose, the technical solutions adopted in the embodiments of this application are as follows:

[0009] On the one hand, an embodiment of the present application provides an adaptive equalization circuit. The adaptive equalization circuit includes an equalizer, a gain amplifier, a signal acquisition unit, and a digital control unit. The signal acquisition unit includes a low-pass filter, a first power detection module, and a first comparator. The output end of the equalizer is connected to the gain amplifier to form a signal path. The output end of the equalizer, the low-pass filter, the first power detection module, and the first input end of the first comparator are connected in sequence. The second input end of the first comparator is used to connect to a reference level. The digital control unit is respectively connected to the output end of the first comparator and the gain amplifier. Among them,

[0010] The low-pass filter is used to filter out the high-frequency components in the output signal of the equalizer and pass the low-frequency components;

[0011] The first power detection module is used to convert the input low-frequency components into a first DC signal;

[0012] The first comparator is used to compare the first DC signal with the reference level and transmit the first comparison result to the digital control unit;

[0013] The digital control unit is used to adjust the reference level according to the first comparison result until the first comparison result output by the first comparator conforms to a predetermined signal pattern; and adjust the gain of the gain amplifier according to the reference level corresponding to the predetermined signal pattern.

[0014] Optionally, the signal acquisition unit further includes a high-pass filter, a second power detection module, and a second comparator. The cut-off frequency of the high-pass filter is the same as that of the low-pass filter. The output end of the equalizer, the high-pass filter, the second power detection module, and the first input end of the second comparator are connected in sequence. The second input end of the second comparator is connected to the first power detection module. The output end of the second comparator is connected to the digital control unit. The digital control unit is also connected to the equalizer. Among them,

[0015] The high-pass filter is used to filter out the low-frequency components in the output signal of the equalizer and pass the high-frequency components;

[0016] The second power detection module is used to convert the input high-frequency components into a second DC signal;

[0017] The second comparator is used to compare the first DC signal with the second DC signal and transmit the second comparison result to the digital control unit;

[0018] The digital control unit is used to adjust the equalization value of the equalizer according to the second comparison result until the comparison result output by the second comparator conforms to a predetermined signal pattern.

[0019] Optionally, the digital control unit includes an equalization convergence detection module and an equalization control module. The equalization convergence detection module is connected to the equalization control module. The equalization convergence detection module is connected to the output end of the second comparator, and the equalization control module is connected to the equalizer. Among them,

[0020] The equalization convergence detection module is used to judge whether it conforms to a predetermined signal pattern according to the second comparison result;

[0021] If not, the equalization control module adjusts the equalization value of the equalizer.

[0022] Optionally, the first end of the second comparator is the in-phase input end, the second end of the second comparator is the anti-phase input end. The digital control unit is used to reduce the equalization value of the equalizer when the second comparison result is at a high level, and increase the equalization value of the equalizer when the second comparison result is at a low level.

[0023] Optionally, the digital control unit is further used to control the signal acquisition unit to enter the sleep state after adjusting the gain of the gain amplifier, and wake up the signal acquisition unit after a preset time period.

[0024] Optionally, the predetermined signal pattern is a pattern in which low levels and high levels alternate within a sampling period.

[0025] Optionally, in the predetermined signal pattern, the digital control unit is further used to obtain a first reference level corresponding to when the first comparison result is at a low level and a second reference level corresponding to when the first comparison result is at a high level, and determine a target reference level according to the average value of the first reference level and the second reference level, so as to adjust the gain of the gain amplifier through the target reference level.

[0026] Optionally, the first end of the first comparator is the in-phase input end, the second end of the first comparator is the anti-phase input end. The digital control unit is used to increase the reference level when the first comparison result is at a high level, and decrease the reference level when the first comparison result is at a low level.

[0027] On the other hand, an embodiment of the present application further provides an adaptive equalization method, which is applied to the digital control unit of an adaptive equalization circuit. The method includes:

[0028] Obtain the first comparison result output by the first comparator;

[0029] Adjust the reference level according to the first comparison result until the first comparison result conforms to a predetermined signal pattern;

[0030] Adjust the gain of the gain amplifier according to the reference level corresponding to the predetermined signal pattern.

[0031] Optionally, the signal acquisition unit further includes a high-pass filter, a second power detection module, and a second comparator. The cut-off frequency of the high-pass filter is the same as that of the low-pass filter. The output end of the equalizer, the high-pass filter, the second power detection module, and the first input end of the second comparator are connected in sequence. The second input end of the second comparator is connected to the first power detection module. The output end of the second comparator is connected to the digital control unit, and the digital control unit is further connected to the equalizer. Before the step of obtaining the first comparison result output by the first comparator, the method further includes:

[0032] Obtain a second comparison result output by the second comparator;

[0033] Adjust the equalization value of the equalizer according to the second comparison result until the second comparison result conforms to a predetermined signal pattern.

[0034] Compared with the prior art, the present application has the following beneficial effects:

[0035] The present application provides an adaptive equalization circuit and an adaptive equalization method. The adaptive equalization circuit includes an equalizer, a gain amplifier, a signal acquisition unit, and a digital control unit. The signal acquisition unit includes a low-pass filter, a first power detection module, and a first comparator. The output end of the equalizer is connected to the gain amplifier to form a signal path. The output end of the equalizer, the low-pass filter, the first power detection module, and the first input end of the first comparator are connected in sequence. The second input end of the first comparator is used to input a reference level. The digital control unit is respectively connected to the output end of the first comparator and the gain amplifier. Among them, the low-pass filter is used to filter out the high-frequency components in the output signal of the equalizer and pass the low-frequency components; the first power detection module is used to convert the input low-frequency components into a first DC signal; the first comparator is used to compare the first DC signal with the reference level and transmit the first comparison result to the digital control unit; the digital control unit is used to adjust the reference level according to the first comparison result until the first comparison result output by the first comparator conforms to a predetermined signal pattern; and adjust the gain of the gain amplifier according to the reference level corresponding to the predetermined signal pattern.

[0036] On the one hand, since the adaptive equalization circuit provided in this application is provided with a first comparator and a digital control unit, and the digital control unit can dynamically adjust the reference level according to the comparison result of the first comparator, and finally adjust the gain of the gain amplifier according to the adjusted reference level, thereby realizing the dynamic adjustment of the gain, making the gain of the gain amplifier match the equalization value of the equalizer, without the need to operate at the maximum gain in real time, reducing the power consumption of the entire adaptive equalization circuit. On the other hand, the digital control unit is introduced into the adaptive equalization circuit provided in this application. Compared with the pure analog circuit solution in the prior art, the circuit provided in this application can further reduce power consumption.

[0037] To make the above objects, features, and advantages of the present application more obvious and understandable, the following specifically presents preferred embodiments and, in conjunction with the accompanying drawings, provides detailed descriptions as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] To more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments. It should be understood that the following drawings only show certain embodiments of the present application and should not be regarded as limiting the scope. For those of ordinary skill in the art, other related drawings can also be obtained based on these drawings without creative efforts.

[0039] Figure 1 Schematic diagram of a typical CTLE circuit structure in the prior art.

[0040] Figure 2 Schematic diagram of a spectrum equalization circuit structure in the prior art.

[0041] Figure 3 Schematic diagram of the modules of the adaptive equalization circuit provided in the embodiments of the present application.

[0042] Figure 4 Another schematic diagram of the modules of the adaptive equalization circuit provided in the embodiments of the present application.

[0043] Figure 5 Schematic flowchart of the adaptive equalization method provided in the embodiments of the present application.

[0044] In the figure:

[0045] 110 - Equalizer; 120 - Gain amplifier; 130 - Signal acquisition unit; 140 - Digital control unit; 131 - Low-pass filter; 132 - First power detection module; 133 - First comparator; 134 - High-pass filter; 135 - Second power detection module; 136 - Second comparator; 141 - Amplitude detection module; 142 - Equalization convergence detection module; 143 - Equalization control module. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0046] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of this application. Obviously, the described embodiments are some, but not all, of the embodiments of this application. Components of the embodiments of this application generally described and illustrated in the drawings herein may be arranged and designed in a variety of different configurations.

[0047] Therefore, the following detailed description of the embodiments of this application provided in the drawings is not intended to limit the scope of this application that is claimed, but is merely representative of selected embodiments of this application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of this application without creative efforts fall within the scope of protection of this application.

[0048] It should be noted that like reference numerals and letters denote like items in the following drawings. Therefore, once an item is defined in one drawing, it does not require further definition and explanation in subsequent drawings. At the same time, in the description of this application, terms such as "first" and "second" are only used for descriptive distinction and cannot be construed as indicating or implying relative importance.

[0049] It should be noted that, in this document, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or sequence between these entities or operations.

[0050] The following will describe in detail some embodiments of this application with reference to the accompanying drawings. Without conflict, the following embodiments and the features in the embodiments may be combined with each other.

[0051] Please refer to Figure 1 , which is a typical CTLE circuit structure in the prior art. In this CTLE circuit, it includes two symmetric branches. Each branch includes a capacitor, a resistor, a switching transistor, and a current source connected in sequence. The switching transistors on the two branches respectively receive a first input signal VinP and a second input signal VinN. An adjustable capacitor Cs and an adjustable resistor Rs are also connected in parallel between the endpoints where the switching transistor and the current source are connected. The endpoints where the resistors and the switching transistors in the two branches are connected serve as output terminals and output a signal Vout. This CTLE unit realizes high-pass transmission characteristics through the source negative feedback resistor and capacitor, and complements the low-pass characteristics of the channel to achieve frequency compensation, ultimately generating a relatively flat frequency response.

[0052] By adjusting the values of the adjustable capacitor Cs and an adjustable resistor Rs, the equalization degree (i.e., the equalization value) of the CTLE can be adjusted. Currently, there are two common ways to adjust the equalization value of the CTLE. One is to directly set the values of the adjustable capacitor Cs and the adjustable resistor Rs through the system. For example, when inputting signal A, the capacitance value of the adjustable capacitor Cs is set to a1, and the resistance value of the adjustable resistor Rs is set to b1; when inputting signal B, the capacitance value of the adjustable capacitor Cs is set to a2, and the resistance value of the adjustable resistor Rs is set to b2, so as to achieve the equalization of the CTLE with different equalization values under different working conditions.

[0053] Another way to adjust the equalization value of the CTLE is adaptive adjustment, that is, the CTLE can automatically adjust the equalization value according to the high-frequency loss degree of the input signal to achieve an adaptive effect. Spectrum balancing is a common CTLE adaptive equalization method. Figure 2 Fig. shows the traditional spectrum balancing circuit structure, such as Figure 2 shown, on the signal path between the CTLE and the VGA, a feedback branch (the part within the dotted box in the figure) is added, and the equalization value of the CTLE is dynamically adjusted through the feedback branch to achieve the adaptive equalization of the CTLE.

[0054] Among them, the feedback branch includes a high-pass filter, a low-pass filter, a rectifier, a V / I converter, and a charge pump. In the figure, C1 is a filter capacitor, and C2 represents the charge pump. The same cut-off frequency fc is set in both the high-pass filter and the low-pass filter. At this cut-off frequency, an ideal random code signal can be divided into two parts, a high-frequency component and a low-frequency component with the same energy, by the high-pass filter and the low-pass filter. For the signal after passing through the channel, its high-frequency component is attenuated, and the high-frequency component passing through the filter is less than the low-frequency component. Through the rectifier, the V / I converter, and the charge pump, the difference between the high-frequency component and the low-frequency component is converted into a voltage signal and fed back to the CTLE to adjust the equalization degree of the CTLE. This structure is completely completed by analog circuits, and a large amount of power consumption is required to process high-speed signals. At the same time, since only the equalization value of the CTLE can be adaptively equalized in this circuit and the gain value of the VGA cannot be adjusted, in order to ensure that the gain of the VGA can meet the requirements under any working conditions, the gain of the VGA is generally set to the maximum value, resulting in a relatively large overall power consumption.

[0055] In view of this, in order to solve the above problems, the present application provides an adaptive equalization circuit. The following is an exemplary description of the adaptive equalization circuit provided by the present application:

[0056] As an implementation manner, please refer to Figure 3, the adaptive equalization circuit includes an equalizer 110, a gain amplifier 120, a signal acquisition unit 130, and a digital control unit 140. The signal acquisition unit 130 includes a low-pass filter 131, a first power detection module 132, and a first comparator 133. The output end of the equalizer 110 is connected to the gain amplifier 120 to form a signal path. The output end of the equalizer 110, the low-pass filter 131, the first power detection module 132, and the first input end of the first comparator 133 are connected in sequence. The second input end of the first comparator 133 is used to input a reference level. The digital control unit 140 is respectively connected to the output end of the first comparator 133 and the gain amplifier 120. Among them, the low-pass filter 131 is used to filter out the high-frequency components in the output signal of the equalizer 110 and pass the low-frequency components; the first power detection module 132 is used to convert the input low-frequency components into a first DC signal; the first comparator 133 is used to compare the first DC signal with the reference level and transmit the first comparison result to the digital control unit 140; the digital control unit 140 is used to adjust the reference level according to the first comparison result until the first comparison result output by the first comparator 133 conforms to a predetermined signal pattern; and adjust the gain of the gain amplifier 120 according to the reference level corresponding to the predetermined signal pattern.

[0057] Among them, the cut-off frequency fc of the low-pass filter 131 is generally set to 0.28fs, where fs represents the signal rate. The equalizer 110 described in this application is a CTLE, and the gain amplifier 120 described in this application is a VGA. By comparing the low-frequency components output by the low-pass filter 131 with the reference level, the signal amplitude output by the equalizer 110 is judged, and then the gain of the subsequent gain amplifier 120 is dynamically adjusted, ensuring the matching between the equalization value of the equalizer 110 and the gain of the gain amplifier 120, and thus reducing the power consumption of the entire adaptive equalization circuit. Moreover, by adjusting the gain of the subsequent gain amplifier 120, the linearity of the signal can also be ensured to meet the system requirements. At the same time, by using the combination of the first comparator 133 and the digital control unit 140 to replace the traditional pure analog circuit, it can also play a role in further reducing power consumption.

[0058] The specific principle is described below:

[0059] In the digital control unit 140, an amplitude detection module 141 is provided. The amplitude detection module 141 is connected to the output end of the first comparator 133 and the gain amplifier 120. After setting the equalization value of the equalizer 110 through software or directly locking the equalization value of the equalizer 110 through the adaptive equalization technology, it is necessary to detect the output amplitude of the equalizer 110.

[0060] Specifically, the low-frequency component in the output signal of the low-pass filter 131 is utilized, and the first power detection module 132 is used to convert the low-frequency component into a first DC signal. Then, the first comparator 133 compares the first DC signal with a reference level and transmits the first comparison result to the digital control unit 140. The amplitude detection module 141 in the digital control unit 140 determines whether the first comparison result conforms to a predetermined signal pattern. If it conforms, the current reference level is locked, and the gain of the gain amplifier 120 is adjusted according to the current reference level; if it does not conform, the reference level is adjusted until the first comparison result conforms to the predetermined signal pattern.

[0061] Theoretically, after the equalization value of the equalizer 110 is locked, the gain of the gain amplifier 120 that matches the equalization value is also relatively fixed. Therefore, in order to determine the gain that matches the equalization value and thus reduce the circuit power consumption, it is necessary to continuously adjust the reference level until the reference level is adjusted to a value that is basically equal to the first DC signal corresponding to the low-frequency component. It can be seen that when adjusting the reference level in this application, if the value of the reference level is less than the first DC signal, the reference level is increased; if the value of the reference level is greater than the first DC signal, the reference level is decreased until the reference level is maintained near the first DC signal.

[0062] Therefore, the predetermined signal pattern described in this application is a pattern in which low levels and high levels alternate within a sampling period. Generally, the sampling period is 8 or more clock cycles.

[0063] That is, when the value of the reference level is basically equal to the first DC signal, if the reference level is increased at this time, the first comparison result output by the first comparator 133 is 0 (i.e., low level); the amplitude detection module 141 will decrease the reference level. At this time, the first comparison result output by the first comparator 133 is 1 (i.e., low level); when the amplitude detection module 141 detects that the first comparison result is 1, it will also decrease the value of the reference level, causing the first comparison result output by the first comparator 133 to be 0 again, and so on. Therefore, when the reference level is basically equal to the first DC signal, the first comparator 133 outputs "01010101...", that is, the output of the first comparator 133 is an alternation of low levels and high levels. If within the sampling period, the first comparator 133 outputs "11111111..." or "00000000...", that is, when the first comparator 133 outputs a long 1 or a long 0 within the sampling period, it means that the difference between the current reference level and the first DC signal is still large, and at this time, the value of the reference level needs to be adjusted.

[0064] It should be noted that the adjustment of the reference level needs to be based on the connection relationship of the specific circuit. For example, when the first terminal of the first comparator 133 is the non-inverting input terminal and the second terminal of the first comparator 133 is the inverting input terminal, the amplitude detection module 141 will increase the reference level when the first comparison result is high, and decrease the reference level when the first comparison result is low. If the first terminal of the first comparator 133 is the inverting input terminal and the second terminal of the first comparator 133 is the non-inverting input terminal, the amplitude detection module 141 will decrease the reference level when the first comparison result is high, and increase the reference level when the first comparison result is low.

[0065] In one implementation, the signal acquisition unit 130 includes a reference level generation module, which is connected to the second terminal of the first comparator 133 and the digital control unit 140. On this basis, the digital control unit 140 described in the present application increases or decreases the reference level, that is, the digital control unit 140 sends an instruction to the reference level generation module to enable the reference level generation module to generate the required reference level.

[0066] Moreover, in order to ensure the accuracy during the reference level adjustment process, the amplitude detection module 141 generally adjusts the reference level according to the minimum adjustment step. For example, if the current reference level is 2V and the minimum adjustment step is 0.1V, when the reference level is less than the first DC signal, the amplitude detection module 141 will increase the reference level to 2.1V; if the reference level is still less than the first DC signal at this time, the amplitude detection module 141 will increase the reference level to 2.2V, and so on. And, in order to improve the adjustment efficiency, the initial value of the reference level can be set to the value after the last adjustment is completed, or set to the historical experience value under the current working condition. For example, if the initial value of the reference level is set to 2V, the reference level can be quickly adjusted to a value substantially equal to the first DC signal.

[0067] It should also be noted that the gain of the gain amplifier 120 is adjusted by the reference level described in the present application. Actually, the digital control unit 140 stores a correspondence table between the reference level and the gain. A one-to-one correspondence between the reference level and the gain is set in this table. Through the correspondence table between the reference level and the gain, the target gain can be determined according to the value of the current reference level. The amplitude detection module 141 sends the determined target gain to the gain amplifier 120, and thus the gain adjustment of the gain amplifier 120 can be realized.

[0068] Moreover, in order to make the determined target gain more accurate, when a predetermined signal pattern appears, the digital control unit 140 is further configured to obtain a first reference level corresponding to a low level of the first comparison result and a second reference level corresponding to a high level of the first comparison result, and determine a target reference level based on the average value of the first reference level and the second reference level, so as to adjust the gain of the gain amplifier 120 through the target reference level. For example, if the first reference level is 2.2V and the second reference level is 2.1V, the determined target reference level is (2.2V + 2.1V) / 2 = 2.15V. Then, the amplitude detection module 141 determines the target gain from the correspondence table between the reference level and the gain, such as the target gain is 0.5, and sends the target gain to the gain amplifier 120.

[0069] After determining the target gain, the digital control unit 140 locks the target gain and controls the signal acquisition unit 130 to enter the sleep state. Meanwhile, a timer is provided inside the digital control unit 140, which can wake up the signal acquisition unit 130 after a preset duration.

[0070] That is, in this application, after determining the target gain, it is not necessary for the entire adaptive equalization circuit to continuously operate. Instead, the low-pass filter 131, the first power detection module 132, and the first comparator 133 are controlled to power off to reduce power consumption. At this time, the gain amplifier 120 will maintain the target gain and continue to operate. After a period of time (such as 1S or 2S), the digital control unit 140 controls the signal acquisition unit 130 to power on and work again, and re-determines the target gain. Thus, the requirement for real-time gain adjustment can be met under the condition of low power consumption.

[0071] In addition, in this application, the adaptive equalization technology is used to determine the equalization value. On this basis, please refer to Figure 4, the signal acquisition unit 130 further includes a high-pass filter 134, a second power detection module 135, and a second comparator 136. The high-pass filter 134 has the same cut-off frequency as the low-pass filter 131. The output end of the equalizer 110, the high-pass filter 134, the second power detection module 135, and the first input end of the second comparator 136 are connected in sequence. The second input end of the second comparator 136 is connected to the first power detection module 132. The output end of the second comparator 136 is connected to the digital control unit 140. The digital control unit 140 is also connected to the equalizer 110. Among them, the high-pass filter 134 is used to filter out the low-frequency components in the output signal of the equalizer 110 and pass the high-frequency components; the second power detection module 135 is used to convert the input high-frequency components into a second DC signal; the second comparator 136 is used to compare the first DC signal with the second DC signal and transmit the second comparison result to the digital control unit 140; the digital control unit 140 is used to adjust the equalization value of the equalizer 110 according to the second comparison result until the comparison result output by the second comparator 136 conforms to a predetermined signal pattern.

[0072] Among them, the digital control unit 140 includes an equalization convergence detection module 142 and an equalization control module 143. The equalization convergence detection module 142 is connected to the equalization control module 143. The equalization convergence detection module 142 is connected to the output end of the second comparator 136. The equalization control module 143 is connected to the equalizer 110. The equalization convergence detection module 142 is used to judge whether it conforms to a predetermined signal pattern according to the second comparison result; if not, the equalization control module 143 is used to adjust the equalization value of the equalizer 110. If so, the equalization value is locked.

[0073] Similar to the gain adjustment, in the equalization value adjustment, the preset signal pattern is also a pattern in which low levels and high levels alternate within a sampling period, that is, within a sampling period, when the second comparator 136 outputs "01010101...", it can be determined that the equalization value is near the optimal equalization value, and the digital control unit 140 will lock this equalization value.

[0074] At the same time, the adjustment of the equalization value is similar to the adjustment of the reference level. Among them, when the first end of the second comparator 136 is the in-phase input end and the second end of the second comparator 136 is the anti-phase input end, the digital control unit 140 reduces the equalization value of the equalizer 110 when the second comparison result is high and increases the equalization value of the equalizer 110 when the second comparison result is low. When the first end of the second comparator 136 is the reverse input end and the second end of the second comparator 136 is the in-phase input end, the digital control unit 140 increases the equalization value of the equalizer 110 when the second comparison result is high and reduces the equalization value of the equalizer 110 when the second comparison result is low.

[0075] The following will describe the overall technical solution of the present application in conjunction with Figure 4 :

[0076] After the register sends an enable signal to the digital control unit 140, the signal control unit will set the initial equalization value of the equalizer 110 and the initial reference level of the first comparator 133. The initial equalization value and the initial reference level can be the equalization value and the reference level locked by the system last time, or can be fixed values set by the system, which are not limited herein.

[0077] After the signal attenuated by the link enters the equalizer 110, the high-pass filter 134 and the low-pass filter 131 with the cut-off frequency of fc respectively filter the low-frequency component and the high-frequency component of the signal. After filtering, the high-frequency component is output through the high-pass filter 134, and the low-frequency component is output through the low-pass filter 131. At the same time, the first power detection module 132 and the second power detection module 135 respectively convert the low-frequency component and the high-frequency component into the first DC signal and the second DC signal. The second comparator 136 compares the first DC signal and the second DC signal, and sends the second comparison result obtained after comparison to the digital control unit 140.

[0078] After receiving the signal output by the second comparator 136, the digital control unit 140 performs the following processing: when the signal is 1, the equalization value is decreased; when the signal is 0, the equalization value is increased. The decrease or increase of the equalization value described in the present application means that the capacitance value of the variable capacitor Cs and / or the resistance value of the variable resistor Rs in Figure 1 are adjusted accordingly. At the same time, the digital control unit 140 will detect whether the signal appears in the situation of "01010101..." within a certain period. When the equalization value adjusted by the digital control unit 140 reaches near the optimal value, the output of the second comparator 136 will appear in the situation of "01010101...". At this time, the digital control unit 140 will lock the equalization value, that is, temporarily fix the equalization value and no longer adjust the equalization value.

[0079] After locking the equalization value, continue to adjust the gain of the gain amplifier 120. At this time, the digital control unit 140 adjusts the reference level based on the first comparison result of the first comparator 133. Specifically, when the first comparison result is 1, the reference level is increased; when the first comparison result is 0, the reference level is decreased. At the same time, the digital control unit 140 controls to detect whether the first comparison result appears in the situation of "01010101..." within a certain period. When the reference level adjusted by the digital control unit 140 reaches near the optimal value, the output of the first comparator 133 will appear in the situation of "01010101...". At this time, the digital control unit 140 can lock the current reference level, determine the target gain, and then lock the target gain.

[0080] For example, if the initial reference level is set to 2V, during the adjustment process, the adjustment is performed in the minimum adjustment step of 0.1V. When the digital control unit 140 controls the reference level to repeatedly adjust at 2.1V, 2.2V, 2.1V, 2.2V..., and the first comparison result shows the situation of "01010101..." within a certain period, it is determined that the reference level is already near the optimal value at this time. The digital control unit 140 determines the average value of 2.1V and 2.2V, which is 2.15V, and based on 2.15V, determines the current target gain as 0.5 from the correspondence table between the reference level and the gain. Then, the target gain is locked and sent to the gain amplifier 120, so that the gain amplifier 120 operates at a gain of 0.5.

[0081] Since the best equalization value and gain will not change within a short time after locking the equalization value and the gain, the digital control unit 140 can control the entire signal acquisition unit 130 to power off, and the equalizer 110 and the gain amplifier 120 continue to operate according to the locked equalization value and target gain. After a preset time, the digital control unit 140 wakes up the signal acquisition unit 130 again, and the signal acquisition unit 130 continues to output the first comparison signal and the second comparison signal to the digital control unit 140, so that the digital control unit 140 can determine the next round of equalization value and target gain, realizing real-time adjustment of the equalization value and the target gain, and at the same time reducing the power consumption of the entire adaptive equalization circuit.

[0082] Based on the above implementation manner, the embodiment of the present application further provides an adaptive equalization method, which is applied to the digital control unit 140 of the adaptive equalization circuit. Please refer to Figure 5 , and the method includes:

[0083] S102, obtaining the first comparison result output by the first comparator.

[0084] S104, adjusting the reference level according to the first comparison result until the first comparison result conforms to a predetermined signal pattern.

[0085] S106, adjusting the gain of the gain amplifier 120 according to the reference level corresponding to the predetermined signal pattern.

[0086] Among them, the signal acquisition unit 130 further includes a high-pass filter 134, a second power detection module 135, and a second comparator 136. The high-pass filter 134 has the same cut-off frequency as the low-pass filter 131. The output end of the equalizer 110, the high-pass filter 134, the second power detection module 135, and the first input end of the second comparator 136 are connected in sequence. The second input end of the second comparator 136 is connected to the first power detection module 132. The output end of the second comparator 136 is connected to the digital control unit 140, and the digital control unit 140 is also connected to the equalizer 110. Before S102, the method further includes:

[0087] S101-1, obtaining a second comparison result output by the second comparator 136.

[0088] S101-2, adjusting the equalization value of the equalizer 110 according to the second comparison result until the second comparison result conforms to a predetermined signal pattern.

[0089] In summary, the present application provides an adaptive equalization circuit and an adaptive equalization method. The adaptive equalization circuit includes an equalizer, a gain amplifier, a signal acquisition unit, and a digital control unit. The signal acquisition unit includes a low-pass filter, a first power detection module, and a first comparator. The output end of the equalizer is connected to the gain amplifier to form a signal path. The output end of the equalizer, the low-pass filter, the first power detection module, and the first input end of the first comparator are connected in sequence. The second input end of the first comparator is used to input a reference level. The digital control unit is respectively connected to the output end of the first comparator and the gain amplifier. Among them, the low-pass filter is used to filter out the high-frequency components in the output signal of the equalizer and pass the low-frequency components; the first power detection module is used to convert the input low-frequency components into a first DC signal; the first comparator is used to compare the first DC signal with the reference level and transmit the first comparison result to the digital control unit; the digital control unit is used to adjust the reference level according to the first comparison result until the first comparison result output by the first comparator conforms to a predetermined signal pattern; and adjust the gain of the gain amplifier according to the reference level corresponding to the predetermined signal pattern. On the one hand, since the first comparator and the digital control unit are provided in the adaptive equalization circuit provided by the present application, and the digital control unit can dynamically adjust the reference level according to the comparison result of the first comparator, and finally adjust the gain of the gain amplifier according to the adjusted reference level, thereby realizing the dynamic adjustment of the gain, making the gain of the gain amplifier match the equalization value of the equalizer, without the need to operate at the maximum gain in real time, reducing the power consumption of the entire adaptive equalization circuit. On the other hand, the digital control unit is introduced in the adaptive equalization circuit provided by the present application. Compared with the prior art of a pure analog circuit solution, the circuit provided by the present application can further reduce power consumption.

[0090] A comparator is added to the IO port of the serial communication system provided by this application. Through the combination of digital and analog methods, it is determined whether the slave stretches the SCL low level. Moreover, the comparator accurately compares the reference threshold with the voltage value of the external signal terminal, and the digital-side host can accurately pause sending data signals to the slave according to the set signal of the comparator, with higher accuracy and faster response. At the same time, since the comparator is directly adopted, the use of counters can be reduced, and it has the advantages of small area and low power consumption.

[0091] The foregoing are only the preferred embodiments of this application and are not intended to limit this application. For those skilled in the art, this application can have various changes and modifications. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of this application shall be included within the protection scope of this application.

[0092] For those skilled in the art, it is obvious that this application is not limited to the details of the above-described exemplary embodiments, and without departing from the spirit or basic characteristics of this application, this application can be implemented in other specific forms. Therefore, from any point of view, the embodiments should be regarded as exemplary and non-limiting. The scope of this application is defined by the appended claims rather than the above description. Therefore, it is intended to embrace all changes falling within the meaning and scope of the equivalent elements of the claims in this application. Any reference signs in the claims should not be regarded as limiting the claimed rights.

Claims

1. An adaptive equalization circuit, characterized in that, The adaptive equalization circuit includes an equalizer, a gain amplifier, a signal acquisition unit, and a digital control unit. The signal acquisition unit includes a low-pass filter, a first power detection module, and a first comparator. The output end of the equalizer is connected to the gain amplifier to form a signal path. The output end of the equalizer, the low-pass filter, the first power detection module, and the first input end of the first comparator are connected in sequence. The second input end of the first comparator is used to input a reference level. The digital control unit is respectively connected to the output end of the first comparator and the gain amplifier; wherein, The low-pass filter is used to filter out the high-frequency components in the output signal of the equalizer and pass the low-frequency components; The first power detection module is used to convert the input low-frequency components into a first DC signal; The first comparator is used to compare the first DC signal with the reference level and transmit the first comparison result to the digital control unit; The digital control unit is used to adjust the reference level according to the first comparison result until the first comparison result output by the first comparator conforms to a predetermined signal pattern; and adjust the gain of the gain amplifier according to the reference level corresponding to the predetermined signal pattern.

2. The adaptive equalization circuit according to claim 1, wherein The signal acquisition unit further includes a high-pass filter, a second power detection module, and a second comparator. The cut-off frequency of the high-pass filter is the same as that of the low-pass filter. The output end of the equalizer, the high-pass filter, the second power detection module, and the first input end of the second comparator are connected in sequence. The second input end of the second comparator is connected to the first power detection module. The output end of the second comparator is connected to the digital control unit. The digital control unit is also connected to the equalizer; wherein, The high-pass filter is used to filter out the low-frequency components in the output signal of the equalizer and pass the high-frequency components; The second power detection module is used to convert the input high-frequency components into a second DC signal; The second comparator is used to compare the first DC signal with the second DC signal and transmit the second comparison result to the digital control unit; The digital control unit is used to adjust the equalization value of the equalizer according to the second comparison result until the comparison result output by the second comparator conforms to a predetermined signal pattern.

3. The adaptive equalization circuit according to claim 2, wherein The digital control unit includes an equalization convergence detection module and an equalization control module. The equalization convergence detection module is connected to the equalization control module. The equalization convergence detection module is connected to the output end of the second comparator. The equalization control module is connected to the equalizer; wherein, The equalization convergence detection module is used to judge whether it conforms to a predetermined signal pattern according to the second comparison result; If not, the equalization control module is used to adjust the equalization value of the equalizer.

4. The adaptive equalization circuit according to claim 2, characterized in that The first terminal of the second comparator is the non-inverting input terminal, and the second terminal of the second comparator is the inverting input terminal. The digital control unit is configured to reduce the equalization value of the equalizer when the second comparison result is high, and increase the equalization value of the equalizer when the second comparison result is low.

5. The adaptive equalization circuit according to claim 1, characterized in that, The digital control unit is further configured to control the signal acquisition unit to enter the sleep state after adjusting the gain of the gain amplifier, and wake up the signal acquisition unit after a preset duration.

6. The adaptive equalization circuit according to claim 1, wherein The predetermined signal pattern is a pattern in which low levels and high levels alternate within a sampling period.

7. The adaptive equalization circuit according to claim 6, wherein In the predetermined signal pattern, the digital control unit is further configured to obtain a first reference level corresponding to when the first comparison result is low and a second reference level corresponding to when the first comparison result is high, and determine a target reference level based on the average value of the first reference level and the second reference level, so as to adjust the gain of the gain amplifier through the target reference level.

8. The adaptive equalization circuit according to claim 1, characterized in that, The first terminal of the first comparator is the non-inverting input terminal, and the second terminal of the first comparator is the inverting input terminal. The digital control unit is configured to increase the reference level when the first comparison result is high, and decrease the reference level when the first comparison result is low.

9. An adaptive equalization method, characterized in that, Applied to the digital control unit of the adaptive equalization circuit according to any one of claims 1 to 8, the method includes: Obtaining a first comparison result output by the first comparator; Adjusting the reference level according to the first comparison result until the first comparison result conforms to the predetermined signal pattern; Adjusting the gain of the gain amplifier according to the reference level corresponding to the predetermined signal pattern.

10. The adaptive equalization method according to claim 9, characterized in that, The signal acquisition unit further includes a high-pass filter, a second power detection module, and a second comparator. The cut-off frequency of the high-pass filter is the same as that of the low-pass filter. The output terminal of the equalizer, the high-pass filter, the second power detection module, and the first input terminal of the second comparator are connected in sequence. The second input terminal of the second comparator is connected to the first power detection module. The output terminal of the second comparator is connected to the digital control unit, and the digital control unit is further connected to the equalizer; Before the step of obtaining the first comparison result output by the first comparator, the method further includes: Obtaining a second comparison result output by the second comparator; Adjusting the equalization value of the equalizer according to the second comparison result until the second comparison result conforms to the predetermined signal pattern.

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