Virtual link data transmission method, electronic device and storage medium

Abstract

The present invention provides a virtual link data transmission method, electronic device and storage medium. The method includes: determining an array index of a virtual link according to a bandwidth allocation interval of the virtual link; determining a timing trigger interval and an initial count value corresponding to each virtual link according to the bandwidth allocation interval of each virtual link; determining a link map corresponding to each array index according to the array index of each virtual link; polling the link map corresponding to each array index according to the timing trigger interval and the initial count value corresponding to each virtual link to obtain data to be sent for a virtual link corresponding to a link map that meets a data sending rule; and sending the obtained data to be sent for any virtual link to a network card corresponding to the virtual link, so as to increase the number of virtual links from a software level, so that when the AFDX system network is running, the maximum supported number of virtual links far exceeds the number of virtual links communicated by mainstream hardware.

Description

Technical Field

[0001] The present invention relates to the field of data communications, and in particular to a virtual link data transmission method, electronic equipment, and storage medium. Background Art

[0002] A full-flight simulator is an advanced flight training device that helps pilots improve their flying skills by simulating actual flight environments. The full-flight simulator's ARINC 664 interface card serves as the bridge between the simulator and the computer. It primarily processes AFDX (Avionics Full-Duplex Switched Ethernet) bus signals from the simulator, enabling operations such as simulator data transmission, reception, recording, and analysis. The AFDX system network consists of end systems (ES), AFDX switches, and virtual links (VLs). Its core is a communication mechanism based on virtual links. A virtual link is a conceptualized communication object that defines a logical, unidirectional connection from a source end system to one or more destination end systems. During communication on the full-flight simulator's ARINC 664 interface card, the number of virtual links is a key parameter of the AFDX network architecture. More virtual links means the full-flight simulator has stronger support and simulation capabilities. Increasing the number of virtual links can enable full-motion simulators to support the interconnection of more terminal devices, accommodate more complex avionics system architectures, improve communication flexibility and scalability, optimize bandwidth utilization, and enhance system reliability. This is an inevitable requirement for adapting to modern and future avionics development. However, the number of virtual links on existing full-motion simulator ARINC664 interface boards cannot meet this requirement. Summary of the Invention

[0003] In view of the above technical problems, the technical solution adopted by the present invention is:

[0004] According to one aspect of the present application, a virtual link data transmission method is provided, comprising the following steps:

[0005] Step S100: determining an array index corresponding to each virtual link according to the bandwidth allocation interval of each virtual link;

[0006] Step S200: Determine a timing trigger interval and an initial count value corresponding to each virtual link according to the bandwidth allocation interval of each virtual link; the initial count value is the initial value of the counter corresponding to the virtual link;

[0007] Step S300: Determine a link map corresponding to each array index based on the array index corresponding to each virtual link; each node in the link map corresponds to a virtual link;

[0008] Step S400: polling the link map corresponding to each array index according to the timing trigger interval and the initial count value corresponding to each virtual link to obtain data to be sent for a plurality of virtual links corresponding to the link map that meet the data sending rule;

[0009] Step S500: Send the acquired data to be sent of any virtual link to the network card corresponding to the virtual link.

[0010] In an exemplary embodiment of the present application, step S100 includes:

[0011] Step S110: Obtain the bandwidth allocation interval of each virtual link to obtain a bandwidth allocation interval list A=(A1, A2, ..., A i ,...,A j ); where i=1,2,...,j; j is the number of virtual links; A i Allocate the bandwidth interval for the i-th virtual link;

[0012] Step S120: traverse the bandwidth allocation interval list A. If 0 < A i ≤1, then A i Determine it to be 1, and determine 1 as the array index corresponding to the i-th virtual link;

[0013] If 2 n-1 <A i ≤2 n , then A i Determined to be 2 n , and 2 n Determine the array index corresponding to the i-th virtual link;

[0014] Here, n is an integer greater than or equal to 1.

[0015] In an exemplary embodiment of the present application, step S200 includes:

[0016] Step S210: Determine MIN(A) as the timing trigger interval B; wherein MIN() is a preset minimum value determination function;

[0017] Step S220: Determine the initial count value C corresponding to the i-th virtual link. i =(A i / B)-1.

[0018] In an exemplary embodiment of the present application, step S300 includes:

[0019] Step S310: traverse array indexes corresponding to a plurality of virtual links, and determine virtual links with the same array index as the same array index group to obtain a plurality of array index groups;

[0020] Step S320: Get the link identifiers corresponding to the virtual links in each array index group to obtain a link identifier list set D=(D1, D2, ..., D p ,...,D q ); where p = 1, 2, ..., q; q is the number of array index groups; D p is the link identifier list corresponding to the pth array index group;

[0021] D p =(D p1 ,D p2 ,...,D pe ,...,D pf(p) ); where e=1,2,...,f(p); f(p) is the number of virtual links in the pth array index group; D pe is the link identifier corresponding to the e-th virtual link in the p-th array index group;

[0022] Step S330: Obtain the priority corresponding to each virtual link in the pth array index group to obtain the priority list E corresponding to the pth array index group. p =(E p1 ,E p2 ,...,E pe ,...,E pf(p) ); where E pe is the priority corresponding to the e-th virtual link in the p-th array index group;

[0023] Step S340: sort the priority list E corresponding to the pth array index group in descending order of priority. p Sort to get the sorted priority list F corresponding to the pth array index group p =(F p1 ,F p2 ,...,F pe ,...,F pf(p) ); where F pe The e-th priority level determined after prioritizing the p-th array index group;

[0024] Step S350: F p1 ,F p2 ,...,F pe ,...,F pf(p) The corresponding f(p) link identifiers are placed in the same balanced binary search tree in descending order according to the node height to obtain the initial link node tree corresponding to the p-th array index group;

[0025] Step S360: Perform height balancing processing on the initial link node tree corresponding to the p-th array index group to obtain a link graph corresponding to the p-th array index group.

[0026] In an exemplary embodiment of the present application, step S400 includes:

[0027] Step S410: every time trigger interval B, obtain the initial count value of the virtual link in each array index group to obtain the initial count value list G = (G1, G2, ..., G p ,...,G q ); where G p is the initial value of the count of virtual links in the pth array index group;

[0028] Step S420: If G p =0, then perform in-order traversal on several nodes in the link graph corresponding to the p-th array index group, and obtain the data to be sent of several virtual links corresponding to the link graph of the p-th array index group in sequence.

[0029] In an exemplary embodiment of the present application, step S420 further includes:

[0030] Step S421: If G p > 0, then let G p =G p -1, and returns to step S410.

[0031] In an exemplary embodiment of the present application, step S420 further includes:

[0032] Step S422: If each initial count value in the initial count value list G is zero, return to step S220.

[0033] In an exemplary embodiment of the present application, step S500 includes:

[0034] Step S510: When data to be sent on any virtual link is obtained, a network card identifier corresponding to the virtual link is obtained;

[0035] Step S520: Send the data to be sent of the virtual link to the network card with the network card identifier corresponding to the virtual link.

[0036] According to one aspect of the present application, a non-transitory computer-readable storage medium is provided, in which at least one instruction or at least one program is stored. The at least one instruction or the at least one program is loaded and executed by a processor to implement the aforementioned virtual link data transmission method.

[0037] According to one aspect of the present application, an electronic device is provided, including a processor and the aforementioned non-transitory computer-readable storage medium.

[0038] The present invention has at least the following beneficial effects:

[0039] The virtual link data transmission method of the present invention first determines an array index corresponding to each virtual link based on the bandwidth allocation interval of each virtual link, then determines a timing trigger interval and an initial count value corresponding to each virtual link based on the bandwidth allocation interval of each virtual link, and determines a link map corresponding to each array index based on the array index corresponding to each virtual link. Based on the timing trigger interval and the initial count value corresponding to each virtual link, the link map corresponding to each array index is polled to obtain to-be-sent data for several virtual links corresponding to the link map that meets data transmission rules. The obtained to-be-sent data for any virtual link is sent to the network card corresponding to the virtual link, thereby increasing the number of virtual links at the software level. When the AFDX system network is running, the maximum number of virtual links supported far exceeds the number of virtual links communicated by mainstream hardware, and virtual links can be sorted and searched according to priority with a time complexity of logn. When the processor frequency is sufficient, the performance is comparable to that of traditional hardware logic gate units. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0041] Figure 1 This is a flowchart of a virtual link data transmission method provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0042] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making any creative efforts shall fall within the scope of protection of the present invention.

[0043] Existing ARINC 664-compliant network cards generally do not support a large number of virtual links. Due to the strong binding between virtual links and MAC addresses (Media Access Control Addresses), manufacturers generally use FPGAs (Field-Programmable Gate Arrays) to implement virtual link scheduling, using hardware logic to compare virtual link priorities for link scheduling. However, the comparison circuitry requires a large number of logic gates, and each virtual link requires its own parameters, such as bandwidth allocation gap (BAG) and jitter (a measure of signal timing error), which consumes a large amount of register memory. Due to the limited resources of FPGAs, the number of virtual links supported on actual cards is typically limited to approximately 128 to 256. This low number of virtual links makes it difficult to meet the link mapping requirements of multiple terminal devices during flight simulation in full-flight simulators, resulting in a high probability of critical subsystems being forced to share virtual links. Furthermore, AFDX requires dual redundant channels to ensure link reliability, further reducing the number of available virtual links. Therefore, virtual links implemented using traditional FPGA logic have many limitations and cannot be applied to the virtual link implementation of ARINC 664 interface cards in modern full-flight simulators.

[0044] Therefore, based on the defects in the existing network cards that comply with the ARINC664 standard, a virtual link data transmission method of the present application is proposed, such as Figure 1 As shown, the following steps are included:

[0045] Step S100: determining an array index corresponding to each virtual link according to the bandwidth allocation interval of each virtual link;

[0046] The array index corresponding to the virtual link indicates that the bandwidth allocation interval corresponding to the virtual link is adjusted to a bandwidth allocation interval that complies with the AFDX standard.

[0047] Furthermore, step S100 includes steps S110 to S120:

[0048] Step S110: Obtain the bandwidth allocation interval of each virtual link to obtain a bandwidth allocation interval list A=(A1, A2, ..., A i ,...,A j ); where i=1,2,...,j; j is the number of virtual links; A i Allocate the bandwidth interval for the i-th virtual link;

[0049] Step S120: traverse the bandwidth allocation interval list A. If 0 < A i ≤1, then A iDetermine it to be 1, and determine 1 as the array index corresponding to the i-th virtual link;

[0050] If 2 n-1 <A i ≤2 n , then A i Determined to be 2 n , and 2 n Determine the array index corresponding to the i-th virtual link;

[0051] Here, n is an integer greater than or equal to 1.

[0052] The bandwidth allocation intervals of all virtual links are rounded up to the nearest power of 2. If the bandwidth allocation interval of a virtual link is between two adjacent powers of 2, the bandwidth allocation interval of the virtual link is determined to be the larger of the two powers of 2 (for example, if the bandwidth allocation interval of a virtual link is 1.8 milliseconds, the bandwidth allocation interval of the virtual link is determined to be 2, and its corresponding array index is also 2; if the bandwidth allocation interval of a virtual link is 5.7 milliseconds, the bandwidth allocation interval of the virtual link is determined to be 8, and its corresponding array index is also 8), so that the bandwidth allocation interval of each virtual link complies with the AFDX standard (1 millisecond, 2 milliseconds, 4 milliseconds, 8 milliseconds, ..., 128 milliseconds).

[0053] Step S200: Determine a timing trigger interval and an initial count value corresponding to each virtual link according to the bandwidth allocation interval of each virtual link;

[0054] The initial count value is the initial value of the counter corresponding to the virtual link. The counter is used to subsequently determine whether the virtual link meets the data transmission and reception requirements within the scheduling period.

[0055] Further, step S200 includes steps S210 to S220:

[0056] Step S210: Determine MIN(A) as the timing trigger interval B; wherein MIN() is a preset minimum value determination function;

[0057] Step S220: Determine the initial count value C corresponding to the i-th virtual link. i =(A i / B)-1.

[0058] Step S300: Determine a link graph corresponding to each array index according to the array index corresponding to each virtual link;

[0059] Each node in the link graph corresponds to a virtual link.

[0060] Further, step S300 includes steps S310 to S360:

[0061] Step S310: traverse array indexes corresponding to a plurality of virtual links, and determine virtual links with the same array index as the same array index group to obtain a plurality of array index groups;

[0062] Step S320: Get the link identifiers corresponding to the virtual links in each array index group to obtain a link identifier list set D=(D1, D2, ..., D p ,...,D q ); where p = 1, 2, ..., q; q is the number of array index groups; D p is the link identifier list corresponding to the pth array index group;

[0063] D p =(D p1 ,D p2 ,...,D pe ,...,D pf(p) ); where e=1,2,...,f(p); f(p) is the number of virtual links in the pth array index group; D pe is the link identifier corresponding to the e-th virtual link in the p-th array index group;

[0064] Step S330: Obtain the priority corresponding to each virtual link in the pth array index group to obtain the priority list E corresponding to the pth array index group. p =(E p1 ,E p2 ,...,E pe ,...,E pf(p) ); where E pe is the priority corresponding to the e-th virtual link in the p-th array index group;

[0065] The priority corresponding to each virtual link is a value reserved by the user. The lower the value, the higher the priority, which means that the data transmission and reception of the virtual link is more important.

[0066] Step S340: sort the priority list E corresponding to the pth array index group in descending order of priority. p Sort to get the sorted priority list F corresponding to the pth array index group p =(F p1 ,F p2 ,...,F pe ,...,F pf(p) ); where F pe The e-th priority level determined after prioritizing the p-th array index group;

[0067] Step S350: F p1 ,F p2 ,...,F pe ,...,F pf(p) The corresponding f(p) link identifiers are placed in the same balanced binary search tree in descending order according to the node height to obtain the initial link node tree corresponding to the p-th array index group;

[0068] Step S360: Perform height balancing processing on the initial link node tree corresponding to the p-th array index group to obtain a link graph corresponding to the p-th array index group.

[0069] Height balancing is a node manipulation method for balanced binary search trees (AVL trees). The difference in height (balance factor) between the two subtrees of any node in the tree is at most 1. If the insertion or deletion of any node causes the balance factor to exceed 1, a rotation operation is required to restore balance. When inserting a new element, it is recursively placed in the left or right subtree, starting from the root node, according to priority, until the node is empty. When deleting an element, leaf nodes are simply deleted; nodes with a single child are moved to the deletion position; and nodes with two children are replaced by an in-order predecessor or successor node. Whether inserting or deleting, the height of each ancestor node is updated from the changed position and checked for balance. Height balancing involves node manipulation for LL, RR, LR, and RL balanced binary search trees. The specific node rotation operation in this process is an existing method for balanced binary search trees and will not be detailed here.

[0070] By using a balanced binary search tree at the software level to implement virtual link scheduling based on priority and time slices, the limitations of the number of logic gate circuits stacked by hardware resources are avoided, and the number of virtual links supported by the AFDX network architecture of the ARINC664 interface board is increased. Compared with the limitations on the number of virtual links brought by logic gate circuits and hardware resources in FPGAs, the balanced binary search tree is implemented based on CPU processors and memory. The maximum number of virtual links supported at runtime far exceeds that of mainstream hardware-implemented interface boards, and virtual links can be sorted and searched according to priority with a time complexity of logn. When the CPU frequency is sufficient, its performance is no less than that of traditional FPGA implementations.

[0071] Step S400: polling the link map corresponding to each array index according to the timing trigger interval and the initial count value corresponding to each virtual link to obtain data to be sent for a plurality of virtual links corresponding to the link map that meet the data sending rule;

[0072] By setting different CPU affinities for several virtual links in the link graph corresponding to different array indexes, several virtual links are bound to different CPUs. The bound CPUs provide computing and processing execution operations for the virtual links. (For example, if there are five virtual links and a four-core CPU processor, each virtual link is bound to these four CPU processors by setting a different CPU affinity. CPU affinity is set by the user.)

[0073] Further, step S400 includes steps S410 to S422:

[0074] Step S410: every time trigger interval B, obtain the initial count value of the virtual link in each array index group to obtain the initial count value list G = (G1, G2, ..., G p ,...,G q ); where G p is the initial value of the count of virtual links in the pth array index group;

[0075] Step S420: If G p = 0, then perform in-order traversal on several nodes in the link graph corresponding to the p-th array index group, sequentially obtain the data to be sent for several virtual links corresponding to the link graph of the p-th array index group, and execute step S500;

[0076] Step S421: If G p > 0, then let G p =G p -1, and returns to step S410.

[0077] Step S422: If each initial count value in the initial count value list G is zero, return to step S220.

[0078] At every timed trigger interval B, the initial count value of the virtual link in each array index group at the current moment is obtained. The initial count values ​​of several virtual links in the same array index group are the same. Then, based on the initial count value corresponding to each array index group, it is judged whether the virtual link in each array index group meets the data transmission and reception requirements. That is, when the initial count value corresponding to any array index group is zero, it means that the virtual link in the array index group meets the data transmission and reception requirements. Then, based on the priority of the several virtual links in the array index group, the data to be sent of each virtual link in the array index group is obtained in turn; if the initial count value corresponding to the array index group is not zero, it means If it indicates that the virtual links in the array index group do not meet the requirements for data transmission and reception, then it is in the data waiting to be sent stage, the initial count value corresponding to the array index group is reduced by one, and the process returns to step S410, and continues to wait for the start of the next data scheduling cycle (that is, after the next timing trigger interval B), and performs polling scheduling on each array index group in turn until the initial count values ​​corresponding to all array index groups are zero. After obtaining the data to be sent of the virtual links in all array index groups, the initial count values ​​corresponding to all array index groups are reset (that is, set to the initial count value determined in step S220), and continue to perform new data scheduling on the virtual links in each array index group.

[0079] Step S500: Send the acquired data to be sent of any virtual link to the network card corresponding to the virtual link;

[0080] Furthermore, step S500 includes steps S510 to S520:

[0081] Step S510: When data to be sent on any virtual link is obtained, a network card identifier corresponding to the virtual link is obtained;

[0082] Step S520: Send the data to be sent of the virtual link to the network card with the network card identifier corresponding to the virtual link.

[0083] After obtaining the data to be sent for any virtual link, the data is sent to the network interface card (NIC) corresponding to the virtual link based on the DPDK (Data Plane Development Kit) architecture. The interrupt mode is enabled using the rte_eth_dev_rx_intr_ctl interface of DPDK. The data to be sent is directly stored in the rte_mempool memory pool accessible by DMA (Direct Memory Access). The data to be sent is sent using rte_eth_tx_burst, bypassing the switching between user mode and kernel mode to implement DMA transmission of memory data to the physical NIC.

[0084] The present invention discloses a virtual link data transmission method, applied to an ARINC 664 interface card for a full-motion simulator. The method first determines an array index corresponding to each virtual link based on the bandwidth allocation interval of each virtual link. A timing trigger interval and an initial count value corresponding to each virtual link are then determined based on the bandwidth allocation interval of each virtual link. Furthermore, a link map corresponding to each array index is determined based on the array index corresponding to each virtual link. Based on the timing trigger interval and the initial count value corresponding to each virtual link, the link map corresponding to each array index is polled to obtain data to be transmitted for a number of virtual links corresponding to the link map that meet data transmission rules. The obtained data to be transmitted for any virtual link is then sent to the network card corresponding to the virtual link. This method increases the number of virtual links at the software level, enabling the maximum number of virtual links supported during network operation in the AFDX system to far exceed the number of virtual links communicated by mainstream hardware. This method expands the data communication scheduling capabilities of the virtual links by increasing the number of virtual links. Furthermore, the method can perform sorting and search functions based on priority with a time complexity of logn. Given a sufficient processor frequency, the method achieves performance comparable to that of traditional hardware logic gate units.

[0085] An embodiment of the present invention further provides a computer program product comprising program code. When the program product is run on an electronic device, the program code is used to enable the electronic device to execute the steps of the method according to various exemplary embodiments of the present invention described above in this specification.

[0086] Furthermore, although the steps of the method of the present disclosure are described in a particular order in the accompanying drawings, this does not require or imply that the steps must be performed in this particular order, or that all steps shown must be performed to achieve the desired results. Additionally or alternatively, some steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps.

[0087] Through the description of the above embodiments, it will be readily understood by those skilled in the art that the example embodiments described herein can be implemented via software or via a combination of software and necessary hardware. Therefore, the technical solutions according to the embodiments of the present disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, USB flash drive, or mobile hard drive) or on a network and includes several instructions for enabling a computing device (such as a personal computer, server, mobile terminal, or network device) to execute the methods according to the embodiments of the present disclosure.

[0088] In an exemplary embodiment of the present disclosure, an electronic device capable of implementing the above method is also provided.

[0089] Those skilled in the art will appreciate that various aspects of the present invention may be implemented as systems, methods, or program products. Therefore, various aspects of the present invention may be implemented in the following forms: entirely in hardware, entirely in software (including firmware, microcode, etc.), or in a combination of hardware and software, collectively referred to herein as "circuits," "modules," or "systems."

[0090] The electronic device according to this embodiment of the present invention is merely an example and should not limit the functions and scope of use of the embodiments of the present invention.

[0091] The electronic device is implemented as a general-purpose computing device. Components of the electronic device may include, but are not limited to, the at least one processor, the at least one memory, and a bus connecting different system components (including the memory and the processor).

[0092] The storage stores program codes, which can be executed by the processor, so that the processor performs the steps according to various exemplary embodiments of the present invention described in the above “Exemplary Method” section of this specification.

[0093] The memory may include readable media in the form of volatile memory, such as random access memory (RAM) and / or cache memory, and may further include read only memory (ROM).

[0094] The storage may also include a program / utility having a set (at least one) of program modules, such program modules including but not limited to: an operating system, one or more application programs, other program modules, and program data, each of which or some combination may include an implementation of a network environment.

[0095] The bus may represent one or more of several types of bus structures, including a memory bus or memory controller, a peripheral bus, an accelerated graphics port, a processor, or a local bus using any of a variety of bus architectures.

[0096] An electronic device may also communicate with one or more external devices (e.g., a keyboard, pointing device, Bluetooth device, etc.), one or more devices that enable a user to interact with the electronic device, and / or any device that enables the electronic device to communicate with one or more other computing devices (e.g., a router, modem, etc.). This communication may occur via an input / output (I / O) interface. Furthermore, the electronic device may communicate with one or more networks (e.g., a local area network (LAN), a wide area network (WAN), and / or a public network such as the Internet) via a network adapter.

[0097] In exemplary embodiments of the present disclosure, a computer-readable storage medium is also provided, on which is stored a program product capable of implementing the aforementioned methods of this specification. In some possible implementations, various aspects of the present invention may also be implemented in the form of a program product comprising program code. When the program product is executed on a terminal device, the program code is configured to cause the terminal device to execute the steps according to various exemplary embodiments of the present invention described in the "Exemplary Methods" section of this specification.

[0098] The program product may utilize any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. The readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or component, or any combination thereof. More specific examples (a non-exhaustive list) of readable storage media include: an electrical connection having one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof.

[0099] A computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, which carries readable program code. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A readable signal medium may also be any readable medium other than a readable storage medium that can transmit, propagate, or transfer a program for use by or in conjunction with an instruction execution system, apparatus, or device.

[0100] The program code embodied on the readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

[0101] Program code for performing the operations of the present invention can be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java, C++, and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code can be executed entirely on the user computing device, partially on the user device, as a stand-alone software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server. In the case of a remote computing device, the remote computing device can be connected to the user computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0102] Furthermore, the figures above are merely illustrative of the processes included in the method according to exemplary embodiments of the present invention and are not intended to be limiting. It is readily understood that the processes illustrated in the figures above do not indicate or limit the temporal order of these processes. Furthermore, it is readily understood that these processes may be executed synchronously or asynchronously, for example, in multiple modules.

[0103] It should be noted that although several modules or units of the device for action execution are mentioned in the detailed description above, this division is not mandatory. In fact, according to the embodiments of the present disclosure, the features and functions of two or more modules or units described above can be concretized in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided into multiple modules or units to be concretized.

[0104] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. A virtual link data transmission method, characterized in that: The steps include: Step S100: determining an array index corresponding to each virtual link according to a bandwidth allocation interval of each virtual link; Step S200: Determine a timing trigger interval and an initial count value corresponding to each virtual link according to the bandwidth allocation interval of each virtual link; the initial count value is an initial value of a counter corresponding to the virtual link; Step S300: Determine a link map corresponding to each array index according to the array index corresponding to each virtual link; each node in the link map corresponds to one virtual link; Step S400: Poll the link map corresponding to each array index according to the timing trigger interval and the initial count value corresponding to each virtual link to obtain data to be sent for a plurality of virtual links corresponding to the link map that meets the data sending rule; Step S500: Send the acquired data to be sent of any of the virtual links to the network card corresponding to the virtual link; Wherein, the step S300 includes steps S310 to S360: Step S310: traverse array indexes corresponding to a plurality of virtual links, and determine the virtual links with the same array index as the same array index group, so as to obtain a plurality of array index groups; Step S320: Obtain link identifiers corresponding to a number of virtual links in each array index group to obtain a link identifier list set D=(D1, D2, ..., D p ,...,D q ); wherein p=1,2,...,q; q is the number of array index groups; D p is a list of link identifiers corresponding to the pth array index group; D p =(D p1 ,D p2 ,...,D pe ,...,D pf(p) ); wherein, e=1,2,...,f(p); f(p) is the number of virtual links in the p-th array index group; D pe is the link identifier corresponding to the e-th virtual link in the p-th array index group; Step S330: Obtain the priority corresponding to each virtual link in the pth array index group to obtain the priority list E corresponding to the pth array index group. p =(E p1 ,E p2 ,...,E pe ,...,E pf(p) ); where E pe is the priority corresponding to the e-th virtual link in the p-th array index group; Step S340: sort the priority list E corresponding to the pth array index group in descending order of priority. p Sort to obtain the sorted priority list F corresponding to the pth array index group p =(F p1 ,F p2 ,...,F pe ,...,F pf(p) ); where F pe the e-th priority level determined after priority sorting for the p-th array index group; Step S350: F p1 ,F p2 ,...,F pe ,...,F pf(p) The corresponding f(p) link identifiers are placed in the same balanced binary search tree in descending order according to the node height, so as to obtain the initial link node tree corresponding to the p-th array index group; Step S360: Perform height balancing processing on the initial link node tree corresponding to the p-th array index group to obtain a link graph corresponding to the p-th array index group.

2. The method according to claim 1, characterized in that The step S100 includes: Step S110: Obtain the bandwidth allocation interval of each virtual link to obtain a bandwidth allocation interval list A=(A1, A2, ..., A i ,...,A j ); where i=1,2,...,j; j is the number of the virtual links; A i A bandwidth allocation interval for the i-th virtual link; Step S120: traverse the bandwidth allocation interval list A. If 0 < A i ≤1, then A i Determine it to be 1, and determine 1 as the array index corresponding to the i-th virtual link; If 2 n-1 <A i ≤2 n , then A i Determined to be 2 n , and 2 n Determine the array index corresponding to the i-th virtual link; Here, n is an integer greater than or equal to 1.

3. The method according to claim 2, characterized in that The step S200 includes: Step S210: Determine MIN(A) as the timing trigger interval B; wherein MIN() is a preset minimum value determination function; Step S220: Determine the initial count value C corresponding to the i-th virtual link. i =(A i / B)-1.

4. The method according to claim 1, wherein The step S400 includes: Step S410: every time the timing trigger interval B is set, the initial count value of the virtual link in each array index group is obtained to obtain the initial count value list G = (G1, G2, ..., G p ,...,G q ); where G p is the initial value of the count of virtual links in the pth array index group; Step S420: If G p =0, then perform in-order traversal on several nodes in the link graph corresponding to the p-th array index group, and obtain the data to be sent of several virtual links corresponding to the link graph of the p-th array index group in sequence.

5. The method according to claim 4, characterized in that The step S420 further includes: Step S421: If G p > 0, then let G p =G p -1, and returns to step S410.

6. The method according to claim 5, characterized in that The step S420 further includes: Step S422: If each initial count value in the initial count value list G is zero, return to step S220.

7. The method according to claim 6, characterized in that The step S500 includes: Step S510: When data to be sent of any virtual link is obtained, a network card identifier corresponding to the virtual link is obtained; Step S520: Send the data to be sent of the virtual link to the network card with the network card identifier corresponding to the virtual link.

8. A non-transitory computer-readable storage medium, characterized in that The storage medium stores at least one instruction or at least one program, and the at least one instruction or the at least one program is loaded and executed by the processor to implement the method according to any one of claims 1 to 7.

9. An electronic device, characterized in that: The device comprises a processor and the non-transitory computer-readable storage medium as claimed in claim 8.

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