Semiconductor device, manufacturing method thereof and electronic equipment

Abstract

A semiconductor device, a method of manufacturing the same, and an electronic apparatus, the semiconductor device including: a first read transistor including a first electrode connected to an input signal terminal, a second electrode connected to a capacitor, and a first gate electrode connected to a storage node; a second read transistor including a third electrode connected to the capacitor, a fourth electrode connected to ground, and a second gate electrode connected to the storage node; a write transistor including a fifth electrode connected to the bit line, a sixth electrode connected to the storage node, and a third gate electrode connected to the word line; one end of the capacitor is connected with the second electrode and the third electrode, and the other end of the capacitor is connected with a signal reading end. The semiconductor device provided by the embodiment of the invention is relatively simple in circuit structure.

Description

Technical Field

[0001] The embodiments of the present application relate to, but are not limited to, the field of semiconductor technology, and particularly refer to a semiconductor device, a manufacturing method thereof, and an electronic device. Background Art

[0002] The progress of artificial intelligence requires the support of powerful computing power. In recent years, with the continuous development of artificial neural network technology, the computing power bottleneck has become increasingly obvious. In the von Neumann architecture, the logic control device and the memory are separate units. The logic control device reads data from the memory, processes it accordingly, and then stores it back in the memory. The data is transmitted back and forth between the logic control device and the memory, and the memory and the logic control device are respectively located in different chips. The back-and-forth transmission of data between different chips leads to high power consumption and low performance.

[0003] As a new computing architecture, the core of in-memory computing is to integrate storage and computing. The technologies of generalized in-memory computing are divided into three categories, namely processing near memory (PNM), processing in memory (PIM), and computing in memory (CIM). Processing in memory is the in-memory computing in the narrow sense. Processing in memory can realize in-memory processing of data, reduce the number of data flows, and achieve computing acceleration. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail in this article. This overview is not intended to limit the protection scope of the present application.

[0005] The embodiments of the present application provide a semiconductor device, a manufacturing method thereof, and an electronic device, and the circuit structure of the semiconductor device is relatively simple.

[0006] The embodiments of the present application provide a semiconductor device, including: a first read transistor, a second read transistor, a write transistor, and a capacitor;

[0007] The first read transistor includes a first electrode connected to an input signal terminal, a second electrode connected to the capacitor, and a first gate electrode connected to a storage node;

[0008] The second read transistor includes a third electrode connected to the capacitor, a fourth electrode connected to a ground terminal, and a second gate electrode connected to the storage node;

[0009] The write transistor includes a fifth electrode connected to a bit line, a sixth electrode connected to the storage node, and a third gate electrode connected to a word line;

[0010] One end of the capacitor is connected to the second electrode and the third electrode, and the other end is connected to the readout signal terminal.

[0011] In some embodiments, the first read transistor and the write transistor are N-type transistors, and the second read transistor is a P-type transistor.

[0012] In some embodiments, the first read transistor and the second read transistor are spaced apart on the same main surface of the substrate, and the write transistor is stacked above the first read transistor and the second read transistor.

[0013] In some embodiments, the capacitor is located between the first gate electrode and the second gate electrode, and the capacitor is located between the write transistor and the substrate.

[0014] In some embodiments, the first read transistor and the second read transistor are planar transistors; the first read transistor includes a first semiconductor layer connecting the first electrode and the second electrode, and the second read transistor includes a second semiconductor layer connecting the third electrode and the fourth electrode. Both the first semiconductor layer and the second semiconductor layer extend along a first direction parallel to the substrate;

[0015] The write transistor includes a third semiconductor layer connecting the fifth electrode and the sixth electrode, and the third semiconductor layer extends along the first direction;

[0016] The first read transistor and the second read transistor are arranged at intervals in the first direction.

[0017] In some embodiments, the third semiconductor layer extends from the region corresponding to the first semiconductor layer to the region corresponding to the second semiconductor layer in the first direction.

[0018] In some embodiments, the materials of the first semiconductor layer and the second semiconductor layer contain silicon, and the material of the third semiconductor layer contains a metal oxide semiconductor material.

[0019] In some embodiments, the material of the first semiconductor layer is N-type doped silicon, the material of the second semiconductor layer is P-type doped silicon, and the material of the third semiconductor layer is a metal oxide containing at least one of indium, gallium, zinc, and tin.

[0020] In some embodiments, a method for manufacturing the semiconductor device includes:

[0021] Forming the first read transistor and the second read transistor on the same main surface of the substrate;

[0022] The capacitor is formed on a side of the first read transistor or the second read transistor away from the substrate;

[0023] The write transistor is formed on a side of the capacitor away from the substrate.

[0024] An embodiment of the present application also provides an electronic device, which includes the semiconductor device provided in the embodiment of the present application as above.

[0025] A semiconductor device, a manufacturing method thereof, and an electronic device provided in an embodiment of the present application. The semiconductor device includes: a first read transistor, including a first electrode connected to an input signal terminal, a second electrode connected to a capacitor, and a first gate electrode connected to a storage node; a second read transistor, including a third electrode connected to the capacitor, a fourth electrode connected to a ground terminal, and a second gate electrode connected to the storage node; a write transistor, including a fifth electrode connected to a bit line, a sixth electrode connected to the storage node, and a third gate electrode connected to a word line; one end of the capacitor is connected to the second electrode and the third electrode, and the other end is connected to a readout signal terminal. The circuit structure of the semiconductor device in the embodiment of the present application is relatively simple.

[0026] Other features and advantages of the present application will be described in the following specification, and, in part, will be obvious from the specification, or will be understood by implementing the present application. The objectives and advantages of the present application can be realized and obtained by the structures specifically pointed out in the specification and the drawings. Description of the Drawings

[0027] The drawings are used to provide an understanding of the technical solutions of the present application, and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solutions of the present application, and do not constitute a limitation to the technical solutions of the present application.

[0028] Figure 1 A logic circuit diagram of a semiconductor device provided for an exemplary embodiment of the present application;

[0029] Figure 2A A three-dimensional structure schematic diagram of a semiconductor device provided for an exemplary embodiment of the present application;

[0030] Figure 2B For Figure 2A A three-dimensional structure schematic diagram of the semiconductor device shown from another angle;

[0031] Figure 2C For Figure 2A A longitudinal cross-sectional structure schematic diagram of the semiconductor device shown;

[0032] Figure 3 A logic circuit diagram of another semiconductor device for an exemplary embodiment of the present application;

[0033] Figure 4 The circuit connection diagram when two read transistors are regarded as voltage-controlled resistors;

[0034] Figure 5 For Figure 3 The schematic diagram of the calculation process of the semiconductor device shown for in-memory analog computing;

[0035] Figure 6A The circuit diagram for simulating two-dimensional vector calculation using the semiconductor device of the embodiment of the present application;

[0036] Figure 6B The simulation calculation result of two-dimensional vector calculation using the semiconductor device of the embodiment of the present application;

[0037] Figure 7A The three-dimensional structure schematic diagram after forming a capacitor in the manufacturing method of a semiconductor device provided by an exemplary embodiment of the present application;

[0038] Figure 7B For Figure 7A The longitudinal cross-sectional structure schematic diagram of the device shown;

[0039] Figure 8A The three-dimensional structure schematic diagram after forming a storage node in the manufacturing method of a semiconductor device provided by an exemplary embodiment of the present application;

[0040] Figure 8B For Figure 8A The longitudinal cross-sectional structure schematic diagram of the device shown;

[0041] Figure 9A The three-dimensional structure schematic diagram after forming a second write transistor in the manufacturing method of a semiconductor device provided by an exemplary embodiment of the present application;

[0042] Figure 9B For Figure 9A The longitudinal cross-sectional structure schematic diagram of the device shown. Detailed implementation manners

[0043] To make the objectives, technical solutions and advantages of the present application clearer and more understandable, the embodiments of the present application will be described in detail below with reference to the accompanying drawings. It should be noted that, without conflict, the embodiments and features in the embodiments of the present application can be combined arbitrarily with each other.

[0044] The embodiments of the present application do not necessarily limit the sizes shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect the true proportions. In addition, the drawings schematically show ideal examples, and the embodiments of the present application are not limited to the shapes or values shown in the drawings.

[0045] The ordinal numbers such as "first" and "second" in this application are set to avoid confusion of components and do not represent any order, quantity, or importance.

[0046] In this application, for convenience, terms indicating orientation or positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are used to describe the positional relationship of components with reference to the accompanying drawings. This is only for the convenience of describing this specification and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation to this application. The positional relationship of components changes appropriately according to the direction describing each component. Therefore, it is not limited to the terms described in the disclosure and can be appropriately replaced according to the situation.

[0047] In this application, unless otherwise clearly specified and limited, the terms "mount", "connect", and "couple" shall be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, an indirect connection through an intermediate member, or the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood according to specific situations.

[0048] In this application, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode.

[0049] In this application, it can be that the first electrode is the drain electrode and the second electrode is the source electrode, or it can be that the first electrode is the source electrode and the second electrode is the drain electrode. In the case of using transistors with opposite polarities or when the current direction changes during circuit operation, etc., the functions of the "source electrode" and the "drain electrode" sometimes exchange with each other. Therefore, in this application, if not specifically stated, the "source electrode" and the "drain electrode" can exchange with each other.

[0050] In this application, "electrically connected" or "connected" includes the situation where components are connected together through an element having a certain electrical effect. For example, an electrical signal connection (coupled connection, such as coupled to), or a physical direct connection. There is no particular limitation on the "element having a certain electrical effect" as long as it can transfer electrical signals between the components to be connected. Examples of the "element having a certain electrical effect" include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0051] In the present application, "parallel" means approximately parallel or nearly parallel. For example, the state where the angle formed by two straight lines is more than -10° and less than 10°, thus, it also includes the state where the angle is more than -5° and less than 5°. In addition, "perpendicular" means approximately perpendicular. For example, the state where the angle formed by two straight lines is more than 80° and less than 100°, thus, it also includes the state where the angle is more than 85° and less than 95°.

[0052] In some embodiments of the present application, "film" and "layer" can be interchanged. For example, sometimes the "conductive layer" can be replaced with the "conductive film". Similarly, sometimes the "insulating film" can be replaced with the "insulating layer".

[0053] The statement "A and B are of an integral structure" in the embodiments of the present application may mean that there is no obvious fault or gap or other obvious demarcation interface in the microscopic structure. Generally, a connected film layer patterned on a film layer is integral. For example, A and B are formed of the same material to form a film layer and have a connected structure formed simultaneously through the same patterning process, or B is directly grown on A by epitaxy, and the materials of the two may not be completely the same.

[0054] In the present application, spaced distribution can be understood as separated and independent distribution, which can be achieved by physical disconnection or electrical disconnection. For example, the semiconductor layer between the effective channels corresponding to two transistors is modified to be insulated to achieve electrical spacing between the two channels.

[0055] Transistors using metal oxides such as indium gallium zinc oxide (InGaZnO, IGZO) as the channel material can be used to implement some transistors in in-memory computing circuits due to their low leakage performance. However, it is difficult to miniaturize metal oxide semiconductors such as IGZO, and as the size of IGZO shrinks, its performance becomes difficult to control.

[0056] In neural network computing, matrix-vector multiplication (MVM) or multiply-accumulate operation (MAC) approximately accounts for 70% to 90% of the computing workload. The embodiments of the present application provide a logic circuit and a semiconductor device that can be used at least for MAC simulation computing, which can accelerate neural network training and computing. Each semiconductor device is an in-memory computing unit.

[0057] Figure 1 This is a logic circuit diagram of a semiconductor device provided for an exemplary embodiment of the present application. As Figure 1As shown, the semiconductor device has a 3T1C structure, including: a first read transistor T2, a second read transistor T3, a write transistor T1, and a capacitor C;

[0058] The first read transistor T2 includes a first electrode P1 connected to the input signal terminal 1L, a second electrode P2 connected to the capacitor C, and a first gate electrode G1 connected to the storage node;

[0059] The second read transistor T3 includes a third electrode P3 connected to the capacitor C, a fourth electrode P4 connected to the ground terminal, and a second gate electrode G2 connected to the storage node;

[0060] The write transistor T1 includes a fifth electrode P5 connected to the bit line BL, a sixth electrode P6 connected to the storage node, and a third gate electrode G3 connected to the word line;

[0061] One end of the capacitor C is connected to the second electrode P2 and the third electrode P3, and the other end is connected to the readout signal terminal. Exemplarily, the capacitor C includes a seventh electrode P7 connected to the second electrode P2 and the third electrode P3, and an eighth electrode P8 connected to the output line. The seventh electrode P7 is insulated from the eighth electrode P8.

[0062] The structure of the logic circuit of the semiconductor device according to the embodiments of the present application is simple, facilitating the realization of a semiconductor device with a simple physical structure, and thus the semiconductor device can be manufactured through a simple process.

[0063] Exemplarily, the first read transistor and the write transistor are N-type transistors, and the second read transistor is a P-type transistor. The first read transistor and the second read transistor form a CMOS device, with a relatively small standby current and low power consumption in the standby state.

[0064] Figure 2A It is a schematic three-dimensional structure diagram of a semiconductor device provided by an exemplary embodiment of the present application; Figure 2B is Figure 2A a schematic three-dimensional structure diagram of the semiconductor device shown from another angle; Figure 2C is Figure 2A a schematic longitudinal sectional structure diagram of the semiconductor device shown. As Figures 2A to 2C shown, the semiconductor device is located on the substrate 10. The first read transistor T2 and the second read transistor T3 are arranged at intervals on the same main surface of the substrate 10. The same main surface can be a plane parallel to the substrate 10. The first read transistor T2 or the second read transistor T3 and the write transistor T1 are stacked in a direction perpendicular to the substrate 10, and the write transistor T1 is stacked above the first read transistor T2 and the second read transistor T3.

[0065] In the semiconductor device according to the embodiment of the present application, the write transistor is stacked above the first read transistor and the second read transistor to form a stacked structure, which can reduce the occupied area of the semiconductor device, so that more in-memory computing units can be integrated on a limited chip.

[0066] Exemplarily, as Figures 2A to 2C shown, the first read transistor T2 and the second read transistor T3 are located on the surface of one side of the substrate, and the write transistor T1 is located on the side of the first read transistor T2 and the second read transistor T3 away from the substrate. The write transistor is located above the first read transistor T2 and the second read transistor T3, and the area of the transistor is relatively larger than that of the read transistor.

[0067] Exemplarily, as Figures 2A to 2C shown, the first read transistor T2 and the second read transistor T3 are planar transistors, the capacitor C is located between the first gate electrode G1 and the second gate electrode G2, and the capacitor C is located between the write transistor T1 and the substrate. The seventh electrode P7 and the eighth electrode P8 are stacked on the substrate 10, and the eighth electrode P8 is located on the side away from the substrate 10 of the seventh electrode P7 and is insulated from the write transistor T1.

[0068] Exemplarily, the first read transistor includes a first semiconductor layer connecting the first electrode and the second electrode, the second read transistor includes a second semiconductor layer connecting the third electrode and the fourth electrode, and both the first semiconductor layer and the second semiconductor layer extend along a first direction parallel to the substrate;

[0069] The write transistor includes a third semiconductor layer connecting the fifth electrode and the sixth electrode, and the third semiconductor layer extends along the first direction;

[0070] The first read transistor and the second read transistor are arranged at intervals in the first direction.

[0071] Exemplarily, as Figure 2C shown, the first semiconductor layer includes a first channel region 21 located between the first electrode P1 and the second electrode P2, and the first channel region 21 can extend along a first direction parallel to the substrate 10 or along a direction perpendicular to the substrate 10;

[0072] The second semiconductor layer includes a second channel region 22 located between the third electrode P3 and the fourth electrode P4, and the second channel region 22 can extend along the first direction;

[0073] The third semiconductor layer includes a third channel region 23 located between the fifth electrode P5 and the sixth electrode P6, and the third channel region 23 can extend along the first direction.

[0074] The third semiconductor layer extends in the first direction from the region corresponding to the first semiconductor layer to the region corresponding to the second semiconductor layer.

[0075] The materials of the first semiconductor layer and the second semiconductor layer include silicon, and the material of the third semiconductor layer includes a metal oxide semiconductor material.

[0076] The material of the first semiconductor layer is N-type doped silicon, the material of the second semiconductor layer is P-type doped silicon, and the material of the third semiconductor layer is a metal oxide containing at least one of indium, gallium, zinc, and tin.

[0077] The first direction may be the X direction as shown in Figure 2C . In Figure 2C , the first channel region 21, the second channel region 22, and the third channel region 23 all extend in the first direction.

[0078] As shown in Figure 2C , the first gate electrode G1 and the sixth electrode P6 are connected by a conductive layer 12.

[0079] As shown in Figures 2A to 2C , the first gate electrode G1 and the first channel region 21, the second gate electrode G2 and the second channel region 22, the third gate electrode G3 and the third channel region 23, the first channel region 21 and the second channel region 22, and the seventh electrode P7 and the eighth electrode P8 are insulated from each other by an insulating layer 11. The insulating layer 11 between the first gate electrode G1 and the first channel region 21, the second gate electrode G2 and the second channel region 22, and the third gate electrode G3 and the third channel region 23 is a gate insulating layer.

[0080] Exemplarily, the first read transistor T2 may be an N-type transistor, and the second read transistor T3 may be a P-type transistor. For example, the first read transistor T2 is an NMOS transistor, and the second read transistor T3 is a PMOS transistor. The write transistor T1 is an N-type metal oxide semiconductor field effect transistor.

[0081] In the embodiments of the present application, silicon-based CMOS transistors are used as read transistors, the miniaturization process is more mature, and the stability is good. The mobility of silicon is high, so the read performance of the transistors is better; thin film transistors made of metal oxide semiconductor materials are used as write transistors, and the leakage current is small. Moreover, the length of the channel region formed by the metal oxide semiconductor material is relatively long, which can not only further reduce the leakage current and lower the refresh frequency, but also reduce or even avoid the challenges encountered by the metal oxide semiconductor material during miniaturization, and reduce the processing difficulty.

[0082] Exemplarily, in addition to being planar transistors independently as described above, the first read transistor T2 and the second read transistor T3 may also be super fin field effect transistors, fin field effect transistors, or fully surrounding gate field effect transistors.

[0083] Exemplarily, the first read transistor T2, the second read transistor T3, and the write transistor T1 are all planar transistors.

[0084] Exemplarily, the capacitor C is a coupling capacitor C configured to read the voltages of the first gate electrode G1 and the second gate electrode G2 through a coupling effect during the data read phase. The voltage of the coupling capacitor is the average voltage of the capacitors of multiple in-memory computing units connected to the same read signal line RL.

[0085] The substrate in the embodiments of the present application may be a support structure. For example, it may be a silicon substrate, or a support structure on which other film layers, functions, or circuits are already distributed on the silicon substrate. The devices related to the inventive configuration of the embodiments of the present application are provided on the main surface of the support structure.

[0086] Exemplarily, the main material of the channel regions of the first read transistor and the second read transistor may be silicon. For example, it may be silicon or polysilicon and other materials with a bandgap less than 1.65 eV.

[0087] Exemplarily, the metal oxide semiconductor material may be a wide bandgap material, such as a metal oxide material with a bandgap greater than 1.65 eV.

[0088] For example, the metal oxide semiconductor material may include metal oxides of at least one of the following metals: indium, gallium, zinc, tin, tungsten, magnesium, zirconium, aluminum, hafnium, and other materials. Of course, the metal oxide may not exclude compounds containing other elements, such as elements N, Si, etc.; nor does it exclude containing other trace doping elements.

[0089] In some embodiments, the metal oxide semiconductor material may include any one or more of the following: indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), indium tungsten oxide (InWO, IWO), titanium oxide (TiO), zinc oxide nitride (ZnON), magnesium zinc oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), zirconium zinc tin oxide (ZrZnSnO), etc. As long as the leakage current of the transistor can meet the requirements, it can be specifically adjusted according to the actual situation.

[0090] These materials have a relatively wide bandgap and low leakage current. For example, when the metal oxide material is IGZO, the leakage current of the transistor is less than or equal to 10 -15 A to 10 -18 A, thereby improving the operating performance of the dynamic memory.

[0091] The above-mentioned metal oxide semiconductor materials only emphasize the element type of the materials, not the atomic ratio in the materials and the film quality of the materials.

[0092] Exemplarily, the materials of the bit lines may each independently be selected from any one or more of other metal materials with similar properties such as tungsten, molybdenum, cobalt, etc. The bit lines may be of a single-layer or multi-layer structure. For example, it may be a multi-layer structure formed of titanium (Ti), titanium nitride (TiN), and tungsten (W).

[0093] Exemplarily, the materials of the first gate electrode, the second gate electrode, the third gate electrode, and the word line may each independently be selected from any one or more of the following materials:

[0094] For example, metals including tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, cobalt, etc.; it may be a metal alloy containing the aforementioned metals;

[0095] It can also be metal oxides, metal nitrides, metal silicides, metal carbides, etc., such as highly conductive metal oxide materials like indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide (InO); for example, metal nitride materials such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN).

[0096] Exemplarily, the semiconductor device of the embodiment of the present application can be a semiconductor device for in-memory computing scenarios.

[0097] Figure 3 It is the logic circuit diagram of another semiconductor device of the exemplary embodiment of the present application.

[0098] Regarding Figure 3 the first read transistor T2 and the second read transistor T3 in Figure 4 as voltage-controlled resistors, as shown in Figure 4 which is the circuit connection diagram of the first read transistor and the second read transistor when regarded as voltage-controlled resistors, V in is the voltage input at the input signal terminal, V out is the voltage output at the output line, R T2 and R T3 are the resistances of the first read transistor and the second read transistor respectively, indicating that the first read transistor and the second read transistor are regarded as voltage-controlled resistors).

[0099] V out ≈V in R R (VSN) / (R L (VSN)+R R (VSN))=V in ·W(VSN)

[0100] Figure 3 The output voltage V RL of the in-memory computing unit array shown in

[0101]

[0102] Figure 5 is Figure 3 the schematic diagram of the calculation process of the semiconductor device shown in

[0103] for in-memory analog computing. Figure 3 Taking Figure 3 as an example, the working principle of the in-memory computing unit of the present application is described below. The in-memory computing unit of the embodiment of the present application can be used for vector operations. The structure shown in

[0104] Figure 3 is an array formed by longitudinally repeating the in-memory computing unit and can calculate the vector product. The following is an operation example:

[0104] Write operation: Write weights in sequence [W1 W2 …… W n ( Figure 3 Only one column of in-memory computing units is shown, where W 1、 W2, ……, W n represents the weights of this column of in-memory computing units. If Figure 5 it includes multiple rows and columns of in-memory computing units, then use W 1,1、 W 1,2 、W 1,n 、……、W M,N to represent the weights of multiple rows and columns of in-memory computing units). Taking Wi as an example, set WLi to 1 and other WLs to 0, then set the voltage of bit line BL to Wi and keep it until the writing is completed, which generally takes 1ns to 5ns. Then set WLi and BL to 0 to complete the write operation;

[0105] Read operation: Float the electrode corresponding to the read signal line RL (i.e., not connect to any potential), and connect the voltages [V1, V2, ……, Vn] to be calculated to the input signal terminals 1L1, 1L2, ……, 1Ln;

[0106] Finally, read the voltage value of the read signal line RL to complete the multiplication operation of vector V and W.

[0107] The semiconductor device of the embodiment of the present application is used for simulation of two-dimensional vector calculation, as shown in Figure 6A and Figure 6B . Among them, Figure 6A is the circuit diagram used for simulation, and two in-memory computing units are used. During the calculation process, a 1V DC signal is applied to 1L of unit 1, and a 2V DC signal is applied to 1L of unit 2. Figure 6B is the simulation calculation result, where EN is the enable signal, and the device starts to work when it is at a high level. SN1 and SN2 are the magnitudes of the values stored in the two in-memory computing units, and the voltage value of the read signal line RL is the result output. Figure 6B calculates [1 2] multiplied by [1 1], [1 2] multiplied by [0 1], [1 2] multiplied by [1 0], [1 2] multiplied by [0 0] in sequence, and the level interval of each result is 0.5V, and a total of 4 calculations are performed.

[0108] Therefore, the semiconductor device of the embodiment of the present application can implement existing in-memory analog computing, and can accelerate neural network training and calculation with low power consumption.

[0109] The embodiment of the present application also provides a manufacturing method of the semiconductor device as provided in the embodiment of the present application above. The manufacturing includes:

[0110] Form a first read transistor T2 and a second read transistor T3 on the same main surface of a substrate;

[0111] Form a capacitor C on a side of the first read transistor T2 or the second read transistor T3 away from the substrate;

[0112] Form the write transistor on a side of the capacitor C away from the substrate.

[0113] Figures 7A to 9B and Figures 2A to 2C It is a schematic diagram of the intermediate process of a manufacturing method of a semiconductor device provided by an exemplary embodiment of the present application and the structure of the finally manufactured device.

[0114] As Figures 7A to 9B and Figures 2A to 2C shown, the manufacturing method may include the following steps.

[0115] S10: Form a first read transistor T2 and a second read transistor T3 on the same main surface of a substrate, including:

[0116] Provide a substrate 10, for example, a silicon substrate; form a first electrode P1, a first channel region 21, and a second electrode P2 of the first read transistor T2 on the substrate 10, and form a third electrode P3, a second channel region 22, and a fourth electrode P4 of the second read transistor T3, wherein the first electrode P1, the second electrode P2, the third electrode P3, and the fourth electrode P4 are located on the same main surface and are arranged in sequence in the order of the first electrode P1, the second electrode P2, the third electrode P3, and the fourth electrode P4; the first channel region 21 and the second channel region 22 are located on the same main surface and are insulated from each other by an insulating layer 11 (for example, an STI insulating layer);

[0117] Deposit an insulating layer 11 on a side of the first channel region 21 and the second channel region 22 away from the substrate 10, and sequentially form a first gate electrode G1 and a second gate electrode G2 on a side of the insulating layer 11 away from the substrate 10. For example, a gate electrode layer can be deposited and the first gate electrode G1 and the second gate electrode G2 can be formed simultaneously by a patterning process, as Figure 7A and Figure 7B shown.

[0118] S20: Deposit an insulating layer 11 covering the first read transistor T2 and the second read transistor T3 on the substrate 10, etch a trench in the insulating layer 11, and the trench exposes the first gate electrode G1 and the second gate electrode G2; deposit a conductive material in the trench to form M0 respectively connected to the first gate electrode G1 and the second gate electrode G2, and lead out the first gate electrode G1 and the second gate electrode G2 for subsequent use as storage nodes (SNs), as Figure 8A and Figure 8B shown.

[0119] S30: Etch a trench in the insulating layer 11, where the trench exposes the second electrode P2 and the third electrode P3, and deposit and sequentially form a seventh electrode P7, the insulating layer 11, and an eighth electrode P8 in the trench to obtain a capacitor C, as Figure 9A and Figure 9B shown.

[0120] Exemplarily, the seventh electrode P7 can be formed of the same material as the second electrode P2 or the third electrode P3. In this case, the seventh electrode P7 and the second electrode P2 or the third electrode P3 can be a common electrode or an integrated structure.

[0121] S40: Deposit and form a write transistor T1 on one side of the capacitor C, including: depositing a conductive layer and patterning to form a fifth electrode P5 and a sixth electrode P6 of the first write transistor T1, and sharing the fifth electrode P5 as a bit line BL; depositing a semiconductor layer on the surface of the fifth electrode P5 and the sixth electrode P6 away from the substrate 10 to form a third channel region 23 of the write transistor T1, and depositing a gate electrode layer on the surface of the third channel region 23 away from the substrate 10 to form a third gate electrode G3, as Figures 2A to 2C shown.

[0122] The embodiment of the present application also provides an electronic device, and the electronic device includes the semiconductor device provided by the embodiment of the present application as above.

[0123] Exemplarily, the electronic device can be: a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power supply, etc. The storage device can include the memory in a computer, etc., which is not limited herein.

[0124] Although the disclosed embodiments of the present application are as above, the described content is only an embodiment adopted for facilitating the understanding of the present application, and is not used to limit the present application. Any person skilled in the art within the scope of the present application can make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed by the present application. However, the protection scope of the present application shall still be subject to the scope defined by the appended claims.

Claims

1. A semiconductor device, characterized in that, Comprising: A first read transistor, a second read transistor, a write transistor, and a capacitor; The first read transistor includes a first electrode connected to an input signal terminal, a second electrode connected to the capacitor, and a first gate electrode connected to a storage node; The second read transistor includes a third electrode connected to the capacitor, a fourth electrode connected to a ground terminal, and a second gate electrode connected to the storage node; The write transistor includes a fifth electrode connected to a bit line, a sixth electrode connected to the storage node, and a third gate electrode connected to a word line; One end of the capacitor is connected to the second electrode and the third electrode, and the other end is connected to a readout signal terminal.

2. The semiconductor device according to claim 1, wherein The first read transistor and the write transistor are N-type transistors, and the second read transistor is a P-type transistor.

3. The semiconductor device according to claim 1, wherein The first read transistor and the second read transistor are spaced apart on the same main surface of the substrate, and the write transistor is stacked above the first read transistor and the second read transistor.

4. The semiconductor device according to claim 3, wherein, The capacitor is located between the first gate electrode and the second gate electrode, and the capacitor is located between the write transistor and the substrate.

5. The semiconductor device according to any one of claims 1-4, characterized in that, The first read transistor and the second read transistor are planar transistors; the first read transistor includes a first semiconductor layer connecting the first electrode and the second electrode, the second read transistor includes a second semiconductor layer connecting the third electrode and the fourth electrode, and both the first semiconductor layer and the second semiconductor layer extend along a first direction parallel to the substrate; The write transistor includes a third semiconductor layer connecting the fifth electrode and the sixth electrode, and the third semiconductor layer extends along the first direction; The first read transistor and the second read transistor are arranged at intervals in the first direction.

6. The semiconductor device according to claim 5, wherein, The third semiconductor layer extends from a region corresponding to the first semiconductor layer to a region corresponding to the second semiconductor layer in the first direction.

7. The semiconductor device according to claim 6, wherein, The materials of the first semiconductor layer and the second semiconductor layer contain silicon, and the material of the third semiconductor layer contains a metal oxide semiconductor material.

8. The semiconductor device according to claim 7, characterized in that, The material of the first semiconductor layer is N-type doped silicon, the material of the second semiconductor layer is P-type doped silicon, and the material of the third semiconductor layer is a metal oxide containing at least one of indium, gallium, zinc, and tin.

9. A method for manufacturing a semiconductor device according to any one of claims 1 to 8, characterized in that, Comprising: Forming the first read transistor and the second read transistor on the same main surface of the substrate; Forming the capacitor on a side of the first read transistor or the second read transistor away from the substrate; Forming the write transistor on a side of the capacitor away from the substrate.

10. An electronic device, characterized in that, Comprising the semiconductor device according to any one of claims 1 to 8.

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