Semiconductor element with linear structure and manufacturing method thereof

Abstract

The invention provides a semiconductor device. The semiconductor device includes a substrate, a contact, a landing pad, a bit line and an air gap. The contact is disposed over the substrate. The landing pad is disposed over the contact. The landing pad includes a plug, a first spacer and a second spacer. The plug is disposed over and in contact with the contact. The first spacer is disposed over the plug. The second spacer clamps a protruding portion of the plug. The bit line is disposed over the substrate. The air gap is disposed between the contact and the bit line.

Description

[0001] This application is a divisional application of Chinese Patent Application No. 202410467593.6, titled "Semiconductor Element with Linear Structure and Method for Manufacturing the Same", filed on April 18, 2024. Application No. 202410467593.6 claims the priority and benefits of U.S. Provisional Application No. 18 / 425,115, filed on January 29, 2024, the content of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present disclosure relates to a semiconductor element and a method for manufacturing the semiconductor element. In particular, it relates to a semiconductor element having a plurality of linear structures and a method for manufacturing the same. Background Art

[0003] Semiconductor elements are crucial for many modern applications. With the advancement of electronic technology, the size of semiconductor elements has become smaller and smaller, while providing more powerful functions and containing more integrated circuits. Due to the miniaturization of the size of semiconductor elements, various types and sizes of semiconductor elements providing different functions are integrated and packaged into a single module. In addition, many manufacturing operations are implemented to integrate various types of semiconductor elements.

[0004] However, the manufacturing and integration of semiconductor elements involve many complex steps and operations. The integration of semiconductor elements has become increasingly complex. The increase in the complexity of the manufacturing and integration of semiconductor elements may lead to defects. Therefore, there is a continuous need to improve the manufacturing process of semiconductor elements to solve these problems.

[0005] The above description of "Prior Art" only provides background art and does not admit that the above description of "Prior Art" discloses the subject matter of the present disclosure, does not constitute the prior art of the present disclosure, and any description of the above "Prior Art" should not be taken as any part of the present disclosure. Summary of the Invention

[0006] An embodiment of the present disclosure provides a semiconductor element, including a substrate, a contact, a landing pad, a bit line, and an air gap. The contact is disposed above the substrate. The landing pad is disposed above the contact. The landing pad includes a plug, a first spacer, and a second spacer. The plug is disposed above the contact and is in contact with the contact. The first spacer is disposed above the plug. The second spacer clamps a protruding portion of the plug. The bit line is disposed above the substrate. The air gap is disposed between the contact and the bit line.

[0007] Another embodiment of the present disclosure provides a semiconductor element, including a substrate, an etch stop layer, a first lower plug, a second lower plug, a first upper plug, a second upper plug, and an air gap. The etch stop layer is disposed above the substrate. The first lower plug and the second lower plug are disposed above the substrate and protrude from an upper surface of the etch stop layer. The first upper plug and the second upper plug are respectively disposed above the first lower plug and the second lower plug. The air gap is disposed between the first upper plug and the second upper plug. An upper surface of the first lower plug is circular. The first upper plug contacts a first sidewall of the first lower plug.

[0008] Another embodiment of the present disclosure provides a method for manufacturing a semiconductor element, including providing a substrate; forming a contact on the substrate; forming a bit line on the substrate; forming a liner structure to enclose an air gap, wherein the liner structure is formed between the contact and the bit line; and forming a landing pad above the contact, including: forming a barrier layer; forming a plug to contact the contact; and forming a first spacer and a second spacer above the plug. The first spacer is disposed above the plug, and the second spacer clamps a protruding portion of the plug.

[0009] The present disclosure provides embodiments of a semiconductor element structure and a method for manufacturing the same. In some embodiments, the semiconductor element structure includes a first dielectric liner portion disposed adjacent to a first interconnect structure and a second dielectric liner portion disposed adjacent to a second interconnect structure. The semiconductor element structure further includes a filling portion surrounded by the second dielectric liner portion and an air gap enclosed within the first dielectric liner portion, which helps reduce capacitive coupling between adjacent interconnect structures and can reduce resistance-capacitance (RC) delay. As a result, the performance (e.g., operating speed) and reliability of the semiconductor element structure can be improved.

[0010] The technical features and advantages of the present disclosure have been outlined quite extensively above, so as to enable a better understanding of the following detailed description of the present disclosure. Other technical features and advantages constituting the subject matter of the claims of the present disclosure will be described below. Those skilled in the art to which the present disclosure pertains should understand that the concepts disclosed below and specific embodiments can be readily utilized as a basis for modifying or designing other structures or processes to achieve the same purpose as the present disclosure. Those skilled in the art to which the present disclosure pertains should also understand that such equivalent constructs cannot depart from the spirit and scope of the present disclosure as defined by the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] When associated with the attached Figure 1As will be best understood from the following detailed description when read in conjunction therewith, it should be understood that various features are not drawn to scale in accordance with standard industry practice. In fact, the dimensions of various features may be arbitrarily increased or reduced for clarity of discussion.

[0012] Figure 1 is a cross-sectional schematic diagram illustrating the semiconductor element structure of some embodiments of the present disclosure.

[0013] Figure 2 is a cross-sectional schematic diagram illustrating the semiconductor element structure of some embodiments of the present disclosure.

[0014] Figure 3 is a cross-sectional schematic diagram illustrating the semiconductor element structure of some embodiments of the present disclosure.

[0015] Figure 4 is a cross-sectional schematic diagram illustrating the semiconductor element structure of some embodiments of the present disclosure.

[0016] Figure 5 is a flow schematic diagram illustrating a method for fabricating the semiconductor element structure of some embodiments of the present disclosure.

[0017] Figure 6 is a flow schematic diagram illustrating a method for fabricating the semiconductor element structure of some embodiments of the present disclosure.

[0018] Figure 7 is a cross-sectional schematic diagram illustrating an intermediate stage of sequentially forming a first dielectric layer and a second dielectric layer over a semiconductor substrate during the formation of the semiconductor element structure of some embodiments of the present disclosure.

[0019] Figure 8 is a cross-sectional schematic diagram illustrating an intermediate stage of sequentially forming a first conductive layer, a second conductive layer, and a patterned mask over the second dielectric layer during the formation of the semiconductor element structure of some embodiments of the present disclosure.

[0020] Figure 9 is a cross-sectional schematic diagram illustrating an intermediate stage of forming a first opening and a second opening through the first conductive layer and the second conductive layer using the patterned mask as an etching mask during the formation of the semiconductor element structure of some embodiments of the present disclosure.

[0021] Figure 10 is a cross-sectional schematic diagram illustrating an intermediate stage of removing the patterned mask during the formation of the semiconductor element structure of some embodiments of the present disclosure.

[0022] Figure 11 is a cross-sectional schematic diagram illustrating an intermediate stage of forming a dielectric liner layer in the first opening and the second opening during the formation of the semiconductor element structure of some embodiments of the present disclosure.

[0023] Figure 12 is a cross-sectional schematic view illustrating an intermediate stage of forming a filling layer above a dielectric liner layer during the formation of a semiconductor device structure according to some embodiments of the present disclosure.

[0024] Figure 13 is a cross-sectional schematic view illustrating an intermediate stage of partially removing the filling layer and the dielectric liner layer to expose a second conductive layer during the formation of a semiconductor device structure according to some embodiments of the present disclosure.

[0025] Figure 14 is a cross-sectional schematic view illustrating an intermediate stage of forming a filling layer above a dielectric liner layer during the formation of a semiconductor device structure according to some embodiments of the present disclosure.

[0026] Figure 15 is a cross-sectional schematic view illustrating an intermediate stage of partially removing the filling layer and the dielectric liner layer to expose a second conductive layer during the formation of a semiconductor device structure according to some embodiments of the present disclosure.

[0027] Figure 16 is a cross-sectional schematic view illustrating an intermediate stage of forming a dielectric liner layer in a first opening and a second opening during the formation of a semiconductor device structure according to some embodiments of the present disclosure.

[0028] Figure 17 is a cross-sectional schematic view illustrating an intermediate stage of forming a filling layer above a dielectric liner layer during the formation of a semiconductor device structure according to some embodiments of the present disclosure.

[0029] Figure 18 is a cross-sectional schematic view illustrating an intermediate stage of partially removing the filling layer and the dielectric liner layer to expose a second conductive layer during the formation of a semiconductor device structure according to some embodiments of the present disclosure.

[0030] Figure 19 is a cross-sectional schematic view illustrating an intermediate stage of forming a filling layer above a dielectric liner layer during the formation of a semiconductor device structure according to some embodiments of the present disclosure.

[0031] Figure 20 is a cross-sectional schematic view illustrating an intermediate stage of partially removing the filling layer and the dielectric liner layer to expose a second conductive layer during the formation of a semiconductor device structure according to some embodiments of the present disclosure.

[0032] Figure 21 is a cross-sectional schematic view illustrating a semiconductor structure according to some embodiments of the present disclosure.

[0033] Figures 22 to 41 is a cross-sectional schematic view illustrating an intermediate stage of forming a Figure 21 semiconductor structure shown according to some embodiments of the present disclosure.

[0034] Figure 42ais a cross-sectional schematic diagram illustrating a semiconductor structure according to some embodiments of the present disclosure.

[0035] Figure 42b is a partially enlarged schematic diagram illustrating Figure 42a the semiconductor device shown in some embodiments of the present disclosure.

[0036] Figures 43 to 61 is a cross-sectional schematic diagram illustrating an intermediate stage of forming the semiconductor structure shown in Figure 42a and Figure 42b of the present disclosure.

[0037] Description of reference numerals:

[0038] 10: Preparation method

[0039] 30: Preparation method

[0040] 100a: Semiconductor device structure

[0041] 100b: Semiconductor device structure

[0042] 101: Semiconductor substrate

[0043] 103: First dielectric layer

[0044] 105: Second dielectric layer

[0045] 107: First conductive layer

[0046] 107a: First conductive portion

[0047] 107b: First conductive portion

[0048] 107c: First conductive portion

[0049] 107d: First conductive portion

[0050] 109: Second conductive layer

[0051] 109a: Second conductive portion

[0052] 109b: Second conductive portion

[0053] 109c: Second conductive portion

[0054] 109d: Second conductive portion

[0055] 111: Patterning mask

[0056] 114: Opening

[0057] 116: Opening

[0058] 119a: Interconnection structure

[0059] 119b: Interconnection structure

[0060] 119c: Interconnection structure

[0061] 119d: Interconnection structure

[0062] 124: Opening

[0063] 126: Opening

[0064] 126’: Opening

[0065] 131: Dielectric liner layer

[0066] 131a: Dielectric liner portion

[0067] 131b: Dielectric liner portion

[0068] 131c: Dielectric liner portion

[0069] 131d: Dielectric liner portion

[0070] 134: Air gap

[0071] 137: Filling layer

[0072] 137’: Filling portion

[0073] 139: Filling layer

[0074] 139’: Filling portion

[0075] 141: Covering layer

[0076] 200a: Semiconductor device structure

[0077] 200b: Semiconductor device structure

[0078] 231: Dielectric liner layer

[0079] 231a: Dielectric liner portion

[0080] 231b: Dielectric liner portion

[0081] 231c: Dielectric liner portion

[0082] 231d: Dielectric liner portion

[0083] 234: Gap

[0084] 237: Filling layer

[0085] 237a: Filling portion

[0086] 237b: Filling portion

[0087] 239: Filling layer

[0088] 239a: Filling part

[0089] 239b: Filling part

[0090] 300: Semiconductor structure

[0091] 301: Substrate

[0092] 303: Isolation structure

[0093] 305: Word line

[0094] 305’: Trench opening

[0095] 305a: Bottom layer

[0096] 305b: Intermediate layer

[0097] 305c: Top layer

[0098] 307: Active region

[0099] 307a: First doped region

[0100] 307b: Second doped region

[0101] 309: First insulating film

[0102] 311: Second insulating film

[0103] 313: Third insulating film

[0104] 315: Fourth insulating film

[0105] 317: Contact

[0106] 319: Bit line contact

[0107] 321: First capping layer

[0108] 323: Bit line

[0109] 323-1: Filling material

[0110] 323’: Bit line trench opening

[0111] 325: Capacitor contact

[0112] 325-1: Filling material

[0113] 325’: Contact hole

[0114] 325”: Transition hole

[0115] 325”-1: Narrow part

[0116] 325”-2: Wide part

[0117] 325a: Neck

[0118] 325aW: Width

[0119] 325b: Head

[0120] 325bW: Width

[0121] 325c: Curved side wall

[0122] 327: Plug

[0123] 327a: Protruding part

[0124] 327W: Width

[0125] 329: Landing pad

[0126] 329’: Liner layer

[0127] 329a: First spacer

[0128] 329b: Second spacer

[0129] 329bW: Width

[0130] 331: Liner structure

[0131] 333: Air gap

[0132] 341: Barrier layer

[0133] 341a: Top

[0134] 401: Patterned mask

[0135] 403: Opening

[0136] 405: Opening

[0137] 405W: Width

[0138] 407: Dielectric liner layer

[0139] 407T: Thickness

[0140] 500: Semiconductor element

[0141] 501: Semiconductor substrate

[0142] 501T: Upper surface

[0143] 503: First dielectric layer

[0144] 505: Etch stop layer

[0145] 505T: Upper surface

[0146] 507: The second dielectric layer

[0147] 507T: The upper surface

[0148] 509: Photoresist pattern

[0149] 512: Opening

[0150] 514: Opening

[0151] 517: Metal layer

[0152] 517a: Metal portion

[0153] 517b: Metal portion

[0154] 517c: Metal portion

[0155] 518: Opening

[0156] 519a: Metal plug

[0157] 519a1: Upper part

[0158] 519a2: Lower part

[0159] 519b: Metal plug

[0160] 519c: Metal plug

[0161] 521a: Silicide layer

[0162] 521b: Silicide layer

[0163] 521c: Silicide layer

[0164] 523: The third dielectric layer

[0165] 525: Photoresist pattern

[0166] 528: Opening

[0167] 530: Opening

[0168] 532: Gap

[0169] 535: Energy-removable material

[0170] 536a1: Air gap

[0171] 536b1: Air gap

[0172] 536c1: Air gap

[0173] 536a2: Air gap

[0174] 536b2: Air gap

[0175] 536c2: Air gap

[0176] 537: Metal layer

[0177] 537a: Second metal plug

[0178] 537b: Second metal plug

[0179] 537c: Second metal plug

[0180] 539: Fourth dielectric layer

[0181] 550a: Bit line

[0182] 550b: Bit line

[0183] 550c: Bit line

[0184] 560a: Pad structure

[0185] 560b: Pad structure

[0186] 565a: Air gap

[0187] 565b: Air gap

[0188] 601: Patterned mask

[0189] 603: Opening

[0190] 605: Opening

[0191] 605W: Width

[0192] 607: Dielectric liner layer

[0193] 607T: Thickness

[0194] A: First region

[0195] B: Second region

[0196] E: Edge

[0197] H1: Height

[0198] H2: Height

[0199] S11: Step

[0200] S13: Step

[0201] S15: Step

[0202] S17: Step

[0203] S19: Step

[0204] S21: Step

[0205] S23: Step

[0206] S25: Step

[0207] S27: Step

[0208] S31: Step

[0209] S33: Step

[0210] S35: Step

[0211] S37: Step

[0212] S39: Step

[0213] S41: Step

[0214] S43: Step

[0215] S45: Step

[0216] S47: Step

[0217] SW1: First side wall

[0218] SW2: Second side wall

[0219] T1: Thickness

[0220] T2: Thickness

[0221] TP: Highest point

[0222] TS: Upper surface

[0223] TSA1: Upper surface area

[0224] TSA2: Upper surface area

[0225] W1: Width

[0226] W2: Width

[0227] W3: Width

[0228] W4: Width

[0229] Z: Direction Detailed implementation manners

[0230] Specific examples of components and configurations are described below to simplify the embodiments of the present disclosure. Of course, these embodiments are for illustration only and are not intended to limit the scope of the present disclosure. For example, in the description, when the first component is formed on the second component, it may include embodiments where the first and second components are in direct contact, or it may include embodiments where additional components are formed between the first and second components such that the first and second components are not in direct contact. Additionally, embodiments of the present disclosure may repeat reference numerals and / or letters in many examples. The purpose of these repetitions is to simplify and clarify, and unless otherwise specified in the text, they do not themselves represent a specific relationship between various embodiments and / or the configurations discussed.

[0231] In addition, for ease of description, spatially relative terms such as "beneath", "below", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or feature shown in the figures to another (other) element or feature. The spatially relative terms are intended to encompass different orientations of the element in use or operation in addition to the orientation shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly.

[0232] Figure 1 is a cross-sectional schematic diagram illustrating the semiconductor element structure 100a of some embodiments of the present disclosure. As Figure 1 shown, according to some embodiments, the semiconductor element structure 100a includes a semiconductor substrate 101, a first dielectric layer 103 disposed above the semiconductor substrate 101, and a second dielectric layer 105 disposed above the first dielectric layer 103. In some embodiments, the semiconductor element structure 100a also includes a plurality of interconnect structures 119a, 119b, 119c, and 119d disposed above the second dielectric layer 105.

[0233] In some embodiments, the interconnect structures 119a, 119b, 119c, and 119d are separated from each other. Each of the interconnect structures 119a, 119b, 119c, and 119d includes a first conductive portion and a second conductive portion disposed above the first conductive portion. For example, the interconnect structure 119a includes a first conductive portion 107a and a second conductive portion 109a, the interconnect structure 119b includes a first conductive portion 107b and a second conductive portion 109b, the interconnect structure 119c includes a first conductive portion 107c and a second conductive portion 109c, and the interconnect structure 119d includes a first conductive portion 107d and a second conductive portion 109d.

[0234] In some embodiments, the semiconductor element structure 100a includes dielectric pad portions 131a, 131b, 131c, and 131d disposed above the second dielectric layer 105. Each of the dielectric pad portions 131a, 131b, 131c, and 131d is disposed between two adjacent interconnect structures. In some embodiments, each of the dielectric pad portions 131a, 131b, 131c, and 131d is in direct contact with a first conductive portion and a second conductive portion of two adjacent interconnect structures. In some embodiments, an air gap 134 is enclosed in the dielectric pad portion 131a, and a filling portion 137' is surrounded by the dielectric pad portion 131d.

[0235] In some embodiments, the filling portion 137' is separated from the second dielectric layer 105 by the dielectric pad portion 131d. In some embodiments, the filling portion 137' is separated from two adjacent interconnect structures 119c and 119d by the dielectric pad portion 131d. Additionally, the semiconductor element structure 100a includes a capping layer 141 disposed above the interconnect structures 119a, 119b, 119c, 119d, the dielectric pad portions 131a, 131b, 131c, 131d, and the filling portion 137'. In some embodiments, the capping layer 141 is in direct contact with the upper surfaces of the interconnect structures 119a, 119b, 119c, 119d (i.e., the upper surfaces of the second conductive portions 109a, 109b, 109c, 109d), the upper surfaces of the dielectric pad portions 131a, 131b, 131c, 131d, and the upper surface of the filling portion 137'.

[0236] Furthermore, the semiconductor element structure 100a has a first region A and a second region B. In some embodiments, the interconnect structures 119a and 119b, the dielectric pad portions 131a and 131b, and the air gap 134 are located in the first region A. In some embodiments, the interconnect structures 119c and 119d, the dielectric pad portions 131c and 131d, and the filling portion 137' are located in the second region B.

[0237] As Figure 1 shown, according to some embodiments, the space between the interconnect structures 119a and 119b is occupied by the dielectric pad portion 131a and the air gap 134, and the space between the interconnect structures 119c and 119d is occupied by the dielectric pad portion 131d and the filling portion 137'. Since the space occupied by the dielectric pad portion 131a and the air gap 134 is smaller than the space occupied by the dielectric pad portion 131d and the filling portion 137', the first region A is also referred to as a small gap filling region, and the second region B is also referred to as a large gap filling region.

[0238] In some embodiments, at Figure 1In the cross-sectional view, the space occupied by the dielectric pad portion 131a and the air gap 134 has a width W1, the space occupied by the dielectric pad portion 131d and the filling portion 137' has a width W2, and the width W2 is greater than the width W1. The width W1 is also referred to as the bottom width of the dielectric pad portion 131a, and the width W2 is also referred to as the bottom width of the dielectric pad portion 131d. In some embodiments, the bottom width W2 of the dielectric pad portion 131d in the large gap filling region B is greater than the bottom width W1 of the dielectric pad portion 131a in the small gap filling region A.

[0239] In Figure 1 , four interconnect structures 119a, 119b, 119c, 119d and four dielectric pad portions 131a, 131b, 131c, 131d are shown. However, the number is not limited thereto. In some other embodiments, the number of interconnect structures and dielectric pad portions can be adjusted based on design requirements. Similarly, in Figure 1 , an air gap 134 is shown in the small gap filling region A, and a filling portion 137' is shown in the large gap filling region B. It should be understood that the number is not limited thereto. For example, in some other embodiments, the number of air gaps in the small gap filling region A and the number of filling portions in the large gap filling region B can be adjusted according to design requirements.

[0240] Figure 2 is a cross-sectional schematic diagram illustrating the semiconductor element structure 100b of some embodiments of the present disclosure. The semiconductor element structure 100b is similar to the semiconductor element structure 100a. However, according to some embodiments, in the semiconductor element structure 100b, the filling portion 137' is replaced by another filling portion 139', and the materials of the filling portions 137' and 139' are different.

[0241] In some embodiments, the filling portion 137' of the semiconductor element structure 100a includes a low-k dielectric material, and the filling portion 139' of the semiconductor element structure 100b includes an energy-removable material. In some embodiments, the filling portion 139' including the energy-removable material is surrounded by the dielectric pad portion 131d. The details of this embodiment are similar to the details of the previously described embodiments and will not be repeated here.

[0242] Figure 3It is a cross-sectional schematic diagram illustrating the semiconductor element structure 200a of some embodiments of the present disclosure. The semiconductor element structure 200a is similar to the semiconductor element structure 100a. However, in the semiconductor element structure 200a, dielectric pad portions 231a and 231b are formed in the first region A (i.e., the small gap filling region), dielectric pad portions 231c and 231d are formed in the second region B (i.e., the large gap filling region), a filling portion 237a is surrounded by the dielectric pad portion 231a, and a filling portion 237b is surrounded by the dielectric pad portion 231d. In the semiconductor element structure 200a, there is no air gap in the dielectric pad portion 231a of the first region A.

[0243] According to some embodiments, similar to the semiconductor element structure 100a, the bottom width W2 of the dielectric pad portion 231d is greater than the bottom width W1 of the dielectric pad portion 231a. In addition, in some embodiments, the materials of the filling portions 237a and 237b are the same. For example, the filling portions 237a and 237b include a low-k dielectric material.

[0244] In some embodiments, the filling portion 237a in the first region A has a width W3, the filling portion 237b in the second region B has a width W4, and the width W4 is greater than the width W3. In some embodiments, the covering layer 141 is in direct contact with the upper surfaces of the filling portions 237a and 237b. The details of this embodiment are similar to the details of the previously described embodiments and will not be repeated here.

[0245] Figure 4 It is a cross-sectional schematic diagram illustrating the semiconductor element structure 200b of some embodiments of the present disclosure. The semiconductor element structure 200b is similar to the semiconductor element structure 200a. However, in the semiconductor element structure 200b, the filling portions 237a and 237b are respectively replaced by filling portions 239a and 239b. According to some embodiments, the materials of the filling portions 239a and 239b are the same, but different from the materials of the filling portions 237a and 237b in the semiconductor element structure 200a.

[0246] In some embodiments, the filling portions 237a and 237b of the semiconductor element structure 200a include a low-k dielectric material, and the filling portions 239a and 239b of the semiconductor element structure 200b include an energy-removable material. The details of this embodiment are similar to the details of the previously described embodiments and will not be repeated here.

[0247] Figure 5It is a process flow diagram illustrating a method for fabricating a semiconductor device structure (e.g., semiconductor device structure 100a or 100b) according to some embodiments of the present disclosure. The fabrication method 10 includes steps S11, S13, S15, S17, S19, S21, S23, S25, and S27. Figure 5 Steps S11 to S27 of Figures 7 to 15 will be described in detail with reference to the following drawings (e.g.,

[0248] Figure 6 It is a process flow diagram illustrating a method for fabricating a semiconductor device structure (e.g., semiconductor device structure 200a or 200b) according to some embodiments of the present disclosure. The fabrication method 30 includes steps S31, S33, S35, S37, S39, S41, S43, S45, and S47. Figure 6 Steps S31 to S47 of Figures 16 to 20 will be described in detail with reference to the following drawings (e.g.,

[0249] Figures 7 - 13 It is a cross-sectional view illustrating an intermediate stage of forming a semiconductor device structure 100a according to some embodiments. As Figure 7 shown, a semiconductor substrate 101 is provided. The semiconductor substrate 101 may be a semiconductor wafer, such as a silicon wafer.

[0250] Alternatively or additionally, the semiconductor substrate 101 may include an elemental semiconductor material, a compound semiconductor material, and / or an alloy semiconductor material. Examples of elemental semiconductor materials may include crystalline silicon, polycrystalline silicon, amorphous silicon, germanium, and / or diamond, but are not limited thereto. Examples of compound semiconductor materials may include silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide, but are not limited thereto. Examples of alloy semiconductor materials may include SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP, but are not limited thereto.

[0251] In some embodiments, the semiconductor substrate 101 includes an epitaxial layer. For example, the semiconductor substrate 101 has an epitaxial layer covering a bulk semiconductor. In some embodiments, the semiconductor substrate 101 is a semiconductor-on-insulator substrate, which may include a substrate, a buried oxide layer above the substrate, and a semiconductor layer above the buried oxide layer, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. The semiconductor-on-insulator substrate can be fabricated using separation by implanted oxygen (SIMOX), wafer bonding, and / or other suitable methods.

[0252] According to some embodiments, as Figure 7As shown, a first dielectric layer 103 and a second dielectric layer 105 are sequentially formed over a semiconductor substrate 101. Each step is shown as Figure 5 Steps S11 and S13 in the manufacturing method 10 shown. In some embodiments, the first dielectric layer 103 and the second dielectric layer 105 are made of or include silicon oxide, silicon nitride, or silicon oxynitride. In some embodiments, the first dielectric layer 103 is made of or includes borosilicate glass (BSG), silicon dioxide (SiO2), or a combination thereof. In some embodiments, the second dielectric layer 105 is made of or includes borophosphosilicate glass (BPSG), tetraethyl orthosilicate (TEOS), or a combination thereof.

[0253] The manufacturing technique of the first dielectric layer 103 may include a deposition process, such as a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, a spin coating process, or other suitable methods. Some processes for forming the second dielectric layer 105 are similar to or the same as those for forming the first dielectric layer 103, and will not be described herein again. Additionally, the second dielectric layer 105 may also be referred to as an interlayer dielectric (ILD) layer.

[0254] Next, according to some embodiments, as Figure 8 shown, a first conductive layer 107 and a second conductive layer 109 are sequentially formed over the second dielectric layer 105. Each step is shown as Figure 5 Steps S15 and S17 in the manufacturing method 10 shown. In some embodiments, the first conductive layer 107 and the second conductive layer 109 are made of or include tungsten (W), aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), other suitable materials, or a combination thereof. In some embodiments, the first conductive layer 107 is made of or includes titanium nitride (TiN), and the second conductive layer 109 is made of or includes tungsten (W).

[0255] The manufacturing technique of the first conductive layer 107 may include a deposition process, such as a CVD process, a PVD process, an ALD process, a metalorganic chemical vapor deposition (MOCVD) process, a sputtering process, an electroplating process, or other suitable methods. Some processes for forming the second conductive layer 109 are similar to or the same as those for forming the first conductive layer 107, and will not be described herein again. Additionally, the first conductive layer 107 may also be referred to as a barrier layer.

[0256] Still refer to Figure 8 , according to some embodiments, a patterned mask 111 having a plurality of openings (e.g., openings 114 and 116) is formed over the second conductive layer 109. In some embodiments, the opening 114 is located in the first region A, the opening 116 is located in the second region B, and the second conductive layer 109 is partially exposed by the openings 114 and 116. In some embodiments, the width of the opening 116 (i.e., width W2) is greater than the width of the opening 114 (i.e., width W1). In some embodiments, the second conductive layer 109 and the patterned mask 111 include different materials such that the etch selectivity can be different in subsequent etching processes.

[0257] Subsequently, according to some embodiments, an etching process is performed using the patterned mask 111 as an etch mask to form openings 124 and 126 to penetrate through the first conductive layer 107 and the second conductive layer 109, as Figure 9 shown. In some embodiments, a width (i.e., width W2) of the opening 126 in the second region B is greater than a width (i.e., width W1) of the opening 124 in the first region A. Each step is shown as Figure 5 step S19 in the manufacturing method 10 shown.

[0258] In addition, according to some embodiments, an upper surface area TSA2 of the second dielectric layer 105 exposed by the opening 126 is greater than an upper surface area TSA1 of the second dielectric layer 105 exposed by the opening 124. In some embodiments, the etching process for forming the openings 124 and 126 includes a wet etching process, a dry etching process, or a combination thereof.

[0259] After forming the openings 124 and 126, a plurality of interconnect structures 119a, 119b, 119c, and 119d are obtained. In some embodiments, the remaining portions of the first conductive layer 107 and the second conductive layer 109 are hereinafter referred to as the first conductive portions 107a, 107b, 107c, 107d and the second conductive portions 109a, 109b, 109c, 109d. As described above, according to some embodiments, as Figure 9 shown, each of the interconnect structures 119a, 119b, 119c, and 119d includes a first conductive portion and a second conductive portion disposed above the first conductive portion.

[0260] Then, according to some embodiments, as Figure 10 shown, the patterned mask 111 is removed. In some embodiments, the patterned mask 111 is removed by a lift-off process, an ashing process, an etching process, or other suitable processes. After removing the patterned mask 111, the upper surfaces of the second conductive portions 109a, 109b, 109c, and 109d are exposed.

[0261] Next, according to some embodiments, as Figure 11 shown, a dielectric liner layer 131 is conformally formed over Figure 10 the structure. In some embodiments, the dielectric liner layer 131 is formed in openings 124 and 126 and over the upper surfaces of the second conductive portions 109a, 109b, 109c, and 109d. Each step is shown as Figure 5 step S21 in the fabrication method 10 as shown.

[0262] In some embodiments, the thickness of the dielectric liner layer 131 is adjusted such that an air gap 134 is enclosed in the portion of the dielectric liner layer 131 that fills the opening 124, while the opening 126 remains unfilled by the dielectric liner layer 131. In some embodiments, the dielectric liner layer 131 has a thickness T1, the width W1 of the opening 124 is less than twice the thickness T1, and the width W2 of the opening 126 is greater than twice the thickness T1.

[0263] Furthermore, in some embodiments, the dielectric liner layer 131 is made of or includes boron carbonitride (BCN). However, any other suitable dielectric material can be utilized. The fabrication technique of the dielectric liner layer 131 can include a deposition process, such as a CVD process, a PVD process, an ALD process, a spin coating process, or other suitable methods. In some embodiments, the air gap 134 is enclosed (or sealed) in the portion of the dielectric liner layer 131 that fills the opening 124. In other words, the air gap 134 is not exposed.

[0264] Subsequently, according to some embodiments, as Figure 12 shown, a filling layer 137 is formed over the dielectric liner layer 131. In some embodiments, Figure 11 the remaining portion of the opening 126 (also referred to as 126') in the structure is filled with the filling layer 137. Each step is shown as Figure 5 step S23 in the fabrication method 10 as shown.

[0265] In some embodiments, since the air gap 134 in the first region A is surrounded by the dielectric liner layer 131, the air gap 134 is separated from the filling layer 137 by the dielectric liner layer 131. In some embodiments, the filling layer 137 is made of or includes a low-k dielectric material. For example, the dielectric constant (k value) of the low-k dielectric material can be less than about 3.0. In some embodiments, the fabrication technique of the filling layer 137 includes a sputtering process. However, any other suitable deposition method can be utilized.

[0266] Then, according to some embodiments, as Figure 16As shown, the filling layer 137 and the dielectric liner layer 131 are partially removed to expose the interconnect structures 119a, 119b, 119c, and 119d (i.e., the second conductive portions 109a, 109b, 109c, and 109d). Each step is shown as Figure 5 step S25 in the manufacturing method 10 shown. After partially removing the filling layer 137 and the dielectric liner layer 131, dielectric liner portions 131a, 131b, 131c, 131d and a filling portion 137' are obtained.

[0267] In some embodiments, the dielectric liner portions 131a, 131b and the air gap 134 are located in the first region A, and the dielectric liner portions 131c, 131d and the filling portion 137' are located in the second region B. In some embodiments, the filling layer 137 and the dielectric liner layer 131 are partially removed by a planarization process, an etch-back process, or a combination thereof. The planarization process may include a chemical mechanical polishing (CMP) process.

[0268] Next, according to some embodiments, as Figure 1 shown, a covering layer 141 is formed over the interconnect structures 119a, 119b, 119c, and 119d. In some embodiments, the covering layer 141 is formed over and in direct contact with the upper surfaces of the interconnect structures 119a, 119b, 119c, 119d (i.e., the upper surfaces of the second conductive portions 109a, 109b, 109c, 109d), the upper surfaces of the dielectric liner portions 131a, 131b, 131c, 131d, and the upper surface of the filling portion 137'. Each step is shown as Figure 5 step S27 in the manufacturing method 10 shown.

[0269] In some embodiments, the covering layer 141 is made of or includes a silicon-based material, such as silicon nitride (Si3N4), silicon oxynitride (SiON), or silicon dioxide (SiO2). In some embodiments, the covering layer 141 is made of or includes a carbonitride, with or without an additional dopant such as boron (B). The manufacturing technique of the covering layer 141 may include a deposition process, such as a CVD process, a PVD process, an ALD process, a spin coating process, or other suitable methods. After forming the covering layer 141, the semiconductor element structure 100a can be obtained.

[0270] Figure 14 and Figure 15is a cross-sectional view illustrating an intermediate stage of forming a semiconductor device structure 100b according to some embodiments. It should be noted that, before the structure shown in Figure 14 the forming steps of the semiconductor device structure 100b are substantially the same as those of the semiconductor device structure 100a shown in Figures 7 - 11 and the relevant detailed description can be referred to the foregoing, and will not be repeated here.

[0271] According to some embodiments, as shown in Figure 14 after forming the dielectric liner layer 131, a filling layer 139 is formed over the dielectric liner layer 131. In some embodiments, the remaining portion of the opening 126 (i.e., Figure 11 126’ in Figure 5 is filled with the filling layer 139. Each step is shown as step S23 in the preparation method 10 shown in

[0272] In some embodiments, since the air gap 134 in the first region A is surrounded by the dielectric liner layer 131, the air gap 134 is separated from the filling layer 139 by the dielectric liner layer 131. In some embodiments, the filling layer 139 is made of or includes an energy-removable material. In some embodiments, the energy-removable material includes a thermally decomposable material. In some other embodiments, the energy-removable material includes a photon-decomposable material, an electron-beam-decomposable material, or other suitable energy-decomposable materials. In some embodiments, the energy-removable material includes a base material and a decomposable pore-forming agent material that is substantially removed once exposed to an energy source (such as heat).

[0273] In this case, the base material may include hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), porous polyarylether (PAE), porous SiLK, or porous silicon dioxide (SiO2), and the decomposable pore-forming agent material may include a pore-forming organic compound, which can provide porosity for the space originally occupied by the energy-removable material (i.e., the filling layer 139) in subsequent processes. In some embodiments, the fabrication technique of the filling layer 139 includes a sputtering process. However, any other suitable deposition method can be utilized.

[0274] Subsequently, according to some embodiments, as shown in Figure 15 part of the filling layer 139 and the dielectric liner layer 131 are removed to expose the interconnect structures 119a, 119b, 119c, and 119d (i.e., the second conductive portions 109a, 109b, 109c, and 109d). Each step is shown as step S25 in the preparation method 10 shown in Figure 5 After partially removing the filling layer 139 and the dielectric liner layer 131, the dielectric liner portions 131a, 131b, 131c, 131d and the filling portion 139’ are obtained.

[0275] In some embodiments, the dielectric pad portions 131a, 131b and the air gap 134 are located in the first region A, and the dielectric pad portions 131c, 131d and the filling portion 139' are located in the second region B. In some embodiments, the filling layer 139 and the dielectric pad layer 131 are partially removed by a planarization process, an etch-back process, or a combination thereof. The planarization process may include a CMP process.

[0276] Then, according to some embodiments, as Figure 2 shown, a capping layer 141 is formed over the interconnect structures 119a, 119b, 119c and 119d. In some embodiments, the capping layer 141 is formed over and in direct contact with the upper surfaces of the interconnect structures 119a, 119b, 119c, 119d (i.e., the upper surfaces of the second conductive portions 109a, 109b, 109c, 109d), the upper surfaces of the dielectric pad portions 131a, 131b, 131c, 131d, and the upper surface of the filling portion 139'. Each step is shown as Figure 5 step S27 in the manufacturing method 10 shown.

[0277] Details of the capping layer 141 may be substantially the same as those shown and discussed in Figure 1 and thus are not repeated here. After the capping layer 141 is formed, the semiconductor element structure 100b can be obtained. In some embodiments, a heat treatment process may be performed to transform the filling portion 139' into an air gap (not shown in the figures). In some embodiments, the heat treatment process is optional. In some embodiments, the temperature used in the heat treatment process may be high enough to effectively burn off the filling portion 139', leaving an air gap surrounded by the dielectric pad portion 131d and the capping layer 141. In some other embodiments, the temperature used in the heat treatment process is selected such that the filling portion 139' is transformed into an air gap surrounded or enclosed by the remaining portion of the filling portion 139'.

[0278] Figures 16 to 18 is a cross-sectional view illustrating an intermediate stage of forming a semiconductor element structure 200a according to some embodiments. It should be noted that the formation steps of the semiconductor element structure 200a before the structure shown in Figure 16 are substantially the same as the formation steps of the semiconductor element structure 100a shown in Figures 7 - 10 ( Figure 6 steps S31 to S39 in the manufacturing method 30 shown are the same as Figure 5The steps S11 to S19 in the preparation method 10 shown are the same), and the relevant detailed description can be referred to the foregoing, and will not be elaborated herein.

[0279] According to some embodiments, as Figure 16 shown, after the openings 124 and 126 are formed, a dielectric liner layer 231 is conformally formed on Figure 10 the structure above. In some embodiments, the dielectric liner layer 231 is formed in the openings 124 and 126 and above the upper surfaces of the second conductive portions 109a, 109b, 109c, and 109d. Each step is shown as Figure 6 step S41 in the preparation method 30 shown.

[0280] In some embodiments, the thickness of the dielectric liner layer 231 is adjusted such that the width of a gap 234 (i.e., the remaining portion of the opening 124) formed in the first region A is less than the width of the opening 126' (i.e., the remaining portion of the opening 126) formed in the second region B. For example, the width W4 of the opening 126' is greater than the width W3 of the gap 234. In some embodiments, the width W3 represents a width measured at the widest part of the gap 234.

[0281] In addition, please refer to Figure 10 and Figure 16 , the dielectric liner layer 231 has a thickness T2, the width W1 of the opening 124 is less than twice the thickness T2, and the width W2 of the opening 126 is greater than twice the thickness T2. In some embodiments, the opening 124 in the first region A is partially filled with the dielectric liner layer 231, and there is no closed air gap in the dielectric liner layer 231. Some of the materials and processes for forming the dielectric liner layer 231 are similar or the same as those for forming the dielectric liner layer 131, and will not be elaborated herein.

[0282] Next, according to some embodiments, as Figure 17 shown, a fill layer 237 is formed above the dielectric liner layer 231. In some embodiments, the gap 234 (i.e., the remaining portion of the opening 124 after the dielectric liner layer 231 is formed) in the first region A and the opening 126' (i.e., the remaining portion of the opening 126 after the dielectric liner layer 231 is formed) in the second region B are filled with the fill layer 237. Each step is shown as Figure 6 step S43 in the preparation method 30 shown.

[0283] In some embodiments, the fill layer 237 is made of or includes a low-k dielectric material. For example, the dielectric constant (k value) of the low-k dielectric material can be less than about 3.0. In some embodiments, the fabrication technique of the fill layer 237 includes a sputtering process. However, any other suitable deposition method can be utilized.

[0284] Subsequently, according to some embodiments, such as Figure 18 shown, the fill layer 237 and the dielectric liner layer 231 are partially removed to expose the interconnect structures 119a, 119b, 119c, and 119d (i.e., the second conductive portions 109a, 109b, 109c, and 109d). Each step is shown as Figure 6 step S45 in the manufacturing method 30 shown. After the fill layer 237 and the dielectric liner layer 231 are partially removed, dielectric liner portions 231a, 231b, 231c, 231d and fill portions 237a and 237b are obtained.

[0285] In some embodiments, the dielectric liner portions 231a, 231b and the fill portion 237a are located in the first region A, and the dielectric liner portions 231c, 231d and the fill portion 237b are located in the second region B. In some embodiments, the fill layer 237 and the dielectric liner layer 231 are partially removed by a planarization process, an etch-back process, or a combination thereof. The planarization process may include a CMP process.

[0286] Then, according to some embodiments, such as Figure 3 shown, a cover layer 141 is formed over the interconnect structures 119a, 119b, 119c, and 119d. In some embodiments, the cover layer 141 is formed over the upper surfaces of the interconnect structures 119a, 119b, 119c, 119d (i.e., the upper surfaces of the second conductive portions 109a, 109b, 109c, 109d), the upper surfaces of the dielectric liner portions 231a, 231b, 231c, 231d, and the upper surfaces of the fill portions 237a, 237b and is in direct contact with the upper surfaces of the interconnect structures 119a, 119b, 119c, 119d (i.e., the upper surfaces of the second conductive portions 109a, 109b, 109c, 109d), the upper surfaces of the dielectric liner portions 231a, 231b, 231c, 231d, and the upper surfaces of the fill portions 237a, 237b. Each step is shown as Figure 6 step S47 in the manufacturing method 30 shown.

[0287] Details of the cover layer 141 may be substantially the same as those Figure 1 shown and discussed in, and thus will not be repeated here. After the cover layer 141 is formed, the semiconductor device structure 200a is obtained.

[0288] Figure 19 and Figure 20 are cross-sectional views illustrating intermediate stages of forming a semiconductor device structure 200b according to some embodiments. It should be noted that the formation steps of the semiconductor device structure 200b before the structure Figure 19 shown are the same as thoseFigure 16 The formation steps of the semiconductor device structure 200a shown are substantially the same, and the relevant detailed description can be referred to the foregoing, and will not be repeated here.

[0289] According to some embodiments, as Figure 19 shown, after forming the dielectric liner layer 231, a filling layer 239 is formed over the dielectric liner layer 231. In some embodiments, the gaps 234 and the openings 126' are filled with the filling layer 239. Each step is shown as Figure 6 step S43 in the manufacturing method 30 shown.

[0290] In some embodiments, the filling layer 239 is made of or includes an energy-removable material. The details of the energy-removable material can be substantially the same as those Figure 14 shown and discussed in, and thus will not be repeated here. In some embodiments, the fabrication technique of the filling layer 239 includes a sputtering process. However, any other suitable deposition method can be utilized.

[0291] Next, according to some embodiments, as Figure 20 shown, the filling layer 239 and the dielectric liner layer 231 are partially removed to expose the interconnect structures 119a, 119b, 119c, and 119d (i.e., the second conductive portions 109a, 109b, 109c, and 109d). Each step is shown as Figure 6 step S45 in the manufacturing method 30 shown. After partially removing the filling layer 239 and the dielectric liner layer 231, the dielectric liner portions 231a, 231b, 231c, 231d and the filling portions 239a and 239b are obtained.

[0292] In some embodiments, the dielectric liner portions 231a, 231b and the filling portion 239a are located in the first region A, and the dielectric liner portions 231c, 231d and the filling portion 239b are located in the second region B. In some embodiments, the filling layer 239 and the dielectric liner layer 231 are partially removed by a planarization process, an etch-back process, or a combination thereof. The planarization process can include a CMP process.

[0293] Subsequently, according to some embodiments, as Figure 4As shown, a covering layer 141 is formed over the interconnect structures 119a, 119b, 119c, and 119d. In some embodiments, the covering layer 141 is formed over and in direct contact with the upper surfaces of the interconnect structures 119a, 119b, 119c, 119d (i.e., the upper surfaces of the second conductive portions 109a, 109b, 109c, 109d), the dielectric pad portions 231a, 231b, 231c, 231d, and the filling portions 239a, 239b. Each step is shown as Figure 6 step S45 in the preparation method 30 shown.

[0294] Details of the covering layer 141 can be substantially the same as those Figure 1 shown and discussed therein, and thus will not be repeated here. After the covering layer 141 is formed, the semiconductor element structure 200b can be obtained. In some embodiments, a heat treatment process can be performed to transform the filling portions 239a and 239b into air gaps (not shown in the figures). In some embodiments, the heat treatment process is optional. In some embodiments, the temperature used in the heat treatment process can be high enough to effectively burn off the filling portions 239a and 239b to form air gaps. In some other embodiments, the temperature used in the heat treatment process is selected such that air gaps surrounded or enclosed by the remaining portions of the filled portions are obtained in the first region A and / or the second region B of the semiconductor element structure 200b.

[0295] The present disclosure provides embodiments of a semiconductor element structure and a method for preparing the same. In some embodiments, the semiconductor element structure (e.g., the semiconductor element structure 100a or 100b) includes a first interconnect structure, a second interconnect structure, a first dielectric pad portion disposed adjacent to the first interconnect structure, and a second dielectric pad portion disposed adjacent to the second interconnect structure. The semiconductor element structure further includes a filling portion surrounded by the second dielectric pad portion, and an air gap is enclosed in the first dielectric pad portion, which helps reduce the capacitive coupling between adjacent interconnect structures and can reduce the RC delay. As a result, the performance (e.g., operating speed) and reliability of the semiconductor element structure can be improved.

[0296] In some embodiments, the semiconductor element structure (e.g., semiconductor element structures 200a or 200b) includes a first interconnect structure, a second interconnect structure, a first dielectric pad portion disposed adjacent to the first interconnect structure, and a second dielectric pad portion disposed adjacent to the second interconnect structure. The semiconductor element structure further includes a first fill portion surrounded by the first dielectric pad portion and a second fill portion surrounded by the second dielectric pad portion. The materials of the first fill portion and the second fill portion can be selected to reduce the capacitive coupling between adjacent interconnect structures, and the RC delay can be reduced. As a result, the performance (e.g., operating speed) and reliability of the semiconductor element structure can be improved. In addition, the first fill portion and the second fill portion having different widths can be formed of the same material by the same process steps. Therefore, the manufacturing cost and processing time can be reduced.

[0297] In some embodiments, semiconductor element structures 100a, 100b, 200a, and / or 200b can be integrated into another structure, such as Figure 21 a semiconductor structure 300 with metal plugs shown in FIG. and a semiconductor element 500 with contacts shown in FIG. 42.

[0298] Please refer to Figure 21 . Figure 21 is a schematic diagram of a semiconductor structure 300 according to some embodiments of the present disclosure. In some embodiments, the semiconductor structure 300 includes a memory structure.

[0299] The semiconductor structure 300 includes a substrate 301, a plurality of isolation structures 303, a plurality of word lines 305, an active region 307, a first insulating film 309, a second insulating film 311, a third insulating film 313, a fourth insulating film 315, a contact 317, a bit line contact 319, a first capping layer 321, a bit line 323, a plurality of capacitor contacts 325, a plurality of plugs 327, and a plurality of landing pads 329. As Figure 21 shown, the semiconductor structure 300 further includes a plurality of pad structures 331 and a plurality of air gaps 333 respectively disposed in the plurality of pad structures 331.

[0300] A plurality of isolation structures 303 may be disposed in the substrate 301 and separated from each other. The plurality of isolation structures 303 define the active regions 307. A plurality of word lines 305 may be disposed in the substrate 301 and separated from each other. Each of the plurality of word lines 305 includes a bottom layer 305a, an intermediate layer 305b, and a top layer 305c. The bottom layers 305a may be respectively disposed inwardly in the substrate 301. The intermediate layers 305b may be respectively disposed correspondingly on the bottom layers 305a. An upper surface of the intermediate layers 305b may be lower than an upper surface of the substrate 301. The top layers 305c may be respectively disposed correspondingly on the intermediate layers 305b. An upper surface of the top layer 305c may be in the same vertical plane as the upper surface of the substrate 301.

[0301] The active region 307 may include a first doped region 307a and a plurality of second doped regions 307b. The first doped region 307a is disposed between adjacent pairs of the plurality of word lines 305. The second doped regions 307b are respectively disposed between the plurality of isolation structures 303 and the plurality of word lines 305.

[0302] A first insulating film 309 may be disposed on the substrate 301. The contact 317 is disposed in the first insulating film 309 and electrically connected to the first doped region 307a. The capacitor contacts 325 are respectively disposed on the second doped regions 307b and electrically connected to the second doped regions 307b respectively. In some embodiments, the contact 317 includes tungsten.

[0303] A second insulating film 311 may be disposed on the first insulating film 309. The bit line contact 319 may be disposed in the second insulating film 311. A first capping layer 321 may be disposed in the second insulating film 311 and on an upper surface of the contact 317. The first capping layer 321 is disposed between the bit line contact 319 and the contact 317. Additionally, the first capping layer 321 may be disposed on sidewalls of the bit line contact 319 and attached to the sidewalls of the bit line contact 319. In some embodiments, the first capping layer 321 includes tungsten nitride.

[0304] A third insulating film 313 may be disposed on the second insulating film 311. The bit line 323 may be disposed in the third insulating film 313 and on the bit line contact 319 and the first capping layer 321. A fourth insulating film 315 may be disposed on the third insulating film 313. A plurality of plugs 327 may be provided to penetrate the fourth insulating film 315. The plurality of plugs 327 may be respectively electrically connected to the capacitor contacts 325.

[0305] Each capacitor contact 325 includes a neck portion 325a and a head portion 325b above the neck portion 325a. A width 325bW measured at the widest part of the head portion 325b is greater than a width 325aW of the neck portion 325a. In some embodiments, the head portion 325b has a curved sidewall 325c. In some embodiments, the head portion 325b has a tapered profile.

[0306] Each landing pad 329 includes a first spacer 329a and a second spacer 329b. The first spacer 329a is disposed on a protruding portion 327a of the capacitor plug 327, and the second spacer 329b is disposed on a sidewall of the protruding portion 327a. In some embodiments, a width 329bW of the second spacer 329b is greater than a width 327W of the capacitor plug 327. A topmost surface of the second spacer 329b is higher than an upper surface of the first spacer 329a. In some embodiments, the first spacer 329a includes polysilicon, and the second spacer 329b includes a metal silicide of the polysilicon of the first spacer 329a. In some embodiments, the landing pad 329 is formed above the capacitor contact 325 with the capacitor plug 327, the first spacer 329a, and the second spacer 329b. In some embodiments, the first spacer 329a, the second spacer 329b, and the capacitor plug 327 are collectively referred to as the landing pad 329.

[0307] Each pad structure 331 is disposed in the second insulating film 311 and the third insulating film 313. Additionally, each pad structure 331 is disposed between the capacitor contact 325 and the bit line 323. An air gap 333 is disposed in the pad structure 331 and is surrounded by the pad structure 331.

[0308] In some embodiments, the pad structure 331 and the air gap 333 have a relatively lower dielectric layer than the second insulating film 311 and / or the third insulating film 313. Therefore, the effective capacitance between the capacitor contact 325 and the bit line 323 can be reduced. In other words, the capacitive coupling between the capacitor contact 325 and the adjacent bit line 323 can be reduced, and the RC constant can be reduced.

[0309] It should be noted that the number of the pad structures 331 and the air gaps 333 provided is for illustrative purposes, however, the present disclosure is not limited thereto. Various numbers of the pad structures 331 and the air gaps 333 are within the scope contemplated by the present disclosure.

[0310] In other embodiments, the air gap 333 may not be surrounded by the pad structure 331. In such embodiments, the air gap 333 is exposed to the fourth insulating film 315.

[0311] Please refer to Figures 22 to 41 . Figures 22 to 41is a cross-sectional view illustrating an intermediate stage of forming a semiconductor structure 300 in accordance with some embodiments of the present disclosure.

[0312] In Figure 22 a substrate 301 may be provided. For example, the substrate 301 may include silicon, doped silicon, silicon germanium, silicon on insulator, silicon on sapphire, silicon germanium on insulator, silicon carbide, germanium, gallium arsenide, gallium phosphide, gallium arsenide phosphide, gallium phosphide, or indium gallium phosphide.

[0313] In Figure 23 a plurality of isolation structures 303 may be formed in the substrate 301. The plurality of isolation structures 303 are separated from each other in the cross-sectional view and define active regions 307. For example, the plurality of isolation structures 303 may include an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, fluoride-doped silicate, or the like. In some embodiments, silicon oxynitride refers to a substance containing silicon, nitrogen, and oxygen, where the proportion of oxygen is greater than that of nitrogen. Silicon nitride oxide refers to a substance containing silicon, oxygen, and nitrogen, where the proportion of nitrogen is greater than that of oxygen.

[0314] In Figure 24 a plurality of trench openings 305' may be formed in the substrate 301. A photolithography process may be used to pattern the substrate 301 to define the positions of the plurality of trench openings 305'. An etching process such as an anisotropic dry etching process may be performed to form the plurality of trench openings 305' in the substrate 301.

[0315] In Figure 25 after the etching process, a plurality of bottom layers 305a may be formed accordingly and attached to the sidewalls and bottoms of the plurality of trench openings 305'. For example, the plurality of bottom layers 305a may include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, or the like.

[0316] In Figure 26 a plurality of intermediate layers 305b may be formed accordingly on the plurality of bottom layers 305a. The upper surfaces of the plurality of intermediate layers 305b may be lower than an upper surface of the substrate 301. For example, the plurality of intermediate layers 305b may include doped polysilicon, a metal material, or a metal silicide. For example, the metal silicide may be nickel silicide, platinum silicide, titanium silicide, molybdenum silicide, cobalt silicide, tantalum silicide, tungsten silicide, or the like. A plurality of top layers 305c may be formed accordingly on the plurality of intermediate layers 305b. The upper surfaces of the plurality of top layers 305c may be in the same vertical plane as the upper surface of the substrate 301. For example, the plurality of top layers 305c may include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, or the like.

[0317] In Figure 27In [the structure], a first doped region 307a and a second doped region 307b may be formed in the active region 307 of the substrate 301. The first doped region 307a is disposed between a plurality of adjacent pairs of word lines 305. The second doped regions 307b are respectively disposed between a plurality of isolation structures 303 and the plurality of word lines 305. The first doped region 307a and the second doped region 307b are doped with dopants such as phosphorus, arsenic, or antimony, respectively. The first doped region 307a and the second doped region 307b respectively have a doping concentration ranging from about 1E17 atoms / cm 3 to about 1E19 atoms / cm 3 .

[0318] In Figure 28 , a first insulating film 309 may be formed on the substrate 301. For example, the first insulating film 309 may include silicon nitride, silicon oxide, silicon oxynitride, undoped quartz glass, borosilicate glass, phosphosilicate glass, borophosphosilicate glass, or a combination thereof, but is not limited thereto.

[0319] In Figure 29 , a contact 317 may be formed in the first insulating film 309. A photolithography process may be used to pattern the first insulating film 309 to define the position of the contact 317. An etching process, such as an anisotropic dry etching process, may be performed after the photolithography process to form an opening in the first insulating film 309. After the etching process, a conductive material, such as aluminum, copper, tungsten, cobalt, or other suitable metal or metal alloy, is deposited in the opening by a metallization process, such as chemical vapor deposition, physical vapor deposition, sputtering, or a similar process, to form the contact 317. A planarization process, such as chemical mechanical polishing, may be performed after the metallization process to remove the excess deposited material and provide a substantially flat surface for subsequent processing steps.

[0320] The contact 317 is disposed on the first doped region 307a and is electrically connected to the first doped region 307a. In an embodiment, the contact 317 includes tungsten. When an upper surface of the contact 317 is exposed to oxygen or air, a plurality of defects may easily form on the upper surface of the contact 317 including tungsten. These defects may affect the yield of the semiconductor structure 300.

[0321] A second insulating film 311 may be formed on the first insulating film 309. The second insulating film 311 may include the same material as that of the first insulating film 309, but is not limited thereto. A photolithography process may be used to pattern the second insulating film 311 to define the positions of the bit line contacts 319. An etching process, such as an anisotropic dry etching process, may be performed after the photolithography process to form a bit line contact opening in the second insulating film 311. An upper surface of the contact 317 may be exposed through the bit line contact opening. Optionally, a cleaning process using a reducing agent may be performed to remove defects on the upper surface of the contact 317. The reducing agent may be titanium tetrachloride, tantalum tetrachloride, or a combination thereof.

[0322] After the cleaning process, a first capping layer 321 may be formed to cover the bottom and sidewalls of the bit line contact opening. In some embodiments, the first capping layer 321 includes tungsten nitride. The first capping layer 321 may prevent the upper surface of the contact 317 from being exposed to oxygen or air; thus, the first capping layer 321 may reduce the formation of defects on the upper surface of the contact 317. A conductive material, such as aluminum, copper, tungsten, cobalt, or other suitable metal or metal alloy, is deposited in the bit line contact by a metallization process, such as chemical vapor deposition, physical vapor deposition, sputtering, or a similar process, to form the bit line contact 319. A planarization process, such as chemical mechanical polishing, may be performed after the metallization process to remove the excess deposited material and provide a substantially planar surface for subsequent processing steps.

[0323] In Figure 30 a third insulating film 313 may be formed on the second insulating film 311. The third insulating film 313 may include the same material as that of the first insulating film 309, but is not limited thereto. A photolithography process may be used to pattern the third insulating film 313 to define the positions of the bit lines 323. An etching process, such as an anisotropic dry etching process, may be performed after the photolithography process to form bit line trench openings 323' in the third insulating film 313. In some embodiments, the photolithography process may also pattern the third insulating film 313 to define the positions of a plurality of contact holes 325', and an etching process may be performed to form the plurality of contact holes 325' to penetrate the third insulating film 313, the second insulating film 311, and the first insulating film 309. In other words, the contact holes 325' are considered deep holes, while the bit line trench openings 323' are considered relatively shallow holes.

[0324] In Figure 31In [the structure], the bit line trench openings 323' and the contact holes 325' can be filled with materials by processes such as chemical vapor deposition, physical vapor deposition, sputtering, or similar processes. In some embodiments, the contact holes 325' are deeper than the bit line trench openings 323', and the bit line trench openings 323' can be completely filled with the filling material 323-1, while the contact holes 325' can be partially filled with the filling material 325-1, and the filling material 325-1 can be the same as the filling material 323-1. In some embodiments, the upper part of the contact holes 325' in the third insulating film 313 is not filled with the filling material 325-1.

[0325] In Figure 32 [the structure], an etching process such as an isotropic etching process can be performed to remove a part of the third insulating film 313 around the contact holes 325' to form a plurality of via holes 325", which have a narrow part 325"-1 occupied by the filling material 325-1 in the second insulating film 311 and a wide part 325"-2 in the third insulating film 313.

[0326] In Figure 33 [the structure], the filling material 325-1 and the filling material 323-1 are respectively stripped from the via holes 325" and the bit line trench openings 323'. After stripping the filling materials, a conductive material such as aluminum, copper, tungsten, cobalt, or other suitable metal or metal alloy is deposited in the plurality of bit line trench openings 323' by a metallization process such as chemical vapor deposition, physical vapor deposition, sputtering, or similar processes to form the bit lines 323 and in the via holes 325" to form a plurality of capacitor contacts 325. A planarization process, such as chemical mechanical polishing, can be performed after the metallization process to remove the excess deposited material and provide a substantially flat surface for subsequent processing steps.

[0327] The capacitor contacts 325 include a neck 325a and a head 325b above the neck 325a. In some embodiments, the head 325b has a curved sidewall 325c. In some embodiments, the head 325b has a tapered profile.

[0328] In Figure 34 [the structure], a patterned mask 401 having a plurality of openings 403 is formed on the third insulating film 313. The third insulating film 313 is partially exposed through the openings 403. In some embodiments, the third insulating film 313 and the patterned mask 401 include different materials, such that the etching selectivity can be different in subsequent etching processes.

[0329] In Figure 35Therein, a patterned mask 401 is used as an etching mask to perform an etching process so as to form a plurality of openings 405 to penetrate through the second insulating film 311 and the third insulating film 313. The first insulating film 309 is partially exposed through the openings 405. In some embodiments, the etching process for forming the openings 405 includes a wet etching process, a dry etching process, or a combination thereof.

[0330] In Figure 36 therein, the patterned mask 401 is removed. In some embodiments, the patterned mask 401 is removed by a lift-off process, an ashing process, an etching process, or other suitable processes. After removing the patterned mask 401, the upper surface of the third insulating film 313, the head 325b of the capacitor contact 325, and the bit line 323 are exposed.

[0331] In Figure 37 therein, a dielectric liner layer 407 is conformally formed in the openings 405 and above the upper surface of the third insulating film 313, the head 325b of the capacitor contact 325, and the bit line 323.

[0332] In some embodiments, a thickness 407T of the dielectric liner layer 407 is adjusted such that an air gap 333 is enclosed in a portion of the dielectric liner layer 407 that fills the openings 405. In some embodiments, a width 405W of the openings 405 is less than twice the thickness 407T of the dielectric liner layer 407.

[0333] Furthermore, in some embodiments, the dielectric liner layer 407 is made of or includes boron carbonitride (BCN). However, any other suitable dielectric material can be utilized. The fabrication technique of the dielectric liner layer 407 can include a deposition process such as a CVD process, a PVD process, an ALD process, a spin coating process, or other suitable methods. In some embodiments, the air gap 333 is enclosed (or sealed) in the portion of the dielectric liner layer 407 that fills the openings 405.

[0334] In Figure 38 therein, a portion of the dielectric liner layer 407 is removed to form a liner structure 331. In some embodiments, the dielectric liner layer 407 is removed by a planarization process, an etch-back process, or a combination thereof. The planarization process can include a chemical mechanical polishing (CMP) process. It should be understood that the air gap 333 does not protrude from the upper surface of the third insulating film 313. Thus, after the planarization process and / or the etch-back process, the air gap 333 is still enclosed (or sealed) by the liner structure 331.

[0335] In Figure 39In [the structure], a fourth insulating film 315 may be formed on the third insulating film 313. The fourth insulating film 315 may include the same material as that of the first insulating film 309, but is not limited thereto. A photolithography process may be used to pattern the fourth insulating film 315 to define the positions of a plurality of capacitor plugs 327.

[0336] After the photolithography process, an etching process, such as an anisotropic dry etching process, may be performed to form a plurality of plug openings through the fourth insulating film 315 to expose the heads 325b. After the etching process, a conductive material, such as aluminum, copper, tungsten, cobalt, or other suitable metal or metal alloy, is deposited in the plurality of plug openings by a metallization process, such as chemical vapor deposition, physical vapor deposition, sputtering, or a similar process, to form a plurality of capacitor plugs 327 above the heads 325b. In some embodiments, a plurality of barrier layers 341 may be respectively disposed between the capacitor plugs 327 and the fourth insulating film 315. A planarization process, such as chemical mechanical polishing, may be performed after the metallization process to remove the excess deposited material and provide a substantially flat surface for subsequent processing steps.

[0337] In Figure 40 [the structure], a re-etch process is performed to remove a top portion of the fourth insulating film 315 to expose a protruding portion 327a of the capacitor plug 327 and a top portion 341a of the barrier layer 341. In some embodiments, after the re-etch process, the upper surface of the capacitor plug 327 is higher than the upper surface of the fourth insulating film 315, and the sidewalls of the exposed top portion 341a are exposed.

[0338] In Figure 41 [the structure], a deposition process is performed to form a liner layer 329', which covers the upper surface of the fourth insulating film 315, the upper surface of the protruding portion 327a, the upper surface of the top portion 341a, and the sidewalls of the top portion 341a. In some embodiments, the liner layer 329' is a silicon-containing layer, such as a polysilicon layer.

[0339] After depositing the liner layer 329', a heat treatment is performed to form a plurality of landing pads 329 above the fourth insulating film 315. Each landing pad 329 includes a first spacer (metal silicide) 329a above the capacitor plug 327, the barrier layer 341, and the protruding portion 327a, and a second spacer (metal silicide) 329b on the sidewalls of the top portion 341a. In some embodiments, the heat treatment is a silicidation process.

[0340] The heat treatment transforms a protruding portion 327a and a part of the liner layer 329' into a first spacer 329a, and transforms a top 341a of the barrier layer 341 and the liner layer 329' into a second spacer 329b. Based on the above heat treatment, photolithography technology is not used to form the landing pad 329, that is, the landing pad 329 is self-aligned with the capacitor plug 327. In some embodiments, the thickness and shape of the protruding portion 327a and the top 341a can be changed after the heat treatment ( Figure 21 not shown in

[0341] After the heat treatment, a semiconductor structure 300 is formed.

[0342] Please refer to Figure 42a and Figure 42b . Figure 42a is a schematic diagram of a semiconductor element 500 according to some embodiments of the present disclosure. Figure 42b is a partially enlarged view of a semiconductor element 500 according to some embodiments of the present disclosure. In some embodiments, the semiconductor element 500 includes a memory structure, such as a dynamic random access memory (DRAM). The semiconductor element 500 includes a first dielectric layer 503, a metal plug 519a, a metal plug 519b, and a metal plug 519c disposed above a semiconductor substrate 501.

[0343] The semiconductor element 500 includes a first dielectric layer 503, a metal plug 519a, a metal plug 519b, and a metal plug 519c disposed above a semiconductor substrate 501. In addition, in some embodiments, an etch stop layer 505 is disposed above the first dielectric layer 503, and the metal plugs 519a, 519b, and 519c protrude from the etch stop layer 505.

[0344] It should be understood that although Figure 42a only three first metal plugs are shown, the present disclosure is not limited thereto. According to product requirements, the number of first metal plugs in the semiconductor element 500 can be less than or more than three. Please refer to Figure 42b , the first metal plug 519a has an upper portion 519a1 protruding from an upper surface 505T of the etch stop layer 505 and a lower portion 519a2 below the upper portion 519a1.

[0345] In some embodiments, the first metal plug 519a, the first metal plug 519b, and the first metal plug 519c are the same. It should be understood that the following disclosure related to the first metal plug 519a can be applied to the first metal plug 519b and the first metal plug 519c.

[0346] In some embodiments, the etch stop layer 505 and the first dielectric layer 503 surround the lower portion 519a2 of the first metal plug 519a, and the upper portion 519a1 of the first metal plug 519a has a circular (or curved) upper surface TS. In some embodiments, the etch stop layer 505 and the first dielectric layer 503 are adjacent to the sidewalls of the lower portion 519a2. In some embodiments, the upper surface TS of the upper portion 519a1 is convex, and the upper surface TS connects a first sidewall SW1 of the upper portion 519a1 to a second sidewall SW2 of the upper portion 519a1.

[0347] In addition, the semiconductor device 500 includes a second metal plug 537a, a second metal plug 537b, and a second metal plug 537c disposed above the first metal plug 519a, the first metal plug 519b, and the first metal plug 519c, respectively. The semiconductor device 500 further includes a second dielectric layer 507 and a third dielectric layer 523. The second dielectric layer 507 is disposed above the etch stop layer 505, and the third dielectric layer 523 is disposed above the second dielectric layer 507. The semiconductor device 500 further includes a silicide layer 521a, a silicide layer 521b, and a silicide layer 521c. The silicide layer 521a is disposed between the first metal plug 519a and the second metal plug 537a; the silicide layer 521b is disposed between the first metal plug 519b and the second metal plug 537b; and the silicide layer 521c is disposed between the first metal plug 519c and the second metal plug 537c.

[0348] By forming the silicide layers 521a, 521b, and 521c, the contact resistance between the first metal plugs (e.g., 519a, 519b, 519c) and the second metal plugs (e.g., 537a, 537b, 537c) can be reduced, thereby improving the performance of the semiconductor device 500. However, in some other embodiments, the silicide layers 521a, 521b, 521c may be omitted.

[0349] The second metal plug 537a extends to contact the upper surface 505T of the etch stop layer 505. In some embodiments, the first sidewall SW1 of the upper portion 519a1 is in direct contact with the second metal plug 537a, and the second sidewall SW2 of the upper portion 519a1 is in direct contact with the second dielectric layer 507.

[0350] The second dielectric layer 507 is separated from the first sidewall SW1. A height H1 of the first sidewall SW1 is substantially the same as a height H2 of the second dielectric layer 507. In the context of the present disclosure, the term "substantially" means preferably at least 90%, more preferably 95%, even more preferably 98%, and most preferably 99%.

[0351] More specifically, the upper surface TS of the upper part 519a1 has a highest point TP, and the highest point TP is higher than the upper surface 507T of the second dielectric layer 507. That is to say, the upper part 519a1 protrudes from the upper surface 507T of the second dielectric layer 507.

[0352] In addition, the upper surface TS of the upper part 519a1 is separated from the second metal plug 537a by a silicide layer 521a, and the silicide layer 521a extends between the upper surface TS and the third dielectric layer 523. A part of the silicide layer 521a is exposed in the third dielectric layer 523 and is in direct contact with the third dielectric layer 523. In other words, a part of the third dielectric layer 523 is disposed above the upper part 519a1.

[0353] The second metal plug 537a is separated from the second dielectric layer 507 by an air gap 536a1 and an air gap 536a2; the second metal plug 537b is separated from the second dielectric layer 507 by an air gap 536b1 and an air gap 536b2; and the second metal plug 537c is separated from the second dielectric layer 507 via an air gap 536c1 and an air gap 536c2.

[0354] By forming the air gaps 536a1, 536a2, 536b1, 536b2, 536c1 and 536c2, the parasitic capacitance between adjacent second metal plugs can be reduced, thereby improving the operating speed of the semiconductor element 500. However, in some embodiments, the air gaps 536a1, 536a2, 536b1, 536b2, 536c1 and 536c2 can be omitted.

[0355] The semiconductor element 500 further includes a bit line 550a, a bit line 550b, a bit line 550c and a fourth dielectric layer 539. The bit lines 550a, 550b and 550c are disposed above the second metal plugs 537a, 537b and 537c and are electrically connected to the second metal plugs 537a, 537b and 537c, and the bit lines 550a, 550b and 550c are also electrically connected to the first metal plugs 519a, 519b and 519c through the second metal plugs 537a, 537b and 537c. The fourth dielectric layer 539 surrounds the bit lines 550a, 550b and 550c.

[0356] In semiconductor device 500, since the first metal plugs 519a, 519b, and 519c have circular upper surfaces, the contact area between the first metal plugs 519a, 519b, 519c and the second metal plugs 537a, 537b, 537c is increased compared to a configuration in which the first metal plugs have flat upper surfaces and the second metal plugs are perfectly aligned with the first metal plugs. The circular upper surfaces of the first metal plugs 519a, 519b, and 519c can cause the resistance values between the first metal plugs 519a, 519b, 519c and the second metal plugs 537a, 537b, 537c to decrease correspondingly, thereby improving the overall device performance.

[0357] In addition, since the first metal plugs 519a, 519b, and 519c do not have sharp portions, the electric field intensity on the circular upper surfaces of the first metal plugs 519a, 519b, and 519c is evenly distributed. Therefore, the lifespan of the semiconductor device 500 can be significantly extended, and the performance and reliability of the device can be improved. In addition, since the etch stop layer 505 is adjacent to the sidewalls of the first metal plugs 519a, 519b, and 519c, the underlying electronic components can be prevented from being exposed during the process of forming the second metal plugs 537a, 537b, and 537c, and the problems caused by misalignment between the first metal plugs 519a, 519b, 519c and the second metal plugs 537a, 537b, 537c can be prevented or reduced.

[0358] In addition, the semiconductor device 500 further includes a pad structure 560a and a pad structure 560b. The pad structure 560a is disposed between the second metal plug 537a and the second metal plug 537b, and the pad structure 560b is disposed between the second metal plug 537b and the second metal plug 537c.

[0359] As Figure 42a and Figure 42b shown, the semiconductor device 500 includes an air gap 565a and an air gap 565b respectively surrounded by the pad structure 560a and the pad structure 560b. The pad structures 560a and 560b extend from the upper surface 505T of the fourth dielectric layer 539 to the lower surface. The pad structures 560a and 560b do not contact the bit lines 550a, 550b, and 550c. In other words, the pad structures 560a and 560b penetrate through the entire second dielectric layer 507 and the entire third dielectric layer 523.

[0360] In various embodiments, the pad structure 560b and the air gap 565b can be omitted.

[0361] By forming the liner structures 560a, the liner structures 560b, the air gaps 565a, and the air gaps 565b, the parasitic capacitance between adjacent second metal plugs can be reduced, thereby improving the operating speed of the semiconductor device 500.

[0362] Please refer to Figures 43 to 61 。 Figures 43 to 61 is a cross-sectional view illustrating an intermediate stage of forming a semiconductor device 500 in accordance with some embodiments of the present disclosure.

[0363] In Figure 43 , a semiconductor substrate 501 is provided. The semiconductor substrate 501 may be part of an integrated circuit (IC) chip that includes various passive and active microelectronic components, such as resistors, capacitors, inductors, diodes, p-type field effect transistors (pFETs), n-type field effect transistors (nFETs), metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused MOS (LDMOS) transistors, high-voltage transistors, high-frequency transistors, fin field effect transistors (FinFETs), other suitable IC components, or combinations thereof.

[0364] Depending on the IC manufacturing stage, the semiconductor substrate 501 may include features configured to form IC features (e.g., doped regions, isolation features, gate features, source / drain features, interconnect features, other features, or combinations thereof). For clarity, the semiconductor substrate 501 has been simplified. It should be understood that additional features may be added to the semiconductor substrate 501, and some of the features described below may be replaced, modified, or eliminated in other embodiments.

[0365] A first dielectric layer 503, an etch stop layer 505, and a second dielectric layer 507 are sequentially disposed over the semiconductor substrate 501.

[0366] The material of the first dielectric layer 503 includes silicon oxide, silicon carbide, silicon nitride, silicon oxynitride, other suitable materials, or combinations thereof, and the fabrication technique of the first dielectric layer 503 includes a deposition process, such as a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, a spin coating process, or other suitable processes.

[0367] Some of the materials and processes used to form the etch stop layer 505 and the second dielectric layer 507 are similar or the same as those used to form the first dielectric layer 503, and are not described herein again. It should be understood that, according to some embodiments, the material of the etch stop layer 505 is different from the material of the second dielectric layer 507.

[0368] After forming the second dielectric layer 507, a photoresist pattern 509 having a plurality of openings 512 is disposed over the second dielectric layer 507, and the openings 512 expose the second dielectric layer 507. In some embodiments, the fabrication technique of the photoresist pattern 509 may include a deposition process and a patterning process.

[0369] The deposition process for forming the photoresist pattern 509 may include a CVD process, a high density plasma chemical vapor deposition (HDPCVD) process, a spin coating process, or other suitable processes. The patterning process for forming the photoresist pattern 509 may include a photolithography process. The photolithography process may include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, and drying (e.g., hard baking).

[0370] In Figure 44 this step, an etching process is performed on the semiconductor substrate 501 using the photoresist pattern 509 as a mask. The etching process is performed until the upper surface 501T of the semiconductor substrate 501 is exposed, and a plurality of openings 514 are formed below the openings 512.

[0371] The openings 514 are surrounded by the remaining second dielectric layer 507, the remaining etch stop layer 505, and the remaining first dielectric layer 503. The etching process may be a dry etching process, a wet etching process, or a combination thereof.

[0372] In Figure 45 this step, a metal layer 517 is deposited to fill the openings 514 and the openings 512. The metal layer 517 also extends onto the photoresist pattern 509.

[0373] In some embodiments, the metal layer 517 includes copper (Cu). In some other embodiments, the metal layer 517 includes tungsten (W), cobalt (Co), titanium (Ti), aluminum (Al), tantalum (Ta), or other suitable materials. Additionally, in some embodiments, the fabrication technique of the metal layer 517 includes a CVD process, a PVD process, an ALD process, a plating (e.g., electroplating) process, a sputtering process, or other suitable processes.

[0374] In Figure 46 this step, a portion of the metal layer 517 on the photoresist pattern 509 is removed to form a metal portion 517a, a metal portion 517b, and a metal portion 517c. More specifically, according to some embodiments, the portions of the metal layer 517 covering the photoresist pattern 509 are removed, and the portions of the metal layer 517 deposited into the openings 512 and 514 are retained.

[0375] In some embodiments, an excess portion of the metal layer 517 is removed by a planarization process or an etching process. The planarization process may be a chemical mechanical polishing (CMP) process.

[0376] In Figure 47 , the photoresist pattern 509 is removed. In some embodiments, during the removal process of the photoresist pattern 509, a portion of the metal portions 517a, 517b, 517c protruding from an upper surface 507T of the second dielectric layer 507 is slightly etched, and first metal plugs 519a, 519b, 519c (i.e., the remaining metal portions 517a, 517b, 517c) are obtained.

[0377] Specifically, according to some embodiments, each of the first metal plugs 519a, 519b, 519c penetrates the second dielectric layer 507, the etch stop layer 505, and the first dielectric layer 503 to electrically connect to an electronic component in the semiconductor substrate 501.

[0378] In Figure 48 , an anisotropic etching process is performed to partially remove the first metal plug 519a, the first metal plug 519b, and the first metal plug 519c, such that each etched first metal plug 519a, 519b, and 519c has a circular (or curved) upper surface TS. In some embodiments, the upper surface TS is a convex surface.

[0379] As described above, the highest point TP of the upper surface TS is higher than the upper surface 507T of the second dielectric layer 507. More specifically, an edge E of the upper surface TS is in direct contact with the upper surface 507T of the second dielectric layer 507. In some embodiments, the anisotropic etching process is a dry etching process.

[0380] In Figure 49 , silicide layers 521a, 521b, and 521c are disposed above the first metal plugs 519a, the first metal plugs 519b, and the first metal plugs 519c by a silicidation process. In some embodiments, the silicidation process includes a metal material deposition process and an annealing process performed in sequence. In some embodiments, the deposition process of the silicidation process includes a PVD process, an ALD process, or other suitable processes. After the annealing process, the unreacted metal material is removed.

[0381] In some embodiments, the silicide layers 521a, 521b, and 521c include one or more of copper silicide, tungsten silicide, cobalt silicide, titanium silicide, nickel silicide, and molybdenum silicide. As described above, by forming the silicide layers 521a, 521b, and 521c, the contact resistance between the first metal plugs (e.g., 519a, 519b, and 519c) and the upper conductive components (e.g., the second metal plugs 537a, 537b, and 537c shown in FIG. 42) can be reduced, thereby improving the performance of the device. In some other embodiments, the silicidation process is not performed and the silicide layers 521a, 521b, and 521c can be omitted.

[0382] In Figure 50 it, a third dielectric layer 523 is formed to cover the second dielectric layer 507 and the silicide layers 521a, 521b, and 521c. The upper surface TS is separated from the third dielectric layer 523 via the silicide layers 521a, 521b, and 521c. Some of the materials and processes for forming the third dielectric layer 523 are similar to or the same as those for forming the first dielectric layer 503, and will not be described again here. In some embodiments, the material of the third dielectric layer 523 is different from the material of the etch stop layer 505.

[0383] In Figure 51 it, a photoresist pattern 525 having a plurality of openings 528 is disposed above the third dielectric layer 523, and the third dielectric layer 523 is exposed through the openings 528. Some of the materials and processes for forming the photoresist pattern 525 are similar to or the same as those for forming the photoresist pattern 509, and will not be described again here.

[0384] In Figure 52 it, the photoresist pattern 525 is used as a mask to perform an etching process on the structure. The etching process is performed until the silicide layers 521a, 521b, and 521c or the first metal plugs 519a, 519b, and 519c are exposed. A plurality of openings 530 are formed in the remaining third dielectric layer 523, and a plurality of gaps 532 are formed in the remaining second dielectric layer 507. Additionally, the etching process can be a dry etching process, a wet etching process, or a combination thereof.

[0385] In some embodiments, the positions of the openings 518 above the second dielectric layer 507 cause some portions of the second dielectric layer 507 to be exposed during the etching process for the openings 530, and the exposed portions of the second dielectric layer 507 are removed to form the gaps 532. According to some embodiments, the upper surface 505T of the etch stop layer 505 is exposed through the gaps 532. As described above, the etch stop layer 505 can protect the underlying electronic components from being exposed during the etching process.

[0386] In addition, each of the first metal plugs 519a, 519b, and 519c has a first sidewall SW1 and a second sidewall SW2 opposite to the first sidewall SW1. In some embodiments, the first sidewall SW1 is exposed through the gap 532, while the second sidewall SW2 is still covered by the second dielectric layer 507. In some embodiments, after forming the openings 530 and the gaps 532, some portions of the silicide layers 521a, 521b, and 521c are sandwiched between the third dielectric layer 523 and the corresponding first metal plugs.

[0387] In Figure 53 it, an energy-removable material 535 is disposed above the sidewalls of the openings 518, the sidewalls of the openings 530, and the sidewalls of the gaps 532. Since the energy-removable material 535 occupies a part of the openings 528 and the openings 530, the space of the openings 528 and the openings 530 is reduced.

[0388] In some embodiments, the energy-removable material 535 includes a thermally decomposable material. In some other embodiments, the energy-removable material 535 includes a photon-decomposable material, an electron-beam-decomposable material, or other suitable energy-decomposable materials. Specifically, in some embodiments, the energy-removable material 535 includes a base material and a decomposable pore-forming agent material that is substantially removed once exposed to an energy source (such as heat).

[0389] In some embodiments, the base material may include hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), porous polyarylether (PAE), porous SiLK, or porous silicon dioxide (SiO2), and the decomposable pore-forming agent material may include a pore-forming organic compound, which can provide porosity for the space originally occupied by the energy-removable material 535 in subsequent processes.

[0390] In some embodiments, the fabrication technique of the energy-removable material 535 includes a deposition process and an etching process. In some embodiments, the deposition process includes CVD, PVD, ALD, spin coating, or other suitable processes, and the etching process includes a reactive ion etching (RIE) process for removing the excess portion above the photoresist pattern 525.

[0391] In Figure 54 it, the openings 518, the openings 530, and the gaps 532 are filled with a metal layer 537, and the metal layer 537 extends onto the photoresist pattern 525. The metal layer 537 is then in direct contact with the first metal plugs 519a, 519b, 519c, and the etch stop layer 505.

[0392] In some embodiments, the metal layer 537 includes copper (Cu). In some other embodiments, the metal layer 537 includes tungsten (W), cobalt (Co), titanium (Ti), aluminum (Al), tantalum (Ta), or other suitable materials. Additionally, in some embodiments, the fabrication techniques for the metal layer 537 include CVD processes, PVD processes, ALD processes, plating (e.g., electroplating) processes, sputtering processes, or other suitable processes.

[0393] In Figure 55 , a planarization process is performed to remove the photoresist pattern 525, the excess portions of the metal layer 537, and the energy-removable material 535 above the third dielectric layer 523. The planarization process can be a CMP process.

[0394] In Figure 56 , a patterned mask 601 having a plurality of openings 603 is formed over the third dielectric layer 523, the metal layer 537, and the energy-removable material 535. The third dielectric layer 523 is partially exposed through the openings 603. In some embodiments, the third dielectric layer 523 and the patterned mask 601 include different materials such that the etch selectivity can be different in subsequent etching processes.

[0395] In Figure 57 , the patterned mask 601 is used as an etch mask to perform an etching process to form a plurality of openings 605 that penetrate the third dielectric layer 523 and the second dielectric layer 507. The etch stop layer 505 is partially exposed through the openings 605. In some embodiments, the etching process for forming the openings 605 includes a wet etching process, a dry etching process, or a combination thereof.

[0396] In Figure 58 , the patterned mask 601 is removed. In some embodiments, the patterned mask 601 is removed by a lift-off process, an ashing process, an etching process, or other suitable processes. After removing the patterned mask 601, the upper surfaces of the third dielectric layer 523, the metal layer 537, and the energy-removable material 535 are exposed.

[0397] In Figure 59 , a dielectric liner layer 607 is conformally formed in the openings 605 and over the upper surfaces of the etch stop layer 505, the third dielectric layer 523, the metal layer 537, and the energy-removable material 535.

[0398] In some embodiments, a thickness 607T of the dielectric liner layer 607 is adjusted such that an air gap 565a and an air gap 565b are enclosed in the respective portions of the dielectric liner layer 607 filling the openings 605. In some embodiments, a width 605W of the openings 605 is less than twice the thickness 607T of the dielectric liner layer 607.

[0399] In addition, in some embodiments, the dielectric liner layer 607 is made of or includes boron carbonitride (BCN). However, any other suitable dielectric material may be utilized. Fabrication techniques for the dielectric liner layer 607 may include a deposition process such as a CVD process, a PVD process, an ALD process, a spin coating process, or other suitable methods. In some embodiments, the air gaps 565a and 565b are enclosed (or sealed) in respective portions of the dielectric liner layer 607 that fill the openings 605. In other words, the air gaps 565a and 565b are not exposed.

[0400] In Figure 60 , the dielectric liner layer 607 is partially removed to become a liner structure 560a and a liner structure 560b. In some embodiments, the dielectric liner layer 607 is removed by a planarization process, an etch-back process, or a combination thereof. The planarization process may include a chemical mechanical polishing (CMP) process. It should be understood that the air gaps 565a and 565b do not protrude from the upper surface of the third dielectric layer 523, and thus, after the planarization process and / or the etch-back process, the air gaps 565a and 565b are still enclosed (or sealed) by the liner structures 560a and 560b, respectively.

[0401] In Figure 61 , a fourth dielectric layer 539 is formed to cover the third dielectric layer 523, the energy-removable material 535, the second metal plugs 537a, 537b, 537c, the liner structure 560a, and the liner structure 560b. Some of the materials and processes for forming the fourth dielectric layer 539 are similar to or the same as those for forming the first dielectric layer 103, and thus will not be described again here.

[0402] After forming the fourth dielectric layer 539, bit lines 550a, 550b, and 550c are formed in the fourth dielectric layer 539. In some embodiments, the bit lines 550a, 550b, and 550c are formed by a lithography process for defining a plurality of bit line positions, a deposition process for depositing materials for forming the plurality of bit lines at the positions defined by the lithography process, and a CMP process for planarizing the upper surfaces of the bit lines 550a, 550b, and 550c.

[0403] After forming the bit lines 550a, 550b, and 550c, a heat treatment is used to remove the decomposable pore-forming agent material of the energy-removable material 535 to generate a plurality of pores, and the pores are filled with air such that air gaps 536a1, 536a2, 536b1, 536b2, 536c1, 536c2 are obtained between the second metal plugs 537a, 537b, 537c and the third dielectric layer 523, as Figure 42a shown.

[0404] In some other embodiments, the heat treatment process may be replaced by a light treatment process, an electron beam treatment process, a combination thereof, or other suitable energy treatment processes. For example, ultraviolet (UV) light or a laser may be used to remove the decomposable pore-forming material of the energy-removable material 535 to obtain air gaps 536a1, 536a2, 536b1, 536b2, 536c1, 536c2.

[0405] As described above, since the dielectric constant of air is relatively low, the parasitic capacitance in the second metal plugs 537a, 537b, 537c can be reduced by applying air gaps (such as air gaps 536a1, 536a2, 536b1, 536b2, 536c1, 536c2, 565a, and 565b) to the semiconductor element 500, thereby improving the operating speed of the semiconductor element 500. In some other embodiments, the energy-removable material 535 and the air gaps 536a1, 536a2, 536b1, 536b2, 536c1, 536c2 are not formed. In these cases, the second metal plugs 537a, 537b, 537c may be in direct contact with the third dielectric layer 523.

[0406] Since the first metal plugs 519a, 519b, and 519c have a circular (or curved) upper surface TS, the contact area between the first metal plugs 519a, 519b, 519c and the second metal plugs 537a, 537b, 537c (or the contact area between the silicide layers 521a, 521b, 521c and the second metal plugs 537a, 537b, 537c) is increased compared to a configuration where the first metal plugs have a flat upper surface and the second metal plugs are perfectly aligned with the first metal plugs. The increased contact area of the circular upper surface TS can result in a corresponding reduction in the resistance value between the first metal plugs 519a, 519b, 519c and the second metal plugs 537a, 537b, 537c, thus improving the overall performance of the component.

[0407] Furthermore, since the first metal plugs 519a, 519b, 519c do not have sharp portions, the electric field intensity is uniformly distributed on the circular upper surface TS of the first metal plugs 519a, 519b, 519c. Therefore, the lifespan of the semiconductor element 500 can be significantly extended, and the performance and reliability of the component can be improved.

[0408] In addition, since the etch stop layer 505 is adjacent to the sidewalls of the first metal plugs 519a, 519b, 519c, the underlying electronic components can be prevented from being exposed during the process of forming the second metal plugs 537a, 537b, 537c, and problems caused by misalignment between the first metal plugs 519a, 519b, 519c and the second metal plugs 537a, 537b, 537c can be prevented or reduced.

[0409] One embodiment of the present disclosure provides a semiconductor device, including a substrate, a contact, a landing pad, a bit line, and an air gap. The contact is disposed above the substrate. The landing pad is disposed above the contact. The landing pad includes a plug, a first spacer, and a second spacer. The plug is disposed above the contact and in contact with the contact. The first spacer is disposed above the plug. The second spacer clamps a protruding portion of the plug. The bit line is disposed above the substrate. The air gap is disposed between the contact and the bit line.

[0410] Another embodiment of the present disclosure provides a semiconductor device, including a substrate, an etch stop layer, a first lower plug, a second lower plug, a first upper plug, a second upper plug, and an air gap. The etch stop layer is disposed above the substrate. The first lower plug and the second lower plug are disposed above the substrate and protrude from an upper surface of the etch stop layer. The first upper plug and the second upper plug are respectively disposed above the first lower plug and the second lower plug. The air gap is disposed between the first upper plug and the second upper plug. An upper surface of the first lower plug is circular. The first upper plug is in contact with a first sidewall of the first lower plug.

[0411] Another embodiment of the present disclosure provides a method for manufacturing a semiconductor device, including providing a substrate; forming a contact above the substrate; forming a bit line above the substrate; forming a liner structure to enclose an air gap, wherein the liner structure is formed between the contact and the bit line; and forming a landing pad above the contact, including: forming a barrier layer; forming a plug to contact the contact; and forming a first spacer and a second spacer above the plug. The first spacer is disposed above the plug, and the second spacer clamps a protruding portion of the plug.

[0412] Embodiments of the present disclosure have some advantageous features. In some embodiments, a semiconductor device structure includes a first dielectric pad portion and a second dielectric pad portion disposed adjacent to a first interconnect structure and a second interconnect structure, respectively. The semiconductor device structure also includes a filling portion surrounded by the second dielectric pad portion, and an air gap enclosed within the first dielectric pad portion, which helps to reduce capacitive coupling between adjacent interconnect structures and can reduce resistance-capacitance (RC) delay. As a result, the performance and reliability of the semiconductor device structure can be improved.

[0413] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alterations can be made without departing from the spirit and scope of the present disclosure as defined by the claims. For example, many of the processes described above can be implemented in different ways, and many of the processes described above can be replaced by other processes or combinations thereof.

[0414] Furthermore, the scope of the present application is not limited to the specific embodiments of the processes, machines, manufactures, compositions of matter, means, methods, and steps described in the specification. Those skilled in the art can understand from the disclosure of the present disclosure that existing or future-developed processes, machines, manufactures, compositions of matter, means, methods, or steps that perform the same function or achieve substantially the same result as the corresponding embodiments described herein can be used in accordance with the present disclosure. Accordingly, these processes, machines, manufactures, compositions of matter, means, methods, or steps are included within the scope of the claims of the present application.

Claims

1. A semiconductor device, comprising: a substrate; an etch stop layer disposed over the substrate; a first lower plug and a second lower plug disposed over the substrate and protruding from an upper surface of the etch stop layer; a first upper plug and a second upper plug respectively disposed over the first lower plug and the second lower plug; an air gap disposed between the first upper plug and the second upper plug; and a pad structure disposed between the first upper plug and the second upper plug, wherein the pad structure encloses the air gap, wherein an upper surface of the first lower plug is circular, wherein the first upper plug contacts a first sidewall of the first lower plug.

2. The semiconductor device according to claim 1, wherein the first upper plug further contacts the etch stop layer.

3. The semiconductor device according to claim 1, further comprising: a first dielectric layer disposed over the substrate, wherein the etch stop layer is disposed over the first dielectric layer; a second dielectric layer disposed over the etch stop layer; and a third dielectric layer disposed over the second dielectric layer.

4. The semiconductor device according to claim 3, wherein a second sidewall of the first lower plug contacts the second dielectric layer.

5. The semiconductor device according to claim 4, wherein a height of the first sidewall of the first lower plug is substantially the same as a height of the second sidewall of the first lower plug.

6. The semiconductor device according to claim 3, wherein the first sidewall of the first lower plug is spaced apart from the second dielectric layer.

7. The semiconductor device according to claim 3, wherein the third dielectric layer partially covers the first lower plug.

8. The semiconductor device according to claim 3, further comprising: a first metal silicide layer disposed on the first lower plug; and a second metal silicide layer disposed on the second lower plug.

9. The semiconductor device according to claim 8, wherein the first upper plug contacts the first metal silicide layer, and the second upper plug contacts the second metal silicide layer.

10. The semiconductor device according to claim 8, wherein the first metal silicide layer and the second metal silicide layer contact the third dielectric layer.

11. The semiconductor device according to claim 1, further comprising: a fourth dielectric layer disposed over the first upper plug, the second upper plug and the pad structure; and a first bit line and a second bit line disposed in the fourth dielectric layer, wherein the first bit line and the second bit line are respectively disposed over the first upper plug and the second upper plug.

12. The semiconductor device according to claim 11, wherein the pad structure does not contact the first bit line, and the pad structure does not contact the second bit line.

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