Semiconductor device and method of manufacturing the same
By forming a free layer of gap wall covering on the opposite side walls of the bit line, the damage and redeposition contamination of the barrier layer by ion beam etching is solved, and the performance of semiconductor devices is ensured, and it is suitable for small-sized and high-performance electronic devices.
Patent Information
- Application Number
- CN202410162065.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-01-24
- Filing Date
- 2024-02-05
- Publication Date
- 2025-07-29
AI Technical Summary
In the existing MRAM manufacturing process, damage to the barrier layer and redeposition contamination by ion beam etching affects the performance of semiconductor devices and cannot meet the needs of small-size and high-performance electronic devices.
The gap wall is formed on the opposite side walls of the bit line, covering the portions of the free layers facing each other in the first direction to avoid damage to the barrier layer by ion beam etching and reduce redeposition contamination.
The overlapping part of the free layer and the bit line is effectively protected, avoiding damage to the barrier layer by ion beam etching, and ensuring that the performance of the semiconductor device is not affected.
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Figure CN120390412A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a semiconductor device and a method for manufacturing the same. Background Art
[0002] Magnetic random access memory (MRAM) provides performance comparable to that of volatile static random access memory (SRAM), density comparable to that of volatile dynamic random access memory (DRAM), and lower power consumption. Compared with non-volatile flash memory, MRAM provides a faster access time and less degradation over time, while flash memory is limited by a finite number of rewrite cycles.
[0003] The basic storage unit of MRAM can be referred to as a magnetic tunneling junction (MTJ). For example, an MTJ can include a sandwich structure (e.g., free layer / barrier layer / pinned layer) composed of two ferromagnetic layers and an insulating layer sandwiched therebetween. When the magnetization direction of the free layer is the same as that of the pinned layer (also referred to as the "parallel state"), the resistance value measured between the upper and lower electrodes of the MTJ is smaller, while when the magnetization direction of the free layer is opposite to that of the pinned layer (also referred to as the "antiparallel state"), the resistance value measured between the upper and lower electrodes of the MTJ is larger. Thus, data can be stored through the resistance difference.
[0004] However, as electronic devices continue to develop towards smaller sizes and higher performance, there may be some problems with the current existing MRAM manufacturing processes and they may not meet the requirements of current or future electronic devices. For example, in the manufacturing process of forming the barrier layer, the damage to the barrier layer by ion-beam etch (IBE) or the contamination of re-deposition has a significant impact on the performance of the MRAM expected for current or future applications. Therefore, those skilled in the art continue to strive to improve the MRAM manufacturing process. Summary of the Invention
[0005] The present invention provides a semiconductor device and a method for manufacturing the same. In one embodiment, the spacer walls on the opposite sidewalls of the bit line include portions covering the first sidewalls of the free layers that are opposite to each other in a first direction. In this way, in the manufacturing process of forming the barrier layer, the damage to the barrier layer by ion-beam etch is away from the portion of the free layer that overlaps with the bit line (i.e., the effective region), so that the performance of the semiconductor device is not affected.
[0006] An embodiment of the present invention provides a semiconductor device, which includes a plurality of first structures, a plurality of second structures, and a plurality of barrier layers. The first structures extend in a first direction and are spaced apart from each other in a second direction intersecting the first direction. Each first structure includes a word line, a selector on the word line, and at least one synthetic antiferromagnetic (SAF) structure on the selector. The second structures are above the first structures, extend in the second direction, and are spaced apart from each other in the first direction. Each second structure includes a bit line spanning a plurality of synthetic antiferromagnetic structures in the second direction, a plurality of free layers between the bit line and the synthetic antiferromagnetic structures, and a plurality of spacer walls respectively on opposite sidewalls of the bit line. The free layers are disposed at positions where the bit line and the word line intersect each other. The spacer walls include portions covering the first sidewalls of the free layers facing each other in the first direction. The barrier layers are between the first structures and the second structures, extend in the second direction, and are spaced apart from each other in the first direction.
[0007] In some embodiments, the portion of the spacer wall covers the top surface of the barrier layer located therebelow.
[0008] In some embodiments, in each first structure, at least one synthetic antiferromagnetic structure includes a plurality of synthetic antiferromagnetic structures spaced apart from each other in the first direction.
[0009] In some embodiments, the portion of the spacer wall overlaps with the barrier layer and the synthetic antiferromagnetic structure in a third direction perpendicular to the first direction and the second direction.
[0010] In some embodiments, the barrier layer includes sidewalls coplanar with the sidewalls of the synthetic antiferromagnetic structure.
[0011] In some embodiments, the semiconductor device further includes a plurality of insulating layers. Each insulating layer is below the bit line and between the plurality of free layers, wherein the plurality of insulating layers cover the second sidewalls of the free layers facing each other in the second direction.
[0012] An embodiment of the present invention provides a semiconductor device, which includes a plurality of first structures, a plurality of second structures, and at least one barrier layer. The first structures extend in a first direction and are spaced apart from each other in a second direction intersecting the first direction. Each first structure includes a word line, a selector on the word line, and a synthetic antiferromagnetic (SAF) structure on the selector. The second structures are above the first structures, extend in the second direction, and are spaced apart from each other in the first direction. Each second structure includes a bit line spanning a plurality of synthetic antiferromagnetic structures in the second direction and a plurality of free layers between the bit line and the plurality of synthetic antiferromagnetic structures. The free layers are disposed at positions where the bit line and the word line intersect each other. At least one barrier layer is between the first structures and the second structures.
[0013] In some embodiments, the at least one barrier layer is a continuous single film layer.
[0014] In some embodiments, the at least one barrier layer includes a plurality of barrier layers spaced apart from each other in the first direction and the second direction, and each barrier layer is disposed between each first structure and each second structure.
[0015] An embodiment of the present invention provides a method for manufacturing a semiconductor device, which includes the following steps: forming a plurality of first structures, wherein the plurality of first structures extend in a first direction and are spaced apart from each other in a second direction intersecting the first direction, and each first structure includes a word line, a selector on the word line, and at least one synthetic antiferromagnetic (SAF) structure on the selector; forming a barrier material layer covering the plurality of first structures; forming a plurality of second structures on the barrier material layer, wherein the plurality of second structures extend in the second direction and are spaced apart from each other in the first direction. Each second structure includes a bit line spanning a plurality of synthetic antiferromagnetic structures in the second direction, a plurality of free layers between the bit line and the plurality of synthetic antiferromagnetic structures, and a plurality of spacer walls respectively on opposite sidewalls of the bit line, wherein the free layers are formed at positions where the bit line and the word line intersect each other, and the spacer walls include portions covering first sidewalls of the free layers opposite to each other in the first direction; and removing portions of the barrier material layer exposed by the plurality of second structures to form a plurality of barrier layers, wherein the barrier layers extend in the second direction and are spaced apart from each other in the first direction.
[0016] In some embodiments, the portions of the spacer walls cover the top surfaces of the barrier layers located thereunder.
[0017] In some embodiments, the method for manufacturing a semiconductor device further includes removing, in the portions of the barrier material layer exposed by the plurality of second structures, the portions of the antiferromagnetic structure below the portions, such that at least one antiferromagnetic structure in each first structure is formed as a plurality of antiferromagnetic structures spaced apart from each other in a first direction.
[0018] Based on the above, in the semiconductor device and its manufacturing method according to one of the above embodiments, the spacer walls on the opposite sidewalls of the bit line include portions covering the first sidewalls of the free layers opposite to each other in the first direction, so that in the manufacturing process of forming the barrier layer, the damage to the barrier layer caused by ion-beam etch (IBE) is away from the portion of the free layer overlapping with the bit line (i.e., the effective region), without affecting the performance of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] Figures 1 to 6 is a cross-sectional schematic view of a method for manufacturing a semiconductor device according to an embodiment of the present invention;
[0020] Figure 7A is along a cross-section of an embodiment of the present invention Figure 6 The cross-sectional schematic view taken along the line X-X';
[0021] Figure 7B is along a cross-section of an embodiment of the present invention Figure 6 The cross-sectional schematic view taken along the line Y-Y';
[0022] Figure 8 is a cross-sectional schematic view of a semiconductor device according to another embodiment of the present invention;
[0023] Figure 9 is a cross-sectional schematic view of a semiconductor device according to another embodiment of the present invention.
[0024] SYMBOL DESCRIPTION
[0025] 10, 20, 30: Semiconductor device
[0026] BL: Bit line
[0027] BML: Barrier material layer
[0028] D1: First direction
[0029] D2: Second direction
[0030] D3: Third direction
[0031] FL: Free layer
[0032] IL: Insulating layer
[0033] OTS: Selector
[0034] S1: First structure
[0035] S2: Second structure
[0036] SAF, SAF’: Synthetic antiferromagnetic structure
[0037] SW: Spacer wall
[0038] TBL, TBL’, TBL”: Barrier layer
[0039] WL: Word line Detailed implementation manners
[0040] The present invention will be described more fully with reference to the accompanying drawings of this embodiment. However, the present invention can be embodied in various different forms and should not be limited to the embodiments described herein. The thicknesses of layers and regions in the drawings are enlarged for clarity. The same or similar reference numerals denote the same or similar elements, and will not be repeated in the following paragraphs.
[0041] It should be understood that when an element is referred to as being “on” or “connected to” another element, it can be directly on or connected to the other element, or there may also be intervening elements. When an element is referred to as being “directly on” or “directly connected to” another element, there are no intervening elements. As used herein, “connected” can refer to physical and / or electrical connection, and “electrical connection” or “coupling” can mean that there are other elements between two elements. The “electrical connection” used herein can include physical connection (such as wired connection) and physical disconnection (such as wireless connection).
[0042] As used herein, “about”, “approximate” or “substantially” includes the value mentioned and the average value within an acceptable deviation range of a specific value that can be determined by those of ordinary skill in the art, considering the specific amount of the measurement being discussed and the error associated with the measurement (i.e., the limitations of the measurement system). For example, “about” can mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, ±5%. Furthermore, the “about”, “approximate” or “substantially” used herein can select a more acceptable deviation range or standard deviation according to optical properties, etching properties or other properties, and may not use one standard deviation for all properties.
[0043] The terms used herein are only for describing exemplary embodiments and do not limit the present invention. In such a case, unless otherwise explained in the context, the singular form includes the plural form.
[0044] Figures 1 to 6 is a cross-sectional schematic view of a manufacturing method of a semiconductor device according to an embodiment of the present invention. Figure 7A is an embodiment of the present invention alongFigure 6 Schematic cross-sectional view taken along section line X-X' Figure 7B is a cross-sectional view taken along the section line Figure 6 Y-Y' of an embodiment of the present invention.
[0045] In some embodiments, a method of manufacturing a semiconductor device (such as the semiconductor device 10 shown in Figure 6 ) may include the following steps.
[0046] First, as shown in Figure 2 , a plurality of first structures S1 extending in a first direction D1 and spaced apart from each other in a second direction D2 intersecting the first direction D1 are formed. Each first structure S1 includes a word line WL, a selector OTS on the word line WL, and at least one synthetic antiferromagnetic (SAF) structure SAF on the selector OTS. The word line WL may include a conductive material such as a metal or a metal alloy. The metal and the metal alloy may be, for example, Cu, Al, Ti, Ta, W, Pt, Cr, Mo, or an alloy thereof. The selector OTS may include an ovonic threshold switch (OTS). The selector OTS may include a phase change material such as germanium-antimony-tellurium (GeSbTe, GST). The synthetic antiferromagnetic structure SAF may include multiple layers of different materials. For example, the synthetic antiferromagnetic structure SAF may include a stack of one or more ferromagnetic layers and one or more non-magnetic layers. For example, the synthetic antiferromagnetic structure SAF may be formed by a non-magnetic layer sandwiched between two ferromagnetic layers or may be a stack of alternating non-magnetic layers and ferromagnetic layers. The ferromagnetic layer may be formed of, for example, the following materials: Co, Fe, Ni, Pt, CoPt, CoFe, NiFe, CoFeB, CoFeBW, an alloy thereof, or a combination thereof. The non-magnetic layer may be formed of, for example, the following materials: Cu, Ru, Ir, Pt, W, Ta, Mg, or a combination thereof.
[0047] In some embodiments, the first structure S1 may be formed on a substrate (not shown). The substrate may include a semiconductor substrate, a semiconductor on insulator (SOI) substrate, and / or an element layer and an interconnect layer formed on the semiconductor substrate or the SOI substrate.
[0048] The semiconductor material in a semiconductor substrate or an SOI substrate may include elemental semiconductors, alloy semiconductors, or compound semiconductors. For example, the elemental semiconductor may include Si or Ge. The alloy semiconductor may include SiGe, SiGeC, etc. The compound semiconductor may include SiC, group III-V semiconductor materials, or group II-VI semiconductor materials. The group III-V semiconductor materials may include GaN, GaP, GaAs, AlN, AlP, AlAs, InN, InP, InAs, GaNP, GaNAs, GaPAs, AlNP, AlNAs, AlPAs, InNP, InNAs, InPAs, GaAlNP, GaAlNAs, GaAlPAs, GaInNP, GaInNAs, GaInPAs, InAlNP, InAlNAs, or InAlPAs. The group II-VI semiconductor materials may include CdS, CdSe, CdTe, ZnS, ZnSe, ZnTe, HgS, HgSe, HgTe, CdSeS, CdSeTe, CdSTe, ZnSeS, ZnSeTe, ZnSTe, HgSeS, HgSeTe, HgSTe, CdZnS, CdZnSe, CdZnTe, CdHgS, CdHgSe, CdHgTe, HgZnS, HgZnSe, HgZnTe, CdZnSeS, CdZnSeTe, CdZnSTe, CdHgSeS, CdHgSeTe, CdHgSTe, HgZnSeS, HgZnSeTe, or HgZnSTe. The semiconductor material may be doped with dopants of a first conductivity type or dopants of a second conductivity type complementary to the first conductivity type. For example, the first conductivity type may be P-type, and the second conductivity type may be N-type.
[0049] The device layer may include active devices such as metal oxide semiconductor field effect transistors (MOSFETs), passive devices such as resistors, inductors, or capacitors, or combinations thereof. The interconnect layer may include dielectric layers formed by front-end-of-line (FEOL) and / or back-end-of-line (BEOL) processes and / or conductor layers and / or conductive vias embedded therein. The dielectric layer may include dielectric materials such as oxides (e.g., silicon oxide) or nitrides (e.g., silicon nitride). The conductor layer and the conductive via may each include conductive materials such as metals or metal alloys. The metal and the metal alloy may be, for example, Cu, Al, Ti, Ta, W, Pt, Cr, Mo, or alloys thereof.
[0050] In some embodiments, the first structure S1 may be formed by the following steps. First, please refer toFigure 1 , a plurality of word lines WL extending in a first direction D1 and spaced apart from each other in a second direction D2 are formed, and selectors OTS are formed on each word line WL. In some embodiments, a word line material layer (not shown) and a selector material layer (not shown) may be sequentially formed on a substrate, and then a patterning process is performed on the word line material layer and the selector material layer to form the word lines WL and the selectors OTS.
[0051] Next, a synthetic antiferromagnetic structure SAF is formed on each selector OTS. In some embodiments, an SAF material layer (not shown) may be formed on the selector OTS, and then a patterning process is performed on the SAF material layer using ion-beam etch (IBE) to form the synthetic antiferromagnetic structure SAF.
[0052] Then, refer to Figure 2 and Figure 3 , a barrier material layer BML covering the plurality of first structures S1 is formed. The barrier material layer BML includes materials such as MgO, AlO, AlN, or SrTiO3. In some embodiments, an insulating layer (not shown) may be formed between the plurality of first structures S1 before forming the barrier material layer BML. Then, a barrier material layer BML covering the plurality of first structures S1 is formed on the insulating layer.
[0053] Thereafter, a plurality of second structures (such as the second structure S2 shown in Figure 5 ) are formed on the barrier material layer BML. In some embodiments, a plurality of second structures may be formed on the barrier material layer BML through the following steps.
[0054] First, refer to Figure 3 and Figure 4 , a plurality of free layers FL are formed on the barrier material layer BML. In some embodiments, the plurality of free layers FL may be spaced apart from each other in the first direction D1 and the second direction D2, and may overlap with the first structure S1 in a third direction D3 perpendicular to the first direction D1 and the second direction D2. The free layer FL may include one or more of the following ferromagnetic materials: cobalt iron boron (CoFeB), cobalt / palladium (CoPd), cobalt iron (CoFe), cobalt iron boron tungsten (CoFeBW), nickel iron (NiFe), Ru, its alloy, or its combination. The free layer FL may be a single layer or a multi-layer. In some embodiments, a free material layer (not shown) may be formed on the barrier material layer BML, and then a patterning process is performed on the free material layer using ion-beam etch (IBE) to form the plurality of free layers FL.
[0055] Next, refer to Figure 4 and Figure 5, bit lines BL can be formed on multiple free layers FL, and multiple spacer walls SW can be formed on opposite sidewalls of the bit lines BL to form multiple second structures S2 including multiple free layers FL, multiple bit lines BL, and multiple spacer walls SW. The multiple second structures S2 extend in a second direction D2 and are spaced apart from each other in a first direction D1. In each second structure S2, the bit line BL spans multiple synthetic antiferromagnetic structures SAF in the second direction D2; multiple free layers FL are formed between the bit line BL and the multiple synthetic antiferromagnetic structures SAF; and multiple spacer walls SW are respectively formed on opposite sidewalls of the bit line BL. The free layer FL can be formed at a position where the bit line BL and the word line WL cross each other, and the spacer wall SW can include a portion covering the first sidewalls of the free layers FL facing each other in the first direction D1.
[0056] The bit line BL can include a conductive material such as a metal or a metal alloy. The metal and the metal alloy can be, for example, Cu, Al, Ti, Ta, W, Pt, Cr, Mo, or an alloy thereof. The spacer wall SW can include a suitable material such as an oxide, a nitride, or a combination thereof.
[0057] Then, refer to Figure 5 and Figure 6 , remove the portions of the barrier material layer BML exposed by the multiple second structures S2 to form multiple barrier layers TBL extending in the second direction D2 and spaced apart from each other in the first direction D1. Based on the spacer wall SW on the opposite sidewalls of the bit line BL including a portion covering the first sidewalls of the free layers FL facing each other in the first direction D1, in the manufacturing process of forming the barrier layer TBL, the damage to the barrier layer TBL by ion-beam etch (IBE) is away from the portion (i.e., the effective region) of the free layer FL overlapping with the bit line BL, without affecting the performance of the semiconductor device. In some embodiments, the said portion of the spacer wall SW covers the top surface of the barrier layer TBL located below it, so that the re-deposition contamination caused by IBE can also be avoided because the top surface of the barrier layer TBL is covered by the spacer wall SW.
[0058] In some embodiments, in removing the portions of the barrier material layer BML exposed by the multiple second structures S2, the portions of the synthetic antiferromagnetic structure SAF below the said portions are also removed, so that the synthetic antiferromagnetic structures SAF in each first structure S1 are formed as multiple synthetic antiferromagnetic structures SAF' spaced apart from each other in the first direction D1.
[0059] Hereinafter, through Figure 6 , Figure 7A and Figure 7BTo illustrate the semiconductor device 10. The semiconductor device 10 can be formed by the method described above, but the present invention is not limited thereto.
[0060] Please refer to Figure 6 , Figure 7A and Figure 7B , the semiconductor device 10 includes a plurality of first structures S1, a plurality of second structures S2, and a plurality of barrier layers TBL between the first structure S1 and the second structure S2. The first structure S1 extends in a first direction D1 and is spaced apart from each other in a second direction D2 intersecting the first direction D1. Each first structure S1 includes a word line WL, a selector OTS on the word line WL, and at least one synthetic antiferromagnetic structure SAF' on the selector OTS. The second structure S2 extends above the first structure S1, in the second direction D2, and is spaced apart from each other in the first direction D1. Each second structure S2 includes a bit line BL spanning a plurality of synthetic antiferromagnetic structures SAF' in the second direction D2, a plurality of free layers FL between the bit line BL and the plurality of synthetic antiferromagnetic structures SAF', and a plurality of spacer walls SW on opposite sidewalls of the bit line BL, respectively. The free layer FL is disposed at a position where the bit line BL and the word line WL cross each other, and the spacer wall SW includes a portion covering the first sidewalls of the free layers FL facing each other in the first direction D1. In some embodiments, the portion of the spacer wall SW covers the top surface of the barrier layer TBL located therebelow. In some embodiments, the portion of the spacer wall SW overlaps the barrier layer TBL and the synthetic antiferromagnetic structure SAF' in a third direction D3 perpendicular to the first direction D1 and the second direction D2. The barrier layer TBL extends in the second direction D2 and is spaced apart from each other in the first direction D1. In some embodiments, the barrier layer TBL includes sidewalls coplanar with the sidewalls of the synthetic antiferromagnetic structure SAF'.
[0061] In some embodiments, in each first structure S1, at least one synthetic antiferromagnetic structure SAF' can be plural, and the plural synthetic antiferromagnetic structures SAF' extend in the second direction D2 and are spaced apart from each other in the first direction D1.
[0062] In some embodiments, the semiconductor device 10 further includes a plurality of insulating layers IL. Each insulating layer IL is below the bit line BL and between the plurality of free layers FL, wherein the plurality of insulating layers IL cover the second sidewalls of the free layers FL facing each other in the second direction D2. In some embodiments, the insulating layer IL can include insulating materials such as oxides (e.g., silicon oxide), nitrides (e.g., silicon nitride), or combinations thereof.
[0063] Figure 8 is a cross-sectional schematic diagram of a semiconductor device according to another embodiment of the present invention. Figure 8 The illustrated semiconductor device 20 and Figure 6Similar to the semiconductor device 10 shown, the main differences are that: the second structure S2 does not include a spacer wall SW; the barrier layers TBL' are spaced apart from each other in the first direction D1 and the second direction D2; and the synthetic antiferromagnetic structure SAF extends in the first direction D1 and is spaced apart from each other in the second direction D2. For ease of explanation, Figure 8 the Figure 6 insulating layer IL shown is omitted.
[0064] Please refer to Figure 8 , the semiconductor device 20 includes a plurality of first structures S1, a plurality of second structures S2, and a plurality of barrier layers TBL'. The first structures S1 extend in the first direction D1 and are spaced apart from each other in the second direction D2 intersecting the first direction D1. Each first structure S1 includes a word line WL, a selector OTS on the word line WL, and a synthetic antiferromagnetic structure SAF on the selector OTS; the second structures S2 extend above the first structures S1, in the second direction D2, and are spaced apart from each other in the first direction D1. Each second structure S2 includes a bit line BL spanning a plurality of synthetic antiferromagnetic structures SAF in the second direction D2 and a plurality of free layers FL between the bit line BL and the plurality of synthetic antiferromagnetic structures SAF. The free layers FL are disposed at positions where the bit line BL and the word line WL intersect each other. The barrier layers TBL' are spaced apart from each other in the first direction D1 and the second direction D2, and each barrier layer TBL' is disposed between each first structure S1 and each second structure S2. In some embodiments, the free layers FL and the barrier layers TBL' can be formed by the following steps. First, a barrier material layer (such as Figure 3 the barrier material layer BML) and a free material layer (not shown) are sequentially formed on the first structure S1. Then, the free material layer and the barrier material layer BML are simultaneously patterned using the same mask as that for forming the free layer FL as shown in Figure 4 to form the free layer FL and the barrier layer TBL'.
[0065] Figure 9 is a cross-sectional schematic view of a semiconductor device according to another embodiment of the present invention. Figure 9 The semiconductor device 30 shown is similar to Figure 8 the semiconductor device 20 shown, and the main difference is that: the barrier layer TBL'' is a continuous single film layer.
[0066] Please refer to Figure 9, the semiconductor device 30 includes a plurality of first structures S1, a plurality of second structures S2, and a barrier layer TBL" between the first structure S1 and the second structure S2. The first structures S1 extend in a first direction D1 and are spaced apart from each other in a second direction D2 intersecting the first direction D1. Each first structure S1 includes a word line WL, a selector OTS on the word line WL, and a synthetic antiferromagnetic structure SAF on the selector OTS. The second structures S2 extend above the first structures S1 in the second direction D2 and are spaced apart from each other in the first direction D1. Each second structure S2 includes a bit line BL spanning a plurality of synthetic antiferromagnetic structures SAF in the second direction D2 and a plurality of free layers FL between the bit line BL and the plurality of synthetic antiferromagnetic structures SAF. The free layers FL are disposed at positions where the bit line BL and the word line WL intersect each other. In some embodiments, the barrier layer TBL" can be formed by the following steps. First, after forming the free layer FL as shown in Figure 4 on the barrier material layer BML, that is, forming the bit line BL spanning a plurality of synthetic antiferromagnetic structures SAF and spanning a plurality of free layers FL on the free layer FL, without performing an additional patterning process on the barrier material layer BML, to form the barrier layer TBL" as shown in Figure 9 . In this way, damage to the barrier layer TBL" caused by IBE can be avoided, and re-deposition contamination caused by IBE can also be avoided.
[0067] In summary, in the above semiconductor device and the method of forming the semiconductor device, the spacer walls on the opposite sidewalls of the bit line include portions covering the first sidewalls of the free layers facing each other in the first direction, so that in the manufacturing process of forming the barrier layer, the damage to the barrier layer caused by ion-beam etch (IBE) is away from the portion of the free layer overlapping with the bit line (i.e., the effective region), without affecting the performance of the semiconductor device.
Claims
1. A semiconductor device, comprising: a plurality of first structures extending in a first direction and spaced apart from each other in a second direction intersecting the first direction, each of the first structures including a word line, a selector on the word line, and at least one synthetic antiferromagnetic (SAF) structure on the selector; a plurality of second structures above the plurality of first structures, extending in the second direction, and spaced apart from each other in the first direction, each of the second structures including a bit line spanning a plurality of the synthetic antiferromagnetic structures in the second direction, a plurality of free layers between the bit line and the plurality of synthetic antiferromagnetic structures, and a plurality of spacer walls on opposite sidewalls of the bit line respectively, wherein the free layers are disposed at positions where the bit line and the word line intersect each other, and the spacer walls include portions covering a first sidewall of the free layers opposite to each other in the first direction; and a plurality of barrier layers between the first structures and the second structures, extending in the second direction, and spaced apart from each other in the first direction.
2. The semiconductor device according to claim 1, wherein the portion of the spacer wall covers a top surface of the barrier layer located therebelow.
3. The semiconductor device according to claim 1, wherein in each of the first structures, at least one of the synthetic antiferromagnetic structures includes a plurality of synthetic antiferromagnetic structures spaced apart from each other in the first direction.
4. The semiconductor device according to claim 3, wherein the portion of the spacer wall overlaps with the barrier layer and the synthetic antiferromagnetic structure in a third direction perpendicular to the first direction and the second direction.
5. The semiconductor device according to claim 3, wherein the barrier layer includes sidewalls coplanar with sidewalls of the synthetic antiferromagnetic structure.
6. The semiconductor device according to claim 1, further comprising: a plurality of insulating layers, each of the insulating layers below the bit line and between the plurality of free layers, wherein the plurality of insulating layers cover a second sidewall of the free layers opposite to each other in the second direction.
7. A semiconductor device, comprising: a plurality of first structures extending in a first direction and spaced apart from each other in a second direction intersecting the first direction, each of the first structures including a word line, a selector on the word line, and a synthetic antiferromagnetic (SAF) structure on the selector; a plurality of second structures above the plurality of first structures, extending in the second direction, and spaced apart from each other in the first direction, each of the second structures including a bit line spanning a plurality of the synthetic antiferromagnetic structures in the second direction and a plurality of free layers between the bit line and the plurality of synthetic antiferromagnetic structures, wherein the free layers are disposed at positions where the bit line and the word line intersect each other; and at least one barrier layer between the first structures and the second structures.
8. The semiconductor device according to claim 7, wherein the at least one barrier layer is a continuous single film layer.
9. The semiconductor device according to claim 7, wherein the at least one barrier layer includes a plurality of barrier layers spaced apart from each other in the first direction and the second direction, and each of the barrier layers is disposed between each of the first structures and each of the second structures.
10. A method of manufacturing a semiconductor device, comprising: forming a plurality of first structures, wherein the plurality of first structures extend in a first direction and are spaced apart from each other in a second direction intersecting the first direction, and each of the first structures includes a word line, a selector on the word line, and at least one synthetic antiferromagnetic (SAF) structure on the selector; forming a barrier material layer covering the plurality of first structures; forming a plurality of second structures on the barrier material layer, wherein the plurality of second structures extend in the second direction and are spaced apart from each other in the first direction, and each of the second structures includes a bit line spanning a plurality of the synthetic antiferromagnetic structures in the second direction, a plurality of free layers between the bit line and the plurality of synthetic antiferromagnetic structures, and a plurality of spacer walls respectively on opposite sidewalls of the bit line, wherein the free layers are formed at positions where the bit line and the word line intersect each other, and the spacer walls include portions covering first sidewalls of the free layers opposite to each other in the first direction; and removing portions of the barrier material layer exposed by the plurality of second structures to form a plurality of barrier layers, wherein the barrier layers extend in the second direction and are spaced apart from each other in the first direction.
11. The method of manufacturing a semiconductor device according to claim 10, wherein the portions of the spacer walls cover top surfaces of the barrier layers located thereunder.
12. The method of manufacturing a semiconductor device according to claim 10, further comprising: in removing the portions of the barrier material layer exposed by the plurality of second structures, portions of at least one of the synthetic antiferromagnetic structures under the portions are also removed, such that at least one of the synthetic antiferromagnetic structures in each of the first structures is formed as a plurality of synthetic antiferromagnetic structures spaced apart from each other in the first direction.